1 #define NVOC_GPU_H_PRIVATE_ACCESS_ALLOWED
2 #include "nvoc/runtime.h"
3 #include "nvoc/rtti.h"
4 #include "nvtypes.h"
5 #include "nvport/nvport.h"
6 #include "nvport/inline/util_valist.h"
7 #include "utils/nvassert.h"
8 #include "g_gpu_nvoc.h"
9
10 #ifdef DEBUG
11 char __nvoc_class_id_uniqueness_check_0x7ef3cb = 1;
12 #endif
13
14 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU;
15
16 extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object;
17
18 extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmHalspecOwner;
19
20 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJTRACEABLE;
21
22 void __nvoc_init_OBJGPU(OBJGPU*,
23 NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev,
24 RM_RUNTIME_VARIANT RmVariantHal_rmVariant,
25 TEGRA_CHIP_TYPE TegraChipHal_tegraType,
26 NvU32 DispIpHal_ipver);
27 void __nvoc_init_funcTable_OBJGPU(OBJGPU*);
28 NV_STATUS __nvoc_ctor_OBJGPU(OBJGPU*, NvU32 arg_gpuInstance, NvU32 arg_gpuId, NvUuid * arg_pUuid);
29 void __nvoc_init_dataField_OBJGPU(OBJGPU*);
30 void __nvoc_dtor_OBJGPU(OBJGPU*);
31 extern const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJGPU;
32
33 static const struct NVOC_RTTI __nvoc_rtti_OBJGPU_OBJGPU = {
34 /*pClassDef=*/ &__nvoc_class_def_OBJGPU,
35 /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_OBJGPU,
36 /*offset=*/ 0,
37 };
38
39 static const struct NVOC_RTTI __nvoc_rtti_OBJGPU_Object = {
40 /*pClassDef=*/ &__nvoc_class_def_Object,
41 /*dtor=*/ &__nvoc_destructFromBase,
42 /*offset=*/ NV_OFFSETOF(OBJGPU, __nvoc_base_Object),
43 };
44
45 static const struct NVOC_RTTI __nvoc_rtti_OBJGPU_RmHalspecOwner = {
46 /*pClassDef=*/ &__nvoc_class_def_RmHalspecOwner,
47 /*dtor=*/ &__nvoc_destructFromBase,
48 /*offset=*/ NV_OFFSETOF(OBJGPU, __nvoc_base_RmHalspecOwner),
49 };
50
51 static const struct NVOC_RTTI __nvoc_rtti_OBJGPU_OBJTRACEABLE = {
52 /*pClassDef=*/ &__nvoc_class_def_OBJTRACEABLE,
53 /*dtor=*/ &__nvoc_destructFromBase,
54 /*offset=*/ NV_OFFSETOF(OBJGPU, __nvoc_base_OBJTRACEABLE),
55 };
56
57 static const struct NVOC_CASTINFO __nvoc_castinfo_OBJGPU = {
58 /*numRelatives=*/ 4,
59 /*relatives=*/ {
60 &__nvoc_rtti_OBJGPU_OBJGPU,
61 &__nvoc_rtti_OBJGPU_OBJTRACEABLE,
62 &__nvoc_rtti_OBJGPU_RmHalspecOwner,
63 &__nvoc_rtti_OBJGPU_Object,
64 },
65 };
66
67 const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU =
68 {
69 /*classInfo=*/ {
70 /*size=*/ sizeof(OBJGPU),
71 /*classId=*/ classId(OBJGPU),
72 /*providerId=*/ &__nvoc_rtti_provider,
73 #if NV_PRINTF_STRINGS_ALLOWED
74 /*name=*/ "OBJGPU",
75 #endif
76 },
77 /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_OBJGPU,
78 /*pCastInfo=*/ &__nvoc_castinfo_OBJGPU,
79 /*pExportInfo=*/ &__nvoc_export_info_OBJGPU
80 };
81
82 const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJGPU =
83 {
84 /*numEntries=*/ 0,
85 /*pExportEntries=*/ 0
86 };
87
88 void __nvoc_dtor_Object(Object*);
89 void __nvoc_dtor_RmHalspecOwner(RmHalspecOwner*);
90 void __nvoc_dtor_OBJTRACEABLE(OBJTRACEABLE*);
__nvoc_dtor_OBJGPU(OBJGPU * pThis)91 void __nvoc_dtor_OBJGPU(OBJGPU *pThis) {
92 __nvoc_gpuDestruct(pThis);
93 __nvoc_dtor_Object(&pThis->__nvoc_base_Object);
94 __nvoc_dtor_RmHalspecOwner(&pThis->__nvoc_base_RmHalspecOwner);
95 __nvoc_dtor_OBJTRACEABLE(&pThis->__nvoc_base_OBJTRACEABLE);
96 PORT_UNREFERENCED_VARIABLE(pThis);
97 }
98
__nvoc_init_dataField_OBJGPU(OBJGPU * pThis)99 void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) {
100 ChipHal *chipHal = &staticCast(pThis, RmHalspecOwner)->chipHal;
101 const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx;
102 RmVariantHal *rmVariantHal = &staticCast(pThis, RmHalspecOwner)->rmVariantHal;
103 const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
104 PORT_UNREFERENCED_VARIABLE(pThis);
105 PORT_UNREFERENCED_VARIABLE(chipHal);
106 PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx);
107 PORT_UNREFERENCED_VARIABLE(rmVariantHal);
108 PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
109 pThis->setProperty(pThis, PDB_PROP_GPU_IS_CONNECTED, ((NvBool)(0 == 0)));
110
111 // NVOC Property Hal field -- PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY
112 // default
113 {
114 pThis->setProperty(pThis, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY, ((NvBool)(0 != 0)));
115 }
116
117 // NVOC Property Hal field -- PDB_PROP_GPU_TEGRA_SOC_IGPU
118 // default
119 {
120 pThis->setProperty(pThis, PDB_PROP_GPU_TEGRA_SOC_IGPU, ((NvBool)(0 != 0)));
121 }
122
123 // NVOC Property Hal field -- PDB_PROP_GPU_ATS_SUPPORTED
124 // default
125 {
126 pThis->setProperty(pThis, PDB_PROP_GPU_ATS_SUPPORTED, ((NvBool)(0 != 0)));
127 }
128
129 // NVOC Property Hal field -- PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE
130 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */
131 {
132 pThis->setProperty(pThis, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE, ((NvBool)(0 == 0)));
133 }
134 // default
135 else
136 {
137 pThis->setProperty(pThis, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE, ((NvBool)(0 != 0)));
138 }
139
140 // NVOC Property Hal field -- PDB_PROP_GPU_ZERO_FB
141 // default
142 {
143 pThis->setProperty(pThis, PDB_PROP_GPU_ZERO_FB, ((NvBool)(0 != 0)));
144 }
145
146 // NVOC Property Hal field -- PDB_PROP_GPU_BAR1_BAR2_DISABLED
147 // default
148 {
149 pThis->setProperty(pThis, PDB_PROP_GPU_BAR1_BAR2_DISABLED, ((NvBool)(0 != 0)));
150 }
151
152 // NVOC Property Hal field -- PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE
153 // default
154 {
155 pThis->setProperty(pThis, PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE, ((NvBool)(0 != 0)));
156 }
157
158 // NVOC Property Hal field -- PDB_PROP_GPU_MIG_SUPPORTED
159 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */
160 {
161 pThis->setProperty(pThis, PDB_PROP_GPU_MIG_SUPPORTED, ((NvBool)(0 == 0)));
162 }
163 // default
164 else
165 {
166 pThis->setProperty(pThis, PDB_PROP_GPU_MIG_SUPPORTED, ((NvBool)(0 != 0)));
167 }
168
169 // NVOC Property Hal field -- PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED
170 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */
171 {
172 pThis->setProperty(pThis, PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED, ((NvBool)(0 == 0)));
173 }
174 // default
175 else
176 {
177 pThis->setProperty(pThis, PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED, ((NvBool)(0 != 0)));
178 }
179
180 // NVOC Property Hal field -- PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED
181 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
182 {
183 pThis->setProperty(pThis, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED, ((NvBool)(0 == 0)));
184 }
185 // default
186 else
187 {
188 pThis->setProperty(pThis, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED, ((NvBool)(0 != 0)));
189 }
190
191 // NVOC Property Hal field -- PDB_PROP_GPU_IS_COT_ENABLED
192 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
193 {
194 pThis->setProperty(pThis, PDB_PROP_GPU_IS_COT_ENABLED, ((NvBool)(0 == 0)));
195 }
196 // default
197 else
198 {
199 pThis->setProperty(pThis, PDB_PROP_GPU_IS_COT_ENABLED, ((NvBool)(0 != 0)));
200 }
201
202 // Hal field -- bIsFlexibleFlaSupported
203 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
204 {
205 pThis->bIsFlexibleFlaSupported = ((NvBool)(0 == 0));
206 }
207 // default
208 else
209 {
210 pThis->bIsFlexibleFlaSupported = ((NvBool)(0 != 0));
211 }
212
213 // NVOC Property Hal field -- PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED
214 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
215 {
216 pThis->setProperty(pThis, PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED, ((NvBool)(0 == 0)));
217 }
218 // default
219 else
220 {
221 pThis->setProperty(pThis, PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED, ((NvBool)(0 != 0)));
222 }
223
224 // NVOC Property Hal field -- PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE
225 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
226 {
227 pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 == 0)));
228 }
229 // default
230 else
231 {
232 pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 != 0)));
233 }
234
235 // NVOC Property Hal field -- PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED
236 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
237 {
238 pThis->setProperty(pThis, PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED, ((NvBool)(0 == 0)));
239 }
240
241 // NVOC Property Hal field -- PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK
242 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
243 {
244 pThis->setProperty(pThis, PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK, ((NvBool)(0 != 0)));
245 }
246 // default
247 else
248 {
249 pThis->setProperty(pThis, PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK, ((NvBool)(0 == 0)));
250 }
251 pThis->setProperty(pThis, PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE, ((NvBool)(0 == 0)));
252
253 // NVOC Property Hal field -- PDB_PROP_GPU_CC_FEATURE_CAPABLE
254 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
255 {
256 pThis->setProperty(pThis, PDB_PROP_GPU_CC_FEATURE_CAPABLE, ((NvBool)(0 == 0)));
257 }
258 // default
259 else
260 {
261 pThis->setProperty(pThis, PDB_PROP_GPU_CC_FEATURE_CAPABLE, ((NvBool)(0 != 0)));
262 }
263
264 // NVOC Property Hal field -- PDB_PROP_GPU_APM_FEATURE_CAPABLE
265 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */
266 {
267 pThis->setProperty(pThis, PDB_PROP_GPU_APM_FEATURE_CAPABLE, ((NvBool)(0 == 0)));
268 }
269 // default
270 else
271 {
272 pThis->setProperty(pThis, PDB_PROP_GPU_APM_FEATURE_CAPABLE, ((NvBool)(0 != 0)));
273 }
274
275 // NVOC Property Hal field -- PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX
276 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
277 {
278 pThis->setProperty(pThis, PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX, ((NvBool)(0 == 0)));
279 }
280 // default
281 else
282 {
283 pThis->setProperty(pThis, PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX, ((NvBool)(0 != 0)));
284 }
285
286 // NVOC Property Hal field -- PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF
287 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
288 {
289 pThis->setProperty(pThis, PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF, ((NvBool)(0 == 0)));
290 }
291
292 // NVOC Property Hal field -- PDB_PROP_GPU_IS_SOC_SDM
293 // default
294 {
295 pThis->setProperty(pThis, PDB_PROP_GPU_IS_SOC_SDM, ((NvBool)(0 != 0)));
296 }
297
298 // NVOC Property Hal field -- PDB_PROP_GPU_DISP_PB_REQUIRES_SMMU_BYPASS
299 pThis->setProperty(pThis, PDB_PROP_GPU_DISP_PB_REQUIRES_SMMU_BYPASS, ((NvBool)(0 == 0)));
300 pThis->setProperty(pThis, PDB_PROP_GPU_FASTPATH_SEQ_ENABLED, ((NvBool)(0 != 0)));
301
302 pThis->deviceInstance = 32;
303
304 // Hal field -- isVirtual
305 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
306 {
307 pThis->isVirtual = ((NvBool)(0 == 0));
308 }
309 else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */
310 {
311 pThis->isVirtual = ((NvBool)(0 != 0));
312 }
313
314 // Hal field -- isGspClient
315 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */
316 {
317 pThis->isGspClient = ((NvBool)(0 == 0));
318 }
319 else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
320 {
321 pThis->isGspClient = ((NvBool)(0 != 0));
322 }
323
324 pThis->bIsDebugModeEnabled = ((NvBool)(0 != 0));
325
326 pThis->numOfMclkLockRequests = 0U;
327
328 pThis->bUseRegisterAccessMap = !(0);
329
330 pThis->boardInfo = ((void *)0);
331
332 pThis->bIsMigRm = ((NvBool)(0 != 0));
333
334 // Hal field -- bUnifiedMemorySpaceEnabled
335 // default
336 {
337 pThis->bUnifiedMemorySpaceEnabled = ((NvBool)(0 != 0));
338 }
339
340 // Hal field -- bWarBug200577889SriovHeavyEnabled
341 pThis->bWarBug200577889SriovHeavyEnabled = ((NvBool)(0 != 0));
342
343 // Hal field -- bNonPowerOf2ChannelCountSupported
344 pThis->bNonPowerOf2ChannelCountSupported = ((NvBool)(0 != 0));
345
346 // Hal field -- bNeed4kPageIsolation
347 // default
348 {
349 pThis->bNeed4kPageIsolation = ((NvBool)(0 != 0));
350 }
351
352 // Hal field -- bInstLoc47bitPaWar
353 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
354 {
355 pThis->bInstLoc47bitPaWar = ((NvBool)(0 == 0));
356 }
357
358 // Hal field -- bIsBarPteInSysmemSupported
359 // default
360 {
361 pThis->bIsBarPteInSysmemSupported = ((NvBool)(0 != 0));
362 }
363
364 // Hal field -- bClientRmAllocatedCtxBuffer
365 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
366 {
367 pThis->bClientRmAllocatedCtxBuffer = ((NvBool)(0 == 0));
368 }
369 // default
370 else
371 {
372 pThis->bClientRmAllocatedCtxBuffer = ((NvBool)(0 != 0));
373 }
374
375 pThis->bIterativeMmuWalker = ((NvBool)(0 == 0));
376
377 // Hal field -- bVidmemPreservationBrokenBug3172217
378 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
379 {
380 pThis->bVidmemPreservationBrokenBug3172217 = ((NvBool)(0 == 0));
381 }
382 // default
383 else
384 {
385 pThis->bVidmemPreservationBrokenBug3172217 = ((NvBool)(0 != 0));
386 }
387
388 // Hal field -- bInstanceMemoryAlwaysCached
389 // default
390 {
391 pThis->bInstanceMemoryAlwaysCached = ((NvBool)(0 != 0));
392 }
393
394 // Hal field -- bComputePolicyTimesliceSupported
395 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
396 {
397 pThis->bComputePolicyTimesliceSupported = ((NvBool)(0 == 0));
398 }
399
400 // Hal field -- bSriovCapable
401 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
402 {
403 pThis->bSriovCapable = ((NvBool)(0 == 0));
404 }
405
406 // Hal field -- bRecheckSliSupportAtResume
407 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
408 {
409 pThis->bRecheckSliSupportAtResume = ((NvBool)(0 == 0));
410 }
411
412 // Hal field -- bGpuNvEncAv1Supported
413 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */
414 {
415 pThis->bGpuNvEncAv1Supported = ((NvBool)(0 == 0));
416 }
417 // default
418 else
419 {
420 pThis->bGpuNvEncAv1Supported = ((NvBool)(0 != 0));
421 }
422
423 pThis->bIsGspOwnedFaultBuffersEnabled = ((NvBool)(0 != 0));
424
425 // Hal field -- bVfResizableBAR1Supported
426 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
427 {
428 pThis->bVfResizableBAR1Supported = ((NvBool)(0 == 0));
429 }
430 // default
431 else
432 {
433 pThis->bVfResizableBAR1Supported = ((NvBool)(0 != 0));
434 }
435
436 // Hal field -- bVoltaHubIntrSupported
437 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
438 {
439 pThis->bVoltaHubIntrSupported = ((NvBool)(0 == 0));
440 }
441 }
442
443 NV_STATUS __nvoc_ctor_Object(Object* );
444 NV_STATUS __nvoc_ctor_RmHalspecOwner(RmHalspecOwner* );
445 NV_STATUS __nvoc_ctor_OBJTRACEABLE(OBJTRACEABLE* );
__nvoc_ctor_OBJGPU(OBJGPU * pThis,NvU32 arg_gpuInstance,NvU32 arg_gpuId,NvUuid * arg_pUuid)446 NV_STATUS __nvoc_ctor_OBJGPU(OBJGPU *pThis, NvU32 arg_gpuInstance, NvU32 arg_gpuId, NvUuid * arg_pUuid) {
447 NV_STATUS status = NV_OK;
448 status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object);
449 if (status != NV_OK) goto __nvoc_ctor_OBJGPU_fail_Object;
450 status = __nvoc_ctor_RmHalspecOwner(&pThis->__nvoc_base_RmHalspecOwner);
451 if (status != NV_OK) goto __nvoc_ctor_OBJGPU_fail_RmHalspecOwner;
452 status = __nvoc_ctor_OBJTRACEABLE(&pThis->__nvoc_base_OBJTRACEABLE);
453 if (status != NV_OK) goto __nvoc_ctor_OBJGPU_fail_OBJTRACEABLE;
454 __nvoc_init_dataField_OBJGPU(pThis);
455
456 status = __nvoc_gpuConstruct(pThis, arg_gpuInstance, arg_gpuId, arg_pUuid);
457 if (status != NV_OK) goto __nvoc_ctor_OBJGPU_fail__init;
458 goto __nvoc_ctor_OBJGPU_exit; // Success
459
460 __nvoc_ctor_OBJGPU_fail__init:
461 __nvoc_dtor_OBJTRACEABLE(&pThis->__nvoc_base_OBJTRACEABLE);
462 __nvoc_ctor_OBJGPU_fail_OBJTRACEABLE:
463 __nvoc_dtor_RmHalspecOwner(&pThis->__nvoc_base_RmHalspecOwner);
464 __nvoc_ctor_OBJGPU_fail_RmHalspecOwner:
465 __nvoc_dtor_Object(&pThis->__nvoc_base_Object);
466 __nvoc_ctor_OBJGPU_fail_Object:
467 __nvoc_ctor_OBJGPU_exit:
468
469 return status;
470 }
471
__nvoc_init_funcTable_OBJGPU_1(OBJGPU * pThis)472 static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) {
473 ChipHal *chipHal = &staticCast(pThis, RmHalspecOwner)->chipHal;
474 const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx;
475 RmVariantHal *rmVariantHal = &staticCast(pThis, RmHalspecOwner)->rmVariantHal;
476 const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
477 PORT_UNREFERENCED_VARIABLE(pThis);
478 PORT_UNREFERENCED_VARIABLE(chipHal);
479 PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx);
480 PORT_UNREFERENCED_VARIABLE(rmVariantHal);
481 PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
482
483 // Hal function -- gpuConstructDeviceInfoTable
484 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
485 {
486 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
487 {
488 pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_VGPUSTUB;
489 }
490 else
491 {
492 pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_FWCLIENT;
493 }
494 }
495 // default
496 else
497 {
498 pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_56cd7a;
499 }
500
501 // Hal function -- gpuGetNameString
502 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
503 {
504 pThis->__gpuGetNameString__ = &gpuGetNameString_VGPUSTUB;
505 }
506 else
507 {
508 pThis->__gpuGetNameString__ = &gpuGetNameString_KERNEL;
509 }
510
511 // Hal function -- gpuGetShortNameString
512 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
513 {
514 pThis->__gpuGetShortNameString__ = &gpuGetShortNameString_VGPUSTUB;
515 }
516 else
517 {
518 pThis->__gpuGetShortNameString__ = &gpuGetShortNameString_KERNEL;
519 }
520
521 // Hal function -- gpuInitBranding
522 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
523 {
524 pThis->__gpuInitBranding__ = &gpuInitBranding_VGPUSTUB;
525 }
526 else
527 {
528 pThis->__gpuInitBranding__ = &gpuInitBranding_FWCLIENT;
529 }
530
531 // Hal function -- gpuInitProperties
532 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
533 {
534 pThis->__gpuInitProperties__ = &gpuInitProperties_b3696a;
535 }
536 else
537 {
538 pThis->__gpuInitProperties__ = &gpuInitProperties_FWCLIENT;
539 }
540
541 // Hal function -- gpuBuildKernelVideoEngineList
542 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
543 {
544 pThis->__gpuBuildKernelVideoEngineList__ = &gpuBuildKernelVideoEngineList_56cd7a;
545 }
546 else
547 {
548 pThis->__gpuBuildKernelVideoEngineList__ = &gpuBuildKernelVideoEngineList_IMPL;
549 }
550
551 // Hal function -- gpuInitVideoLogging
552 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
553 {
554 pThis->__gpuInitVideoLogging__ = &gpuInitVideoLogging_56cd7a;
555 }
556 else
557 {
558 pThis->__gpuInitVideoLogging__ = &gpuInitVideoLogging_IMPL;
559 }
560
561 // Hal function -- gpuFreeVideoLogging
562 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
563 {
564 pThis->__gpuFreeVideoLogging__ = &gpuFreeVideoLogging_b3696a;
565 }
566 else
567 {
568 pThis->__gpuFreeVideoLogging__ = &gpuFreeVideoLogging_IMPL;
569 }
570
571 // Hal function -- gpuDestroyKernelVideoEngineList
572 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
573 {
574 pThis->__gpuDestroyKernelVideoEngineList__ = &gpuDestroyKernelVideoEngineList_b3696a;
575 }
576 else
577 {
578 pThis->__gpuDestroyKernelVideoEngineList__ = &gpuDestroyKernelVideoEngineList_IMPL;
579 }
580
581 // Hal function -- gpuPowerOff
582 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
583 {
584 pThis->__gpuPowerOff__ = &gpuPowerOff_46f6a7;
585 }
586 else
587 {
588 pThis->__gpuPowerOff__ = &gpuPowerOff_KERNEL;
589 }
590
591 // Hal function -- gpuWriteBusConfigReg
592 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
593 {
594 pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GH100;
595 }
596 else
597 {
598 pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GM107;
599 }
600
601 // Hal function -- gpuReadBusConfigReg
602 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
603 {
604 pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GH100;
605 }
606 else
607 {
608 pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GM107;
609 }
610
611 // Hal function -- gpuReadBusConfigRegEx
612 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
613 {
614 pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_5baef9;
615 }
616 else
617 {
618 pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_GM107;
619 }
620
621 // Hal function -- gpuReadFunctionConfigReg
622 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
623 {
624 pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_5baef9;
625 }
626 else
627 {
628 pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_GM107;
629 }
630
631 // Hal function -- gpuWriteFunctionConfigReg
632 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
633 {
634 pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_5baef9;
635 }
636 else
637 {
638 pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_GM107;
639 }
640
641 // Hal function -- gpuWriteFunctionConfigRegEx
642 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
643 {
644 pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_5baef9;
645 }
646 else
647 {
648 pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_GM107;
649 }
650
651 // Hal function -- gpuReadVgpuConfigReg
652 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
653 {
654 pThis->__gpuReadVgpuConfigReg__ = &gpuReadVgpuConfigReg_GH100;
655 }
656 // default
657 else
658 {
659 pThis->__gpuReadVgpuConfigReg__ = &gpuReadVgpuConfigReg_46f6a7;
660 }
661
662 // Hal function -- gpuGetIdInfo
663 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
664 {
665 pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GH100;
666 }
667 else
668 {
669 pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GM107;
670 }
671
672 // Hal function -- gpuGenGidData
673 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
674 {
675 pThis->__gpuGenGidData__ = &gpuGenGidData_VGPUSTUB;
676 }
677 else
678 {
679 pThis->__gpuGenGidData__ = &gpuGenGidData_FWCLIENT;
680 }
681
682 // Hal function -- gpuGetChipSubRev
683 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
684 {
685 pThis->__gpuGetChipSubRev__ = &gpuGetChipSubRev_4a4dee;
686 }
687 else
688 {
689 pThis->__gpuGetChipSubRev__ = &gpuGetChipSubRev_FWCLIENT;
690 }
691
692 // Hal function -- gpuGetSkuInfo
693 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
694 {
695 pThis->__gpuGetSkuInfo__ = &gpuGetSkuInfo_VGPUSTUB;
696 }
697 else
698 {
699 pThis->__gpuGetSkuInfo__ = &gpuGetSkuInfo_92bfc3;
700 }
701
702 // Hal function -- gpuGetRegBaseOffset
703 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
704 {
705 pThis->__gpuGetRegBaseOffset__ = &gpuGetRegBaseOffset_TU102;
706 }
707 else
708 {
709 pThis->__gpuGetRegBaseOffset__ = &gpuGetRegBaseOffset_FWCLIENT;
710 }
711
712 // Hal function -- gpuHandleSanityCheckRegReadError
713 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
714 {
715 pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GH100;
716 }
717 else
718 {
719 pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GM107;
720 }
721
722 // Hal function -- gpuHandleSecFault
723 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
724 {
725 pThis->__gpuHandleSecFault__ = &gpuHandleSecFault_GH100;
726 }
727 // default
728 else
729 {
730 pThis->__gpuHandleSecFault__ = &gpuHandleSecFault_b3696a;
731 }
732
733 // Hal function -- gpuSanityCheckVirtRegAccess
734 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
735 {
736 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
737 {
738 pThis->__gpuSanityCheckVirtRegAccess__ = &gpuSanityCheckVirtRegAccess_GH100;
739 }
740 else
741 {
742 pThis->__gpuSanityCheckVirtRegAccess__ = &gpuSanityCheckVirtRegAccess_TU102;
743 }
744 }
745 else
746 {
747 pThis->__gpuSanityCheckVirtRegAccess__ = &gpuSanityCheckVirtRegAccess_56cd7a;
748 }
749
750 // Hal function -- gpuGetChildrenPresent
751 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000040UL) )) /* ChipHal: TU104 */
752 {
753 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU104;
754 }
755 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000080UL) )) /* ChipHal: TU106 */
756 {
757 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU106;
758 }
759 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */
760 {
761 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GA100;
762 }
763 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
764 {
765 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GH100;
766 }
767 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000320UL) )) /* ChipHal: TU102 | TU116 | TU117 */
768 {
769 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU102;
770 }
771 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */
772 {
773 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GA102;
774 }
775 else
776 {
777 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_AD102;
778 }
779
780 // Hal function -- gpuGetClassDescriptorList
781 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000040UL) )) /* ChipHal: TU104 */
782 {
783 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU104;
784 }
785 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000080UL) )) /* ChipHal: TU106 */
786 {
787 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU106;
788 }
789 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000200UL) )) /* ChipHal: TU117 */
790 {
791 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU117;
792 }
793 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */
794 {
795 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GA100;
796 }
797 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
798 {
799 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GH100;
800 }
801 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000120UL) )) /* ChipHal: TU102 | TU116 */
802 {
803 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU102;
804 }
805 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */
806 {
807 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GA102;
808 }
809 else
810 {
811 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_AD102;
812 }
813
814 // Hal function -- gpuGetPhysAddrWidth
815 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
816 {
817 pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_GH100;
818 }
819 else
820 {
821 pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_TU102;
822 }
823
824 // Hal function -- gpuInitSriov
825 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
826 {
827 pThis->__gpuInitSriov__ = &gpuInitSriov_VGPUSTUB;
828 }
829 else
830 {
831 pThis->__gpuInitSriov__ = &gpuInitSriov_FWCLIENT;
832 }
833
834 // Hal function -- gpuDeinitSriov
835 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
836 {
837 pThis->__gpuDeinitSriov__ = &gpuDeinitSriov_56cd7a;
838 }
839 else
840 {
841 pThis->__gpuDeinitSriov__ = &gpuDeinitSriov_FWCLIENT;
842 }
843
844 // Hal function -- gpuCreateDefaultClientShare
845 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
846 {
847 pThis->__gpuCreateDefaultClientShare__ = &gpuCreateDefaultClientShare_VGPUSTUB;
848 }
849 else
850 {
851 pThis->__gpuCreateDefaultClientShare__ = &gpuCreateDefaultClientShare_56cd7a;
852 }
853
854 // Hal function -- gpuDestroyDefaultClientShare
855 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
856 {
857 pThis->__gpuDestroyDefaultClientShare__ = &gpuDestroyDefaultClientShare_VGPUSTUB;
858 }
859 else
860 {
861 pThis->__gpuDestroyDefaultClientShare__ = &gpuDestroyDefaultClientShare_b3696a;
862 }
863
864 // Hal function -- gpuGetVmmuSegmentSize
865 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
866 {
867 pThis->__gpuGetVmmuSegmentSize__ = &gpuGetVmmuSegmentSize_13cd8d;
868 }
869 else
870 {
871 pThis->__gpuGetVmmuSegmentSize__ = &gpuGetVmmuSegmentSize_72c522;
872 }
873
874 // Hal function -- gpuFuseSupportsDisplay
875 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */
876 {
877 pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_491d52;
878 }
879 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
880 {
881 pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GM107;
882 }
883 else
884 {
885 pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GA100;
886 }
887
888 // Hal function -- gpuGetActiveFBIOs
889 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
890 {
891 pThis->__gpuGetActiveFBIOs__ = &gpuGetActiveFBIOs_VGPUSTUB;
892 }
893 else
894 {
895 pThis->__gpuGetActiveFBIOs__ = &gpuGetActiveFBIOs_FWCLIENT;
896 }
897
898 // Hal function -- gpuCheckPageRetirementSupport
899 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
900 {
901 pThis->__gpuCheckPageRetirementSupport__ = &gpuCheckPageRetirementSupport_VGPUSTUB;
902 }
903 else
904 {
905 pThis->__gpuCheckPageRetirementSupport__ = &gpuCheckPageRetirementSupport_GSPCLIENT;
906 }
907
908 // Hal function -- gpuIsInternalSku
909 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
910 {
911 pThis->__gpuIsInternalSku__ = &gpuIsInternalSku_491d52;
912 }
913 else
914 {
915 pThis->__gpuIsInternalSku__ = &gpuIsInternalSku_FWCLIENT;
916 }
917
918 // Hal function -- gpuClearFbhubPoisonIntrForBug2924523
919 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */
920 {
921 pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_GA100;
922 }
923 // default
924 else
925 {
926 pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_56cd7a;
927 }
928
929 // Hal function -- gpuCheckIfFbhubPoisonIntrPending
930 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */
931 {
932 pThis->__gpuCheckIfFbhubPoisonIntrPending__ = &gpuCheckIfFbhubPoisonIntrPending_GA100;
933 }
934 // default
935 else
936 {
937 pThis->__gpuCheckIfFbhubPoisonIntrPending__ = &gpuCheckIfFbhubPoisonIntrPending_491d52;
938 }
939
940 // Hal function -- gpuGetSriovCaps
941 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
942 {
943 pThis->__gpuGetSriovCaps__ = &gpuGetSriovCaps_46f6a7;
944 }
945 else
946 {
947 pThis->__gpuGetSriovCaps__ = &gpuGetSriovCaps_TU102;
948 }
949
950 // Hal function -- gpuCheckIsP2PAllocated
951 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
952 {
953 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
954 {
955 pThis->__gpuCheckIsP2PAllocated__ = &gpuCheckIsP2PAllocated_108313;
956 }
957 else
958 {
959 pThis->__gpuCheckIsP2PAllocated__ = &gpuCheckIsP2PAllocated_GA100;
960 }
961 }
962 else
963 {
964 pThis->__gpuCheckIsP2PAllocated__ = &gpuCheckIsP2PAllocated_491d52;
965 }
966
967 // Hal function -- gpuPrePowerOff
968 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
969 {
970 pThis->__gpuPrePowerOff__ = &gpuPrePowerOff_46f6a7;
971 }
972 else
973 {
974 pThis->__gpuPrePowerOff__ = &gpuPrePowerOff_56cd7a;
975 }
976
977 // Hal function -- gpuVerifyExistence
978 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
979 {
980 pThis->__gpuVerifyExistence__ = &gpuVerifyExistence_56cd7a;
981 }
982 else
983 {
984 pThis->__gpuVerifyExistence__ = &gpuVerifyExistence_IMPL;
985 }
986
987 // Hal function -- gpuGetFlaVasSize
988 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
989 {
990 pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GH100;
991 }
992 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
993 {
994 pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_474d46;
995 }
996 else
997 {
998 pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GA100;
999 }
1000
1001 // Hal function -- gpuIsAtsSupportedWithSmcMemPartitioning
1002 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
1003 {
1004 pThis->__gpuIsAtsSupportedWithSmcMemPartitioning__ = &gpuIsAtsSupportedWithSmcMemPartitioning_GH100;
1005 }
1006 // default
1007 else
1008 {
1009 pThis->__gpuIsAtsSupportedWithSmcMemPartitioning__ = &gpuIsAtsSupportedWithSmcMemPartitioning_491d52;
1010 }
1011
1012 // Hal function -- gpuIsGlobalPoisonFuseEnabled
1013 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
1014 {
1015 pThis->__gpuIsGlobalPoisonFuseEnabled__ = &gpuIsGlobalPoisonFuseEnabled_VGPUSTUB;
1016 }
1017 else
1018 {
1019 pThis->__gpuIsGlobalPoisonFuseEnabled__ = &gpuIsGlobalPoisonFuseEnabled_FWCLIENT;
1020 }
1021
1022 // Hal function -- gpuDetermineSelfHostedMode
1023 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
1024 {
1025 pThis->__gpuDetermineSelfHostedMode__ = &gpuDetermineSelfHostedMode_KERNEL_GH100;
1026 }
1027 // default
1028 else
1029 {
1030 pThis->__gpuDetermineSelfHostedMode__ = &gpuDetermineSelfHostedMode_b3696a;
1031 }
1032
1033 // Hal function -- gpuDetermineMIGSupport
1034 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
1035 {
1036 pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_b3696a;
1037 }
1038 else
1039 {
1040 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
1041 {
1042 pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_GH100;
1043 }
1044 // default
1045 else
1046 {
1047 pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_b3696a;
1048 }
1049 }
1050
1051 // Hal function -- gpuInitOptimusSettings
1052 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
1053 {
1054 pThis->__gpuInitOptimusSettings__ = &gpuInitOptimusSettings_56cd7a;
1055 }
1056 else
1057 {
1058 pThis->__gpuInitOptimusSettings__ = &gpuInitOptimusSettings_IMPL;
1059 }
1060
1061 // Hal function -- gpuDeinitOptimusSettings
1062 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
1063 {
1064 pThis->__gpuDeinitOptimusSettings__ = &gpuDeinitOptimusSettings_56cd7a;
1065 }
1066 else
1067 {
1068 pThis->__gpuDeinitOptimusSettings__ = &gpuDeinitOptimusSettings_IMPL;
1069 }
1070
1071 // Hal function -- gpuIsSliCapableWithoutDisplay
1072 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
1073 {
1074 pThis->__gpuIsSliCapableWithoutDisplay__ = &gpuIsSliCapableWithoutDisplay_cbe027;
1075 }
1076 // default
1077 else
1078 {
1079 pThis->__gpuIsSliCapableWithoutDisplay__ = &gpuIsSliCapableWithoutDisplay_491d52;
1080 }
1081
1082 // Hal function -- gpuIsCCEnabledInHw
1083 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
1084 {
1085 pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_491d52;
1086 }
1087 else
1088 {
1089 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
1090 {
1091 pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_GH100;
1092 }
1093 // default
1094 else
1095 {
1096 pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_491d52;
1097 }
1098 }
1099
1100 // Hal function -- gpuIsDevModeEnabledInHw
1101 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
1102 {
1103 pThis->__gpuIsDevModeEnabledInHw__ = &gpuIsDevModeEnabledInHw_GH100;
1104 }
1105 // default
1106 else
1107 {
1108 pThis->__gpuIsDevModeEnabledInHw__ = &gpuIsDevModeEnabledInHw_491d52;
1109 }
1110
1111 // Hal function -- gpuIsProtectedPcieEnabledInHw
1112 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
1113 {
1114 pThis->__gpuIsProtectedPcieEnabledInHw__ = &gpuIsProtectedPcieEnabledInHw_GH100;
1115 }
1116 // default
1117 else
1118 {
1119 pThis->__gpuIsProtectedPcieEnabledInHw__ = &gpuIsProtectedPcieEnabledInHw_491d52;
1120 }
1121
1122 // Hal function -- gpuIsCtxBufAllocInPmaSupported
1123 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
1124 {
1125 pThis->__gpuIsCtxBufAllocInPmaSupported__ = &gpuIsCtxBufAllocInPmaSupported_GA100;
1126 }
1127 // default
1128 else
1129 {
1130 pThis->__gpuIsCtxBufAllocInPmaSupported__ = &gpuIsCtxBufAllocInPmaSupported_491d52;
1131 }
1132
1133 // Hal function -- gpuUpdateErrorContainmentState
1134 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
1135 {
1136 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
1137 {
1138 pThis->__gpuUpdateErrorContainmentState__ = &gpuUpdateErrorContainmentState_f91eed;
1139 }
1140 else
1141 {
1142 pThis->__gpuUpdateErrorContainmentState__ = &gpuUpdateErrorContainmentState_GA100;
1143 }
1144 }
1145 else
1146 {
1147 pThis->__gpuUpdateErrorContainmentState__ = &gpuUpdateErrorContainmentState_c04480;
1148 }
1149
1150 // Hal function -- gpuWaitForGfwBootComplete
1151 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
1152 {
1153 pThis->__gpuWaitForGfwBootComplete__ = &gpuWaitForGfwBootComplete_5baef9;
1154 }
1155 else
1156 {
1157 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */
1158 {
1159 pThis->__gpuWaitForGfwBootComplete__ = &gpuWaitForGfwBootComplete_TU102;
1160 }
1161 // default
1162 else
1163 {
1164 pThis->__gpuWaitForGfwBootComplete__ = &gpuWaitForGfwBootComplete_5baef9;
1165 }
1166 }
1167
1168 // Hal function -- gpuGetIsCmpSku
1169 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
1170 {
1171 pThis->__gpuGetIsCmpSku__ = &gpuGetIsCmpSku_491d52;
1172 }
1173 else
1174 {
1175 pThis->__gpuGetIsCmpSku__ = &gpuGetIsCmpSku_ceaee8;
1176 }
1177 }
1178
__nvoc_init_funcTable_OBJGPU(OBJGPU * pThis)1179 void __nvoc_init_funcTable_OBJGPU(OBJGPU *pThis) {
1180 __nvoc_init_funcTable_OBJGPU_1(pThis);
1181 }
1182
1183 void __nvoc_init_Object(Object*);
1184 void __nvoc_init_RmHalspecOwner(RmHalspecOwner*, NvU32, NvU32, NvU32, RM_RUNTIME_VARIANT, TEGRA_CHIP_TYPE, NvU32);
1185 void __nvoc_init_OBJTRACEABLE(OBJTRACEABLE*);
__nvoc_init_OBJGPU(OBJGPU * pThis,NvU32 ChipHal_arch,NvU32 ChipHal_impl,NvU32 ChipHal_hidrev,RM_RUNTIME_VARIANT RmVariantHal_rmVariant,TEGRA_CHIP_TYPE TegraChipHal_tegraType,NvU32 DispIpHal_ipver)1186 void __nvoc_init_OBJGPU(OBJGPU *pThis,
1187 NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev,
1188 RM_RUNTIME_VARIANT RmVariantHal_rmVariant,
1189 TEGRA_CHIP_TYPE TegraChipHal_tegraType,
1190 NvU32 DispIpHal_ipver) {
1191 pThis->__nvoc_pbase_OBJGPU = pThis;
1192 pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object;
1193 pThis->__nvoc_pbase_RmHalspecOwner = &pThis->__nvoc_base_RmHalspecOwner;
1194 pThis->__nvoc_pbase_OBJTRACEABLE = &pThis->__nvoc_base_OBJTRACEABLE;
1195 __nvoc_init_Object(&pThis->__nvoc_base_Object);
1196 __nvoc_init_RmHalspecOwner(&pThis->__nvoc_base_RmHalspecOwner, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver);
1197 __nvoc_init_OBJTRACEABLE(&pThis->__nvoc_base_OBJTRACEABLE);
1198 __nvoc_init_funcTable_OBJGPU(pThis);
1199 }
1200
__nvoc_objCreate_OBJGPU(OBJGPU ** ppThis,Dynamic * pParent,NvU32 createFlags,NvU32 ChipHal_arch,NvU32 ChipHal_impl,NvU32 ChipHal_hidrev,RM_RUNTIME_VARIANT RmVariantHal_rmVariant,TEGRA_CHIP_TYPE TegraChipHal_tegraType,NvU32 DispIpHal_ipver,NvU32 arg_gpuInstance,NvU32 arg_gpuId,NvUuid * arg_pUuid)1201 NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU32 createFlags,
1202 NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev,
1203 RM_RUNTIME_VARIANT RmVariantHal_rmVariant,
1204 TEGRA_CHIP_TYPE TegraChipHal_tegraType,
1205 NvU32 DispIpHal_ipver, NvU32 arg_gpuInstance, NvU32 arg_gpuId, NvUuid * arg_pUuid)
1206 {
1207 NV_STATUS status;
1208 Object *pParentObj = NULL;
1209 OBJGPU *pThis;
1210
1211 // Assign `pThis`, allocating memory unless suppressed by flag.
1212 status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPU), (void**)&pThis, (void**)ppThis);
1213 if (status != NV_OK)
1214 return status;
1215
1216 // Zero is the initial value for everything.
1217 portMemSet(pThis, 0, sizeof(OBJGPU));
1218
1219 // Initialize runtime type information.
1220 __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPU);
1221
1222 pThis->__nvoc_base_Object.createFlags = createFlags;
1223
1224 // Link the child into the parent if there is one unless flagged not to do so.
1225 if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY))
1226 {
1227 pParentObj = dynamicCast(pParent, Object);
1228 objAddChild(pParentObj, &pThis->__nvoc_base_Object);
1229 }
1230 else
1231 {
1232 pThis->__nvoc_base_Object.pParent = NULL;
1233 }
1234
1235 __nvoc_init_OBJGPU(pThis, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver);
1236 status = __nvoc_ctor_OBJGPU(pThis, arg_gpuInstance, arg_gpuId, arg_pUuid);
1237 if (status != NV_OK) goto __nvoc_objCreate_OBJGPU_cleanup;
1238
1239 // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set.
1240 *ppThis = pThis;
1241
1242 return NV_OK;
1243
1244 __nvoc_objCreate_OBJGPU_cleanup:
1245
1246 // Unlink the child from the parent if it was linked above.
1247 if (pParentObj != NULL)
1248 objRemoveChild(pParentObj, &pThis->__nvoc_base_Object);
1249
1250 // Do not call destructors here since the constructor already called them.
1251 if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT)
1252 portMemSet(pThis, 0, sizeof(OBJGPU));
1253 else
1254 {
1255 portMemFree(pThis);
1256 *ppThis = NULL;
1257 }
1258
1259 // coverity[leaked_storage:FALSE]
1260 return status;
1261 }
1262
__nvoc_objCreateDynamic_OBJGPU(OBJGPU ** ppThis,Dynamic * pParent,NvU32 createFlags,va_list args)1263 NV_STATUS __nvoc_objCreateDynamic_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) {
1264 NV_STATUS status;
1265 NvU32 ChipHal_arch = va_arg(args, NvU32);
1266 NvU32 ChipHal_impl = va_arg(args, NvU32);
1267 NvU32 ChipHal_hidrev = va_arg(args, NvU32);
1268 RM_RUNTIME_VARIANT RmVariantHal_rmVariant = va_arg(args, RM_RUNTIME_VARIANT);
1269 TEGRA_CHIP_TYPE TegraChipHal_tegraType = va_arg(args, TEGRA_CHIP_TYPE);
1270 NvU32 DispIpHal_ipver = va_arg(args, NvU32);
1271 NvU32 arg_gpuInstance = va_arg(args, NvU32);
1272 NvU32 arg_gpuId = va_arg(args, NvU32);
1273 NvUuid * arg_pUuid = va_arg(args, NvUuid *);
1274
1275 status = __nvoc_objCreate_OBJGPU(ppThis, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver, arg_gpuInstance, arg_gpuId, arg_pUuid);
1276
1277 return status;
1278 }
1279
1280