1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /***************************************************************************\ 25 |* *| 26 |* NV Architecture Interface *| 27 |* *| 28 |* <nvos.h> defines the Operating System function and ioctl interfaces to *| 29 |* NVIDIA's Unified Media Architecture (TM). *| 30 |* *| 31 \***************************************************************************/ 32 33 #ifndef NVOS_INCLUDED 34 #define NVOS_INCLUDED 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #include "nvstatus.h" 40 41 #include "nvgputypes.h" 42 #include "rs_access.h" 43 #include "nvcfg_sdk.h" 44 45 46 // Temporary include. Please include this directly instead of nvos.h 47 #include "alloc/alloc_channel.h" 48 49 /* local defines here */ 50 #define FILE_DEVICE_NV 0x00008000 51 #define NV_IOCTL_FCT_BASE 0x00000800 52 53 // This is the maximum number of subdevices supported in an SLI 54 // configuration. 55 #define NVOS_MAX_SUBDEVICES 8 56 57 /* Define to indicate the use of Unified status codes - bug 200043705*/ 58 #define UNIFIED_NV_STATUS 1 59 60 /***************************************************************************\ 61 |* NV OS Functions *| 62 \***************************************************************************/ 63 64 /* 65 Result codes for RM APIs, shared for all the APIs 66 67 *** IMPORTANT *** 68 69 Ensure that no NVOS_STATUS value has the highest bit set. That bit 70 is used to passthrough the NVOS_STATUS on code expecting an RM_STATUS. 71 */ 72 #define NVOS_STATUS NV_STATUS 73 74 #define NVOS_STATUS_SUCCESS NV_OK 75 #define NVOS_STATUS_ERROR_CARD_NOT_PRESENT NV_ERR_CARD_NOT_PRESENT 76 #define NVOS_STATUS_ERROR_DUAL_LINK_INUSE NV_ERR_DUAL_LINK_INUSE 77 #define NVOS_STATUS_ERROR_GENERIC NV_ERR_GENERIC 78 #define NVOS_STATUS_ERROR_GPU_NOT_FULL_POWER NV_ERR_GPU_NOT_FULL_POWER 79 #define NVOS_STATUS_ERROR_ILLEGAL_ACTION NV_ERR_ILLEGAL_ACTION 80 #define NVOS_STATUS_ERROR_IN_USE NV_ERR_STATE_IN_USE 81 #define NVOS_STATUS_ERROR_INSUFFICIENT_RESOURCES NV_ERR_INSUFFICIENT_RESOURCES 82 #define NVOS_STATUS_ERROR_INVALID_ACCESS_TYPE NV_ERR_INVALID_ACCESS_TYPE 83 #define NVOS_STATUS_ERROR_INVALID_ARGUMENT NV_ERR_INVALID_ARGUMENT 84 #define NVOS_STATUS_ERROR_INVALID_BASE NV_ERR_INVALID_BASE 85 #define NVOS_STATUS_ERROR_INVALID_CHANNEL NV_ERR_INVALID_CHANNEL 86 #define NVOS_STATUS_ERROR_INVALID_CLASS NV_ERR_INVALID_CLASS 87 #define NVOS_STATUS_ERROR_INVALID_CLIENT NV_ERR_INVALID_CLIENT 88 #define NVOS_STATUS_ERROR_INVALID_COMMAND NV_ERR_INVALID_COMMAND 89 #define NVOS_STATUS_ERROR_INVALID_DATA NV_ERR_INVALID_DATA 90 #define NVOS_STATUS_ERROR_INVALID_DEVICE NV_ERR_INVALID_DEVICE 91 #define NVOS_STATUS_ERROR_INVALID_DMA_SPECIFIER NV_ERR_INVALID_DMA_SPECIFIER 92 #define NVOS_STATUS_ERROR_INVALID_EVENT NV_ERR_INVALID_EVENT 93 #define NVOS_STATUS_ERROR_INVALID_FLAGS NV_ERR_INVALID_FLAGS 94 #define NVOS_STATUS_ERROR_INVALID_FUNCTION NV_ERR_INVALID_FUNCTION 95 #define NVOS_STATUS_ERROR_INVALID_HEAP NV_ERR_INVALID_HEAP 96 #define NVOS_STATUS_ERROR_INVALID_INDEX NV_ERR_INVALID_INDEX 97 #define NVOS_STATUS_ERROR_INVALID_LIMIT NV_ERR_INVALID_LIMIT 98 #define NVOS_STATUS_ERROR_INVALID_METHOD NV_ERR_INVALID_METHOD 99 #define NVOS_STATUS_ERROR_INVALID_OBJECT_BUFFER NV_ERR_BUFFER_TOO_SMALL 100 #define NVOS_STATUS_ERROR_INVALID_OBJECT_ERROR NV_ERR_INVALID_OBJECT 101 #define NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE NV_ERR_INVALID_OBJECT_HANDLE 102 #define NVOS_STATUS_ERROR_INVALID_OBJECT_NEW NV_ERR_INVALID_OBJECT_NEW 103 #define NVOS_STATUS_ERROR_INVALID_OBJECT_OLD NV_ERR_INVALID_OBJECT_OLD 104 #define NVOS_STATUS_ERROR_INVALID_OBJECT_PARENT NV_ERR_INVALID_OBJECT_PARENT 105 #define NVOS_STATUS_ERROR_INVALID_OFFSET NV_ERR_INVALID_OFFSET 106 #define NVOS_STATUS_ERROR_INVALID_OWNER NV_ERR_INVALID_OWNER 107 #define NVOS_STATUS_ERROR_INVALID_PARAM_STRUCT NV_ERR_INVALID_PARAM_STRUCT 108 #define NVOS_STATUS_ERROR_INVALID_PARAMETER NV_ERR_INVALID_PARAMETER 109 #define NVOS_STATUS_ERROR_INVALID_POINTER NV_ERR_INVALID_POINTER 110 #define NVOS_STATUS_ERROR_INVALID_REGISTRY_KEY NV_ERR_INVALID_REGISTRY_KEY 111 #define NVOS_STATUS_ERROR_INVALID_STATE NV_ERR_INVALID_STATE 112 #define NVOS_STATUS_ERROR_INVALID_STRING_LENGTH NV_ERR_INVALID_STRING_LENGTH 113 #define NVOS_STATUS_ERROR_INVALID_XLATE NV_ERR_INVALID_XLATE 114 #define NVOS_STATUS_ERROR_IRQ_NOT_FIRING NV_ERR_IRQ_NOT_FIRING 115 #define NVOS_STATUS_ERROR_MULTIPLE_MEMORY_TYPES NV_ERR_MULTIPLE_MEMORY_TYPES 116 #define NVOS_STATUS_ERROR_NOT_SUPPORTED NV_ERR_NOT_SUPPORTED 117 #define NVOS_STATUS_ERROR_OPERATING_SYSTEM NV_ERR_OPERATING_SYSTEM 118 #define NVOS_STATUS_ERROR_LIB_RM_VERSION_MISMATCH NV_ERR_LIB_RM_VERSION_MISMATCH 119 #define NVOS_STATUS_ERROR_PROTECTION_FAULT NV_ERR_PROTECTION_FAULT 120 #define NVOS_STATUS_ERROR_TIMEOUT NV_ERR_TIMEOUT 121 #define NVOS_STATUS_ERROR_TOO_MANY_PRIMARIES NV_ERR_TOO_MANY_PRIMARIES 122 #define NVOS_STATUS_ERROR_IRQ_EDGE_TRIGGERED NV_ERR_IRQ_EDGE_TRIGGERED 123 #define NVOS_STATUS_ERROR_INVALID_OPERATION NV_ERR_INVALID_OPERATION 124 #define NVOS_STATUS_ERROR_NOT_COMPATIBLE NV_ERR_NOT_COMPATIBLE 125 #define NVOS_STATUS_ERROR_MORE_PROCESSING_REQUIRED NV_WARN_MORE_PROCESSING_REQUIRED 126 #define NVOS_STATUS_ERROR_INSUFFICIENT_PERMISSIONS NV_ERR_INSUFFICIENT_PERMISSIONS 127 #define NVOS_STATUS_ERROR_TIMEOUT_RETRY NV_ERR_TIMEOUT_RETRY 128 #define NVOS_STATUS_ERROR_NOT_READY NV_ERR_NOT_READY 129 #define NVOS_STATUS_ERROR_GPU_IS_LOST NV_ERR_GPU_IS_LOST 130 #define NVOS_STATUS_ERROR_IN_FULLCHIP_RESET NV_ERR_GPU_IN_FULLCHIP_RESET 131 #define NVOS_STATUS_ERROR_INVALID_LOCK_STATE NV_ERR_INVALID_LOCK_STATE 132 #define NVOS_STATUS_ERROR_INVALID_ADDRESS NV_ERR_INVALID_ADDRESS 133 #define NVOS_STATUS_ERROR_INVALID_IRQ_LEVEL NV_ERR_INVALID_IRQ_LEVEL 134 #define NVOS_STATUS_ERROR_MEMORY_TRAINING_FAILED NV_ERR_MEMORY_TRAINING_FAILED 135 #define NVOS_STATUS_ERROR_BUSY_RETRY NV_ERR_BUSY_RETRY 136 #define NVOS_STATUS_ERROR_INSUFFICIENT_POWER NV_ERR_INSUFFICIENT_POWER 137 #define NVOS_STATUS_ERROR_OBJECT_NOT_FOUND NV_ERR_OBJECT_NOT_FOUND 138 #define NVOS_STATUS_ERROR_RESOURCE_LOST NV_ERR_RESOURCE_LOST 139 #define NVOS_STATUS_ERROR_BUFFER_TOO_SMALL NV_ERR_BUFFER_TOO_SMALL 140 #define NVOS_STATUS_ERROR_RESET_REQUIRED NV_ERR_RESET_REQUIRED 141 #define NVOS_STATUS_ERROR_INVALID_REQUEST NV_ERR_INVALID_REQUEST 142 143 #define NVOS_STATUS_ERROR_PRIV_SEC_VIOLATION NV_ERR_PRIV_SEC_VIOLATION 144 #define NVOS_STATUS_ERROR_GPU_IN_DEBUG_MODE NV_ERR_GPU_IN_DEBUG_MODE 145 #define NVOS_STATUS_ERROR_ALREADY_SIGNALLED NV_ERR_ALREADY_SIGNALLED 146 147 /* 148 Note: 149 This version of the architecture has been changed to allow the 150 RM to return a client handle that will subsequently used to 151 identify the client. NvAllocRoot() returns the handle. All 152 other functions must specify this client handle. 153 154 */ 155 /* macro NV01_FREE */ 156 #define NV01_FREE (0x00000000) 157 158 /* NT ioctl data structure */ 159 typedef struct 160 { 161 NvHandle hRoot; 162 NvHandle hObjectParent; 163 NvHandle hObjectOld; 164 NvV32 status; 165 } NVOS00_PARAMETERS; 166 167 /* valid hClass values. */ 168 #define NV01_ROOT (0x0U) 169 // 170 // Redefining it here to maintain consistency with current code 171 // This is also defined in class cl0001.h 172 // 173 #define NV01_ROOT_NON_PRIV (0x00000001) 174 175 // Deprecated, please use NV01_ROOT_CLIENT 176 #define NV01_ROOT_USER NV01_ROOT_CLIENT 177 178 // 179 // This will eventually replace NV01_ROOT_USER in RM client code. Please use this 180 // RM client object type for any new RM client object allocations that are being 181 // added. 182 // 183 #define NV01_ROOT_CLIENT (0x00000041) 184 185 /* macro NV01_ALLOC_MEMORY */ 186 #define NV01_ALLOC_MEMORY (0x00000002) 187 188 /* parameter values */ 189 #define NVOS02_FLAGS_PHYSICALITY 7:4 190 #define NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS (0x00000000) 191 #define NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS (0x00000001) 192 #define NVOS02_FLAGS_LOCATION 11:8 193 #define NVOS02_FLAGS_LOCATION_PCI (0x00000000) 194 #define NVOS02_FLAGS_LOCATION_AGP (0x00000001) 195 #define NVOS02_FLAGS_LOCATION_VIDMEM (0x00000002) 196 #define NVOS02_FLAGS_COHERENCY 15:12 197 #define NVOS02_FLAGS_COHERENCY_UNCACHED (0x00000000) 198 #define NVOS02_FLAGS_COHERENCY_CACHED (0x00000001) 199 #define NVOS02_FLAGS_COHERENCY_WRITE_COMBINE (0x00000002) 200 #define NVOS02_FLAGS_COHERENCY_WRITE_THROUGH (0x00000003) 201 #define NVOS02_FLAGS_COHERENCY_WRITE_PROTECT (0x00000004) 202 #define NVOS02_FLAGS_COHERENCY_WRITE_BACK (0x00000005) 203 #define NVOS02_FLAGS_ALLOC 17:16 204 #define NVOS02_FLAGS_ALLOC_NONE (0x00000001) 205 #define NVOS02_FLAGS_GPU_CACHEABLE 18:18 206 #define NVOS02_FLAGS_GPU_CACHEABLE_NO (0x00000000) 207 #define NVOS02_FLAGS_GPU_CACHEABLE_YES (0x00000001) 208 // If requested, RM will create a kernel mapping of this memory. 209 // Default is no map. 210 #define NVOS02_FLAGS_KERNEL_MAPPING 19:19 211 #define NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP (0x00000000) 212 #define NVOS02_FLAGS_KERNEL_MAPPING_MAP (0x00000001) 213 #define NVOS02_FLAGS_ALLOC_NISO_DISPLAY 20:20 214 #define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO (0x00000000) 215 #define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES (0x00000001) 216 217 // 218 // If the flag is set, the RM will only allow read-only CPU user mappings to the 219 // allocation. 220 // 221 #define NVOS02_FLAGS_ALLOC_USER_READ_ONLY 21:21 222 #define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO (0x00000000) 223 #define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES (0x00000001) 224 225 // 226 // If the flag is set, the RM will only allow read-only DMA mappings to the 227 // allocation. 228 // 229 #define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY 22:22 230 #define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO (0x00000000) 231 #define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES (0x00000001) 232 233 // 234 // If the flag is set, the IO memory allocation can be registered with the RM if 235 // the RM regkey peerMappingOverride is set or the client is privileged. 236 // 237 // See Bug 1630288 "[PeerSync] threat related to GPU.." for more details. 238 // 239 #define NVOS02_FLAGS_PEER_MAP_OVERRIDE 23:23 240 #define NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT (0x00000000) 241 #define NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED (0x00000001) 242 243 // If the flag is set RM will assume the memory pages are of type syncpoint. 244 #define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT 24:24 245 #define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE (0x00000001) 246 247 // 248 // Allow client allocations to go to protected/unprotected video/system memory. 249 // When Ampere Protected Model aka APM or Confidential Compute is enabled and 250 // DEFAULT flag is set by client, allocations go to protected memory. When 251 // protected memory is not enabled, allocations go to unprotected memory. 252 // If APM or CC is not enabled, it is a bug for a client to set the PROTECTED 253 // flag to YES 254 // 255 #define NVOS02_FLAGS_MEMORY_PROTECTION 26:25 256 #define NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT (0x00000000) 257 #define NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED (0x00000001) 258 #define NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED (0x00000002) 259 260 // 261 // If _NO_MAP is requested, the RM in supported platforms will not map the 262 // allocated system or IO memory into user space. The client can later map 263 // memory through the RmMapMemory() interface. 264 // If _NEVER_MAP is requested, the RM will never map the allocated system or 265 // IO memory into user space 266 // 267 #define NVOS02_FLAGS_MAPPING 31:30 268 #define NVOS02_FLAGS_MAPPING_DEFAULT (0x00000000) 269 #define NVOS02_FLAGS_MAPPING_NO_MAP (0x00000001) 270 #define NVOS02_FLAGS_MAPPING_NEVER_MAP (0x00000002) 271 272 // ------------------------------------------------------------------------------------- 273 274 /* parameters */ 275 typedef struct 276 { 277 NvHandle hRoot; 278 NvHandle hObjectParent; 279 NvHandle hObjectNew; 280 NvV32 hClass; 281 NvV32 flags; 282 NvP64 pMemory NV_ALIGN_BYTES(8); 283 NvU64 limit NV_ALIGN_BYTES(8); 284 NvV32 status; 285 } NVOS02_PARAMETERS; 286 287 /* parameter values */ 288 #define NVOS03_FLAGS_ACCESS 1:0 289 #define NVOS03_FLAGS_ACCESS_READ_WRITE (0x00000000) 290 #define NVOS03_FLAGS_ACCESS_READ_ONLY (0x00000001) 291 #define NVOS03_FLAGS_ACCESS_WRITE_ONLY (0x00000002) 292 293 #define NVOS03_FLAGS_PREALLOCATE 2:2 294 #define NVOS03_FLAGS_PREALLOCATE_DISABLE (0x00000000) 295 #define NVOS03_FLAGS_PREALLOCATE_ENABLE (0x00000001) 296 297 #define NVOS03_FLAGS_GPU_MAPPABLE 15:15 298 #define NVOS03_FLAGS_GPU_MAPPABLE_DISABLE (0x00000000) 299 #define NVOS03_FLAGS_GPU_MAPPABLE_ENABLE (0x00000001) 300 301 // ------------------------------------------------------------------------------------ 302 // This flag is required for a hack to be placed inside DD that allows it to 303 // access a dummy ctxdma as a block linear surface. Refer bug 1562766 for details. 304 // 305 // This flag is deprecated, use NVOS03_FLAGS_PTE_KIND. 306 // 307 #define NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE 16:16 308 #define NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_FALSE (0x00000000) 309 #define NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_TRUE (0x00000001) 310 311 /* 312 * This field allows to specify the page kind. If the page kind 313 * is not specified then the page kind associated with the memory will be used. 314 * 315 * In tegra display driver stack, the page kind remains unknown at the time 316 * of memory allocation/import, the page kind can only be known when display 317 * driver client creates a framebuffer from allocated/imported memory. 318 * 319 * This field compatible with NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE flag. 320 */ 321 #define NVOS03_FLAGS_PTE_KIND 17:16 322 #define NVOS03_FLAGS_PTE_KIND_NONE (0x00000000) 323 #define NVOS03_FLAGS_PTE_KIND_BL (0x00000001) 324 #define NVOS03_FLAGS_PTE_KIND_PITCH (0x00000002) 325 326 #define NVOS03_FLAGS_TYPE 23:20 327 #define NVOS03_FLAGS_TYPE_NOTIFIER (0x00000001) 328 329 /* 330 * This is an alias into the LSB of the TYPE field which 331 * actually indicates if a Kernel Mapping should be created. 332 * If the RM should have access to the memory then Enable this 333 * flag. 334 * 335 * Note that the NV_OS03_FLAGS_MAPPING is an alias to 336 * the LSB of the NV_OS03_FLAGS_TYPE. And in fact if 337 * type is NV_OS03_FLAGS_TYPE_NOTIFIER (bit 20 set) 338 * then it implicitly means that NV_OS03_FLAGS_MAPPING 339 * is _MAPPING_KERNEL. If the client wants to have a 340 * Kernel Mapping, it should use the _MAPPING_KERNEL 341 * flag set and the _TYPE_NOTIFIER should be used only 342 * with NOTIFIERS. 343 */ 344 345 #define NVOS03_FLAGS_MAPPING 20:20 346 #define NVOS03_FLAGS_MAPPING_NONE (0x00000000) 347 #define NVOS03_FLAGS_MAPPING_KERNEL (0x00000001) 348 349 #define NVOS03_FLAGS_CACHE_SNOOP 28:28 350 #define NVOS03_FLAGS_CACHE_SNOOP_ENABLE (0x00000000) 351 #define NVOS03_FLAGS_CACHE_SNOOP_DISABLE (0x00000001) 352 353 // HASH_TABLE:ENABLE means that the context DMA is automatically bound into all 354 // channels in the client. This can lead to excessive hash table usage. 355 // HASH_TABLE:DISABLE means that the context DMA must be explicitly bound into 356 // any channel that needs to use it via NvRmBindContextDma. 357 // HASH_TABLE:ENABLE is not supported on NV50 and up, and HASH_TABLE:DISABLE should 358 // be preferred for all new code. 359 #define NVOS03_FLAGS_HASH_TABLE 29:29 360 #define NVOS03_FLAGS_HASH_TABLE_ENABLE (0x00000000) 361 #define NVOS03_FLAGS_HASH_TABLE_DISABLE (0x00000001) 362 363 /* macro NV01_ALLOC_OBJECT */ 364 #define NV01_ALLOC_OBJECT (0x00000005) 365 366 /* parameters */ 367 typedef struct 368 { 369 NvHandle hRoot; 370 NvHandle hObjectParent; 371 NvHandle hObjectNew; 372 NvV32 hClass; 373 NvV32 status; 374 } NVOS05_PARAMETERS; 375 376 /* Valid values for hClass in Nv01AllocEvent */ 377 /* Note that NV01_EVENT_OS_EVENT is same as NV01_EVENT_WIN32_EVENT */ 378 /* TODO: delete the WIN32 name */ 379 #define NV01_EVENT_KERNEL_CALLBACK (0x00000078) 380 #define NV01_EVENT_OS_EVENT (0x00000079) 381 #define NV01_EVENT_WIN32_EVENT NV01_EVENT_OS_EVENT 382 #define NV01_EVENT_KERNEL_CALLBACK_EX (0x0000007E) 383 384 /* NOTE: NV01_EVENT_KERNEL_CALLBACK is deprecated. Please use NV01_EVENT_KERNEL_CALLBACK_EX. */ 385 /* For use with NV01_EVENT_KERNEL_CALLBACK. */ 386 /* NVOS10_EVENT_KERNEL_CALLBACK data structure storage needs to be retained by the caller. */ 387 typedef void (*Callback1ArgVoidReturn)(void *arg); 388 typedef void (*Callback5ArgVoidReturn)(void *arg1, void *arg2, NvHandle hEvent, NvU32 data, NvU32 status); 389 390 /* NOTE: the 'void* arg' below is ok (but unfortunate) since this interface 391 can only be used by other kernel drivers which must share the same ptr-size */ 392 typedef struct 393 { 394 Callback1ArgVoidReturn func; 395 void *arg; 396 } NVOS10_EVENT_KERNEL_CALLBACK; 397 398 /* For use with NV01_EVENT_KERNEL_CALLBACK_EX. */ 399 /* NVOS10_EVENT_KERNEL_CALLBACK_EX data structure storage needs to be retained by the caller. */ 400 /* NOTE: the 'void* arg' below is ok (but unfortunate) since this interface 401 can only be used by other kernel drivers which must share the same ptr-size */ 402 typedef struct 403 { 404 Callback5ArgVoidReturn func; 405 void *arg; 406 } NVOS10_EVENT_KERNEL_CALLBACK_EX; 407 408 /* Setting this bit in index will set the Event to a Broadcast type */ 409 /* i.e. each subdevice under a device needs to see the Event before it's signaled */ 410 #define NV01_EVENT_BROADCAST (0x80000000) 411 412 /* allow non-root resman client to create NV01_EVENT_KERNEL_CALLBACK events */ 413 /* -- this works in debug/develop drivers only (for security reasons)*/ 414 #define NV01_EVENT_PERMIT_NON_ROOT_EVENT_KERNEL_CALLBACK_CREATION (0x40000000) 415 416 /* RM event should be triggered only by the specified subdevice; see cl0005.h 417 * for details re: how to specify subdevice. */ 418 #define NV01_EVENT_SUBDEVICE_SPECIFIC (0x20000000) 419 420 /* RM should trigger the event but shouldn't do the book-keeping of data 421 * associated with that event */ 422 #define NV01_EVENT_WITHOUT_EVENT_DATA (0x10000000) 423 424 /* RM event should be triggered only by the non-stall interrupt */ 425 #define NV01_EVENT_NONSTALL_INTR (0x08000000) 426 427 /* RM event was allocated from client RM, post events back to client RM */ 428 #define NV01_EVENT_CLIENT_RM (0x04000000) 429 430 /* function OS19 */ 431 #define NV04_I2C_ACCESS (0x00000013) 432 433 #define NVOS_I2C_ACCESS_MAX_BUFFER_SIZE 2048 434 435 /* parameters */ 436 typedef struct 437 { 438 NvHandle hClient; 439 NvHandle hDevice; 440 NvU32 paramSize; 441 NvP64 paramStructPtr NV_ALIGN_BYTES(8); 442 NvV32 status; 443 } NVOS_I2C_ACCESS_PARAMS; 444 445 /* current values for command */ 446 #define NVOS20_COMMAND_unused0001 0x0001 447 #define NVOS20_COMMAND_unused0002 0x0002 448 #define NVOS20_COMMAND_STRING_PRINT 0x0003 449 450 /* function OS21 */ 451 #define NV04_ALLOC (0x00000015) 452 453 /* parameters */ 454 typedef struct 455 { 456 NvHandle hRoot; 457 NvHandle hObjectParent; 458 NvHandle hObjectNew; 459 NvV32 hClass; 460 NvP64 pAllocParms NV_ALIGN_BYTES(8); 461 NvU32 paramsSize; 462 NvV32 status; 463 } NVOS21_PARAMETERS; 464 465 #define NVOS64_FLAGS_NONE (0x00000000) 466 #define NVOS64_FLAGS_FINN_SERIALIZED (0x00000001) 467 468 /* New struct with rights requested */ 469 typedef struct 470 { 471 NvHandle hRoot; // [IN] client handle 472 NvHandle hObjectParent; // [IN] parent handle of new object 473 NvHandle hObjectNew; // [INOUT] new object handle, 0 to generate 474 NvV32 hClass; // [in] class num of new object 475 NvP64 pAllocParms NV_ALIGN_BYTES(8); // [IN] class-specific alloc parameters 476 NvP64 pRightsRequested NV_ALIGN_BYTES(8); // [IN] RS_ACCESS_MASK to request rights, or NULL 477 NvU32 paramsSize; // [IN] Size of alloc params 478 NvU32 flags; // [IN] flags for FINN serialization 479 NvV32 status; // [OUT] status 480 } NVOS64_PARAMETERS; 481 482 /* RM Alloc header 483 * 484 * Replacement for NVOS21/64_PARAMETERS where embedded pointers are not allowed. 485 * Input layout for RM Alloc user space calls should be 486 * 487 * +--- NVOS62_PARAMETERS ---+--- RM Alloc parameters ---+ 488 * +--- NVOS65_PARAMETERS ---+--- Rights Requested ---+--- RM Alloc parameters ---+ 489 * 490 * NVOS62_PARAMETERS::paramsSize is the size of RM Alloc parameters 491 * If NVOS65_PARAMETERS::maskSize is 0, Rights Requested will not be present in memory. 492 * 493 */ 494 typedef struct 495 { 496 NvHandle hRoot; // [IN] client handle 497 NvHandle hObjectParent; // [IN] parent handle of the new object 498 NvHandle hObjectNew; // [IN] new object handle 499 NvV32 hClass; // [IN] class num of the new object 500 NvU32 paramSize; // [IN] size in bytes of the RM alloc parameters 501 NvV32 status; // [OUT] status 502 } NVOS62_PARAMETERS; 503 504 #define NVOS65_PARAMETERS_VERSION_MAGIC 0x77FEF81E 505 506 typedef struct 507 { 508 NvHandle hRoot; // [IN] client handle 509 NvHandle hObjectParent; // [IN] parent handle of the new object 510 NvHandle hObjectNew; // [INOUT] new object handle, 0 to generate 511 NvV32 hClass; // [IN] class num of the new object 512 NvU32 paramSize; // [IN] size in bytes of the RM alloc parameters 513 NvU32 versionMagic; // [IN] NVOS65_PARAMETERS_VERISON_MAGIC 514 NvU32 maskSize; // [IN] size in bytes of access mask, or 0 if NULL 515 NvV32 status; // [OUT] status 516 } NVOS65_PARAMETERS; 517 518 /* function OS30 */ 519 #define NV04_IDLE_CHANNELS (0x0000001E) 520 521 /* parameter values */ 522 #define NVOS30_FLAGS_BEHAVIOR 3:0 523 #define NVOS30_FLAGS_BEHAVIOR_SPIN (0x00000000) 524 #define NVOS30_FLAGS_BEHAVIOR_SLEEP (0x00000001) 525 #define NVOS30_FLAGS_BEHAVIOR_QUERY (0x00000002) 526 #define NVOS30_FLAGS_BEHAVIOR_FORCE_BUSY_CHECK (0x00000003) 527 #define NVOS30_FLAGS_CHANNEL 7:4 528 #define NVOS30_FLAGS_CHANNEL_LIST (0x00000000) 529 #define NVOS30_FLAGS_CHANNEL_SINGLE (0x00000001) 530 #define NVOS30_FLAGS_IDLE 30:8 531 #define NVOS30_FLAGS_IDLE_PUSH_BUFFER (0x00000001) 532 #define NVOS30_FLAGS_IDLE_CACHE1 (0x00000002) 533 #define NVOS30_FLAGS_IDLE_GRAPHICS (0x00000004) 534 #define NVOS30_FLAGS_IDLE_MPEG (0x00000008) 535 #define NVOS30_FLAGS_IDLE_MOTION_ESTIMATION (0x00000010) 536 #define NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR (0x00000020) 537 #define NVOS30_FLAGS_IDLE_MSPDEC (0x00000020) 538 #define NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR (0x00000040) 539 #define NVOS30_FLAGS_IDLE_MSVLD (0x00000040) 540 #define NVOS30_FLAGS_IDLE_NVDEC0 NVOS30_FLAGS_IDLE_MSVLD 541 #define NVOS30_FLAGS_IDLE_CIPHER_DMA (0x00000080) 542 #define NVOS30_FLAGS_IDLE_SEC (0x00000080) 543 #define NVOS30_FLAGS_IDLE_CALLBACKS (0x00000100) 544 #define NVOS30_FLAGS_IDLE_MSPPP (0x00000200) 545 #define NVOS30_FLAGS_IDLE_CE0 (0x00000400) 546 #define NVOS30_FLAGS_IDLE_CE1 (0x00000800) 547 #define NVOS30_FLAGS_IDLE_CE2 (0x00001000) 548 #define NVOS30_FLAGS_IDLE_CE3 (0x00002000) 549 #define NVOS30_FLAGS_IDLE_CE4 (0x00004000) 550 #define NVOS30_FLAGS_IDLE_CE5 (0x00008000) 551 #define NVOS30_FLAGS_IDLE_VIC (0x00010000) 552 #define NVOS30_FLAGS_IDLE_MSENC (0x00020000) 553 #define NVOS30_FLAGS_IDLE_NVENC0 NVOS30_FLAGS_IDLE_MSENC 554 #define NVOS30_FLAGS_IDLE_NVENC1 (0x00040000) 555 #define NVOS30_FLAGS_IDLE_NVENC2 (0x00080000) 556 #define NVOS30_FLAGS_IDLE_NVJPG (0x00100000) 557 #define NVOS30_FLAGS_IDLE_NVDEC1 (0x00200000) 558 #define NVOS30_FLAGS_IDLE_NVDEC2 (0x00400000) 559 #define NVOS30_FLAGS_IDLE_ACTIVECHANNELS (0x00800000) 560 #define NVOS30_FLAGS_IDLE_ALL_ENGINES (NVOS30_FLAGS_IDLE_GRAPHICS | \ 561 NVOS30_FLAGS_IDLE_MPEG | \ 562 NVOS30_FLAGS_IDLE_MOTION_ESTIMATION | \ 563 NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR | \ 564 NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR | \ 565 NVOS30_FLAGS_IDLE_CIPHER_DMA | \ 566 NVOS30_FLAGS_IDLE_MSPDEC | \ 567 NVOS30_FLAGS_IDLE_NVDEC0 | \ 568 NVOS30_FLAGS_IDLE_SEC | \ 569 NVOS30_FLAGS_IDLE_MSPPP | \ 570 NVOS30_FLAGS_IDLE_CE0 | \ 571 NVOS30_FLAGS_IDLE_CE1 | \ 572 NVOS30_FLAGS_IDLE_CE2 | \ 573 NVOS30_FLAGS_IDLE_CE3 | \ 574 NVOS30_FLAGS_IDLE_CE4 | \ 575 NVOS30_FLAGS_IDLE_CE5 | \ 576 NVOS30_FLAGS_IDLE_NVENC0 | \ 577 NVOS30_FLAGS_IDLE_NVENC1 | \ 578 NVOS30_FLAGS_IDLE_NVENC2 | \ 579 NVOS30_FLAGS_IDLE_VIC | \ 580 NVOS30_FLAGS_IDLE_NVJPG | \ 581 NVOS30_FLAGS_IDLE_NVDEC1 | \ 582 NVOS30_FLAGS_IDLE_NVDEC2) 583 #define NVOS30_FLAGS_WAIT_FOR_ELPG_ON 31:31 584 #define NVOS30_FLAGS_WAIT_FOR_ELPG_ON_NO (0x00000000) 585 #define NVOS30_FLAGS_WAIT_FOR_ELPG_ON_YES (0x00000001) 586 587 /* parameters */ 588 typedef struct 589 { 590 NvHandle hClient; 591 NvHandle hDevice; 592 NvHandle hChannel; 593 NvV32 numChannels; 594 595 NvP64 phClients NV_ALIGN_BYTES(8); 596 NvP64 phDevices NV_ALIGN_BYTES(8); 597 NvP64 phChannels NV_ALIGN_BYTES(8); 598 599 NvV32 flags; 600 NvV32 timeout; 601 NvV32 status; 602 } NVOS30_PARAMETERS; 603 604 /* function OS32 */ 605 typedef void (*BindResultFunc)(void * pVoid, NvU32 gpuMask, NvU32 bState, NvU32 bResult); 606 607 #define NV04_VID_HEAP_CONTROL (0x00000020) 608 /************************************************************************* 609 ************************ New Heap Interface ****************************** 610 *************************************************************************/ 611 // NVOS32 Descriptor types 612 // 613 // NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR: The dma-buf object 614 // pointer, provided by the linux kernel buffer sharing sub-system. 615 // This descriptor can only be used by kernel space rm-clients. 616 // 617 #define NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS 0 618 #define NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY 1 619 #define NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY 2 620 #define NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR 3 621 #define NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE 4 622 #define NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR 5 623 #define NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR 6 624 #define NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS 7 625 // NVOS32 function 626 #define NVOS32_FUNCTION_ALLOC_SIZE 2 627 #define NVOS32_FUNCTION_FREE 3 628 // #define NVOS32_FUNCTION_HEAP_PURGE 4 629 #define NVOS32_FUNCTION_INFO 5 630 #define NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT 6 631 // #define NVOS32_FUNCTION_DESTROY 7 632 // #define NVOS32_FUNCTION_RETAIN 9 633 // #define NVOS32_FUNCTION_REALLOC 10 634 #define NVOS32_FUNCTION_DUMP 11 635 // #define NVOS32_FUNCTION_INFO_TYPE_ALLOC_BLOCKS 12 636 #define NVOS32_FUNCTION_ALLOC_SIZE_RANGE 14 637 #define NVOS32_FUNCTION_REACQUIRE_COMPR 15 638 #define NVOS32_FUNCTION_RELEASE_COMPR 16 639 // #define NVOS32_FUNCTION_MODIFY_DEFERRED_TILES 17 640 #define NVOS32_FUNCTION_GET_MEM_ALIGNMENT 18 641 #define NVOS32_FUNCTION_HW_ALLOC 19 642 #define NVOS32_FUNCTION_HW_FREE 20 643 // #define NVOS32_FUNCTION_SET_OFFSET 21 644 // #define NVOS32_FUNCTION_IS_TILED 22 645 // #define NVOS32_FUNCTION_ENABLE_RESOURCE 23 646 // #define NVOS32_FUNCTION_BIND_COMPR 24 647 #define NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR 27 648 649 typedef struct 650 { 651 NvP64 sgt NV_ALIGN_BYTES(8); 652 NvP64 gem NV_ALIGN_BYTES(8); 653 } NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS; 654 655 #define NVOS32_FLAGS_BLOCKINFO_VISIBILITY_CPU (0x00000001) 656 typedef struct 657 { 658 NvU64 startOffset NV_ALIGN_BYTES(8); 659 NvU64 size NV_ALIGN_BYTES(8); 660 NvU32 flags; 661 } NVOS32_BLOCKINFO; 662 663 // NVOS32 IVC-heap number delimiting value 664 #define NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP 0 // When IVC heaps are present, 665 // IVC-heap number specified 666 // as part of 'NVOS32_PARAMETERS' 667 // which is less or equal to this 668 // constant indicates that allocation 669 // should not be done on IVC heap. 670 // Explanation of IVC-heap number is 671 // under 'AllocSize' structure below. 672 673 typedef struct 674 { 675 NvHandle hRoot; // [IN] - root object handle 676 NvHandle hObjectParent; // [IN] - device handle 677 NvU32 function; // [IN] - heap function, see below FUNCTION* defines 678 NvHandle hVASpace; // [IN] - VASpace handle 679 NvS16 ivcHeapNumber; // [IN] - When IVC heaps are present: either 1) number of the IVC heap 680 // shared between two VMs or 2) number indicating that allocation 681 // should not be done on an IVC heap. Values greater than constant 682 // 'NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP' define set 1) 683 // and values less or equal to that constant define set 2). 684 // When IVC heaps are present, correct IVC-heap number must be specified. 685 // When IVC heaps are absent, IVC-heap number is diregarded. 686 // RM provides for each VM a bitmask of heaps with each bit 687 // specifying the other peer that can use the partition. 688 // Each bit set to one can be enumerated, such that the bit 689 // with lowest significance is enumerated with one. 690 // 'ivcHeapNumber' parameter specifies this enumeration value. 691 // This value is used to uniquely identify a heap shared between 692 // two particular VMs. 693 // Illustration: 694 // bitmask: 1 1 0 1 0 = 0x1A 695 // possible 'ivcHeapNumber' values: 3, 2, 1 696 NvV32 status; // [OUT] - returned NVOS32* status code, see below STATUS* defines 697 NvU64 total NV_ALIGN_BYTES(8); // [OUT] - returned total size of heap 698 NvU64 free NV_ALIGN_BYTES(8); // [OUT] - returned free space available in heap 699 700 union 701 { 702 // NVOS32_FUNCTION_ALLOC_SIZE 703 struct 704 { 705 NvU32 owner; // [IN] - memory owner ID 706 NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) 707 NvU32 type; // [IN] - surface type, see below TYPE* defines 708 NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines 709 NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated 710 NvU32 format; // [IN/OUT] - format requested, and format allocated 711 NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated 712 NvU32 zcullCovg; // [OUT] - zcull covg allocated 713 NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses 714 NvU32 width; // [IN] - width "hint" used for zcull region allocations 715 NvU32 height; // [IN] - height "hint" used for zcull region allocations 716 NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated 717 NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on 718 NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset 719 NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit 720 NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address 721 NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range 722 NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. 723 NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated 724 NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) 725 NvS32 numaNode; // [IN] - NUMA node from which memory should be allocated 726 } AllocSize; 727 728 // NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT 729 struct 730 { 731 NvU32 owner; // [IN] - memory owner ID 732 NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) 733 NvU32 type; // [IN] - surface type, see below TYPE* defines 734 NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines 735 NvU32 height; // [IN] - height of surface in pixels 736 NvS32 pitch; // [IN/OUT] - desired pitch AND returned actual pitch allocated 737 NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated 738 NvU32 width; //[IN] - width of surface in pixels 739 NvU32 format; // [IN/OUT] - format requested, and format allocated 740 NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated 741 NvU32 zcullCovg; // [OUT] - zcull covg allocated 742 NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses 743 NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated 744 NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on 745 NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset 746 NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit 747 NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address 748 NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range 749 NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. 750 NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated 751 NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) 752 NvS32 numaNode; // [IN] - NUMA node from which memory should be allocated 753 } AllocTiledPitchHeight; 754 755 // NVOS32_FUNCTION_FREE 756 struct 757 { 758 NvU32 owner; // [IN] - memory owner ID 759 NvHandle hMemory; // [IN] - unique memory handle 760 NvU32 flags; // [IN] - heap free flags (must be NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED) 761 } Free; 762 763 // NVOS32_FUNCTION_RELEASE_COMPR 764 struct 765 { 766 NvU32 owner; // [IN] - memory owner ID 767 NvU32 flags; // [IN] - must be NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED 768 NvHandle hMemory; // [IN] - unique memory handle (valid if _RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED 769 } ReleaseCompr; 770 771 // NVOS32_FUNCTION_REACQUIRE_COMPR 772 struct 773 { 774 NvU32 owner; // [IN] - memory owner ID 775 NvU32 flags; // [IN] - must be NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED 776 NvHandle hMemory; // [IN] - unique memory handle (valid if _REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED 777 } ReacquireCompr; 778 779 // NVOS32_FUNCTION_INFO 780 struct 781 { 782 NvU32 attr; // [IN] - memory heap attributes requested 783 NvU64 offset NV_ALIGN_BYTES(8); // [OUT] - base of largest free block 784 NvU64 size NV_ALIGN_BYTES(8); // [OUT] - size of largest free block 785 NvU64 base NV_ALIGN_BYTES(8); // [OUT] - returned heap phys base 786 } Info; 787 788 // NVOS32_FUNCTION_DUMP 789 struct 790 { 791 NvU32 flags; // [IN] - see _DUMP_FLAGS 792 // [IN] - if NULL, numBlocks is the returned number of blocks in 793 // heap, else returns all blocks in eHeap 794 // if non-NULL points to a buffer that is at least numBlocks 795 // * sizeof(NVOS32_HEAP_DUMP_BLOCK) bytes. 796 NvP64 pBuffer NV_ALIGN_BYTES(8); 797 // [IN/OUT] - if pBuffer is NULL, will number of blocks in heap 798 // if pBuffer is non-NULL, is input containing the size of 799 // pBuffer in units of NVOS32_HEAP_DUMP_BLOCK. This must 800 // be greater than or equal to the number of blocks in the 801 // heap. 802 NvU32 numBlocks; 803 } Dump; 804 805 // NVOS32_FUNCTION_DESTROY - no extra parameters needed 806 807 // NVOS32_FUNCTION_ALLOC_SIZE_RANGE 808 struct 809 { 810 NvU32 owner; // [IN] - memory owner ID 811 NvHandle hMemory; // [IN] - unique memory handle 812 NvU32 type; // [IN] - surface type, see below TYPE* defines 813 NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines 814 NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated 815 NvU32 format; // [IN/OUT] - format requested, and format allocated 816 NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated 817 NvU32 zcullCovg; // [OUT] - zcull covg allocated 818 NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses 819 NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated 820 NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on 821 NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset 822 NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit 823 NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range 824 NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. 825 NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address 826 NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated 827 NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) 828 NvS32 numaNode; // [IN] - NUMA node from which memory should be allocated 829 } AllocSizeRange; 830 831 // additions for Longhorn 832 #define NVAL_MAX_BANKS (4) 833 #define NVAL_MAP_DIRECTION 0:0 834 #define NVAL_MAP_DIRECTION_DOWN 0x00000000 835 #define NVAL_MAP_DIRECTION_UP 0x00000001 836 837 // NVOS32_FUNCTION_GET_MEM_ALIGNMENT 838 struct 839 { 840 NvU32 alignType; // Input 841 NvU32 alignAttr; 842 NvU32 alignInputFlags; 843 NvU64 alignSize NV_ALIGN_BYTES(8); 844 NvU32 alignHeight; 845 NvU32 alignWidth; 846 NvU32 alignPitch; 847 NvU32 alignPad; 848 NvU32 alignMask; 849 NvU32 alignOutputFlags[NVAL_MAX_BANKS]; // We could compress this information but it is probably not that big of a deal 850 NvU32 alignBank[NVAL_MAX_BANKS]; 851 NvU32 alignKind; 852 NvU32 alignAdjust; // Output -- If non-zero the amount we need to adjust the offset 853 NvU32 alignAttr2; 854 } AllocHintAlignment; 855 856 struct 857 { 858 NvU32 allocOwner; // [IN] - memory owner ID 859 NvHandle allochMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) 860 NvU32 flags; 861 NvU32 allocType; // Input 862 NvU32 allocAttr; 863 NvU32 allocInputFlags; 864 NvU64 allocSize NV_ALIGN_BYTES(8); 865 NvU32 allocHeight; 866 NvU32 allocWidth; 867 NvU32 allocPitch; 868 NvU32 allocMask; 869 NvU32 allocComprCovg; 870 NvU32 allocZcullCovg; 871 NvP64 bindResultFunc NV_ALIGN_BYTES(8); // BindResultFunc 872 NvP64 pHandle NV_ALIGN_BYTES(8); 873 NvHandle hResourceHandle; // Handle to RM container 874 NvU32 retAttr; // Output Indicates the resources that we allocated 875 NvU32 kind; 876 NvU64 osDeviceHandle NV_ALIGN_BYTES(8); 877 NvU32 allocAttr2; 878 NvU32 retAttr2; // Output Indicates the resources that we allocated 879 NvU64 allocAddr NV_ALIGN_BYTES(8); 880 // [out] from GMMU_COMPR_INFO in drivers/common/shared/inc/mmu/gmmu_fmt.h 881 struct 882 { 883 NvU32 compPageShift; 884 NvU32 compressedKind; 885 NvU32 compTagLineMin; 886 NvU32 compPageIndexLo; 887 NvU32 compPageIndexHi; 888 NvU32 compTagLineMultiplier; 889 } comprInfo; 890 // [out] fallback uncompressed kind. 891 NvU32 uncompressedKind; 892 } HwAlloc; 893 894 // NVOS32_FUNCTION_HW_FREE 895 struct 896 { 897 NvHandle hResourceHandle; // Handle to RM Resource Info 898 NvU32 flags; // Indicate if HW Resources and/or Memory 899 } HwFree; 900 // Updated interface check. 901 #define NV_RM_OS32_ALLOC_OS_DESCRIPTOR_WITH_OS32_ATTR 1 902 903 // NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR 904 struct 905 { 906 NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) 907 NvU32 type; // [IN] - surface type, see below TYPE* defines 908 NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines 909 NvU32 attr; // [IN] - attributes for memory placement/properties, see below 910 NvU32 attr2; // [IN] - attributes GPU_CACHEABLE 911 NvP64 descriptor NV_ALIGN_BYTES(8); // [IN] - descriptor address 912 NvU64 limit NV_ALIGN_BYTES(8); // [IN] - allocated size -1 913 NvU32 descriptorType; // [IN] - descriptor type(Virtual | nvmap Handle) 914 } AllocOsDesc; 915 916 } data; 917 } NVOS32_PARAMETERS; 918 919 typedef struct 920 { 921 NvU32 owner; // owner id - NVOS32_BLOCK_TYPE_FREE or defined by client during heap_alloc 922 NvU32 format; // arch specific format/kind 923 NvU64 begin NV_ALIGN_BYTES(8); // start of allocated memory block 924 NvU64 align NV_ALIGN_BYTES(8); // actual start of usable memory, aligned to chip specific boundary 925 NvU64 end NV_ALIGN_BYTES(8); // end of usable memory. end - align + 1 = size of block 926 } NVOS32_HEAP_DUMP_BLOCK; 927 928 929 #define NVOS32_DELETE_RESOURCES_ALL 0 930 931 // type field 932 #define NVOS32_TYPE_IMAGE 0 933 #define NVOS32_TYPE_DEPTH 1 934 #define NVOS32_TYPE_TEXTURE 2 935 #define NVOS32_TYPE_VIDEO 3 936 #define NVOS32_TYPE_FONT 4 937 #define NVOS32_TYPE_CURSOR 5 938 #define NVOS32_TYPE_DMA 6 939 #define NVOS32_TYPE_INSTANCE 7 940 #define NVOS32_TYPE_PRIMARY 8 941 #define NVOS32_TYPE_ZCULL 9 942 #define NVOS32_TYPE_UNUSED 10 943 #define NVOS32_TYPE_SHADER_PROGRAM 11 944 #define NVOS32_TYPE_OWNER_RM 12 945 #define NVOS32_TYPE_NOTIFIER 13 946 #define NVOS32_TYPE_RESERVED 14 947 #define NVOS32_TYPE_PMA 15 948 #define NVOS32_TYPE_STENCIL 16 949 #define NVOS32_NUM_MEM_TYPES 17 950 951 // Surface attribute field - bitmask of requested attributes the surface 952 // should have. 953 // This value is updated to reflect what was actually allocated, and so this 954 // field must be checked after every allocation to determine what was 955 // allocated. Pass in the ANY tags to indicate that RM should fall back but 956 // still succeed the alloc. 957 // for example, if tiled_any is passed in, but no tile ranges are available, 958 // RM will allocate normal memory and indicate that in the returned attr field. 959 // Each returned attribute will have the REQUIRED field set if that attribute 960 // applies to the allocated surface. 961 962 #define NVOS32_ATTR_NONE 0x00000000 963 964 #define NVOS32_ATTR_DEPTH 2:0 965 #define NVOS32_ATTR_DEPTH_UNKNOWN 0x00000000 966 #define NVOS32_ATTR_DEPTH_8 0x00000001 967 #define NVOS32_ATTR_DEPTH_16 0x00000002 968 #define NVOS32_ATTR_DEPTH_24 0x00000003 969 #define NVOS32_ATTR_DEPTH_32 0x00000004 970 #define NVOS32_ATTR_DEPTH_64 0x00000005 971 #define NVOS32_ATTR_DEPTH_128 0x00000006 972 973 #define NVOS32_ATTR_COMPR_COVG 3:3 974 #define NVOS32_ATTR_COMPR_COVG_DEFAULT 0x00000000 975 #define NVOS32_ATTR_COMPR_COVG_PROVIDED 0x00000001 976 977 // Surface description - number of AA samples 978 // This number should only reflect AA done in hardware, not in software. For 979 // example, OpenGL's 8x AA mode is a mix of 2x hardware multisample and 2x2 980 // software supersample. 981 // OpenGL should specify ATTR_AA_SAMPLES of 2 in this case, not 8, because 982 // the hardware will be programmed to run in 2x AA mode. 983 // Note that X_VIRTUAL_Y means X real samples with Y samples total (i.e. Y 984 // does not indicate the number of virtual samples). For instance, what 985 // arch and HW describe as NV_PGRAPH_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 986 // corresponds to NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 here. 987 988 #define NVOS32_ATTR_AA_SAMPLES 7:4 989 #define NVOS32_ATTR_AA_SAMPLES_1 0x00000000 990 #define NVOS32_ATTR_AA_SAMPLES_2 0x00000001 991 #define NVOS32_ATTR_AA_SAMPLES_4 0x00000002 992 #define NVOS32_ATTR_AA_SAMPLES_4_ROTATED 0x00000003 993 #define NVOS32_ATTR_AA_SAMPLES_6 0x00000004 994 #define NVOS32_ATTR_AA_SAMPLES_8 0x00000005 995 #define NVOS32_ATTR_AA_SAMPLES_16 0x00000006 996 #define NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_8 0x00000007 997 #define NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 0x00000008 998 #define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16 0x00000009 999 #define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32 0x0000000A 1000 1001 // Zcull region (NV40 and up) 1002 // If ATTR_ZCULL is REQUIRED or ANY and ATTR_DEPTH is UNKNOWN, the 1003 // allocation will fail. 1004 // If ATTR_DEPTH or ATTR_AA_SAMPLES is not accurate, erroneous rendering 1005 // may result. 1006 #define NVOS32_ATTR_ZCULL 11:10 1007 #define NVOS32_ATTR_ZCULL_NONE 0x00000000 1008 #define NVOS32_ATTR_ZCULL_REQUIRED 0x00000001 1009 #define NVOS32_ATTR_ZCULL_ANY 0x00000002 1010 #define NVOS32_ATTR_ZCULL_SHARED 0x00000003 1011 1012 // Compression (NV20 and up) 1013 // If ATTR_COMPR is REQUIRED or ANY and ATTR_DEPTH is UNKNOWN, the 1014 // allocation will fail. 1015 // If ATTR_DEPTH or ATTR_AA_SAMPLES is not accurate, performance will 1016 // suffer heavily 1017 #define NVOS32_ATTR_COMPR 13:12 1018 #define NVOS32_ATTR_COMPR_NONE 0x00000000 1019 #define NVOS32_ATTR_COMPR_REQUIRED 0x00000001 1020 #define NVOS32_ATTR_COMPR_ANY 0x00000002 1021 #define NVOS32_ATTR_COMPR_PLC_REQUIRED NVOS32_ATTR_COMPR_REQUIRED 1022 #define NVOS32_ATTR_COMPR_PLC_ANY NVOS32_ATTR_COMPR_ANY 1023 #define NVOS32_ATTR_COMPR_DISABLE_PLC_ANY 0x00000003 1024 1025 // 1026 // Force the allocation to go to the reserved heap. 1027 // This flag is used for KMD allocations when MIG is enabled. 1028 // 1029 #define NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP 14:14 1030 #define NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_NO 0x00000000 1031 #define NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_YES 0x00000001 1032 1033 // Format 1034 // _BLOCK_LINEAR is only available for nv50+. 1035 #define NVOS32_ATTR_FORMAT 17:16 1036 // Macros representing the low/high bits of NVOS32_ATTR_FORMAT 1037 // bit range. These provide direct access to the range limits 1038 // without needing to split the low:high representation via 1039 // ternary operator, thereby avoiding MISRA 14.3 violation. 1040 #define NVOS32_ATTR_FORMAT_LOW_FIELD 16 1041 #define NVOS32_ATTR_FORMAT_HIGH_FIELD 17 1042 #define NVOS32_ATTR_FORMAT_PITCH 0x00000000 1043 #define NVOS32_ATTR_FORMAT_SWIZZLED 0x00000001 1044 #define NVOS32_ATTR_FORMAT_BLOCK_LINEAR 0x00000002 1045 1046 #define NVOS32_ATTR_Z_TYPE 18:18 1047 #define NVOS32_ATTR_Z_TYPE_FIXED 0x00000000 1048 #define NVOS32_ATTR_Z_TYPE_FLOAT 0x00000001 1049 1050 #define NVOS32_ATTR_ZS_PACKING 21:19 1051 #define NVOS32_ATTR_ZS_PACKING_S8 0x00000000 // Z24S8 and S8 share definition 1052 #define NVOS32_ATTR_ZS_PACKING_Z24S8 0x00000000 1053 #define NVOS32_ATTR_ZS_PACKING_S8Z24 0x00000001 1054 #define NVOS32_ATTR_ZS_PACKING_Z32 0x00000002 1055 #define NVOS32_ATTR_ZS_PACKING_Z24X8 0x00000003 1056 #define NVOS32_ATTR_ZS_PACKING_X8Z24 0x00000004 1057 #define NVOS32_ATTR_ZS_PACKING_Z32_X24S8 0x00000005 1058 #define NVOS32_ATTR_ZS_PACKING_X8Z24_X24S8 0x00000006 1059 #define NVOS32_ATTR_ZS_PACKING_Z16 0x00000007 1060 // NOTE: ZS packing and color packing fields are overlaid 1061 #define NVOS32_ATTR_COLOR_PACKING NVOS32_ATTR_ZS_PACKING 1062 #define NVOS32_ATTR_COLOR_PACKING_A8R8G8B8 0x00000000 1063 #define NVOS32_ATTR_COLOR_PACKING_X8R8G8B8 0x00000001 1064 1065 1066 1067 // 1068 // For virtual allocs to choose page size for the region. Specifying 1069 // _DEFAULT will select a virtual page size that allows for a surface 1070 // to be mixed between video and system memory and allow the surface 1071 // to be migrated between video and system memory. For tesla chips, 1072 // 4KB will be used. For fermi chips with dual page tables, a virtual 1073 // address with both page tables will be used. 1074 // 1075 // For physical allocation on chips with page swizzle this field is 1076 // used to select the page swizzle. This later also sets the virtual 1077 // page size, but does not have influence over selecting a migratable 1078 // virtual address. That must be selected when mapping the physical 1079 // memory. 1080 // 1081 // BIG_PAGE = 64 KB on PASCAL 1082 // = 64 KB or 128 KB on pre_PASCAL chips 1083 // 1084 // HUGE_PAGE = 2 MB on PASCAL+ 1085 // = 2 MB or 512 MB on AMPERE+ 1086 // = not supported on pre_PASCAL chips. 1087 // 1088 // To request for a HUGE page size, 1089 // set NVOS32_ATTR_PAGE_SIZE to _HUGE and NVOS32_ATTR2_PAGE_SIZE_HUGE to 1090 // the desired size. 1091 // 1092 #define NVOS32_ATTR_PAGE_SIZE 24:23 1093 #define NVOS32_ATTR_PAGE_SIZE_DEFAULT 0x00000000 1094 #define NVOS32_ATTR_PAGE_SIZE_4KB 0x00000001 1095 #define NVOS32_ATTR_PAGE_SIZE_BIG 0x00000002 1096 #define NVOS32_ATTR_PAGE_SIZE_HUGE 0x00000003 1097 1098 #define NVOS32_ATTR_LOCATION 26:25 1099 #define NVOS32_ATTR_LOCATION_VIDMEM 0x00000000 1100 #define NVOS32_ATTR_LOCATION_PCI 0x00000001 1101 #define NVOS32_ATTR_LOCATION_AGP 0x00000002 1102 #define NVOS32_ATTR_LOCATION_ANY 0x00000003 1103 1104 // 1105 // _DEFAULT implies _CONTIGUOUS for video memory currently, but 1106 // may be changed to imply _NONCONTIGUOUS in the future. 1107 // _ALLOW_NONCONTIGUOUS enables falling back to the noncontiguous 1108 // vidmem allocator if contig allocation fails. 1109 // 1110 #define NVOS32_ATTR_PHYSICALITY 28:27 1111 #define NVOS32_ATTR_PHYSICALITY_DEFAULT 0x00000000 1112 #define NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS 0x00000001 1113 #define NVOS32_ATTR_PHYSICALITY_CONTIGUOUS 0x00000002 1114 #define NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS 0x00000003 1115 1116 #define NVOS32_ATTR_COHERENCY 31:29 1117 #define NVOS32_ATTR_COHERENCY_UNCACHED 0x00000000 1118 #define NVOS32_ATTR_COHERENCY_CACHED 0x00000001 1119 #define NVOS32_ATTR_COHERENCY_WRITE_COMBINE 0x00000002 1120 #define NVOS32_ATTR_COHERENCY_WRITE_THROUGH 0x00000003 1121 #define NVOS32_ATTR_COHERENCY_WRITE_PROTECT 0x00000004 1122 #define NVOS32_ATTR_COHERENCY_WRITE_BACK 0x00000005 1123 1124 // ATTR2 fields 1125 #define NVOS32_ATTR2_NONE 0x00000000 1126 1127 // 1128 // DEFAULT - Let lower level drivers pick optimal page kind. 1129 // PREFER_NO_ZBC - Prefer other types of compression over ZBC when 1130 // selecting page kind. 1131 // PREFER_ZBC - Prefer ZBC over other types of compression when 1132 // selecting page kind. 1133 // REQUIRE_ONLY_ZBC - Require a page kind that enables ZBC but disables 1134 // other types of compression (i.e. 2C page kind). 1135 // INVALID - Aliases REQUIRE_ONLY_ZBC, which is not supported 1136 // by all RM implementations. 1137 // 1138 #define NVOS32_ATTR2_ZBC 1:0 1139 #define NVOS32_ATTR2_ZBC_DEFAULT 0x00000000 1140 #define NVOS32_ATTR2_ZBC_PREFER_NO_ZBC 0x00000001 1141 #define NVOS32_ATTR2_ZBC_PREFER_ZBC 0x00000002 1142 #define NVOS32_ATTR2_ZBC_REQUIRE_ONLY_ZBC 0x00000003 1143 #define NVOS32_ATTR2_ZBC_INVALID 0x00000003 1144 1145 // 1146 // DEFAULT - Highest performance cache policy that is coherent with the highest 1147 // performance CPU mapping. Typically this is gpu cached for video 1148 // memory and gpu uncached for system memory. 1149 // YES - Enable gpu caching if supported on this surface type. For system 1150 // memory this will not be coherent with direct CPU mappings. 1151 // NO - Disable gpu caching if supported on this surface type. 1152 // INVALID - Clients should never set YES and NO simultaneously. 1153 // 1154 #define NVOS32_ATTR2_GPU_CACHEABLE 3:2 1155 #define NVOS32_ATTR2_GPU_CACHEABLE_DEFAULT 0x00000000 1156 #define NVOS32_ATTR2_GPU_CACHEABLE_YES 0x00000001 1157 #define NVOS32_ATTR2_GPU_CACHEABLE_NO 0x00000002 1158 #define NVOS32_ATTR2_GPU_CACHEABLE_INVALID 0x00000003 1159 1160 // 1161 // DEFAULT - GPU-dependent cache policy 1162 // YES - Enable gpu caching for p2p mem 1163 // NO - Disable gpu caching for p2p mem 1164 // 1165 #define NVOS32_ATTR2_P2P_GPU_CACHEABLE 5:4 1166 #define NVOS32_ATTR2_P2P_GPU_CACHEABLE_DEFAULT 0x00000000 1167 #define NVOS32_ATTR2_P2P_GPU_CACHEABLE_YES 0x00000001 1168 #define NVOS32_ATTR2_P2P_GPU_CACHEABLE_NO 0x00000002 1169 1170 // This applies to virtual allocs only. See NVOS46_FLAGS_32BIT_POINTER. 1171 #define NVOS32_ATTR2_32BIT_POINTER 6:6 1172 #define NVOS32_ATTR2_32BIT_POINTER_DISABLE 0x00000000 1173 #define NVOS32_ATTR2_32BIT_POINTER_ENABLE 0x00000001 1174 1175 // 1176 // Whether or not a NUMA Node ID has been specified. 1177 // If yes, the NUMA node ID specified in numaNode will be used. 1178 // If no, memory can be allocated from any socket (numaNode will be ignored). 1179 // Specified numaNode must be of a CPU's memory 1180 // 1181 1182 #define NVOS32_ATTR2_FIXED_NUMA_NODE_ID 7:7 1183 #define NVOS32_ATTR2_FIXED_NUMA_NODE_ID_NO 0x00000000 1184 #define NVOS32_ATTR2_FIXED_NUMA_NODE_ID_YES 0x00000001 1185 1186 // 1187 // Force SMMU mapping on GPU physical allocation in Tegra 1188 // SMMU mapping for GPU physical allocation decided internally by RM 1189 // This attribute provide an override to RM policy for verification purposes. 1190 // 1191 #define NVOS32_ATTR2_SMMU_ON_GPU 10:8 1192 #define NVOS32_ATTR2_SMMU_ON_GPU_DEFAULT 0x00000000 1193 #define NVOS32_ATTR2_SMMU_ON_GPU_DISABLE 0x00000001 1194 #define NVOS32_ATTR2_SMMU_ON_GPU_ENABLE 0x00000002 1195 1196 // 1197 // Make comptag allocation aligned to compression cacheline size. 1198 // Specifying this attribute will make RM allocate comptags worth an entire 1199 // comp cacheline. The allocation will be offset aligned to number of comptags/comp cacheline. 1200 // 1201 #define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN 11:11 1202 #define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF 0x0 1203 #define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_ON 0x1 1204 #define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_DEFAULT \ 1205 NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF 1206 1207 // Allocation preferred in high or low priority memory 1208 #define NVOS32_ATTR2_PRIORITY 13:12 1209 #define NVOS32_ATTR2_PRIORITY_DEFAULT 0x0 1210 #define NVOS32_ATTR2_PRIORITY_HIGH 0x1 1211 #define NVOS32_ATTR2_PRIORITY_LOW 0x2 1212 1213 // PMA: Allocation is an RM internal allocation (RM-only) 1214 #define NVOS32_ATTR2_INTERNAL 14:14 1215 #define NVOS32_ATTR2_INTERNAL_NO 0x0 1216 #define NVOS32_ATTR2_INTERNAL_YES 0x1 1217 1218 // Allocate 2C instead of 2CZ 1219 #define NVOS32_ATTR2_PREFER_2C 15:15 1220 #define NVOS32_ATTR2_PREFER_2C_NO 0x00000000 1221 #define NVOS32_ATTR2_PREFER_2C_YES 0x00000001 1222 1223 // Allocation used by display engine; RM verifies display engine has enough 1224 // address bits or remapper available. 1225 #define NVOS32_ATTR2_NISO_DISPLAY 16:16 1226 #define NVOS32_ATTR2_NISO_DISPLAY_NO 0x00000000 1227 #define NVOS32_ATTR2_NISO_DISPLAY_YES 0x00000001 1228 1229 // 1230 // !!WARNING!!! 1231 // 1232 // This flag is introduced as a temporary WAR to enable color compression 1233 // without ZBC. 1234 // 1235 // This dangerous flag can be used by UMDs to instruct RM to skip the zbc 1236 // table refcounting that RM does today, when the chosen PTE kind has ZBC 1237 // support. 1238 // 1239 // Currently we do not have a safe per process zbc slot management and 1240 // refcounting mechanism between RM and UMD and hence, any process can 1241 // access any other process's zbc entry in the global zbc table (without mask) 1242 // Inorder to flush the ZBC table for slot reuse RM cannot track which 1243 // process is using which zbc slot. Hence RM has a global refcount for the 1244 // zbc table to flush and reuse the entries if the PTE kind supports zbc. 1245 // 1246 // This scheme poses a problem if there are apps that are persistent such as 1247 // the desktop components that can have color compression enabled which will 1248 // always keep the refcount active. Since these apps can live without 1249 // ZBC, UMD can disable ZBC using masks. 1250 // 1251 // In such a case, if UMD so chooses to disable ZBC, this flag should be used 1252 // to skip refcounting as by default RM would refcount the ZBC table. 1253 // 1254 // NOTE: There is no way for RM to enforce/police this, and we totally rely 1255 // on UMD to use a zbc mask in the pushbuffer method to prevent apps from 1256 // accessing the ZBC table. 1257 // 1258 #define NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT 17:17 1259 #define NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_NO 0x00000000 1260 #define NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_YES 0x00000001 1261 1262 // Allocation requires ISO bandwidth guarantees 1263 #define NVOS32_ATTR2_ISO 18:18 1264 #define NVOS32_ATTR2_ISO_NO 0x00000000 1265 #define NVOS32_ATTR2_ISO_YES 0x00000001 1266 1267 // 1268 // Turn off blacklist feature for video memory allocation 1269 // This attribute should be used only by Kernel client (KMD), to mask 1270 // the blacklisted pages for the allocation. This is done so that the clients 1271 // will manage the above masked blacklisted pages after the allocation. It will 1272 // return to RM's pool after the allocation was free-d.RmVidHeapCtrl returns 1273 // NV_ERR_INSUFFICIENT_PERMISSIONS if it is being called by non-kernel clients. 1274 // 1275 1276 // TODO: Project ReLingo - This term is marked for deletion. Use PAGE_OFFLINING. 1277 #define NVOS32_ATTR2_BLACKLIST 19:19 1278 #define NVOS32_ATTR2_BLACKLIST_ON 0x00000000 1279 #define NVOS32_ATTR2_BLACKLIST_OFF 0x00000001 1280 #define NVOS32_ATTR2_PAGE_OFFLINING 19:19 1281 #define NVOS32_ATTR2_PAGE_OFFLINING_ON 0x00000000 1282 #define NVOS32_ATTR2_PAGE_OFFLINING_OFF 0x00000001 1283 1284 // 1285 // For virtual allocs to choose the HUGE page size for the region. 1286 // NVOS32_ATTR_PAGE_SIZE must be set to _HUGE to use this. 1287 // Currently, the default huge page is 2MB, so a request with _DEFAULT 1288 // set will always be interpreted as 2MB. 1289 // Not supported on pre_AMPERE chips. 1290 // 1291 #define NVOS32_ATTR2_PAGE_SIZE_HUGE 21:20 1292 #define NVOS32_ATTR2_PAGE_SIZE_HUGE_DEFAULT 0x00000000 1293 #define NVOS32_ATTR2_PAGE_SIZE_HUGE_2MB 0x00000001 1294 #define NVOS32_ATTR2_PAGE_SIZE_HUGE_512MB 0x00000002 1295 1296 // Allow read-only or read-write user CPU mappings 1297 #define NVOS32_ATTR2_PROTECTION_USER 22:22 1298 #define NVOS32_ATTR2_PROTECTION_USER_READ_WRITE 0x00000000 1299 #define NVOS32_ATTR2_PROTECTION_USER_READ_ONLY 0x00000001 1300 1301 // Allow read-only or read-write device mappings 1302 #define NVOS32_ATTR2_PROTECTION_DEVICE 23:23 1303 #define NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE 0x00000000 1304 #define NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY 0x00000001 1305 1306 // Deprecated. To be deleted once client code has removed references. 1307 #define NVOS32_ATTR2_USE_EGM 24:24 1308 #define NVOS32_ATTR2_USE_EGM_FALSE 0x00000000 1309 #define NVOS32_ATTR2_USE_EGM_TRUE 0x00000001 1310 1311 // 1312 // Allow client allocations to go to protected/unprotected video/system memory. 1313 // When Ampere Protected Model aka APM or Confidential Compute is enabled and 1314 // DEFAULT flag is set by client, allocations go to protected memory. When 1315 // protected memory is not enabled, allocations go to unprotected memory. 1316 // If APM or CC is not enabled, it is a bug for a client to set the PROTECTED 1317 // flag to YES 1318 // 1319 #define NVOS32_ATTR2_MEMORY_PROTECTION 26:25 1320 #define NVOS32_ATTR2_MEMORY_PROTECTION_DEFAULT 0x00000000 1321 #define NVOS32_ATTR2_MEMORY_PROTECTION_PROTECTED 0x00000001 1322 #define NVOS32_ATTR2_MEMORY_PROTECTION_UNPROTECTED 0x00000002 1323 // 1324 // Force the allocation to go to guest subheap. 1325 // This flag is used by vmiop plugin to allocate from GPA 1326 // 1327 #define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP 27:27 1328 #define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_NO 0x00000000 1329 #define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_YES 0x00000001 1330 1331 // 1332 // When allocating memory, register the memory descriptor to GSP-RM 1333 // so that GSP-RM is aware of and can access it 1334 // 1335 #define NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM 31:31 1336 #define NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_FALSE 0x00000000 1337 #define NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_TRUE 0x00000001 1338 1339 /** 1340 * NVOS32 ALLOC_FLAGS 1341 * 1342 * NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT 1343 * 1344 * NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP 1345 * 1346 * NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN 1347 * 1348 * NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE 1349 * 1350 * NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE 1351 * 1352 * NVOS32_ALLOC_FLAGS_BANK_HINT 1353 * 1354 * NVOS32_ALLOC_FLAGS_BANK_FORCE 1355 * 1356 * NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT 1357 * 1358 * NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE 1359 * 1360 * NVOS32_ALLOC_FLAGS_BANK_GROW_UP 1361 * Only relevant if bank_hint or bank_force are set 1362 * 1363 * NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN 1364 * Only relevant if bank_hint or bank_force are set 1365 * 1366 * NVOS32_ALLOC_FLAGS_LAZY 1367 * Lazy allocation (deferred pde, pagetable creation) 1368 * 1369 * NVOS32_ALLOC_FLAGS_NO_SCANOUT 1370 * Set if surface will never be scanned out 1371 * 1372 * NVOS32_ALLOC_FLAGS_PITCH_FORCE 1373 * Fail alloc if supplied pitch is not aligned 1374 * 1375 * NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED 1376 * Memory handle provided to be associated with this allocation 1377 * 1378 * NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED 1379 * By default memory is mapped into the CPU address space 1380 * 1381 * NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM 1382 * Allocate persistent video memory 1383 * 1384 * NVOS32_ALLOC_FLAGS_USE_BEGIN_END 1385 * Use rangeBegin & rangeEnd fields in allocs other than size/range 1386 * 1387 * NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED 1388 * Allocate TurboCipher encrypted region 1389 * 1390 * NVOS32_ALLOC_FLAGS_VIRTUAL 1391 * Allocate virtual memory address space 1392 * 1393 * NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX 1394 * Force allocation internal index 1395 * 1396 * NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED 1397 * This flag is depreciated and allocations will fail. 1398 * 1399 * NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED 1400 * Must be used with NVOS32_ALLOC_FLAGS_VIRTUAL. 1401 * Page tables for this allocation will be managed outside of RM. 1402 * 1403 * NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE 1404 * 1405 * NVOS32_ALLOC_FLAGS_PROTECTED 1406 * Allocate in a protected memory region if available 1407 * 1408 * NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP 1409 * Map kernel os descriptor 1410 * 1411 * NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE 1412 * On WDDM all address spaces are created with MINIMIZE_PTETABLE_SIZE 1413 * to reduce the overhead of private address spaces per application, 1414 * at the cost of holes in the virtual address space. 1415 * 1416 * Shaders have short pointers that are required to be within a 1417 * GPU dependent 32b range. 1418 * 1419 * MAXIMIZE_ADDRESS_SPACE will reverse the MINIMIZE_PTE_TABLE_SIZE 1420 * flag with certain restrictions: 1421 * - This flag only has an effect when the allocation has the side 1422 * effect of creating a new PDE. It does not affect existing PDEs. 1423 * - The first few PDEs of the address space are kept minimum to allow 1424 * small applications to use fewer resources. 1425 * - By default this operations on the 0-4GB address range. 1426 * - If USE_BEGIN_END is specified the setting will apply to the 1427 * specified range instead of the first 4GB. 1428 * 1429 * NVOS32_ALLOC_FLAGS_SPARSE 1430 * Denote that a virtual address range is "sparse". Must be used with 1431 * NVOS32_ALLOC_FLAGS_VIRTUAL. Creation of a "sparse" virtual address range 1432 * denotes that an unmapped virtual address range should "not" fault but simply 1433 * return 0's. 1434 * 1435 * NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED 1436 * This a special flag that can be used only by kernel(root) clients 1437 * to allocate memory out of a protected region of the address space 1438 * If this flag is set by non kernel clients then the allocation will 1439 * fail. 1440 * 1441 * NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC 1442 * 1443 * NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY 1444 * If new pagetable need to be allocated prefer them in sysmem (if supported by the gpu) 1445 * 1446 * NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD 1447 * As per KMD request to eliminate extra allocation 1448 * 1449 * NVOS32_ALLOC_FLAGS_WPR1 1450 * Allocate in a WPR1 region if available 1451 * 1452 * NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X 1453 * If using zcull sharing and this surface is fsaa, then don't allocate an additional non-FSAA region. 1454 * 1455 * NVOS32_ALLOC_FLAGS_WPR2 1456 * Allocate in a WPR1 region if available 1457 */ 1458 #define NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT 0x00000001 1459 #define NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP 0x00000002 1460 #define NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN 0x00000004 1461 #define NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE 0x00000008 1462 #define NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE 0x00000010 1463 #define NVOS32_ALLOC_FLAGS_BANK_HINT 0x00000020 1464 #define NVOS32_ALLOC_FLAGS_BANK_FORCE 0x00000040 1465 #define NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT 0x00000080 1466 #define NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE 0x00000100 1467 #define NVOS32_ALLOC_FLAGS_BANK_GROW_UP 0x00000000 1468 #define NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN 0x00000200 1469 #define NVOS32_ALLOC_FLAGS_LAZY 0x00000400 1470 #define NVOS32_ALLOC_FLAGS_FORCE_REVERSE_ALLOC 0x00000800 1471 #define NVOS32_ALLOC_FLAGS_NO_SCANOUT 0x00001000 1472 #define NVOS32_ALLOC_FLAGS_PITCH_FORCE 0x00002000 1473 #define NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED 0x00004000 1474 #define NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED 0x00008000 1475 #define NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM 0x00010000 1476 #define NVOS32_ALLOC_FLAGS_USE_BEGIN_END 0x00020000 1477 #define NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED 0x00040000 1478 #define NVOS32_ALLOC_FLAGS_VIRTUAL 0x00080000 1479 #define NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX 0x00100000 1480 #define NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED 0x00200000 1481 #define NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED 0x00400000 1482 #define NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE 0x00800000 1483 #define NVOS32_ALLOC_FLAGS_PROTECTED 0x01000000 1484 #define NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP 0x02000000 // TODO BUG 2488679: fix alloc flag aliasing 1485 #define NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE 0x02000000 1486 #define NVOS32_ALLOC_FLAGS_SPARSE 0x04000000 1487 #define NVOS32_ALLOC_FLAGS_USER_READ_ONLY 0x04000000 // TODO BUG 2488682: remove this after KMD transition 1488 #define NVOS32_ALLOC_FLAGS_DEVICE_READ_ONLY 0x08000000 // TODO BUG 2488682: remove this after KMD transition 1489 #define NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED 0x08000000 1490 #define NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC 0x10000000 1491 #define NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY 0x20000000 1492 #define NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD 0x40000000 1493 #define NVOS32_ALLOC_FLAGS_WPR1 0x40000000 // TODO BUG 2488672: fix alloc flag aliasing 1494 #define NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X 0x80000000 1495 #define NVOS32_ALLOC_FLAGS_WPR2 0x80000000 // TODO BUG 2488672: fix alloc flag aliasing 1496 1497 // Internal flags used for RM's allocation paths 1498 #define NVOS32_ALLOC_INTERNAL_FLAGS_CLIENTALLOC 0x00000001 // RM internal flags - not sure if this should be exposed even. Keeping it here. 1499 #define NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB 0x00000004 // RM internal flags - not sure if this should be exposed even. Keeping it here. 1500 #define NVOS32_ALLOC_FLAGS_MAXIMIZE_4GB_ADDRESS_SPACE NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE // Legacy name 1501 1502 // 1503 // Bitmask of flags that are only valid for virtual allocations. 1504 // 1505 #define NVOS32_ALLOC_FLAGS_VIRTUAL_ONLY ( \ 1506 NVOS32_ALLOC_FLAGS_VIRTUAL | \ 1507 NVOS32_ALLOC_FLAGS_LAZY | \ 1508 NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED | \ 1509 NVOS32_ALLOC_FLAGS_SPARSE | \ 1510 NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE | \ 1511 NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY ) 1512 1513 // COMPR_COVG_* allows for specification of what compression resources 1514 // are required (_MIN) and necessary (_MAX). Default behavior is for 1515 // RM to provide as much as possible, including none if _ANY is allowed. 1516 // Values for min/max are (0-100, a %) * _COVG_SCALE (so max value is 1517 // 100*100==10000). _START is used to specify the % offset into the 1518 // region to begin the requested coverage. 1519 // _COVG_BITS allows specification of the number of comptags per ROP tile. 1520 // A value of 0 is default and allows RM to choose based upon MMU/FB rules. 1521 // All other values for _COVG_BITS are arch-specific. 1522 // Note: NVOS32_ATTR_COMPR_COVG_PROVIDED must be set for this feature 1523 // to be available (verif-only). 1524 #define NVOS32_ALLOC_COMPR_COVG_SCALE 10 1525 #define NVOS32_ALLOC_COMPR_COVG_BITS 1:0 1526 #define NVOS32_ALLOC_COMPR_COVG_BITS_DEFAULT 0x00000000 1527 #define NVOS32_ALLOC_COMPR_COVG_BITS_1 0x00000001 1528 #define NVOS32_ALLOC_COMPR_COVG_BITS_2 0x00000002 1529 #define NVOS32_ALLOC_COMPR_COVG_BITS_4 0x00000003 1530 #define NVOS32_ALLOC_COMPR_COVG_MAX 11:2 1531 #define NVOS32_ALLOC_COMPR_COVG_MIN 21:12 1532 #define NVOS32_ALLOC_COMPR_COVG_START 31:22 1533 1534 1535 // Note: NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED must be set for this feature 1536 // to be enabled. 1537 // If FALLBACK_ALLOW is set, a fallback from LOW_RES_Z or LOW_RES_ZS 1538 // to HIGH_RES_Z is allowed if the surface can't be fully covered. 1539 #define NVOS32_ALLOC_ZCULL_COVG_FORMAT 3:0 1540 #define NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_Z 0x00000000 1541 #define NVOS32_ALLOC_ZCULL_COVG_FORMAT_HIGH_RES_Z 0x00000002 1542 #define NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_ZS 0x00000003 1543 #define NVOS32_ALLOC_ZCULL_COVG_FALLBACK 4:4 1544 #define NVOS32_ALLOC_ZCULL_COVG_FALLBACK_DISALLOW 0x00000000 1545 #define NVOS32_ALLOC_ZCULL_COVG_FALLBACK_ALLOW 0x00000001 1546 1547 1548 // _ALLOC_COMPTAG_OFFSET allows the caller to specify the starting 1549 // offset for the comptags for a given surface, primarily for test only. 1550 // To specify an offset, set _USAGE_FIXED or _USAGE_MIN in conjunction 1551 // with _START. 1552 // 1553 // _USAGE_FIXED sets a surface's comptagline to start at the given 1554 // starting value. If the offset has already been assigned, then 1555 // the alloc call fails. 1556 // 1557 // _USAGE_MIN sets a surface's comptagline to start at the given 1558 // starting value or higher, depending on comptagline availability. 1559 // In this case, if the offset has already been assigned, the next 1560 // available comptagline (in increasing order) will be assigned. 1561 // 1562 // For Fermi, up to 2^17 comptags may be allowed, but the actual, 1563 // usable limit depends on the size of the compbit backing store. 1564 // 1565 // For Pascal, up to 2 ^ 18 comptags may be allowed 1566 // From Turing. up to 2 ^ 20 comptags may be allowed 1567 // 1568 // See also field ctagOffset in struct NVOS32_PARAMETERS. 1569 #define NVOS32_ALLOC_COMPTAG_OFFSET_START 19:0 1570 #define NVOS32_ALLOC_COMPTAG_OFFSET_START_DEFAULT 0x00000000 1571 #define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE 31:30 1572 #define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_DEFAULT 0x00000000 1573 #define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_OFF 0x00000000 1574 #define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_FIXED 0x00000001 1575 #define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_MIN 0x00000002 1576 1577 1578 // REALLOC flags field 1579 #define NVOS32_REALLOC_FLAGS_GROW_ALLOCATION 0x00000000 1580 #define NVOS32_REALLOC_FLAGS_SHRINK_ALLOCATION 0x00000001 1581 #define NVOS32_REALLOC_FLAGS_REALLOC_UP 0x00000000 // towards/from high memory addresses 1582 #define NVOS32_REALLOC_FLAGS_REALLOC_DOWN 0x00000002 // towards/from memory address 0 1583 1584 // RELEASE_COMPR, REACQUIRE_COMPR flags field 1585 #define NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED 0x000000001 1586 1587 #define NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED 0x000000001 1588 1589 1590 // FREE flags field 1591 #define NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED 0x00000001 1592 1593 // DUMP flags field 1594 #define NVOS32_DUMP_FLAGS_TYPE 1:0 1595 #define NVOS32_DUMP_FLAGS_TYPE_FB 0x00000000 1596 #define NVOS32_DUMP_FLAGS_TYPE_CLIENT_PD 0x00000001 1597 #define NVOS32_DUMP_FLAGS_TYPE_CLIENT_VA 0x00000002 1598 #define NVOS32_DUMP_FLAGS_TYPE_CLIENT_VAPTE 0x00000003 1599 1600 #define NVOS32_BLOCK_TYPE_FREE 0xFFFFFFFF 1601 #define NVOS32_INVALID_BLOCK_FREE_OFFSET 0xFFFFFFFF 1602 1603 #define NVOS32_MEM_TAG_NONE 0x00000000 1604 1605 /* 1606 * NV_CONTEXT_DMA_ALLOCATION_PARAMS - Allocation params to create context dma 1607 through NvRmAlloc. 1608 */ 1609 typedef struct 1610 { 1611 NvHandle hSubDevice; 1612 NvV32 flags; 1613 NvHandle hMemory; 1614 NvU64 offset NV_ALIGN_BYTES(8); 1615 NvU64 limit NV_ALIGN_BYTES(8); 1616 } NV_CONTEXT_DMA_ALLOCATION_PARAMS; 1617 1618 /* 1619 * NV_MEMORY_ALLOCATION_PARAMS - Allocation params to create memory through 1620 * NvRmAlloc. Flags are populated with NVOS32_ defines. 1621 */ 1622 typedef struct 1623 { 1624 NvU32 owner; // [IN] - memory owner ID 1625 NvU32 type; // [IN] - surface type, see below TYPE* defines 1626 NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines 1627 1628 NvU32 width; // [IN] - width of surface in pixels 1629 NvU32 height; // [IN] - height of surface in pixels 1630 NvS32 pitch; // [IN/OUT] - desired pitch AND returned actual pitch allocated 1631 1632 NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated 1633 NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated 1634 1635 NvU32 format; // [IN/OUT] - format requested, and format allocated 1636 NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated 1637 NvU32 zcullCovg; // [OUT] - zcull covg allocated 1638 1639 NvU64 rangeLo NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range 1640 NvU64 rangeHi NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. 1641 1642 NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated 1643 NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on 1644 NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset 1645 NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit 1646 NvP64 address NV_ALIGN_BYTES(8); // [OUT] - returned address 1647 1648 NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) 1649 NvHandle hVASpace; // [IN] - VASpace handle. Used when flag is VIRTUAL. 1650 1651 NvU32 internalflags; // [IN] - internal flags to change allocation behaviors from internal paths 1652 1653 NvU32 tag; // [IN] - memory tag used for debugging 1654 1655 NvS32 numaNode; // [IN] - CPU NUMA node from which memory should be allocated 1656 } NV_MEMORY_ALLOCATION_PARAMS; 1657 1658 /* 1659 * NV_OS_DESC_MEMORY_ALLOCATION_PARAMS - Allocation params to create OS 1660 * described memory through NvRmAlloc. Flags are populated with NVOS32_ defines. 1661 */ 1662 typedef struct 1663 { 1664 NvU32 type; // [IN] - surface type, see below TYPE* defines 1665 NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines 1666 NvU32 attr; // [IN] - attributes for memory placement/properties, see below 1667 NvU32 attr2; // [IN] - attributes GPU_CACHEABLE 1668 NvP64 descriptor NV_ALIGN_BYTES(8); // [IN] - descriptor address 1669 NvU64 limit NV_ALIGN_BYTES(8); // [IN] - allocated size -1 1670 NvU32 descriptorType; // [IN] - descriptor type(Virtual | nvmap Handle) 1671 NvU32 tag; // [IN] - memory tag used for debugging 1672 } NV_OS_DESC_MEMORY_ALLOCATION_PARAMS; 1673 1674 /* 1675 * NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS - Allocation params to create a memory 1676 * object from user allocated video memory. Flags are populated with NVOS32_* 1677 * defines. 1678 */ 1679 typedef struct 1680 { 1681 NvU32 flags; // [IN] - allocation modifier flags, see NVOS02_FLAGS* defines 1682 NvU64 physAddr NV_ALIGN_BYTES(8); // [IN] - physical address 1683 NvU64 size NV_ALIGN_BYTES(8); // [IN] - mem size 1684 NvU32 tag; // [IN] - memory tag used for debugging 1685 NvBool bGuestAllocated; // [IN] - Set if memory is guest allocated (mapped by VMMU) 1686 } NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS; 1687 1688 /* 1689 * NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS - Allocation params to create 1690 * memory HW resources through NvRmAlloc. Flags are populated with NVOS32_ 1691 * defines. 1692 */ 1693 typedef struct 1694 { 1695 NvU32 owner; // [IN] - memory owner ID 1696 NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines 1697 NvU32 type; // [IN] - surface type, see below TYPE* defines 1698 1699 NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated 1700 NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated 1701 1702 NvU32 height; 1703 NvU32 width; 1704 NvU32 pitch; 1705 NvU32 alignment; 1706 NvU32 comprCovg; 1707 NvU32 zcullCovg; 1708 1709 NvU32 kind; 1710 1711 NvP64 bindResultFunc NV_ALIGN_BYTES(8); // BindResultFunc 1712 NvP64 pHandle NV_ALIGN_BYTES(8); 1713 NvU64 osDeviceHandle NV_ALIGN_BYTES(8); 1714 NvU64 size NV_ALIGN_BYTES(8); 1715 NvU64 allocAddr NV_ALIGN_BYTES(8); 1716 1717 // [out] from GMMU_COMPR_INFO in drivers/common/shared/inc/mmu/gmmu_fmt.h 1718 NvU32 compPageShift; 1719 NvU32 compressedKind; 1720 NvU32 compTagLineMin; 1721 NvU32 compPageIndexLo; 1722 NvU32 compPageIndexHi; 1723 NvU32 compTagLineMultiplier; 1724 1725 // [out] fallback uncompressed kind. 1726 NvU32 uncompressedKind; 1727 1728 NvU32 tag; // [IN] - memory tag used for debugging 1729 } NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS; 1730 1731 /* function OS33 */ 1732 #define NV04_MAP_MEMORY (0x00000021) 1733 1734 // Legacy map and unmap memory flags that don't use DRF_DEF scheme 1735 #define NV04_MAP_MEMORY_FLAGS_NONE (0x00000000) 1736 #define NV04_MAP_MEMORY_FLAGS_USER (0x00004000) 1737 1738 // New map and unmap memory flags. These flags are used for both NvRmMapMemory 1739 // and for NvRmUnmapMemory. 1740 1741 // Mappings can have restricted permissions (read-only, write-only). Some 1742 // RM implementations may choose to ignore these flags, or they may work 1743 // only for certain memory spaces (system, AGP, video memory); in such cases, 1744 // you may get a read/write mapping even if you asked for a read-only or 1745 // write-only mapping. 1746 #define NVOS33_FLAGS_ACCESS 1:0 1747 #define NVOS33_FLAGS_ACCESS_READ_WRITE (0x00000000) 1748 #define NVOS33_FLAGS_ACCESS_READ_ONLY (0x00000001) 1749 #define NVOS33_FLAGS_ACCESS_WRITE_ONLY (0x00000002) 1750 1751 // Persistent mappings are no longer supported 1752 #define NVOS33_FLAGS_PERSISTENT 4:4 1753 #define NVOS33_FLAGS_PERSISTENT_DISABLE (0x00000000) 1754 #define NVOS33_FLAGS_PERSISTENT_ENABLE (0x00000001) 1755 1756 // This flag is a hack to work around bug 150889. It disables the error 1757 // checking in the RM that verifies that the client is not trying to map 1758 // memory past the end of the memory object. This error checking needs to 1759 // be shut off in some cases for a PAE bug workaround in certain kernels. 1760 #define NVOS33_FLAGS_SKIP_SIZE_CHECK 8:8 1761 #define NVOS33_FLAGS_SKIP_SIZE_CHECK_DISABLE (0x00000000) 1762 #define NVOS33_FLAGS_SKIP_SIZE_CHECK_ENABLE (0x00000001) 1763 1764 // Normally, a mapping is created in the same memory space as the client -- in 1765 // kernel space for a kernel RM client, or in user space for a user RM client. 1766 // However, a kernel RM client can specify MEM_SPACE:USER to create a user-space 1767 // mapping in the current RM client. 1768 #define NVOS33_FLAGS_MEM_SPACE 14:14 1769 #define NVOS33_FLAGS_MEM_SPACE_CLIENT (0x00000000) 1770 #define NVOS33_FLAGS_MEM_SPACE_USER (0x00000001) 1771 1772 // The client can ask for direct memory mapping (i.e. no BAR1) if remappers and 1773 // blocklinear are not required. RM can do direct mapping in this case if 1774 // carveout is available. 1775 // DEFAULT: Use direct mapping if available and no address/data translation 1776 // is necessary; reflected otherwise 1777 // DIRECT: Use direct mapping if available, even if some translation is 1778 // necessary (the client is responsible for translation) 1779 // REFLECTED: Always use reflected mapping 1780 #define NVOS33_FLAGS_MAPPING 16:15 1781 #define NVOS33_FLAGS_MAPPING_DEFAULT (0x00000000) 1782 #define NVOS33_FLAGS_MAPPING_DIRECT (0x00000001) 1783 #define NVOS33_FLAGS_MAPPING_REFLECTED (0x00000002) 1784 1785 // The client requests a fifo mapping but doesn't know the offset or length 1786 // DEFAULT: Do error check length and offset 1787 // ENABLE: Don't error check length and offset but have the RM fill them in 1788 #define NVOS33_FLAGS_FIFO_MAPPING 17:17 1789 #define NVOS33_FLAGS_FIFO_MAPPING_DEFAULT (0x00000000) 1790 #define NVOS33_FLAGS_FIFO_MAPPING_ENABLE (0x00000001) 1791 1792 // The client can require that the CPU mapping be to a specific CPU address 1793 // (akin to MAP_FIXED for mmap). 1794 // DISABLED: RM will map the allocation at a CPU VA that RM selects. 1795 // ENABLED: RM will map the allocation at the CPU VA specified by the address 1796 // pass-back parameter to NvRmMapMemory 1797 // NOTES: 1798 // - Used for controlling CPU addresses in CUDA's unified CPU+GPU virtual 1799 // address space 1800 // - Only valid on NvRmMapMemory 1801 // - Implemented on Unix but not VMware 1802 #define NVOS33_FLAGS_MAP_FIXED 18:18 1803 #define NVOS33_FLAGS_MAP_FIXED_DISABLE (0x00000000) 1804 #define NVOS33_FLAGS_MAP_FIXED_ENABLE (0x00000001) 1805 1806 // The client can specify to the RM that the CPU virtual address range for an 1807 // allocation should remain reserved after the allocation is unmapped. 1808 // DISABLE: When this mapping is destroyed, RM will unmap the CPU virtual 1809 // address space used by this allocation. On Linux this corresponds 1810 // to calling munmap on the CPU VA region. 1811 // ENABLE: When the map object is freed, RM will leave the CPU virtual 1812 // address space used by allocation reserved. On Linux this means 1813 // that RM will overwrite the previous mapping with an anonymous 1814 // mapping of instead calling munmap. 1815 // NOTES: 1816 // - When combined with MAP_FIXED, this allows the client to exert 1817 // significant control over the CPU heap 1818 // - Used in CUDA's unified CPU+GPU virtual address space 1819 // - Valid in nvRmUnmapMemory 1820 // - Valid on NvRmMapMemory (specifies RM's behavior whenever the 1821 // mapping is destroyed, regardless of mechanism) 1822 // - Implemented on Unix but not VMware 1823 #define NVOS33_FLAGS_RESERVE_ON_UNMAP 19:19 1824 #define NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE (0x00000000) 1825 #define NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE (0x00000001) 1826 1827 // Internal use only 1828 #define NVOS33_FLAGS_OS_DESCRIPTOR 22:22 1829 #define NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE (0x00000000) 1830 #define NVOS33_FLAGS_OS_DESCRIPTOR_ENABLE (0x00000001) 1831 1832 // 1833 // For use in the linux mapping path. This flag sets the 1834 // caching mode for pcie BAR mappings (from nv_memory_type.h). 1835 // Internal use only. 1836 // 1837 #define NVOS33_FLAGS_CACHING_TYPE 25:23 1838 #define NVOS33_FLAGS_CACHING_TYPE_CACHED 0 1839 #define NVOS33_FLAGS_CACHING_TYPE_UNCACHED 1 1840 #define NVOS33_FLAGS_CACHING_TYPE_WRITECOMBINED 2 1841 #define NVOS33_FLAGS_CACHING_TYPE_WRITEBACK 5 1842 #define NVOS33_FLAGS_CACHING_TYPE_DEFAULT 6 1843 #define NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK 7 1844 1845 // 1846 // For use when Hopper Confidential Compute is operating in devtools mode 1847 // BAR1 access to CPR vidmem is blocked to CPU-RM by default when HCC is 1848 // enabled in both devtools and prod modes. However, certain mappings are 1849 // allowed to go through successfully only in devtools mode. For example, 1850 // CPU mappings made on behalf of devtools, event buffer mappings are allowed 1851 // to happen in devtools mode 1852 // 1853 #define NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC 26:26 1854 #define NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_NO (0x00000000) 1855 #define NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_YES (0x00000001) 1856 1857 /* parameters */ 1858 typedef struct 1859 { 1860 NvHandle hClient; 1861 NvHandle hDevice; // device or sub-device handle 1862 NvHandle hMemory; // handle to memory object if provided -- NULL if not 1863 NvU64 offset NV_ALIGN_BYTES(8); 1864 NvU64 length NV_ALIGN_BYTES(8); 1865 NvP64 pLinearAddress NV_ALIGN_BYTES(8); // pointer for returned address 1866 NvU32 status; 1867 NvU32 flags; 1868 } NVOS33_PARAMETERS; 1869 1870 1871 /* function OS34 */ 1872 #define NV04_UNMAP_MEMORY (0x00000022) 1873 1874 /* parameters */ 1875 typedef struct 1876 { 1877 NvHandle hClient; 1878 NvHandle hDevice; 1879 NvHandle hMemory; 1880 NvP64 pLinearAddress NV_ALIGN_BYTES(8); // ptr to virtual address of mapped memory 1881 NvU32 status; 1882 NvU32 flags; 1883 } NVOS34_PARAMETERS; 1884 1885 /* function OS38 */ 1886 #define NV04_ACCESS_REGISTRY (0x00000026) 1887 1888 /* parameter values */ 1889 #define NVOS38_ACCESS_TYPE_READ_DWORD 1 1890 #define NVOS38_ACCESS_TYPE_WRITE_DWORD 2 1891 #define NVOS38_ACCESS_TYPE_READ_BINARY 6 1892 #define NVOS38_ACCESS_TYPE_WRITE_BINARY 7 1893 1894 #define NVOS38_MAX_REGISTRY_STRING_LENGTH 256 1895 #define NVOS38_MAX_REGISTRY_BINARY_LENGTH 256 1896 1897 /* parameters */ 1898 typedef struct 1899 { 1900 NvHandle hClient; 1901 NvHandle hObject; 1902 NvV32 AccessType; 1903 1904 NvV32 DevNodeLength; 1905 NvP64 pDevNode NV_ALIGN_BYTES(8); 1906 1907 NvV32 ParmStrLength; 1908 NvP64 pParmStr NV_ALIGN_BYTES(8); 1909 1910 NvV32 BinaryDataLength; 1911 NvP64 pBinaryData NV_ALIGN_BYTES(8); 1912 1913 NvV32 Data; 1914 NvV32 Entry; 1915 NvV32 status; 1916 } NVOS38_PARAMETERS; 1917 1918 #define NV04_ALLOC_CONTEXT_DMA (0x00000027) 1919 1920 /* parameter values are the same as NVOS03 -- not repeated here */ 1921 1922 /* parameters */ 1923 typedef struct 1924 { 1925 NvHandle hObjectParent; 1926 NvHandle hSubDevice; 1927 NvHandle hObjectNew; 1928 NvV32 hClass; 1929 NvV32 flags; 1930 NvU32 selector; 1931 NvHandle hMemory; 1932 NvU64 offset NV_ALIGN_BYTES(8); 1933 NvU64 limit NV_ALIGN_BYTES(8); 1934 NvV32 status; 1935 } NVOS39_PARAMETERS; 1936 1937 1938 #define NV04_GET_EVENT_DATA (0x00000028) 1939 1940 typedef struct 1941 { 1942 NvHandle hObject; 1943 NvV32 NotifyIndex; 1944 1945 // 1946 // Holds same information as that of nvgputypes.h::NvNotification's 1947 // info32 and info16. 1948 // 1949 NvV32 info32; 1950 NvU16 info16; 1951 } NvUnixEvent; 1952 1953 /* parameters */ 1954 typedef struct 1955 { 1956 NvP64 pEvent NV_ALIGN_BYTES(8); 1957 NvV32 MoreEvents; 1958 NvV32 status; 1959 } NVOS41_PARAMETERS; 1960 1961 /* function NVOS43 -- deleted 4/09 */ 1962 /* #define NV04_UNIFIED_FREE (0x0000002B) */ 1963 1964 1965 #define NVSIM01_BUS_XACT (0x0000002C) 1966 1967 /* parameters */ 1968 typedef struct 1969 { 1970 NvHandle hClient; // n/a currently 1971 NvHandle hDevice; // n/a currently 1972 NvU32 offset; // phy bus offset 1973 NvU32 bar; // ~0 := phy addr, {0..2} specify gpu bar 1974 NvU32 bytes; // # of bytes 1975 NvU32 write; // 0 := read request 1976 NvU32 data; // in/out based upon 'write' 1977 NvU32 status; 1978 } NVOS2C_PARAMETERS; 1979 1980 /* function NVOS2D -- deleted 4/09 */ 1981 /* #define NVSIM01_BUS_GET_IFACES (0x0000002D) */ 1982 1983 1984 /* function OS46 */ 1985 #define NV04_MAP_MEMORY_DMA (0x0000002E) 1986 1987 /* parameter values */ 1988 #define NVOS46_FLAGS_ACCESS 1:0 1989 #define NVOS46_FLAGS_ACCESS_READ_WRITE (0x00000000) 1990 #define NVOS46_FLAGS_ACCESS_READ_ONLY (0x00000001) 1991 #define NVOS46_FLAGS_ACCESS_WRITE_ONLY (0x00000002) 1992 1993 // 1994 // Compute shaders support both 32b and 64b pointers. This allows mappings 1995 // to be restricted to the bottom 4GB of the address space. How _DISABLE 1996 // is handled is chip specific and may force a pointer above 4GB. 1997 // 1998 #define NVOS46_FLAGS_32BIT_POINTER 2:2 1999 #define NVOS46_FLAGS_32BIT_POINTER_DISABLE (0x00000000) 2000 #define NVOS46_FLAGS_32BIT_POINTER_ENABLE (0x00000001) 2001 2002 #define NVOS46_FLAGS_PAGE_KIND 3:3 2003 #define NVOS46_FLAGS_PAGE_KIND_PHYSICAL (0x00000000) 2004 #define NVOS46_FLAGS_PAGE_KIND_VIRTUAL (0x00000001) 2005 2006 #define NVOS46_FLAGS_CACHE_SNOOP 4:4 2007 #define NVOS46_FLAGS_CACHE_SNOOP_DISABLE (0x00000000) 2008 #define NVOS46_FLAGS_CACHE_SNOOP_ENABLE (0x00000001) 2009 2010 // The client requests a CPU kernel mapping so that SW class could use it 2011 // DEFAULT: Don't map CPU address 2012 // ENABLE: Map CPU address 2013 #define NVOS46_FLAGS_KERNEL_MAPPING 5:5 2014 #define NVOS46_FLAGS_KERNEL_MAPPING_NONE (0x00000000) 2015 #define NVOS46_FLAGS_KERNEL_MAPPING_ENABLE (0x00000001) 2016 2017 // 2018 // Compute shader access control. 2019 // GPUs that support this feature set the NV0080_CTRL_DMA_CAPS_SHADER_ACCESS_SUPPORTED 2020 // property. These were first supported in Kepler. _DEFAULT will match the ACCESS field. 2021 // 2022 #define NVOS46_FLAGS_SHADER_ACCESS 7:6 2023 #define NVOS46_FLAGS_SHADER_ACCESS_DEFAULT (0x00000000) 2024 #define NVOS46_FLAGS_SHADER_ACCESS_READ_ONLY (0x00000001) 2025 #define NVOS46_FLAGS_SHADER_ACCESS_WRITE_ONLY (0x00000002) 2026 #define NVOS46_FLAGS_SHADER_ACCESS_READ_WRITE (0x00000003) 2027 2028 // 2029 // How the PAGE_SIZE field is interpreted is architecture specific. 2030 // 2031 // On Curie chips it is ignored. 2032 // 2033 // On Tesla it is used to guide is used to select which type PDE 2034 // to use. By default the RM will select 4KB for system memory 2035 // and BIG (64KB) for video memory. BOTH is not supported. 2036 // 2037 // Likewise on Fermi this used to select the PDE type. Fermi cannot 2038 // mix page sizes to a single mapping so the page size is determined 2039 // at surface alloation time. 4KB or BIG may be specified but they 2040 // must match the page size selected at allocation time. DEFAULT 2041 // allows the RM to select either a single page size or both PDE, 2042 // while BOTH forces the RM to select a dual page size PDE. 2043 // 2044 // BIG_PAGE = 64 KB on PASCAL 2045 // = 64 KB or 128 KB on pre_PASCAL chips 2046 // 2047 // HUGE_PAGE = 2 MB on PASCAL 2048 // = not supported on pre_PASCAL chips. 2049 // 2050 #define NVOS46_FLAGS_PAGE_SIZE 11:8 2051 #define NVOS46_FLAGS_PAGE_SIZE_DEFAULT (0x00000000) 2052 #define NVOS46_FLAGS_PAGE_SIZE_4KB (0x00000001) 2053 #define NVOS46_FLAGS_PAGE_SIZE_BIG (0x00000002) 2054 #define NVOS46_FLAGS_PAGE_SIZE_BOTH (0x00000003) 2055 #define NVOS46_FLAGS_PAGE_SIZE_HUGE (0x00000004) 2056 2057 // Some systems allow the device to use the system L3 cache when accessing the 2058 // system memory. For example, the iGPU on T19X can allocate from the system L3 2059 // provided the SoC L3 cache is configured for device allocation. 2060 // 2061 // NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT - Use the default L3 allocation 2062 // policy. When using this policy, device memory access will be coherent with 2063 // non-snooping devices such as the display on Tegra. 2064 // 2065 // NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT - Enable L3 allocation if possible. 2066 // When L3 allocation is enabled, device memory access may be cached, and the 2067 // memory access will be coherent only with other snoop-enabled access. This 2068 // flag is a hint and will be ignored if the system does not support L3 2069 // allocation for the device. NVOS46_FLAGS_CACHE_SNOOP_ENABLE must also be set 2070 // for this flag to be effective. 2071 // 2072 // Note: This flag is implemented only by rmapi_tegra. It is not implemented by 2073 // Resman. 2074 // 2075 #define NVOS46_FLAGS_SYSTEM_L3_ALLOC 13:13 2076 #define NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT (0x00000000) 2077 #define NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT (0x00000001) 2078 2079 #define NVOS46_FLAGS_DMA_OFFSET_GROWS 14:14 2080 #define NVOS46_FLAGS_DMA_OFFSET_GROWS_UP (0x00000000) 2081 #define NVOS46_FLAGS_DMA_OFFSET_GROWS_DOWN (0x00000001) 2082 2083 // 2084 // DMA_OFFSET_FIXED is overloaded for two purposes. 2085 // 2086 // 1. For CTXDMA mappings that use DMA_UNICAST_REUSE_ALLOC_FALSE, 2087 // DMA_OFFSET_FIXED_TRUE indicates to use the dmaOffset parameter 2088 // for a fixed address allocation out of the VA space heap. 2089 // DMA_OFFSET_FIXED_FALSE indicates dmaOffset input will be ignored. 2090 // 2091 // 2. For CTXDMA mappings that use DMA_UNICAST_REUSE_ALLOC_TRUE and 2092 // for *ALL* non-CTXDMA mappings, DMA_OFFSET_FIXED_TRUE indicates 2093 // to treat the input dmaOffset as an absolute virtual address 2094 // instead of an offset relative to the virtual allocation being 2095 // mapped into. Whether relative or absolute, the resulting 2096 // virtual address *must* be contained within the specified 2097 // virtual allocation. 2098 // 2099 // Internally, it is also required that the virtual address be aligned 2100 // to the page size of the mapping (obviously cannot map sub-pages). 2101 // For client flexibility the physical offset does not require page alignment. 2102 // This is handled by adding the physical misalignment 2103 // (internally called pteAdjust) to the returned virtual address. 2104 // The *input* dmaOffset can account for this pteAdjust (or not), 2105 // but the returned virtual address always will. 2106 // 2107 #define NVOS46_FLAGS_DMA_OFFSET_FIXED 15:15 2108 #define NVOS46_FLAGS_DMA_OFFSET_FIXED_FALSE (0x00000000) 2109 #define NVOS46_FLAGS_DMA_OFFSET_FIXED_TRUE (0x00000001) 2110 2111 #define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP 19:16 2112 #define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_DEFAULT (0x00000000) 2113 #define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_1 (0x00000001) 2114 #define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_2 (0x00000002) 2115 #define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_4 (0x00000003) 2116 #define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_8 (0x00000004) 2117 #define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_16 (0x00000005) 2118 #define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_32 (0x00000006) 2119 #define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_64 (0x00000007) 2120 #define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_128 (0x00000008) 2121 #define NVOS46_FLAGS_P2P 27:20 2122 2123 #define NVOS46_FLAGS_P2P_ENABLE 21:20 2124 #define NVOS46_FLAGS_P2P_ENABLE_NO (0x00000000) 2125 #define NVOS46_FLAGS_P2P_ENABLE_YES (0x00000001) 2126 #define NVOS46_FLAGS_P2P_ENABLE_NONE NVOS46_FLAGS_P2P_ENABLE_NO 2127 #define NVOS46_FLAGS_P2P_ENABLE_SLI NVOS46_FLAGS_P2P_ENABLE_YES 2128 #define NVOS46_FLAGS_P2P_ENABLE_NOSLI (0x00000002) 2129 // Subdevice ID. Reserved 3 bits for the possibility of 8-way SLI 2130 #define NVOS46_FLAGS_P2P_SUBDEVICE_ID 24:22 2131 #define NVOS46_FLAGS_P2P_SUBDEV_ID_SRC NVOS46_FLAGS_P2P_SUBDEVICE_ID 2132 #define NVOS46_FLAGS_P2P_SUBDEV_ID_TGT 27:25 2133 #define NVOS46_FLAGS_TLB_LOCK 28:28 2134 #define NVOS46_FLAGS_TLB_LOCK_DISABLE (0x00000000) 2135 #define NVOS46_FLAGS_TLB_LOCK_ENABLE (0x00000001) 2136 #define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC 29:29 2137 #define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE (0x00000000) 2138 #define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE (0x00000001) 2139 // 2140 // This flag must be used with caution. Improper use can leave stale entries in the TLB, 2141 // and allow access to memory no longer owned by the RM client or cause page faults. 2142 // Also see corresponding flag for NvUnmapMemoryDma. 2143 // 2144 #define NVOS46_FLAGS_DEFER_TLB_INVALIDATION 31:31 2145 #define NVOS46_FLAGS_DEFER_TLB_INVALIDATION_FALSE (0x00000000) 2146 #define NVOS46_FLAGS_DEFER_TLB_INVALIDATION_TRUE (0x00000001) 2147 2148 /* parameters */ 2149 typedef struct 2150 { 2151 NvHandle hClient; // [IN] client handle 2152 NvHandle hDevice; // [IN] device handle for mapping 2153 NvHandle hDma; // [IN] dma handle for mapping 2154 NvHandle hMemory; // [IN] memory handle for mapping 2155 NvU64 offset NV_ALIGN_BYTES(8); // [IN] offset of region 2156 NvU64 length NV_ALIGN_BYTES(8); // [IN] limit of region 2157 NvV32 flags; // [IN] flags 2158 NvU64 dmaOffset NV_ALIGN_BYTES(8); // [OUT] offset of mapping 2159 // [IN] if FLAGS_DMA_OFFSET_FIXED_TRUE 2160 // *OR* hDma is NOT a CTXDMA handle 2161 // (see NVOS46_FLAGS_DMA_OFFSET_FIXED) 2162 NvV32 status; // [OUT] status 2163 } NVOS46_PARAMETERS; 2164 2165 2166 /* function OS47 */ 2167 #define NV04_UNMAP_MEMORY_DMA (0x0000002F) 2168 2169 #define NVOS47_FLAGS_DEFER_TLB_INVALIDATION 0:0 2170 #define NVOS47_FLAGS_DEFER_TLB_INVALIDATION_FALSE (0x00000000) 2171 #define NVOS47_FLAGS_DEFER_TLB_INVALIDATION_TRUE (0x00000001) 2172 2173 /* parameters */ 2174 typedef struct 2175 { 2176 NvHandle hClient; // [IN] client handle 2177 NvHandle hDevice; // [IN] device handle for mapping 2178 NvHandle hDma; // [IN] dma handle for mapping 2179 NvHandle hMemory; // [IN] memory handle for mapping 2180 NvV32 flags; // [IN] flags 2181 NvU64 dmaOffset NV_ALIGN_BYTES(8); // [IN] dma offset from NV04_MAP_MEMORY_DMA 2182 NvU64 size NV_ALIGN_BYTES(8); // [IN] size to unmap, 0 to unmap entire mapping 2183 NvV32 status; // [OUT] status 2184 } NVOS47_PARAMETERS; 2185 2186 2187 #define NV04_BIND_CONTEXT_DMA (0x00000031) 2188 /* parameters */ 2189 typedef struct 2190 { 2191 NvHandle hClient; // [IN] client handle 2192 NvHandle hChannel; // [IN] channel handle for binding 2193 NvHandle hCtxDma; // [IN] ctx dma handle for binding 2194 NvV32 status; // [OUT] status 2195 } NVOS49_PARAMETERS; 2196 2197 2198 /* function OS54 */ 2199 #define NV04_CONTROL (0x00000036) 2200 2201 #define NVOS54_FLAGS_NONE (0x00000000) 2202 #define NVOS54_FLAGS_IRQL_RAISED (0x00000001) 2203 #define NVOS54_FLAGS_LOCK_BYPASS (0x00000002) 2204 #define NVOS54_FLAGS_FINN_SERIALIZED (0x00000004) 2205 2206 /* parameters */ 2207 typedef struct 2208 { 2209 NvHandle hClient; 2210 NvHandle hObject; 2211 NvV32 cmd; 2212 NvU32 flags; 2213 NvP64 params NV_ALIGN_BYTES(8); 2214 NvU32 paramsSize; 2215 NvV32 status; 2216 } NVOS54_PARAMETERS; 2217 2218 /* RM Control header 2219 * 2220 * Replacement for NVOS54_PARAMETERS where embedded pointers are not allowed. 2221 * Input layout for user space RM Control calls should be: 2222 * 2223 * +--- NVOS63_PARAMETERS ---+--- RM Control parameters ---+ 2224 * 2225 * NVOS63_PARAMETERS::paramsSize is the size of RM Control parameters 2226 * 2227 */ 2228 typedef struct 2229 { 2230 NvHandle hClient; // [IN] client handle 2231 NvHandle hObject; // [IN] object handle 2232 NvV32 cmd; // [IN] control command ID 2233 NvU32 paramsSize; // [IN] size in bytes of the RM Control parameters 2234 NvV32 status; // [OUT] status 2235 } NVOS63_PARAMETERS; 2236 2237 2238 /* function OS55 */ 2239 #define NV04_DUP_OBJECT (0x00000037) 2240 2241 /* parameters */ 2242 typedef struct 2243 { 2244 NvHandle hClient; // [IN] destination client handle 2245 NvHandle hParent; // [IN] parent of new object 2246 NvHandle hObject; // [INOUT] destination (new) object handle 2247 NvHandle hClientSrc; // [IN] source client handle 2248 NvHandle hObjectSrc; // [IN] source (old) object handle 2249 NvU32 flags; // [IN] flags 2250 NvU32 status; // [OUT] status 2251 } NVOS55_PARAMETERS; 2252 2253 #define NV04_DUP_HANDLE_FLAGS_NONE (0x00000000) 2254 #define NV04_DUP_HANDLE_FLAGS_REJECT_KERNEL_DUP_PRIVILEGE (0x00000001) // If set, prevents an RM kernel client from duping unconditionally 2255 // NOTE: Do not declare a NV04_DUP_HANDLE_FLAGS_* value of 0x00000008 2256 // until Bug 2859347 is resolved! This is due to conflicting usage 2257 // of RS_RES_DUP_PARAMS_INTERNAL.flags to pass 2258 // NVOS32_ALLOC_INTERNAL_FLAGS_FLA_MEMORY to an object constructor. 2259 2260 /* function OS56 */ 2261 #define NV04_UPDATE_DEVICE_MAPPING_INFO (0x00000038) 2262 2263 /* parameters */ 2264 typedef struct 2265 { 2266 NvHandle hClient; 2267 NvHandle hDevice; 2268 NvHandle hMemory; 2269 NvP64 pOldCpuAddress NV_ALIGN_BYTES(8); 2270 NvP64 pNewCpuAddress NV_ALIGN_BYTES(8); 2271 NvV32 status; 2272 } NVOS56_PARAMETERS; 2273 2274 /* function OS57 */ 2275 #define NV04_SHARE (0x0000003E) 2276 2277 /* parameters */ 2278 typedef struct 2279 { 2280 NvHandle hClient; // [IN] owner client handle 2281 NvHandle hObject; // [IN] resource to share 2282 RS_SHARE_POLICY sharePolicy; // [IN] share policy entry 2283 NvU32 status; // [OUT] status 2284 } NVOS57_PARAMETERS; 2285 2286 /* parameters */ 2287 typedef struct 2288 { 2289 NvU32 deviceReference; 2290 NvU32 head; 2291 NvU32 state; 2292 NvU8 forceMonitorState; 2293 NvU8 bForcePerfBiosLevel; 2294 NvU8 bIsD3HotTransition; // [OUT] To tell client if it's a D3Hot transition 2295 NvU32 fastBootPowerState; 2296 } NVPOWERSTATE_PARAMETERS, *PNVPOWERSTATE_PARAMETERS; 2297 2298 /***************************************************************************\ 2299 |* Object Allocation Parameters *| 2300 \***************************************************************************/ 2301 2302 // GR engine creation parameters 2303 typedef struct { 2304 NvU32 version; // set to 0x2 2305 NvU32 flags; // input param from a rm client (no flags are currently defined) 2306 NvU32 size; // sizeof(NV_GR_ALLOCATION_PARAMETERS) 2307 NvU32 caps; // output param for a rm client - class dependent 2308 } NV_GR_ALLOCATION_PARAMETERS; 2309 2310 // 2311 // NvAlloc parameters for NV03_DEVICE_XX class 2312 // hClientShare 2313 // For NV50+ this can be set to virtual address space for this 2314 // device. On previous chips this field is ignored. There are 2315 // three possible settings 2316 // NV01_NULL_OBJECT - Use the default global VA space 2317 // Handle to current client - Create a new private address space 2318 // Handle to another client - Attach to other clients address space 2319 // flags 2320 // MAP_PTE_GLOBALLY Deprecated. 2321 // MINIMIZE_PTETABLE_SIZE Pass hint to DMA HAL to use partial page 2322 // tables. Depending on allocation pattern 2323 // this may actually use more instance memory. 2324 // RETRY_PTE_ALLOC_IN_SYS Fallback to PTEs allocation in sysmem. This 2325 // is now enabled by default. 2326 // VASPACE_SIZE Honor vaSpaceSize field. 2327 // 2328 // MAP_PTE Deprecated. 2329 // 2330 // VASPACE_IS_MIRRORED This flag will tell RM to create a mirrored 2331 // kernel PDB for the address space associated 2332 // with this device. When this flag is set 2333 // the address space covered by the top PDE 2334 // is restricted and cannot be allocated out of. 2335 // 2336 // 2337 // VASPACE_BIG_PAGE_SIZE_64k ***Warning this flag will be deprecated do not use***** 2338 // VASPACE_BIG_PAGE_SIZE_128k This flag will choose the big page size of the VASPace 2339 // to 64K/128k if the system supports a configurable size. 2340 // If the system does not support a configurable size then 2341 // defaults will be chosen. 2342 // If the user sets both these bits then this API will fail. 2343 // 2344 // SHARED_MANAGEMENT 2345 // *** Warning: This will be deprecated - see NV_VASPACE_ALLOCATION_PARAMETERS. *** 2346 // 2347 // 2348 // hTargetClient/hTargetDevice 2349 // Deprecated. Can be deleted once client code has removed references. 2350 // 2351 // vaBase 2352 // *** Warning: This will be deprecated - see NV_VASPACE_ALLOCATION_PARAMETERS. *** 2353 // 2354 // vaSpaceSize 2355 // Set the size of the VA space used for this client if allocating 2356 // a new private address space. Is expressed as a size such as 2357 // (1<<32) for a 32b address space. Reducing the size of the address 2358 // space allows the dma chip specific code to reduce the instance memory 2359 // used for page tables. 2360 // 2361 // vaMode 2362 // The vaspace allocation mode. There are three modes supported: 2363 // 1. SINGLE_VASPACE 2364 // An old abstraction that provides a single VA space under a 2365 // device and it's allocated implicityly when an object requires a VA 2366 // space. Typically, this VA space is also shared across clients. 2367 // 2368 // 2. OPTIONAL_MULTIPLE_VASPACES 2369 // Global + multiple private va spaces. In this mode, the old abstraction, 2370 // a single vaspace under a device that is allocated implicitly is still 2371 // being supported. A private VA space is an entity under a device, which/ 2372 // cannot be shared with other clients, but multiple channels under the 2373 // same device can still share a private VA space. 2374 // Private VA spaces (class:90f1,FERMI_VASPACE_A) can be allocated as 2375 // objects through RM APIs. This mode requires the users to know what they 2376 // are doing in terms of using VA spaces. Page fault can easily occur if 2377 // one is not careful with a mixed of an implicit VA space and multiple 2378 // VA spaces. 2379 // 2380 // 3. MULTIPLE_VASPACES 2381 // In this mode, all VA spaces have to be allocated explicitly through RM 2382 // APIs and users have to specify which VA space to use for each object. 2383 // This case prevents users to use context dma, which is not supported and 2384 // can be misleading if used. Therefore, it's more a safeguard mode to 2385 // prevent people making mistakes that are hard to debug. 2386 // 2387 // DEFAULT MODE: 2. OPTIONAL_MULTIPLE_VASPACES 2388 // 2389 // See NV0080_ALLOC_PARAMETERS for allocation parameter structure. 2390 // 2391 2392 #define NV_DEVICE_ALLOCATION_SZNAME_MAXLEN 128 2393 #define NV_DEVICE_ALLOCATION_FLAGS_NONE (0x00000000) 2394 #define NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE_GLOBALLY (0x00000001) 2395 #define NV_DEVICE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE (0x00000002) 2396 #define NV_DEVICE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS (0x00000004) 2397 #define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SIZE (0x00000008) 2398 #define NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE (0x00000010) 2399 #define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_TARGET (0x00000020) 2400 #define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SHARED_MANAGEMENT (0x00000100) 2401 #define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_64k (0x00000200) 2402 #define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_128k (0x00000400) 2403 #define NV_DEVICE_ALLOCATION_FLAGS_RESTRICT_RESERVED_VALIMITS (0x00000800) 2404 2405 /* 2406 *TODO: Delete this flag once CUDA moves to the ctrl call 2407 */ 2408 #define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_MIRRORED (0x00000040) 2409 2410 // XXX NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED should not 2411 // should not be exposed to clients. It should be the default RM 2412 // behavior. 2413 // 2414 // Until it is made the default, certain clients such as OpenGL 2415 // might still need PTABLE allocations to go through PMA, so this 2416 // flag has been temporary exposed. 2417 // 2418 // See bug 1880192 2419 #define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED (0x00001000) 2420 2421 // 2422 // Indicates this device is being created by guest and requires a 2423 // KernelHostVgpuDeviceApi creation in client. 2424 // 2425 #define NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE (0x00002000) 2426 2427 // 2428 // Indicates this device is being created for VGPU plugin use. 2429 // Requires a HostVgpuDevice handle to indicate the guest on which 2430 // this plugin operates. 2431 // 2432 #define NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT (0x00004000) 2433 2434 // 2435 // For clients using unlinked SLI to catch allocations attempts on secondary GPUs 2436 // not accompanied by a fixed offset. 2437 // 2438 #define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_REQUIRE_FIXED_OFFSET (0x00008000) 2439 2440 #define NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES (0x00000000) 2441 #define NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE (0x00000001) 2442 #define NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES (0x00000002) 2443 2444 2445 #define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR 0x00000000 2446 #define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN 0x00000001 2447 #define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_KEY_ROTATION_STATUS 0x00000002 2448 #define NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 3 2449 #define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_VALUE 14:0 2450 #define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS 15:15 2451 #define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE 0x1 2452 #define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_FALSE 0x0 2453 2454 typedef struct 2455 { 2456 NvV32 channelInstance; // One of the n channel instances of a given channel type. 2457 // Note that core channel has only one instance 2458 // while all others have two (one per head). 2459 NvHandle hObjectBuffer; // ctx dma handle for DMA push buffer 2460 NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors/notifications 2461 NvU32 offset; // Initial offset for put/get, usually zero. 2462 NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of UDISP GET/PUT regs 2463 2464 NvU32 flags; 2465 #define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB 1:1 2466 #define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES 0x00000000 2467 #define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO 0x00000001 2468 2469 } NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS; 2470 2471 typedef struct 2472 { 2473 NvV32 channelInstance; // One of the n channel instances of a given channel type. 2474 // All PIO channels have two instances (one per head). 2475 NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors. 2476 NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of control region for PIO channel 2477 } NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS; 2478 2479 // Used for allocating a channel group 2480 typedef struct 2481 { 2482 NvHandle hObjectError; // Error notifier for TSG 2483 NvHandle hObjectEccError; // ECC Error notifier for TSG 2484 NvHandle hVASpace; // VA space handle for TSG 2485 NvU32 engineType; // Engine to which all channels in this TSG are associated with 2486 NvBool bIsCallingContextVgpuPlugin; 2487 } NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS; 2488 2489 /* 2490 * @params: 2491 * @engineId : Engine to which the software runlist be associated with. 2492 * @maxTSGs : Maximum number of TSG entries that will be submitted in this software runlist 2493 * The size of the runlist buffer will be determined by 2494 * 2 * // double buffer 2495 * maxTSGs * // determined by KMD 2496 * maxChannelPerTSG * // Determined by RM 2497 * sizeof(RunlistEntry) // Determined by HW format 2498 * @qosIntrEnableMask: QOS Interrupt bitmask that needs to be enabled for the SW runlist defined below. 2499 */ 2500 typedef struct 2501 { 2502 NvU32 engineId; //(IN) 2503 NvU32 maxTSGs; //(IN) // Size of the RM could return error if the request cannot be accommodated. 2504 NvU32 qosIntrEnableMask; //(IN) // Bitmask for QOS interrupts that needs to be enabled 2505 } NV_SWRUNLIST_ALLOCATION_PARAMS; 2506 2507 #define NV_SWRUNLIST_QOS_INTR_NONE 0x00000000 2508 #define NV_SWRUNLIST_QOS_INTR_RUNLIST_AND_ENG_IDLE_ENABLE NVBIT32(0) 2509 #define NV_SWRUNLIST_QOS_INTR_RUNLIST_IDLE_ENABLE NVBIT32(1) 2510 #define NV_SWRUNLIST_QOS_INTR_RUNLIST_ACQUIRE_ENABLE NVBIT32(2) 2511 #define NV_SWRUNLIST_QOS_INTR_RUNLIST_ACQUIRE_AND_ENG_IDLE_ENABLE NVBIT32(3) 2512 2513 typedef struct 2514 { 2515 NvU32 size; 2516 NvU32 caps; 2517 } NV_ME_ALLOCATION_PARAMETERS; 2518 2519 typedef struct 2520 { 2521 NvU32 size; 2522 NvU32 prohibitMultipleInstances; 2523 NvU32 engineInstance; // Select NVDEC0 or NVDEC1 or NVDEC2 2524 } NV_BSP_ALLOCATION_PARAMETERS; 2525 2526 // 2527 // These are referenced by mdiag mods tests, but do not appear to be used during 2528 // in the RM any longer 2529 // 2530 #define NV_VP_ALLOCATION_FLAGS_STANDARD_UCODE (0x00000000) 2531 #define NV_VP_ALLOCATION_FLAGS_STATIC_UCODE (0x00000001) 2532 #define NV_VP_ALLOCATION_FLAGS_DYNAMIC_UCODE (0x00000002) 2533 2534 // 2535 // NV_VP_ALLOCATION_PARAMETERS.flags 2536 // 2537 // NV_VP_ALLOCATION_FLAGS_AVP_CLIENT are used by Tegra to specify if 2538 // the current allocation with be used by Video or Audio 2539 // 2540 #define NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_VIDEO (0x00000000) 2541 #define NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_AUDIO (0x00000001) 2542 2543 typedef struct 2544 { 2545 NvU32 size; 2546 NvU32 caps; 2547 NvU32 flags; 2548 NvU32 altUcode; 2549 NvP64 rawUcode NV_ALIGN_BYTES(8); 2550 NvU32 rawUcodeSize; 2551 NvU32 numSubClasses; 2552 NvU32 numSubSets; 2553 NvP64 subClasses NV_ALIGN_BYTES(8); 2554 NvU32 prohibitMultipleInstances; 2555 NvP64 pControl NV_ALIGN_BYTES(8); // Used by Tegra to return a mapping to NvE276Control 2556 NvHandle hMemoryCmdBuffer NV_ALIGN_BYTES(8); // Used by Tegra to specify cmd buffer 2557 NvU64 offset NV_ALIGN_BYTES(8); // Used by Tegra to specify an offset into the cmd buffer 2558 2559 } NV_VP_ALLOCATION_PARAMETERS; 2560 2561 typedef struct 2562 { 2563 NvU32 size; 2564 NvU32 prohibitMultipleInstances; 2565 } NV_PPP_ALLOCATION_PARAMETERS; 2566 2567 typedef struct 2568 { 2569 NvU32 size; 2570 NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of MSENC? 2571 NvU32 engineInstance; // Select MSENC/NVENC0 or NVENC1 or NVENC2 2572 } NV_MSENC_ALLOCATION_PARAMETERS; 2573 2574 typedef struct 2575 { 2576 NvU32 size; 2577 NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of SEC2? 2578 } NV_SEC2_ALLOCATION_PARAMETERS; 2579 2580 typedef struct 2581 { 2582 NvU32 size; 2583 NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of NVJPG? 2584 NvU32 engineInstance; 2585 } NV_NVJPG_ALLOCATION_PARAMETERS; 2586 2587 typedef struct 2588 { 2589 NvU32 size; 2590 NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of OFA? 2591 NvU32 engineInstance; 2592 } NV_OFA_ALLOCATION_PARAMETERS; 2593 2594 #define NV04_ADD_VBLANK_CALLBACK (0x0000003D) 2595 2596 #include "class/cl9010.h" // for OSVBLANKCALLBACKPROC 2597 2598 /* parameters */ 2599 /* NOTE: the "void* pParm's" below are ok (but unfortunate) since this interface 2600 can only be used by other kernel drivers which must share the same ptr-size */ 2601 typedef struct 2602 { 2603 NvHandle hClient; // [IN] client handle 2604 NvHandle hDevice; // [IN] device handle for mapping 2605 NvHandle hVblank; // [IN] Vblank handle for control 2606 OSVBLANKCALLBACKPROC pProc; // Routine to call at vblank time 2607 2608 NvV32 LogicalHead; // Logical Head 2609 void *pParm1; 2610 void *pParm2; 2611 NvU32 bAdd; // Add or Delete 2612 NvV32 status; // [OUT] status 2613 } NVOS61_PARAMETERS; 2614 2615 /** 2616 * @brief NvAlloc parameters for VASPACE classes 2617 * 2618 * Used to create a new private virtual address space. 2619 * 2620 * index 2621 * Tegra: With TEGRA_VASPACE_A, index specifies the IOMMU 2622 * virtual address space to be created. Based on the 2623 * index, RM/NVMEM will decide the HW ASID to be used with 2624 * this VA Space. "index" takes values from the 2625 * NVMEM_CLIENT_* defines in 2626 * "drivers/common/inc/tegra/memory/ioctl.h". 2627 * 2628 * Big GPU: With FERMI_VASPACE_A, see NV_VASPACE_ALLOCATION_INDEX_GPU_*. 2629 * 2630 * flags 2631 * MINIMIZE_PTETABLE_SIZE Pass hint to DMA HAL to use partial page tables. 2632 * Depending on allocation pattern this may actually 2633 * use more instance memory. 2634 * 2635 * RETRY_PTE_ALLOC_IN_SYS Fallback to PTEs allocation in sysmem. This is now 2636 * enabled by default. 2637 * 2638 * SHARED_MANAGEMENT 2639 * Indicates management of the VA space is shared with another 2640 * component (e.g. driver layer, OS, etc.). 2641 * 2642 * The initial VA range from vaBase (inclusive) through vaSize (exclusive) 2643 * is managed by RM. The range must be aligned to a top-level PDE's VA 2644 * coverage since backing page table levels for this range are managed by RM. 2645 * All normal RM virtual memory management APIs work within this range. 2646 * 2647 * An external component can manage the remaining VA ranges, 2648 * from 0 (inclusive) to vaBase (exclusive) and from vaSize (inclusive) up to the 2649 * maximum VA limit supported by HW. 2650 * Management of these ranges includes VA sub-allocation and the 2651 * backing lower page table levels. 2652 * 2653 * The top-level page directory is special since it is a shared resource. 2654 * Management of the page directory is as follows: 2655 * 1. Initially RM allocates a page directory for RM-managed PDEs. 2656 * 2. The external component may create a full page directory and commit it 2657 * with NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY. 2658 * This will copy the RM-managed PDEs from the RM-managed page directory 2659 * into the external page directory and commit channels to the external page directory. 2660 * After this point RM will update the external page directory directly for 2661 * operations that modify RM-managed PDEs. 2662 * 3. The external component may use NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY repeatedly 2663 * if it needs to update the page directory again (e.g. to resize or migrate). 2664 * This will copy the RM-managed PDEs from the old external page directory 2665 * into the new external page directory and commit channels to the new page directory. 2666 * 4. The external component may restore management of the page directory back to 2667 * RM with NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY. 2668 * This will copy the RM-managed PDEs from the external page directory 2669 * into the RM-managed page directory and commit channels to the RM-managed page directory. 2670 * After this point RM will update the RM-managed page directory for 2671 * operations that modify RM-managed PDEs. 2672 * Note that operations (2) and (4) are symmetric - the RM perspective of management is identical 2673 * before and after a sequence of SET => ... => UNSET. 2674 * 2675 * IS_MIRRORED <to be deprecated once CUDA uses EXTERNALLY_MANAGED> 2676 * This flag will tell RM to create a mirrored 2677 * kernel PDB for the address space associated 2678 * with this device. When this flag is set 2679 * the address space covered by the top PDE 2680 * is restricted and cannot be allocated out of. 2681 * ENABLE_PAGE_FAULTING 2682 * Enable page faulting if the architecture supports it. 2683 * As of now page faulting is only supported for compute on pascal+. 2684 * IS_EXTERNALLY_OWNED 2685 * This vaspace that has been allocated will be managed by 2686 * an external driver. RM will not own the pagetables for this vaspace. 2687 * 2688 * ENABLE_NVLINK_ATS 2689 * Enables VA translation for this address space using NVLINK ATS. 2690 * Note, the GMMU page tables still exist and take priority over NVLINK ATS. 2691 * VA space object creation will fail if: 2692 * - hardware support is not available (NV_ERR_NOT_SUPPORTED) 2693 * - incompatible options IS_MIRRORED or IS_EXTERNALLY_OWNED are set (NV_ERR_INVALID_ARGUMENT) 2694 * IS_FLA 2695 * Sets FLA flag for this VASPACE 2696 * 2697 * ALLOW_ZERO_ADDRESS 2698 * Allows VASPACE Range to start from zero 2699 * SKIP_SCRUB_MEMPOOL 2700 * Skip scrubbing in MemPool 2701 * 2702 * vaBase [in, out] 2703 * On input, the lowest usable base address of the VA space. 2704 * If 0, RM will pick a default value - 0 is always reserved to respresent NULL pointers. 2705 * The value must be aligned to the largest page size of the VA space. 2706 * Larger values aid in debug since offsets added to NULL pointers will still fault. 2707 * 2708 * On output, the actual usable base address is returned. 2709 * 2710 * vaSize [in,out] 2711 * On input, requested size of the virtual address space in bytes. 2712 * Requesting a smaller size reduces the memory required for the initial 2713 * page directory, but the VAS may be resized later (NV0080_CTRL_DMA_SET_VA_SPACE_SIZE). 2714 * If 0, the default VA space size will be used. 2715 * 2716 * On output, the actual size of the VAS in bytes. 2717 * NOTE: This corresponds to the VA_LIMIT + 1, so the usable size is (vaSize - vaBase). 2718 * 2719 * bigPageSIze 2720 * Set the size of the big page in this address space object. Current HW supports 2721 * either 64k or 128k as the size of the big page. HW that support multiple big 2722 * page size per address space will use this size. Hw that do not support this feature 2723 * will override to the default big page size that is supported by the system. 2724 * If the big page size value is set to ZERO then we will pick the default page size 2725 * of the system. 2726 **/ 2727 typedef struct 2728 { 2729 NvU32 index; 2730 NvV32 flags; 2731 NvU64 vaSize NV_ALIGN_BYTES(8); 2732 NvU64 vaStartInternal NV_ALIGN_BYTES(8); 2733 NvU64 vaLimitInternal NV_ALIGN_BYTES(8); 2734 NvU32 bigPageSize; 2735 NvU64 vaBase NV_ALIGN_BYTES(8); 2736 } NV_VASPACE_ALLOCATION_PARAMETERS; 2737 2738 #define NV_VASPACE_ALLOCATION_FLAGS_NONE (0x00000000) 2739 #define NV_VASPACE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE BIT(0) 2740 #define NV_VASPACE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS BIT(1) 2741 #define NV_VASPACE_ALLOCATION_FLAGS_SHARED_MANAGEMENT BIT(2) 2742 #define NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED BIT(3) 2743 #define NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS BIT(4) 2744 #define NV_VASPACE_ALLOCATION_FLAGS_IS_MIRRORED BIT(5) 2745 #define NV_VASPACE_ALLOCATION_FLAGS_ENABLE_PAGE_FAULTING BIT(6) 2746 #define NV_VASPACE_ALLOCATION_FLAGS_VA_INTERNAL_LIMIT BIT(7) 2747 #define NV_VASPACE_ALLOCATION_FLAGS_ALLOW_ZERO_ADDRESS BIT(8) 2748 #define NV_VASPACE_ALLOCATION_FLAGS_IS_FLA BIT(9) 2749 #define NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL BIT(10) 2750 #define NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE BIT(11) 2751 #define NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET BIT(12) 2752 #define NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED BIT(13) 2753 2754 #define NV_VASPACE_ALLOCATION_INDEX_GPU_NEW 0x00 //<! Create new VASpace, by default 2755 #define NV_VASPACE_ALLOCATION_INDEX_GPU_HOST 0x01 //<! Acquire reference to BAR1 VAS. 2756 #define NV_VASPACE_ALLOCATION_INDEX_GPU_GLOBAL 0x02 //<! Acquire reference to global VAS. 2757 #define NV_VASPACE_ALLOCATION_INDEX_GPU_DEVICE 0x03 //<! Acquire reference to device vaspace 2758 #define NV_VASPACE_ALLOCATION_INDEX_GPU_FLA 0x04 //<! Acquire reference to FLA VAS. 2759 #define NV_VASPACE_ALLOCATION_INDEX_GPU_MAX 0x05 //<! Increment this on adding index entries 2760 2761 2762 #define NV_VASPACE_BIG_PAGE_SIZE_64K (64 * 1024) 2763 #define NV_VASPACE_BIG_PAGE_SIZE_128K (128 * 1024) 2764 2765 /** 2766 * @brief NvAlloc parameters for FERMI_CONTEXT_SHARE_A class 2767 * 2768 * Used to create a new context share object for use by a TSG channel. 2769 * Context share is now used to represent a subcontext within a TSG. 2770 * Refer subcontexts-rm-design.docx for more details. 2771 * 2772 * hVASpace 2773 * Handle of VA Space object associated with the context share. 2774 * All channels using the same using the context share the same va space. 2775 * 2776 * flags 2777 * Options for the context share allocation. 2778 * 2779 * NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT 2780 * Used to specify the subcontext slot 2781 * SYNC 2782 * Use synchronous graphics & compute subcontext 2783 * In VOLTA+ chips, this represent VEID 0 2784 * In pre-VOLTA chips, this represent SCG type 0 2785 * ASYNC 2786 * Use asynchronous compute subcontext 2787 * In VOLTA+ chips, this represent a VEID greater than 0 2788 * In pre-VOLTA chips, this represent SCG type 1 2789 * SPECIFIED 2790 * Force the VEID specified in the subctxId parameter. 2791 * This flag is intended for verif. i.e testing VEID reuse etc. 2792 * 2793 * subctxId 2794 * As input, it is used to specify the subcontext ID, when the _SPECIFIED flag is set. 2795 * As output, it is used to return the subcontext ID allocated by RM. 2796 * This field is intended for verif. 2797 **/ 2798 2799 typedef struct 2800 { 2801 NvHandle hVASpace; 2802 NvU32 flags; 2803 NvU32 subctxId; 2804 } NV_CTXSHARE_ALLOCATION_PARAMETERS; 2805 2806 #define NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT 1:0 2807 #define NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SYNC (0x00000000) 2808 #define NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC (0x00000001) 2809 #define NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SPECIFIED (0x00000002) 2810 2811 /** 2812 * @brief RmTimeoutControl parameters 2813 * 2814 * Used to set various timeout-related features in RM. 2815 * 2816 * cmd 2817 * The timeout-related command to issue to RM. 2818 * 2819 * value 2820 * Used by command, such as the timeout to be set, in milliseconds. 2821 **/ 2822 2823 typedef struct 2824 { 2825 NvU32 cmd; 2826 NvU32 timeoutInMs; 2827 NvU32 deviceInstance; 2828 } NV_TIMEOUT_CONTROL_PARAMETERS; 2829 2830 #define NV_TIMEOUT_CONTROL_CMD_SET_DEVICE_TIMEOUT (0x00000002) 2831 #define NV_TIMEOUT_CONTROL_CMD_RESET_DEVICE_TIMEOUT (0x00000003) 2832 2833 // NV_TIMEOUT_CONTROL_CMD_SET_DEVICE_TIMEOUT sets a maximum timeout value for 2834 // any RM call on a specific device on any thread. It uses 'timeoutInMs' 2835 // as the target timeout and 'deviceInstance' as the target device. 2836 2837 // NV_TIMEOUT_CONTROL_CMD_RESET_DEVICE_TIMEOUT resets the device timeout to its 2838 // default value. It uses 'deviceInstance' as the target device. 2839 2840 /** 2841 * @brief GspTestGetRpcMessageData parameters 2842 * 2843 * This API is used by the user-mode GSP firmware RM to get RPC message data 2844 * from the kernel-mode GSP client RM. 2845 * 2846 * This API is only supported in the GSP testbed environment. 2847 * 2848 * blockNum 2849 * Specifies block number of message data to return. A value of 0 2850 * indicates that the (default) message header and body should be returned 2851 * in the buffer. If additional RPC-specific data is required it can 2852 * be read by continually incrementing the block number and reading the 2853 * next block in sequence. 2854 * msgBufferSize 2855 * Size (in bytes) of buffer pointed to by pMsgBuffer. 2856 * pMsgBuffer 2857 * Address of user-buffer into which RPC message data will be copied. 2858 * status 2859 * Returns status of call. 2860 **/ 2861 typedef struct 2862 { 2863 NvU32 blockNum; // [IN] block # of data to get 2864 NvU32 bufferSize; // [IN] size of pBuffer 2865 NvP64 pBuffer NV_ALIGN_BYTES(8); // [OUT] buffer returning data 2866 NvV32 status; // [OUT] status of call 2867 } NV_GSP_TEST_GET_MSG_BLOCK_PARAMETERS; 2868 2869 /** 2870 * @brief GspTestSendRpcMessageResponse parameters 2871 * 2872 * This API is used to by the user-mode GSP firmware RM to send an RPC message 2873 * response to the kernel-mode GSP client RM. 2874 * 2875 * This API is only supported in the GSP testbed environment. 2876 * 2877 * bufferSize 2878 * Size (in bytes) of buffer pointed to by pBuffer. 2879 * pBuffer 2880 * Address of user-buffer from which RPC response data will be copied. 2881 * status 2882 * Returns status of call. 2883 **/ 2884 typedef struct 2885 { 2886 NvU32 bufferSize; // [IN] size of response data buffer 2887 NvP64 pBuffer NV_ALIGN_BYTES(8); // [IN] response data buffer 2888 NvV32 status; // [OUT] status of call 2889 } NV_GSP_TEST_SEND_MSG_RESPONSE_PARAMETERS; 2890 2891 /** 2892 * @brief GspTestSendEventNotification parameters 2893 * 2894 * This API is used by the user-mode GSP firmware RM to send an event 2895 * notification to the kernel-mode GSP client RM. 2896 * 2897 * This API is only supported in the GSP testbed environment. 2898 * 2899 * hParentClient 2900 * Specifies handle of client that owns object associated with event. 2901 * hSrcResource 2902 * Specifies handle of object associated with event. 2903 * hClass 2904 * Specifies class number (type) of event. 2905 * notifyIndex 2906 * Specifies notifier index associated with event. 2907 * status 2908 * Returns status of call. 2909 **/ 2910 typedef struct 2911 { 2912 NvHandle hParentClient; // [IN] handle of client 2913 NvHandle hSrcResource; // [IN] handle of object 2914 NvU32 hClass; // [IN] class number of event 2915 NvU32 notifyIndex; // [IN] notifier index 2916 NvV32 status; // [OUT] status of call 2917 } NV_GSP_TEST_SEND_EVENT_NOTIFICATION_PARAMETERS; 2918 2919 /* 2920 * NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH 2921 * NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT 2922 * Location is Coherent System memory (also the default option) 2923 * NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH 2924 * Location is Non-Coherent System memory 2925 * NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID 2926 * Location is FB 2927 * 2928 * Currently only used by MODS for the V1 VAB interface. To be deleted. 2929 */ 2930 typedef enum 2931 { 2932 NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT = 0, 2933 NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH, 2934 NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH, 2935 NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID 2936 } NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE; 2937 2938 /** 2939 * @brief Multiclient vidmem access bit allocation params 2940 */ 2941 typedef struct 2942 { 2943 /* [OUT] Dirty/Access tracking */ 2944 NvBool bDirtyTracking; 2945 /* [OUT] Current tracking granularity */ 2946 NvU32 granularity; 2947 /* [OUT] 512B Access bit mask with 1s set on 2948 bits that are reserved for this client */ 2949 NV_DECLARE_ALIGNED(NvU64 accessBitMask[64], 8); 2950 /* Number of entries of vidmem access buffer. Used by VAB v1 - to be deleted */ 2951 NvU32 noOfEntries; 2952 /* Address space of the vidmem access bit buffer. Used by VAB v1 - to be deleted */ 2953 NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE addrSpace; 2954 } NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS; 2955 2956 /** 2957 * @brief HopperUsermodeAParams 2958 * This set of optionalparameters is passed in on allocation of 2959 * HOPPER_USERMODE_A object to specify whether a BAR1/GMMU 2960 * privileged/non-privileged mapping is needed. 2961 */ 2962 2963 typedef struct 2964 { 2965 /** 2966 * [IN] Whether to allocate GMMU/BAR1 mapping or BAR0 mapping. 2967 */ 2968 NvBool bBar1Mapping; 2969 /* [IN] Whether to allocate the PRIV page or regular VF page */ 2970 NvBool bPriv; 2971 } NV_HOPPER_USERMODE_A_PARAMS; 2972 2973 2974 #ifdef __cplusplus 2975 }; 2976 #endif 2977 #endif /* NVOS_INCLUDED */ 2978