1 /* $OpenBSD: trm.h,v 1.9 2024/10/22 21:50:02 jsg Exp $ 2 * ------------------------------------------------------------ 3 * O.S : OpenBSD 4 * File Name : trm.h 5 * Device Driver for Tekram DC395U/UW/F,DC315/U 6 * PCI SCSI Bus Master Host Adapter 7 * (SCSI chip set used Tekram ASIC TRM-S1040) 8 * 9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. 10 * (C)Copyright 2001-2002 Ashley R. Martens and Kenneth R Westerback 11 * ------------------------------------------------------------ 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * ------------------------------------------------------------ 34 */ 35 36 #ifndef _TRM_H 37 #define _TRM_H 38 39 /* 40 * ------------------------------------------------------------ 41 * Segment Entry 42 * ------------------------------------------------------------ 43 */ 44 struct SGentry { 45 u_int32_t address; 46 u_int32_t length; 47 }; 48 49 /* 50 * ----------------------------------------------------------------------- 51 * feature of chip set MAX value 52 * ----------------------------------------------------------------------- 53 */ 54 55 #define TRM_MAX_ADAPTER_NUM 4 56 #define TRM_MAX_TARGETS 16 57 #define TRM_MAX_LUNS 8 58 #define TRM_MAX_SG_LISTENTRY 32 59 #define TRM_MAX_CMD_PER_LUN 32 60 #define TRM_MAX_SRB_CNT TRM_MAX_CMD_PER_LUN*4 61 #define TRM_MAX_PHYSG_BYTE ((TRM_MAX_SG_LISTENTRY - 1) << PGSHIFT) 62 #define TRM_MAX_SYNC_OFFSET 15 63 #define TRM_SEL_TIMEOUT 153 /* 250 ms selection timeout (@40MHz) */ 64 65 /* 66 *----------------------------------------------------------------------- 67 * SCSI Request Block 68 *----------------------------------------------------------------------- 69 */ 70 struct trm_scsi_req_q { 71 TAILQ_ENTRY(trm_scsi_req_q) link; 72 bus_dmamap_t dmamapxfer; 73 u_int32_t PhysSRB; 74 u_int32_t SRBTotalXferLength; 75 u_int32_t SRBSGPhyAddr; /* a segment starting address */ 76 77 u_int16_t SRBState; /* State machine */ 78 #define TRM_FREE 0x0000 79 #define TRM_WAIT 0x0001 80 #define TRM_READY 0x0002 81 #define TRM_MSGOUT 0x0004 /*arbitration+msg_out 1st byte */ 82 #define TRM_EXTEND_MSGIN 0x0010 83 #define TRM_COMMAND 0x0020 84 #define TRM_START 0x0040 /*arbitration+msg_out+command_out */ 85 #define TRM_DISCONNECTED 0x0080 86 #define TRM_DATA_XFER 0x0100 87 #define TRM_XFERPAD 0x0200 88 #define TRM_STATUS 0x0400 89 #define TRM_COMPLETED 0x0800 90 #define TRM_ABORT_SENT 0x1000 91 #define TRM_UNEXPECT_RESEL 0x8000 92 93 u_int8_t AdaptStatus; 94 #define TRM_STATUS_GOOD 0x00 95 #define TRM_SELECTION_TIMED_OUT 0x11 96 #define TRM_OVER_UNDER_RUN 0x12 97 #define TRM_UNEXP_BUS_FREE 0x13 98 #define TRM_TARGET_PHASE_F 0x14 99 #define TRM_INVALID_CCB_OP 0x16 100 #define TRM_LINK_CCB_BAD 0x17 101 #define TRM_BAD_TARGET_DIR 0x18 102 #define TRM_DUPLICATE_CCB 0x19 103 #define TRM_BAD_CCB_OR_SG 0x1A 104 #define TRM_ABORT 0xFF 105 106 u_int8_t CmdBlock[16]; 107 108 u_int8_t ScsiCmdLen; 109 u_int8_t ScsiPhase; 110 111 u_int8_t SRBFlag; 112 #define TRM_AUTO_REQSENSE 0x01 113 #define TRM_SCSI_TIMED_OUT 0x02 114 #define TRM_PARITY_ERROR 0x04 115 #define TRM_ON_GOING_SRB 0x08 116 #define TRM_ON_WAITING_SRB 0x10 117 118 u_int8_t SRBSGCount; 119 u_int8_t SRBSGIndex; 120 u_int8_t TagNumber; 121 #define TRM_NO_TAG 0x00 122 123 u_int8_t TargetStatus; /* SCSI status codes + Tekram: */ 124 #define TRM_SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 125 #define TRM_SCSI_BUS_RST_DETECTED 0xFE /* Scsi Bus Reset detected */ 126 #define TRM_SCSI_SELECT_TIMEOUT 0xFF /* Selection Time out */ 127 128 struct trm_dcb *pSRBDCB; 129 130 struct SGentry SegmentX[TRM_MAX_SG_LISTENTRY]; 131 132 struct scsi_xfer *xs; 133 134 struct scsi_sense_data scsisense; 135 u_int32_t scsisensePhyAddr; 136 }; 137 138 TAILQ_HEAD(SRB_HEAD, trm_scsi_req_q); 139 140 /* 141 *----------------------------------------------------------------------- 142 * Device Control Block 143 *----------------------------------------------------------------------- 144 */ 145 struct trm_dcb { 146 u_int32_t TagMask; 147 148 u_int16_t DCBFlag; 149 #define TRM_WIDE_NEGO_ENABLE 0x0001 150 #define TRM_DOING_WIDE_NEGO 0x0002 151 #define TRM_WIDE_NEGO_DONE 0x0004 152 #define TRM_SYNC_NEGO_ENABLE 0x0008 153 #define TRM_DOING_SYNC_NEGO 0x0010 154 #define TRM_USE_TAG_QUEUING 0x0020 155 #define TRM_QUEUE_FULL 0x0040 156 #define TRM_WIDE_NEGO_16BIT 0x0080 157 #define TRM_QUIRKS_VALID 0x0100 158 #define TRM_BAD_DCB 0x0200 159 160 u_int8_t DevMode; /* trm_target_nvram.NvmTarCfg0 */ 161 162 u_int8_t MaxNegoPeriod; /* Maximum allow sync period */ 163 u_int8_t SyncPeriod; /* Current sync period */ 164 u_int8_t SyncOffset; /* Current sync offset */ 165 166 u_int8_t target; /* SCSI Target ID */ 167 u_int8_t lun; /* SCSI Logical Unit Number */ 168 169 u_int8_t IdentifyMsg; 170 171 struct scsi_link *sc_link; 172 struct trm_scsi_req_q *pActiveSRB; 173 }; 174 175 /* 176 *----------------------------------------------------------------------- 177 * Adapter Control Block 178 *----------------------------------------------------------------------- 179 */ 180 struct trm_softc { 181 struct device sc_device; 182 183 bus_space_handle_t sc_iohandle; 184 bus_space_tag_t sc_iotag; 185 bus_dma_tag_t sc_dmatag; 186 bus_dmamap_t sc_dmamap_control; /* map the control structures */ 187 188 u_int16_t sc_AdapterUnit; /* nth Adapter this driver */ 189 190 u_int8_t sc_AdaptSCSIID; /* Adapter SCSI Target ID */ 191 u_int8_t sc_TagMaxNum; 192 193 u_int8_t sc_config; 194 #define HCC_WIDE_CARD 0x20 195 #define HCC_SCSI_RESET 0x10 196 #define HCC_PARITY 0x08 197 #define HCC_AUTOTERM 0x04 198 #define HCC_LOW8TERM 0x02 199 #define HCC_UP8TERM 0x01 200 201 u_int8_t sc_Flag; 202 #define RESET_DEV 0x01 203 #define RESET_DETECT 0x02 204 #define RESET_DONE 0x04 205 206 u_int8_t MsgCnt; 207 u_int8_t MsgBuf[6]; 208 209 struct SRB_HEAD freeSRB; 210 struct SRB_HEAD goingSRB; 211 struct SRB_HEAD waitingSRB; 212 213 struct mutex sc_srb_mtx; 214 struct scsi_iopool sc_iopool; 215 216 struct trm_dcb *pActiveDCB; 217 struct trm_dcb *pDCB[TRM_MAX_TARGETS][TRM_MAX_LUNS]; 218 219 struct trm_scsi_req_q *SRB; 220 }; 221 222 /* 223 * The SEEPROM structure for TRM_S1040 224 */ 225 struct trm_target_nvram { 226 u_int8_t NvmTarCfg0; /* Target configuration byte 0 */ 227 #define TRM_WIDE 0x20 /* Wide negotiate */ 228 #define TRM_TAG_QUEUING 0x10 /* Enable SCSI tag queuing */ 229 #define TRM_SEND_START 0x08 /* Send start command SPINUP */ 230 #define TRM_DISCONNECT 0x04 /* Enable SCSI disconnect */ 231 #define TRM_SYNC 0x02 /* Sync negotiation */ 232 #define TRM_PARITY 0x01 /* (it should be defined at NAC ) */ 233 234 u_int8_t NvmTarPeriod; /* Target period */ 235 u_int8_t NvmTarCfg2; /* Target configuration byte 2 */ 236 u_int8_t NvmTarCfg3; /* Target configuration byte 3 */ 237 }; 238 239 struct trm_adapter_nvram { 240 u_int8_t NvramSubVendorID[2]; /*0,1 Sub Vendor ID */ 241 u_int8_t NvramSubSysID[2]; /*2,3 Sub System ID */ 242 u_int8_t NvramSubClass; /*4 Sub Class */ 243 u_int8_t NvramVendorID[2]; /*5,6 Vendor ID */ 244 u_int8_t NvramDeviceID[2]; /*7,8 Device ID */ 245 u_int8_t NvramReserved; /*9 Reserved */ 246 struct trm_target_nvram NvramTarget[TRM_MAX_TARGETS]; /* 10 */ 247 u_int8_t NvramScsiId; /*74 Host Adapter SCSI ID */ 248 u_int8_t NvramChannelCfg; /*75 Channel configuration */ 249 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 250 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 251 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 252 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 253 u_int8_t NvramDelayTime; /*76 Power on delay time */ 254 u_int8_t NvramMaxTag; /*77 Maximum tags */ 255 u_int8_t NvramReserved0; /*78 */ 256 u_int8_t NvramBootTarget; /*79 */ 257 u_int8_t NvramBootLun; /*80 */ 258 u_int8_t NvramReserved1; /*81 */ 259 u_int16_t Reserved[22]; /*82,..125 */ 260 u_int16_t NvramCheckSum; /*126,127 */ 261 }; 262 263 /* 264 * The PCI configuration register offsets for the TRM_S1040, and 265 * the associated bit definitions. 266 */ 267 268 #define TRM_S1040_ID 0x00 /* Vendor and Device ID */ 269 #define TRM_S1040_COMMAND 0x04 /* PCI command register */ 270 #define TRM_S1040_IOBASE 0x10 /* I/O Space base address */ 271 #define TRM_S1040_ROMBASE 0x30 /* Expansion ROM Base Address */ 272 #define TRM_S1040_INTLINE 0x3C /* Interrupt line */ 273 274 #define TRM_S1040_SCSI_STATUS 0x80 /* SCSI Status (R) */ 275 #define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */ 276 #define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */ 277 #define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero */ 278 #define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */ 279 #define COMMANDABORT 0x0040 /* SCSI command abort */ 280 #define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */ 281 #define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */ 282 #define PARITYERROR 0x0008 /* SCSI parity error */ 283 #define PHASEMASK 0x0007 /* Phase MSG/CD/IO */ 284 #define PH_DATA_OUT 0x00 /* Data out phase */ 285 #define PH_DATA_IN 0x01 /* Data in phase */ 286 #define PH_COMMAND 0x02 /* Command phase */ 287 #define PH_STATUS 0x03 /* Status phase */ 288 #define PH_BUS_FREE 0x05 /* Invalid phase used as bus free */ 289 #define PH_MSG_OUT 0x06 /* Message out phase */ 290 #define PH_MSG_IN 0x07 /* Message in phase */ 291 #define TRM_S1040_SCSI_CONTROL 0x80 /* SCSI Control (W) */ 292 #define DO_CLRATN 0x0400 /* Clear ATN */ 293 #define DO_SETATN 0x0200 /* Set ATN */ 294 #define DO_CMDABORT 0x0100 /* Abort SCSI command */ 295 #define DO_RSTMODULE 0x0010 /* Reset SCSI chip */ 296 #define DO_RSTSCSI 0x0008 /* Reset SCSI bus */ 297 #define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */ 298 #define DO_DATALATCH 0x0002 /* Enable SCSI bus data latch */ 299 #define DO_HWRESELECT 0x0001 /* Enable hardware reselection */ 300 #define TRM_S1040_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter 5bits(R) */ 301 #define TRM_S1040_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */ 302 #define TRM_S1040_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */ 303 #define INT_SCAM 0x80 /* SCAM selection interrupt */ 304 #define INT_SELECT 0x40 /* Selection interrupt */ 305 #define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */ 306 #define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */ 307 #define INT_RESELECTED 0x08 /* Reselected interrupt */ 308 #define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt */ 309 #define INT_BUSSERVICE 0x02 /* Bus service interrupt */ 310 #define INT_CMDDONE 0x01 /* SCSI command done interrupt */ 311 #define TRM_S1040_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */ 312 /* 313 * Bit Name Definition 314 * 07-05 0 RSVD Reversed. Always 0. 315 * 04 0 OFFSET4 Reversed for LVDS. Always 0. 316 * 03-00 0 OFFSET[03:00] Offset number from 0 to 15 317 */ 318 #define TRM_S1040_SCSI_SYNC 0x85 /* SCSI Synchronous Control (R/W) */ 319 #define LVDS_SYNC 0x20 /* Enable LVDS synchronous */ 320 #define WIDE_SYNC 0x10 /* Enable WIDE synchronous */ 321 #define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */ 322 /* 323 * SYNCM 7 6 5 4 3 2 1 0 324 * Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0 325 * Default 0 0 0 0 0 0 0 0 326 * 327 * 328 * Bit Name Definition 329 * --- ---- ---------- 330 * 07-06 0 RSVD Reversed. Always read 0 331 * 05 0 LVDS Reversed. Always read 0 332 * 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI transfer. 333 * 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode. 334 * 335 * @@ When this bit is set, 336 * the synchronous period bits 2:0 337 * in the Synchronous Mode register 338 * are used to transfer data 339 * at the Fast-20 rate. 340 * @@ When this bit is reset, 341 * the synchronous period bits 2:0 342 * in the Synchronous Mode Register 343 * are used to transfer data 344 * at the Fast-40 rate. 345 * 346 * 02-00 0 PERIOD[2:0]/SXPD[02:00] Synchronous SCSI Transfer Rate. 347 * These 3 bits specify 348 * the Synchronous SCSI Transfer Rate 349 * for Fast-20 and Fast-10. 350 * These bits are also reset 351 * by a SCSI Bus reset. 352 * 353 * For Fast-10 bit ALTPD = 0 and LVDS = 0 354 * and bit2,bit1,bit0 is defined as follows : 355 * 356 * 000 100ns, 10.0 Mbytes/s 357 * 001 150ns, 6.6 Mbytes/s 358 * 010 200ns, 5.0 Mbytes/s 359 * 011 250ns, 4.0 Mbytes/s 360 * 100 300ns, 3.3 Mbytes/s 361 * 101 350ns, 2.8 Mbytes/s 362 * 110 400ns, 2.5 Mbytes/s 363 * 111 450ns, 2.2 Mbytes/s 364 * 365 * For Fast-20 bit ALTPD = 1 and LVDS = 0 366 * and bit2,bit1,bit0 is defined as follows : 367 * 368 * 000 50ns, 20.0 Mbytes/s 369 * 001 75ns, 13.3 Mbytes/s 370 * 010 100ns, 10.0 Mbytes/s 371 * 011 125ns, 8.0 Mbytes/s 372 * 100 150ns, 6.6 Mbytes/s 373 * 101 175ns, 5.7 Mbytes/s 374 * 110 200ns, 5.0 Mbytes/s 375 * 111 250ns, 4.0 Mbytes/s 376 * 377 * For Fast-40 bit ALTPD = 0 and LVDS = 1 378 * and bit2,bit1,bit0 is defined as follows : 379 * 380 * 000 25ns, 40.0 Mbytes/s 381 * 001 50ns, 20.0 Mbytes/s 382 * 010 75ns, 13.3 Mbytes/s 383 * 011 100ns, 10.0 Mbytes/s 384 * 100 125ns, 8.0 Mbytes/s 385 * 101 150ns, 6.6 Mbytes/s 386 * 110 175ns, 5.7 Mbytes/s 387 * 111 200ns, 5.0 Mbytes/s 388 */ 389 #define TRM_S1040_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */ 390 #define TRM_S1040_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */ 391 #define TRM_S1040_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */ 392 #define TRM_S1040_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W) */ 393 #define TRM_S1040_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */ 394 #define EN_SCAM 0x80 /* Enable SCAM selection interrupt */ 395 #define EN_SELECT 0x40 /* Enable selection interrupt */ 396 #define EN_SELTIMEOUT 0x20 /* Enable selection timeout interrupt */ 397 #define EN_DISCONNECT 0x10 /* Enable bus disconnected interrupt */ 398 #define EN_RESELECTED 0x08 /* Enable reselected interrupt */ 399 #define EN_SCSIRESET 0x04 /* Enable SCSI reset detected interrupt*/ 400 #define EN_BUSSERVICE 0x02 /* Enable bus service interrupt */ 401 #define EN_CMDDONE 0x01 /* Enable SCSI command done interrupt */ 402 #define TRM_S1040_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */ 403 #define PHASELATCH 0x40 /* Enable phase latch */ 404 #define INITIATOR 0x20 /* Enable initiator mode */ 405 #define PARITYCHECK 0x10 /* Enable parity check */ 406 #define BLOCKRST 0x01 /* Disable SCSI reset1 */ 407 #define TRM_S1040_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */ 408 #define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */ 409 #define FILTER_DISABLE 0x08 /* Disable SCSI data filter */ 410 #define ACTIVE_NEG 0x02 /* Enable active negation */ 411 #define TRM_S1040_SCSI_CONFIG2 0x8F /* SCSI Configuration 2 (R/W) */ 412 #define TRM_S1040_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */ 413 #define SCMD_COMP 0x12 /* Command complete */ 414 #define SCMD_SEL_ATN 0x60 /* Selection with ATN */ 415 #define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */ 416 #define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */ 417 #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */ 418 #define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */ 419 #define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */ 420 #define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */ 421 #define SCMD_MSGACCEPT 0xD8 /* Message accept */ 422 /* 423 * Code Command Description 424 * 425 * 02 Enable reselection with FIFO 426 * 40 Select without ATN with FIFO 427 * 60 Select with ATN with FIFO 428 * 64 Select with ATN3 with FIFO 429 * A0 Select with ATN and stop with FIFO 430 * C0 Transfer information out with FIFO 431 * C1 Transfer information out with DMA 432 * C2 Transfer information in with FIFO 433 * C3 Transfer information in with DMA 434 * 12 Initiator command complete with FIFO 435 * 50 Initiator transfer information out sequence without ATN with FIFO 436 * 70 Initiator transfer information out sequence with ATN with FIFO 437 * 74 Initiator transfer information out sequence with ATN3 with FIFO 438 * 52 Initiator transfer information in sequence without ATN with FIFO 439 * 72 Initiator transfer information in sequence with ATN with FIFO 440 * 76 Initiator transfer information in sequence with ATN3 with FIFO 441 * 90 Initiator transfer information out command complete with FIFO 442 * 92 Initiator transfer information in command complete with FIFO 443 * D2 Enable selection 444 * 08 Reselection 445 * 48 Disconnect command with FIFO 446 * 88 Terminate command with FIFO 447 * C8 Target command complete with FIFO 448 * 18 SCAM Arbitration/ Selection 449 * 5A Enable reselection 450 * 98 Select without ATN with FIFO 451 * B8 Select with ATN with FIFO 452 * D8 Message Accepted 453 * 58 NOP 454 */ 455 #define TRM_S1040_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */ 456 #define TRM_S1040_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */ 457 #define TRM_S1040_SCSI_TCR0 0x9C /* SCSI Target Control 0 (R/W) */ 458 #define TCR0_WIDE_NEGO_DONE 0x8000 /* Wide nego done */ 459 #define TCR0_SYNC_NEGO_DONE 0x4000 /* Synchronous nego done */ 460 #define TCR0_ENABLE_LVDS 0x2000 /* Enable LVDS synchronous */ 461 #define TCR0_ENABLE_WIDE 0x1000 /* Enable WIDE synchronous */ 462 #define TCR0_ENABLE_ALT 0x0800 /* Enable alternate synchronous */ 463 #define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */ 464 #define TCR0_DO_WIDE_NEGO 0x0080 /* Do wide NEGO */ 465 #define TCR0_DO_SYNC_NEGO 0x0040 /* Do sync NEGO */ 466 #define TCR0_DISCONNECT_EN 0x0020 /* Disconnection enable */ 467 #define TCR0_OFFSET_MASK 0x001F /* Offset number */ 468 #define TRM_S1040_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */ 469 #define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */ 470 #define NON_TAG_BUSY 0x0080 /* Non tag command active */ 471 #define ACTTAG_MASK 0x007F /* Active tags */ 472 473 #define TRM_S1040_DMA_COMMAND 0xA0 /* DMA Command (R/W) */ 474 #define XFERDATAIN 0x0103 /* Transfer data in */ 475 #define XFERDATAOUT 0x0102 /* Transfer data out */ 476 #define TRM_S1040_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */ 477 #define TRM_S1040_DMA_CONTROL 0xA1 /* DMA Control (W) */ 478 #define STOPDMAXFER 0x08 /* Stop DMA transfer */ 479 #define ABORTXFER 0x04 /* Abort DMA transfer */ 480 #define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */ 481 #define STARTDMAXFER 0x01 /* Start DMA transfer */ 482 #define TRM_S1040_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */ 483 #define XFERPENDING 0x80 /* Transfer pending */ 484 #define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */ 485 #define SCSICOMP 0x01 /* SCSI complete interrupt */ 486 #define TRM_S1040_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W) */ 487 #define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */ 488 #define TRM_S1040_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */ 489 #define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature */ 490 #define TRM_S1040_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W) */ 491 #define TRM_S1040_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */ 492 #define TRM_S1040_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */ 493 #define TRM_S1040_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */ 494 495 #define TRM_S1040_GEN_CONTROL 0xD4 /* Global Control */ 496 #define EN_EEPROM 0x10 /* Enable EEPROM programming */ 497 #define AUTOTERM 0x04 /* Enable Auto SCSI terminator */ 498 #define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */ 499 #define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */ 500 #define TRM_S1040_GEN_STATUS 0xD5 /* Global Status */ 501 #define GTIMEOUT 0x80 /* Global timer reach 0 */ 502 #define CON5068 0x10 /* External 50/68 pin connected */ 503 #define CON68 0x08 /* Internal 68 pin connected */ 504 #define CON50 0x04 /* Internal 50 pin connected */ 505 #define WIDESCSI 0x02 /* Wide SCSI card */ 506 #define TRM_S1040_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port */ 507 #define NVR_BITOUT 0x08 /* Serial data out */ 508 #define NVR_BITIN 0x04 /* Serial data in */ 509 #define NVR_CLOCK 0x02 /* Serial clock */ 510 #define NVR_SELECT 0x01 /* Serial select */ 511 #define TRM_S1040_GEN_EDATA 0xD7 /* Parallel EEPROM data port */ 512 #define TRM_S1040_GEN_EADDRESS 0xD8 /* Parallel EEPROM address */ 513 #define TRM_S1040_GEN_TIMER 0xDB /* Global timer */ 514 515 int trm_Interrupt(void *); 516 int trm_init(struct trm_softc *, int); 517 void trm_scsi_cmd(struct scsi_xfer *); 518 519 520 #endif /* trm_h */ 521