1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /* 25 * This file defines CTRL calls that are device specifics. 26 * 27 * This is a platform agnostic file and lists the CTRL calls used by all the 28 * clients, Fabric Manager, MODS or NVSwitch GTEST etc. 29 * 30 * As Fabric Manager relies on driver ABI compatibility the CTRL calls listed in 31 * this file contribute to the driver ABI version. 32 * 33 * Note: ctrl_dev_nvswitch.h and ctrl_dev_internal_nvswitch.h do not share any 34 * data. This helps to keep the driver ABI stable. 35 */ 36 37 #ifndef _CTRL_DEVICE_NVSWITCH_H_ 38 #define _CTRL_DEVICE_NVSWITCH_H_ 39 40 #ifdef __cplusplus 41 extern "C" 42 { 43 #endif 44 45 46 #include "nvtypes.h" 47 #include "nvfixedtypes.h" 48 #include "nvmisc.h" 49 #include "ioctl_common_nvswitch.h" 50 51 /* 52 * CTRL_NVSWITCH_GET_INFO 53 * 54 * Control for querying miscellaneous device information. 55 * 56 * This provides a single API to query for multiple pieces of miscellaneous 57 * information via a single call. 58 * 59 * Parameters: 60 * count [IN] 61 * Count of queries. Max supported queries per-call are 62 * NVSWITCH_GET_INFO_COUNT_MAX 63 * index [IN] 64 * One of the NVSWITCH_GET_INFO_INDEX type value. 65 * 66 * info [OUT] 67 * Data pertaining to the provided NVSWITCH_GET_INFO_INDEX type value. 68 */ 69 70 #define NVSWITCH_GET_INFO_COUNT_MAX 32 71 72 typedef enum nvswitch_get_info_index 73 { 74 NVSWITCH_GET_INFO_INDEX_ARCH = 0x0, 75 NVSWITCH_GET_INFO_INDEX_IMPL, 76 NVSWITCH_GET_INFO_INDEX_CHIPID, 77 NVSWITCH_GET_INFO_INDEX_REVISION_MAJOR, 78 NVSWITCH_GET_INFO_INDEX_REVISION_MINOR, 79 NVSWITCH_GET_INFO_INDEX_REVISION_MINOR_EXT, 80 NVSWITCH_GET_INFO_INDEX_PLATFORM, 81 NVSWITCH_GET_INFO_INDEX_DEVICE_ID, 82 83 NVSWITCH_GET_INFO_INDEX_NUM_PORTS = 0x100, 84 NVSWITCH_GET_INFO_INDEX_ENABLED_PORTS_MASK_31_0, 85 NVSWITCH_GET_INFO_INDEX_ENABLED_PORTS_MASK_63_32, 86 NVSWITCH_GET_INFO_INDEX_NUM_VCS, 87 NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_TABLE_SIZE, 88 NVSWITCH_GET_INFO_INDEX_ROUTING_ID_TABLE_SIZE, 89 NVSWITCH_GET_INFO_INDEX_ROUTING_LAN_TABLE_SIZE, 90 NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_EXTA_TABLE_SIZE, 91 NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_EXTB_TABLE_SIZE, 92 NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_MULTICAST_TABLE_SIZE, 93 94 NVSWITCH_GET_INFO_INDEX_FREQ_KHZ = 0x200, 95 NVSWITCH_GET_INFO_INDEX_VCOFREQ_KHZ, 96 NVSWITCH_GET_INFO_INDEX_VOLTAGE_MVOLT, 97 NVSWITCH_GET_INFO_INDEX_PHYSICAL_ID, 98 99 NVSWITCH_GET_INFO_INDEX_PCI_DOMAIN = 0x300, 100 NVSWITCH_GET_INFO_INDEX_PCI_BUS, 101 NVSWITCH_GET_INFO_INDEX_PCI_DEVICE, 102 NVSWITCH_GET_INFO_INDEX_PCI_FUNCTION, 103 /* See enum modification guidelines at the top of this file */ 104 } NVSWITCH_GET_INFO_INDEX; 105 106 #define NVSWITCH_GET_INFO_INDEX_ARCH_LR10 0x02 107 #define NVSWITCH_GET_INFO_INDEX_IMPL_LR10 0x01 108 109 #define NVSWITCH_GET_INFO_INDEX_ARCH_LS10 0x03 110 #define NVSWITCH_GET_INFO_INDEX_IMPL_LS10 0x01 111 112 #define NVSWITCH_GET_INFO_INDEX_PLATFORM_UNKNOWN 0x00 113 #define NVSWITCH_GET_INFO_INDEX_PLATFORM_RTLSIM 0x01 114 #define NVSWITCH_GET_INFO_INDEX_PLATFORM_FMODEL 0x02 115 #define NVSWITCH_GET_INFO_INDEX_PLATFORM_EMULATION 0x03 116 #define NVSWITCH_GET_INFO_INDEX_PLATFORM_SILICON 0x04 117 118 typedef struct nvswitch_get_info 119 { 120 NvU32 count; 121 NvU32 index[NVSWITCH_GET_INFO_COUNT_MAX]; 122 NvU32 info[NVSWITCH_GET_INFO_COUNT_MAX]; 123 124 } NVSWITCH_GET_INFO; 125 126 /* 127 * CTRL_NVSWITCH_SET_INGRESS_REQUEST_TABLE 128 * 129 * Control for programming ingress request tables. 130 * This interface is only supported on SV10 architecture. All others will 131 * return an error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 132 * 133 * Parameters: 134 * portNum [IN] 135 * A valid port number present in the port masks returned by 136 * NVSWITCH_GET_INFO 137 * firstIndex [IN] 138 * A starting index of the ingress request table from which table entries 139 * should be programmed. 140 * numEntries [IN] 141 * Number of entries to be programmed. Currently, the call supports 142 * programming NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX at a time. 143 * entries [IN] 144 * The entries (entry format is architecture dependent). 145 */ 146 147 #define NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX 256 148 149 /* TODO: document the entry format in detail */ 150 typedef struct nvswitch_ingress_request_entry 151 { 152 NvU32 vcModeValid7_0; 153 NvU32 vcModeValid15_8; 154 NvU32 vcModeValid17_16; 155 NvU32 mappedAddress; 156 NvU32 routePolicy; 157 NvBool entryValid; 158 159 } NVSWITCH_INGRESS_REQUEST_ENTRY; 160 161 typedef struct nvswitch_set_ingress_request_table 162 { 163 NvU32 portNum; 164 NvU32 firstIndex; 165 NvU32 numEntries; 166 NVSWITCH_INGRESS_REQUEST_ENTRY entries[NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX]; 167 168 } NVSWITCH_SET_INGRESS_REQUEST_TABLE; 169 170 /* 171 * CTRL_NVSWITCH_GET_INGRESS_REQUEST_TABLE 172 * 173 * Control for reading ingress request tables. A sparse list of nonzero entries 174 * and their table indices is returned. 175 * 176 * Parameters: 177 * portNum [IN] 178 * A valid port number present in the port masks returned by 179 * NVSWITCH_GET_INFO 180 * firstIndex [IN] 181 * A starting index of the ingress request table from which table entries 182 * should be read. 183 * nextIndex [OUT] 184 * The table index of the next entry to read. Set to INGRESS_MAP_TABLE_SIZE 185 * when the end of the table has been reached. 186 * numEntries [OUT] 187 * Number of entries returned. Currently, the call supports returning up to 188 * NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX entries at a time. 189 * entries [OUT] 190 * Ingress request entries along with their table indices. 191 * Entry format is architecture dependent. 192 */ 193 194 typedef struct nvswitch_ingress_request_idx_entry 195 { 196 NvU32 idx; 197 NVSWITCH_INGRESS_REQUEST_ENTRY entry; 198 199 } NVSWITCH_INGRESS_REQUEST_IDX_ENTRY; 200 201 typedef struct nvswitch_get_ingress_request_table_params 202 { 203 NvU32 portNum; 204 NvU32 firstIndex; 205 NvU32 nextIndex; 206 NvU32 numEntries; 207 NVSWITCH_INGRESS_REQUEST_IDX_ENTRY entries[NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX]; 208 209 } NVSWITCH_GET_INGRESS_REQUEST_TABLE_PARAMS; 210 211 /* 212 * CTRL_NVSWITCH_SET_INGRESS_REQUEST_VALID 213 * 214 * Control for toggling the existing ingress request table entries' validity. 215 * This interface is only supported on SV10 architecture. All others will 216 * return an error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 217 * 218 * Parameters: 219 * portNum [IN] 220 * A valid port number present in the port masks returned by 221 * NVSWITCH_GET_INFO 222 * firstIndex [IN] 223 * A starting index of the ingress request table from which table entries 224 * should be programmed. 225 * numEntries [IN] 226 * Number of entries to be programmed. Currently, the call supports 227 * programming NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX at a time. 228 * entryValid [IN] 229 * If true, an existing entry is marked valid, else will be marked invalid. 230 */ 231 232 typedef struct nvswitch_set_ingress_request_valid 233 { 234 NvU32 portNum; 235 NvU32 firstIndex; 236 NvU32 numEntries; 237 NvBool entryValid[NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX]; 238 239 } NVSWITCH_SET_INGRESS_REQUEST_VALID; 240 241 /* 242 * CTRL_NVSWITCH_SET_INGRESS_RESPONSE_TABLE 243 * 244 * Control for programming ingress response tables. 245 * This interface is only supported on SV10 architecture. All others will 246 * return an error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 247 * 248 * Parameters: 249 * portNum [IN] 250 * A valid port number present in the port masks returned by 251 * NVSWITCH_GET_INFO 252 * firstIndex [IN] 253 * A starting index of the ingress request table from which table entries 254 * should be programmed. 255 * numEntries [IN] 256 * Number of entries to be programmed. Currently, the call supports 257 * programming NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX at a time. 258 * entries [IN] 259 * The entries (entry format is architecture dependent). 260 */ 261 262 #define NVSWITCH_INGRESS_RESPONSE_ENTRIES_MAX 256 263 264 /* TODO: document the entry format in detail */ 265 typedef struct nvswitch_ingress_response_entry 266 { 267 NvU32 vcModeValid7_0; 268 NvU32 vcModeValid15_8; 269 NvU32 vcModeValid17_16; 270 NvU32 routePolicy; 271 NvBool entryValid; 272 273 } NVSWITCH_INGRESS_RESPONSE_ENTRY; 274 275 typedef struct nvswitch_set_ingress_response_table 276 { 277 NvU32 portNum; 278 NvU32 firstIndex; 279 NvU32 numEntries; 280 NVSWITCH_INGRESS_RESPONSE_ENTRY entries[NVSWITCH_INGRESS_RESPONSE_ENTRIES_MAX]; 281 282 } NVSWITCH_SET_INGRESS_RESPONSE_TABLE; 283 284 /* 285 * CTRL_NVSWITCH_SET_REMAP_POLICY 286 * 287 * Control to load remap policy table 288 * This interface is not supported on SV10 architecture. SV10 will return an 289 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 290 * 291 * Parameters: 292 * portNum [IN] 293 * A valid port number present in the port masks returned by 294 * NVSWITCH_GET_INFO 295 * tableSelect [IN] 296 * Remap table selector 297 * firstIndex [IN] 298 * A starting index of the remap table from which table entries 299 * should be programmed. Valid range should be queried using 300 * NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_TABLE_SIZE. 301 * numEntries [IN] 302 * Number of entries to be programmed. Currently, the call supports 303 * programming NVSWITCH_REMAP_POLICY_ENTRIES_MAX at a time. 304 * remapPolicy [IN] 305 * The entries (see NVSWITCH_REMAP_POLICY_ENTRY). 306 */ 307 308 #define NVSWITCH_REMAP_POLICY_ENTRIES_MAX 64 309 310 #define NVSWITCH_REMAP_POLICY_FLAGS_REMAP_ADDR NVBIT(0) 311 #define NVSWITCH_REMAP_POLICY_FLAGS_REQCTXT_CHECK NVBIT(1) 312 #define NVSWITCH_REMAP_POLICY_FLAGS_REQCTXT_REPLACE NVBIT(2) 313 #define NVSWITCH_REMAP_POLICY_FLAGS_ADR_BASE NVBIT(4) 314 #define NVSWITCH_REMAP_POLICY_FLAGS_ADR_OFFSET NVBIT(5) /* Apply address offset */ 315 #define NVSWITCH_REMAP_POLICY_FLAGS_REFLECTIVE NVBIT(30) /* Reflective mapping */ 316 #define NVSWITCH_REMAP_POLICY_FLAGS_ADDR_TYPE NVBIT(31) /* Enforce address type checking */ 317 318 typedef struct nvswitch_remap_policy_entry 319 { 320 NvBool entryValid; 321 NvU32 targetId; /* Unique endpoint ID */ 322 323 NvU32 irlSelect; /* Injection rate limiter (0=none/1=IRL1/2=IRL2) */ 324 325 NvU32 flags; /* See NVSWITCH_REMAP_POLICY_FLAGS_* */ 326 327 NV_DECLARE_ALIGNED(NvU64 address, 8); /* 47-bit remap address. Bits 46:36 are used. */ 328 329 /* reqContext fields are used when */ 330 /* routing function _REQCTXT_CHECK or _REPLACE */ 331 /* is set. */ 332 NvU32 reqCtxMask; /* Used to mask packet request ctxt before */ 333 /* checking. */ 334 335 NvU32 reqCtxChk; /* Post-mask packet request ctxt check value. */ 336 /* Packets that fail compare are converted to */ 337 /* UR response and looped back. */ 338 339 NvU32 reqCtxRep; /* Replaces packet request context when */ 340 /* _REQCTXT_REPLACE is set. */ 341 342 NV_DECLARE_ALIGNED(NvU64 addressOffset, 8); /* offset - base is added to packet address if */ 343 /* routing function _ADR_OFFSET & _ADR_BASE are */ 344 /* set. 64GB offset 1MB aligned on LR10. */ 345 346 NV_DECLARE_ALIGNED(NvU64 addressBase, 8); /* If routing function _ADR_BASE is set, limits */ 347 NV_DECLARE_ALIGNED(NvU64 addressLimit, 8); /* application of _ADR_OFFSET to packet */ 348 /* addresses that pass base/limit bounds check. */ 349 /* Maximum 64GB size 1MB aligned on LR10. */ 350 351 352 } NVSWITCH_REMAP_POLICY_ENTRY; 353 354 typedef enum nvswitch_table_select_remap 355 { 356 NVSWITCH_TABLE_SELECT_REMAP_PRIMARY = 0, 357 NVSWITCH_TABLE_SELECT_REMAP_EXTA, 358 NVSWITCH_TABLE_SELECT_REMAP_EXTB, 359 NVSWITCH_TABLE_SELECT_REMAP_MULTICAST, 360 NVSWITCH_TABLE_SELECT_REMAP_MAX 361 } NVSWITCH_TABLE_SELECT_REMAP; 362 363 typedef struct nvswitch_set_remap_policy 364 { 365 NvU32 portNum; 366 NVSWITCH_TABLE_SELECT_REMAP tableSelect; 367 NvU32 firstIndex; 368 NvU32 numEntries; 369 NVSWITCH_REMAP_POLICY_ENTRY remapPolicy[NVSWITCH_REMAP_POLICY_ENTRIES_MAX]; 370 371 } NVSWITCH_SET_REMAP_POLICY; 372 373 /* 374 * CTRL_NVSWITCH_GET_REMAP_POLICY 375 * 376 * Control to get remap policy table 377 * This interface is not supported on SV10 architecture. SV10 will return unsupported 378 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 379 * 380 * Parameters: 381 * portNum [IN] 382 * A valid port number present in the port masks returned by 383 * NVSWITCH_GET_INFO 384 * tableSelect [IN] 385 * Remap table selector 386 * firstIndex [IN] 387 * A starting index of the remap policy table from which table entries 388 * should be read. 389 * numEntries [OUT] 390 * Number of entries returned. This call returns 391 * NVSWITCH_REMAP_POLICY_ENTRIES_MAX entries at a time. 392 * nextIndex [OUT] 393 * The table index of the next entry to read. Set to INGRESS_REMAPTAB_SIZE 394 * when the end of the table has been reached. 395 * entries [OUT] 396 * The entries (see NVSWITCH_REMAP_POLICY_ENTRY). 397 */ 398 399 400 typedef struct nvswitch_get_remap_policy_params 401 { 402 NvU32 portNum; 403 NVSWITCH_TABLE_SELECT_REMAP tableSelect; 404 NvU32 firstIndex; 405 NvU32 numEntries; 406 NvU32 nextIndex; 407 NVSWITCH_REMAP_POLICY_ENTRY entry[NVSWITCH_REMAP_POLICY_ENTRIES_MAX]; 408 409 } NVSWITCH_GET_REMAP_POLICY_PARAMS; 410 411 /* 412 * CTRL_NVSWITCH_SET_REMAP_POLICY_VALID 413 * 414 * Control to set remap policy tables valid/invalid 415 * This interface is not supported on SV10 architecture. SV10 will return unsupported 416 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 417 * 418 * Parameters: 419 * portNum [IN] 420 * A valid port number present in the port masks returned by 421 * NVSWITCH_GET_INFO 422 * tableSelect [IN] 423 * Remap table selector 424 * firstIndex [IN] 425 * A starting index of the remap policy table from which table entries 426 * should be programmed. 427 * numEntries [IN] 428 * Number of entries to be programmed. The call supports 429 * programming of maximum NVSWITCH_REMAP_POLICY_ENTRIES_MAX at a time. 430 * entryValid [IN] 431 * If true, an existing entry is marked valid, else will be marked invalid. 432 */ 433 434 typedef struct nvswitch_set_remap_policy_valid 435 { 436 NvU32 portNum; 437 NVSWITCH_TABLE_SELECT_REMAP tableSelect; 438 NvU32 firstIndex; 439 NvU32 numEntries; 440 NvBool entryValid[NVSWITCH_REMAP_POLICY_ENTRIES_MAX]; 441 442 } NVSWITCH_SET_REMAP_POLICY_VALID; 443 444 /* 445 * CTRL_NVSWITCH_SET_ROUTING_ID 446 * 447 * Control to load Routing ID table 448 * The routing ID table configures the VC and routing policy as well as the 449 * valid set if ganged link routes. 450 * This interface is not supported on SV10 architecture. SV10 will return an 451 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 452 * 453 * Parameters: 454 * portNum [IN] 455 * A valid port number present in the port masks returned by 456 * NVSWITCH_GET_INFO 457 * firstIndex [IN] 458 * A starting index of the routing ID table from which table entries 459 * should be programmed. Valid range should be queried using 460 * NVSWITCH_GET_INFO_INDEX_ROUTING_ID_TABLE_SIZE. 461 * numEntries [IN] 462 * Number of entries to be programmed. Currently, the call supports programming 463 * maximum of NVSWITCH_ROUTING_ID_ENTRIES_MAX entries at a time. 464 * routingId [IN] 465 * The entries (see NVSWITCH_ROUTING_ID_ENTRY). 466 */ 467 468 #define NVSWITCH_ROUTING_ID_DEST_PORT_LIST_MAX 16 469 #define NVSWITCH_ROUTING_ID_VC_MODE_MAX 4 470 #define NVSWITCH_ROUTING_ID_ENTRIES_MAX 64 471 472 typedef enum nvswitch_routing_id_vcmap 473 { 474 NVSWITCH_ROUTING_ID_VCMAP_SAME = 0x0, 475 NVSWITCH_ROUTING_ID_VCMAP_INVERT, 476 NVSWITCH_ROUTING_ID_VCMAP_ZERO, 477 NVSWITCH_ROUTING_ID_VCMAP_ONE 478 /* See enum modification guidelines at the top of this file */ 479 } NVSWITCH_ROUTING_ID_VCMAP; 480 481 typedef struct nvswitch_routing_id_dest_port_list 482 { 483 NvU32 vcMap; /* NVSWITCH_ROUTING_ID_VCMAP_* */ 484 NvU32 destPortNum; 485 486 } NVSWITCH_ROUTING_ID_DEST_PORT_LIST; 487 488 typedef struct nvswitch_routing_id_entry 489 { 490 NvBool entryValid; 491 NvBool useRoutingLan; 492 NvBool enableIrlErrResponse; 493 NvU32 numEntries; 494 NVSWITCH_ROUTING_ID_DEST_PORT_LIST portList[NVSWITCH_ROUTING_ID_DEST_PORT_LIST_MAX]; 495 496 } NVSWITCH_ROUTING_ID_ENTRY; 497 498 typedef struct nvswitch_set_routing_id 499 { 500 NvU32 portNum; 501 NvU32 firstIndex; 502 NvU32 numEntries; 503 NVSWITCH_ROUTING_ID_ENTRY routingId[NVSWITCH_ROUTING_ID_ENTRIES_MAX]; 504 505 } NVSWITCH_SET_ROUTING_ID; 506 507 /* 508 * CTRL_NVSWITCH_GET_ROUTING_ID 509 * 510 * Control to get routing ID table 511 * This interface is not supported on SV10 architecture. SV10 will return unsupported 512 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 513 * 514 * Parameters: 515 * portNum [IN] 516 * A valid port number present in the port masks returned by 517 * NVSWITCH_GET_INFO 518 * firstIndex [IN] 519 * A starting index of the routing id table from which table entries 520 * should be read. 521 * numEntries [OUT] 522 * Number of entries returned. The call returns only 523 * NVSWITCH_ROUTING_ID_ENTRIES_MAX entries at a time. 524 * nextIndex [OUT] 525 * The table index of the next entry to read. Set to INGRESS_RIDTAB_SIZE 526 * when the end of the table has been reached. 527 * entries [OUT] 528 * The entries (see NVSWITCH_ROUTING_ID_IDX_ENTRY). 529 */ 530 531 typedef struct nvswitch_routing_id_idx_entry 532 { 533 NvU32 idx; 534 NVSWITCH_ROUTING_ID_ENTRY entry; 535 536 } NVSWITCH_ROUTING_ID_IDX_ENTRY; 537 538 typedef struct nvswitch_get_routing_id_params 539 { 540 NvU32 portNum; 541 NvU32 firstIndex; 542 NvU32 numEntries; 543 NvU32 nextIndex; 544 NVSWITCH_ROUTING_ID_IDX_ENTRY entries[NVSWITCH_ROUTING_ID_ENTRIES_MAX]; 545 546 } NVSWITCH_GET_ROUTING_ID_PARAMS; 547 548 /* 549 * CTRL_NVSWITCH_SET_ROUTING_ID_VALID 550 * 551 * Control to set routing ID tables valid/invalid 552 * This interface is not supported on SV10 architecture. SV10 will return unsupported 553 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 554 * 555 * Parameters: 556 * portNum [IN] 557 * A valid port number present in the port masks returned by 558 * NVSWITCH_GET_INFO 559 * firstIndex [IN] 560 * A starting index of the routing lan table from which table entries 561 * should be programmed. 562 * numEntries [IN] 563 * Number of entries to be programmed. This call supports programming 564 * maximum entries of NVSWITCH_ROUTING_ID_ENTRIES_MAX at a time. 565 * entryValid [IN] 566 * If true, an existing entry is marked valid, else will be marked invalid. 567 */ 568 569 typedef struct nvswitch_set_routing_id_valid 570 { 571 NvU32 portNum; 572 NvU32 firstIndex; 573 NvU32 numEntries; 574 NvBool entryValid[NVSWITCH_ROUTING_ID_ENTRIES_MAX]; 575 576 } NVSWITCH_SET_ROUTING_ID_VALID; 577 578 /* 579 * CTRL_NVSWITCH_SET_ROUTING_LAN 580 * 581 * Control to load routing LAN table 582 * This interface is not supported on SV10 architecture. SV10 will return an 583 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 584 * 585 * Parameters: 586 * portNum [IN] 587 * A valid port number present in the port masks returned by 588 * NVSWITCH_GET_INFO 589 * firstIndex [IN] 590 * A starting index of the ingress request table from which table entries 591 * should be programmed. Valid range should be queried using 592 * NVSWITCH_GET_INFO_INDEX_ROUTING_LAN_TABLE_SIZE. 593 * numEntries [IN] 594 * Number of entries to be programmed. Currently, the call supports 595 * programming NVSWITCH_ROUTING_LAN_ENTRIES_MAX at a time. 596 * routingLan [IN] 597 * The entries (see NVSWITCH_ROUTING_LAN_ENTRY). 598 */ 599 600 #define NVSWITCH_ROUTING_LAN_GROUP_SEL_MAX 16 601 #define NVSWITCH_ROUTING_LAN_GROUP_SIZE_MAX 16 602 #define NVSWITCH_ROUTING_LAN_ENTRIES_MAX 64 603 604 typedef struct nvswitch_routing_lan_port_select 605 { 606 NvU32 groupSelect; /* Port list group selector */ 607 NvU32 groupSize; /* Valid range: 1..16 */ 608 609 } NVSWITCH_ROUTING_LAN_PORT_SELECT; 610 611 typedef struct nvswitch_routing_lan_entry 612 { 613 NvBool entryValid; 614 NvU32 numEntries; 615 NVSWITCH_ROUTING_LAN_PORT_SELECT portList[NVSWITCH_ROUTING_LAN_GROUP_SEL_MAX]; 616 617 } NVSWITCH_ROUTING_LAN_ENTRY; 618 619 typedef struct nvswitch_set_routing_lan 620 { 621 NvU32 portNum; 622 NvU32 firstIndex; 623 NvU32 numEntries; 624 NVSWITCH_ROUTING_LAN_ENTRY routingLan[NVSWITCH_ROUTING_LAN_ENTRIES_MAX]; 625 626 } NVSWITCH_SET_ROUTING_LAN; 627 628 /* 629 * CTRL_NVSWITCH_GET_ROUTING_LAN 630 * 631 * Control to get routing LAN table 632 * This interface is not supported on SV10 architecture. SV10 will return unsupported 633 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 634 * 635 * Parameters: 636 * portNum [IN] 637 * A valid port number present in the port masks returned by 638 * NVSWITCH_GET_INFO 639 * firstIndex [IN] 640 * A starting index of the routing lan table from which table entries 641 * should be read. 642 * numEntries [OUT] 643 * Number of entries returned. Currently, the call supports 644 * NVSWITCH_ROUTING_LAN_ENTRIES_MAX at a time. 645 * nextIndex [OUT] 646 * The table index of the next entry to read. Set to INGRESS_RLANTAB_SIZE 647 * when the end of the table has been reached. 648 * entries [OUT] 649 * The entries (see NVSWITCH_ROUTING_LAN_IDX_ENTRY). 650 */ 651 652 typedef struct nvswitch_routing_lan_idx_entry 653 { 654 NvU32 idx; 655 NVSWITCH_ROUTING_LAN_ENTRY entry; 656 657 } NVSWITCH_ROUTING_LAN_IDX_ENTRY; 658 659 typedef struct nvswitch_get_routing_lan_params 660 { 661 NvU32 portNum; 662 NvU32 firstIndex; 663 NvU32 numEntries; 664 NvU32 nextIndex; 665 NVSWITCH_ROUTING_LAN_IDX_ENTRY entries[NVSWITCH_ROUTING_LAN_ENTRIES_MAX]; 666 667 } NVSWITCH_GET_ROUTING_LAN_PARAMS; 668 669 /* 670 * CTRL_NVSWITCH_SET_ROUTING_LAN_VALID 671 * 672 * Control to set routing LAN tables valid/invalid 673 * This interface is not supported on SV10 architecture. SV10 will return unsupported 674 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 675 * 676 * Parameters: 677 * portNum [IN] 678 * A valid port number present in the port masks returned by 679 * NVSWITCH_GET_INFO 680 * firstIndex [IN] 681 * A starting index of the routing lan table from which table entries 682 * should be programmed. 683 * numEntries [IN] 684 * Number of entries to be programmed. Currently, the call supports 685 * programming NVSWITCH_ROUTING_LAN_ENTRIES_MAX at a time. 686 * entryValid [IN] 687 * If true, an existing entry is marked valid, else will be marked invalid. 688 */ 689 690 typedef struct nvswitch_set_routing_lan_valid 691 { 692 NvU32 portNum; 693 NvU32 firstIndex; 694 NvU32 numEntries; 695 NvBool entryValid[NVSWITCH_ROUTING_LAN_ENTRIES_MAX]; 696 697 } NVSWITCH_SET_ROUTING_LAN_VALID; 698 699 /* 700 * CTRL_NVSWITCH_GET_INGRESS_RESPONSE_TABLE 701 * 702 * Control for reading ingress response tables. A sparse list of nonzero entries 703 * and their table indices is returned. 704 * 705 * Parameters: 706 * portNum [IN] 707 * A valid port number present in the port masks returned by 708 * NVSWITCH_GET_INFO 709 * firstIndex [IN] 710 * A starting index of the ingress response table from which table entries 711 * should be read. 712 * nextIndex [OUT] 713 * The table index of the next entry to read. Set to INGRESS_MAP_TABLE_SIZE 714 * when the end of the table has been reached. 715 * numEntries [OUT] 716 * Number of entries returned. Currently, the call supports returning up to 717 * NVSWITCH_INGRESS_RESPONSE_ENTRIES_MAX entries at a time. 718 * entries [OUT] 719 * Ingress response entries along with their table indices. 720 * Entry format is architecture dependent. 721 */ 722 723 typedef struct nvswitch_ingress_response_idx_entry 724 { 725 NvU32 idx; 726 NVSWITCH_INGRESS_RESPONSE_ENTRY entry; 727 728 } NVSWITCH_INGRESS_RESPONSE_IDX_ENTRY; 729 730 typedef struct nvswitch_get_ingress_response_table_params 731 { 732 NvU32 portNum; 733 NvU32 firstIndex; 734 NvU32 nextIndex; 735 NvU32 numEntries; 736 NVSWITCH_INGRESS_RESPONSE_IDX_ENTRY entries[NVSWITCH_INGRESS_RESPONSE_ENTRIES_MAX]; 737 738 } NVSWITCH_GET_INGRESS_RESPONSE_TABLE_PARAMS; 739 740 /* 741 * CTRL_NVSWITCH_GET_VOLTAGE 742 * 743 * Zero(0) indicates that a measurement is not available on the current platform. 744 * 745 */ 746 747 typedef struct 748 { 749 NvU32 vdd_mv; 750 NvU32 dvdd_mv; 751 NvU32 hvdd_mv; 752 } NVSWITCH_CTRL_GET_VOLTAGE_PARAMS; 753 754 /* 755 * CTRL_NVSWITCH_GET_POWER 756 * 757 * Zero(0) indicates that a measurement is not available 758 * on the current platform. 759 */ 760 typedef struct 761 { 762 NvU32 vdd_w; 763 NvU32 dvdd_w; 764 NvU32 hvdd_w; 765 } NVSWITCH_GET_POWER_PARAMS; 766 767 /* 768 * CTRL_NVSWITCH_GET_ERRORS 769 * 770 * Control to query error information. 771 * 772 * Parameters: 773 * errorType [IN] 774 * Allows to query specific class of errors. See NVSWITCH_ERROR_SEVERITY_xxx. 775 * 776 * errorIndex [IN/OUT] 777 * On input: The index of the first error of the specified 'errorType' at which to start 778 * reading out of the driver. 779 * 780 * On output: The index of the first error that wasn't reported through the 'error' array 781 * in this call to CTRL_NVSWITCH_GET_ERRORS. Specific to the specified 'errorType'. 782 * 783 * nextErrorIndex[OUT] 784 * The index that will be assigned to the next error to occur for the specified 'errorType'. 785 * Users of the GET_ERRORS control call may set 'errorIndex' to this field on initialization 786 * to bypass errors that have already occurred without making multiple control calls. 787 * 788 * errorCount [OUT] 789 * Number of errors returned by the call. Currently, errorCount is limited 790 * by NVSWITCH_ERROR_COUNT_SIZE. In order to query all the errors, a 791 * client needs to keep calling the control till errorCount is zero. 792 * error [OUT] 793 * The error entires. 794 */ 795 796 typedef enum nvswitch_error_severity_type 797 { 798 NVSWITCH_ERROR_SEVERITY_NONFATAL = 0, 799 NVSWITCH_ERROR_SEVERITY_FATAL, 800 NVSWITCH_ERROR_SEVERITY_MAX 801 /* See enum modification guidelines at the top of this file */ 802 } NVSWITCH_ERROR_SEVERITY_TYPE; 803 804 typedef enum nvswitch_error_src_type 805 { 806 NVSWITCH_ERROR_SRC_NONE = 0, 807 NVSWITCH_ERROR_SRC_HW 808 /* See enum modification guidelines at the top of this file */ 809 } NVSWITCH_ERROR_SRC_TYPE; 810 811 typedef enum nvswitch_err_type 812 { 813 NVSWITCH_ERR_NO_ERROR = 0x0, 814 815 /* 816 * These error enumerations are derived from the error bits defined in each 817 * hardware manual. 818 * 819 * NVSwitch errors values should start from 10000 (decimal) to be 820 * distinguishable from GPU errors. 821 */ 822 823 /* HOST */ 824 NVSWITCH_ERR_HW_HOST = 10000, 825 NVSWITCH_ERR_HW_HOST_PRIV_ERROR = 10001, 826 NVSWITCH_ERR_HW_HOST_PRIV_TIMEOUT = 10002, 827 NVSWITCH_ERR_HW_HOST_UNHANDLED_INTERRUPT = 10003, 828 NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_START = 10004, 829 NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_END = 10005, 830 NVSWITCH_ERR_HW_HOST_THERMAL_SHUTDOWN = 10006, 831 NVSWITCH_ERR_HW_HOST_IO_FAILURE = 10007, 832 NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE = 10008, 833 NVSWITCH_ERR_HW_HOST_FIRMWARE_RECOVERY_MODE = 10009, 834 NVSWITCH_ERR_HW_HOST_LAST, 835 836 837 /* NPORT: Ingress errors */ 838 NVSWITCH_ERR_HW_NPORT_INGRESS = 11000, 839 NVSWITCH_ERR_HW_NPORT_INGRESS_CMDDECODEERR = 11001, 840 NVSWITCH_ERR_HW_NPORT_INGRESS_BDFMISMATCHERR = 11002, 841 NVSWITCH_ERR_HW_NPORT_INGRESS_BUBBLEDETECT = 11003, 842 NVSWITCH_ERR_HW_NPORT_INGRESS_ACLFAIL = 11004, 843 NVSWITCH_ERR_HW_NPORT_INGRESS_PKTPOISONSET = 11005, 844 NVSWITCH_ERR_HW_NPORT_INGRESS_ECCSOFTLIMITERR = 11006, 845 NVSWITCH_ERR_HW_NPORT_INGRESS_ECCHDRDOUBLEBITERR = 11007, 846 NVSWITCH_ERR_HW_NPORT_INGRESS_INVALIDCMD = 11008, 847 NVSWITCH_ERR_HW_NPORT_INGRESS_INVALIDVCSET = 11009, 848 NVSWITCH_ERR_HW_NPORT_INGRESS_ERRORINFO = 11010, 849 NVSWITCH_ERR_HW_NPORT_INGRESS_REQCONTEXTMISMATCHERR = 11011, 850 NVSWITCH_ERR_HW_NPORT_INGRESS_NCISOC_HDR_ECC_LIMIT_ERR = 11012, 851 NVSWITCH_ERR_HW_NPORT_INGRESS_NCISOC_HDR_ECC_DBE_ERR = 11013, 852 NVSWITCH_ERR_HW_NPORT_INGRESS_ADDRBOUNDSERR = 11014, 853 NVSWITCH_ERR_HW_NPORT_INGRESS_RIDTABCFGERR = 11015, 854 NVSWITCH_ERR_HW_NPORT_INGRESS_RLANTABCFGERR = 11016, 855 NVSWITCH_ERR_HW_NPORT_INGRESS_REMAPTAB_ECC_DBE_ERR = 11017, 856 NVSWITCH_ERR_HW_NPORT_INGRESS_RIDTAB_ECC_DBE_ERR = 11018, 857 NVSWITCH_ERR_HW_NPORT_INGRESS_RLANTAB_ECC_DBE_ERR = 11019, 858 NVSWITCH_ERR_HW_NPORT_INGRESS_NCISOC_PARITY_ERR = 11020, 859 NVSWITCH_ERR_HW_NPORT_INGRESS_REMAPTAB_ECC_LIMIT_ERR = 11021, 860 NVSWITCH_ERR_HW_NPORT_INGRESS_RIDTAB_ECC_LIMIT_ERR = 11022, 861 NVSWITCH_ERR_HW_NPORT_INGRESS_RLANTAB_ECC_LIMIT_ERR = 11023, 862 NVSWITCH_ERR_HW_NPORT_INGRESS_ADDRTYPEERR = 11024, 863 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_INDEX_ERR = 11025, 864 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_INDEX_ERR = 11026, 865 NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_INDEX_ERR = 11027, 866 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_DBE_ERR = 11028, 867 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_DBE_ERR = 11029, 868 NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ECC_DBE_ERR = 11030, 869 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_REQCONTEXTMISMATCHERR = 11031, 870 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_REQCONTEXTMISMATCHERR = 11032, 871 NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_REQCONTEXTMISMATCHERR = 11033, 872 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ACLFAIL = 11034, 873 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ACLFAIL = 11035, 874 NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ACLFAIL = 11036, 875 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ADDRBOUNDSERR = 11037, 876 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ADDRBOUNDSERR = 11038, 877 NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ADDRBOUNDSERR = 11039, 878 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_LIMIT_ERR = 11040, 879 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_LIMIT_ERR = 11041, 880 NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ECC_LIMIT_ERR = 11042, 881 NVSWITCH_ERR_HW_NPORT_INGRESS_MCCMDTOUCADDRERR = 11043, 882 NVSWITCH_ERR_HW_NPORT_INGRESS_READMCREFLECTMEMERR = 11044, 883 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ADDRTYPEERR = 11045, 884 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ADDRTYPEERR = 11046, 885 NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ADDRTYPEERR = 11047, 886 NVSWITCH_ERR_HW_NPORT_INGRESS_LAST, /* NOTE: Must be last */ 887 888 /* NPORT: Egress errors */ 889 NVSWITCH_ERR_HW_NPORT_EGRESS = 12000, 890 NVSWITCH_ERR_HW_NPORT_EGRESS_EGRESSBUFERR = 12001, 891 NVSWITCH_ERR_HW_NPORT_EGRESS_PKTROUTEERR = 12002, 892 NVSWITCH_ERR_HW_NPORT_EGRESS_ECCSINGLEBITLIMITERR0 = 12003, 893 NVSWITCH_ERR_HW_NPORT_EGRESS_ECCHDRDOUBLEBITERR0 = 12004, 894 NVSWITCH_ERR_HW_NPORT_EGRESS_ECCDATADOUBLEBITERR0 = 12005, 895 NVSWITCH_ERR_HW_NPORT_EGRESS_ECCSINGLEBITLIMITERR1 = 12006, 896 NVSWITCH_ERR_HW_NPORT_EGRESS_ECCHDRDOUBLEBITERR1 = 12007, 897 NVSWITCH_ERR_HW_NPORT_EGRESS_ECCDATADOUBLEBITERR1 = 12008, 898 NVSWITCH_ERR_HW_NPORT_EGRESS_NCISOCHDRCREDITOVFL = 12009, 899 NVSWITCH_ERR_HW_NPORT_EGRESS_NCISOCDATACREDITOVFL = 12010, 900 NVSWITCH_ERR_HW_NPORT_EGRESS_ADDRMATCHERR = 12011, 901 NVSWITCH_ERR_HW_NPORT_EGRESS_TAGCOUNTERR = 12012, 902 NVSWITCH_ERR_HW_NPORT_EGRESS_FLUSHRSPERR = 12013, 903 NVSWITCH_ERR_HW_NPORT_EGRESS_DROPNPURRSPERR = 12014, 904 NVSWITCH_ERR_HW_NPORT_EGRESS_POISONERR = 12015, 905 NVSWITCH_ERR_HW_NPORT_EGRESS_PACKET_HEADER = 12016, 906 NVSWITCH_ERR_HW_NPORT_EGRESS_BUFFER_DATA = 12017, 907 NVSWITCH_ERR_HW_NPORT_EGRESS_NCISOC_CREDITS = 12018, 908 NVSWITCH_ERR_HW_NPORT_EGRESS_TAG_DATA = 12019, 909 NVSWITCH_ERR_HW_NPORT_EGRESS_SEQIDERR = 12020, 910 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_HDR_ECC_LIMIT_ERR = 12021, 911 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_HDR_ECC_DBE_ERR = 12022, 912 NVSWITCH_ERR_HW_NPORT_EGRESS_RAM_OUT_HDR_ECC_LIMIT_ERR = 12023, 913 NVSWITCH_ERR_HW_NPORT_EGRESS_RAM_OUT_HDR_ECC_DBE_ERR = 12024, 914 NVSWITCH_ERR_HW_NPORT_EGRESS_NCISOCCREDITOVFL = 12025, 915 NVSWITCH_ERR_HW_NPORT_EGRESS_REQTGTIDMISMATCHERR = 12026, 916 NVSWITCH_ERR_HW_NPORT_EGRESS_RSPREQIDMISMATCHERR = 12027, 917 NVSWITCH_ERR_HW_NPORT_EGRESS_PRIVRSPERR = 12028, 918 NVSWITCH_ERR_HW_NPORT_EGRESS_HWRSPERR = 12029, 919 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_HDR_PARITY_ERR = 12030, 920 NVSWITCH_ERR_HW_NPORT_EGRESS_NCISOC_CREDIT_PARITY_ERR = 12031, 921 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_FLITTYPE_MISMATCH_ERR = 12032, 922 NVSWITCH_ERR_HW_NPORT_EGRESS_CREDIT_TIME_OUT_ERR = 12033, 923 NVSWITCH_ERR_HW_NPORT_EGRESS_INVALIDVCSET_ERR = 12034, 924 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_SIDEBAND_PD_PARITY_ERR = 12035, 925 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR = 12036, 926 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_ECC_DBE_ERR = 12037, 927 NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_LIMIT_ERR = 12038, 928 NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_DBE_ERR = 12039, 929 NVSWITCH_ERR_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_LIMIT_ERR = 12040, 930 NVSWITCH_ERR_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_DBE_ERR = 12041, 931 NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDSGT_ECC_LIMIT_ERR = 12042, 932 NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDSGT_ECC_DBE_ERR = 12043, 933 NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDBUF_ECC_LIMIT_ERR = 12044, 934 NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDBUF_ECC_DBE_ERR = 12045, 935 NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_LIMIT_ERR = 12046, 936 NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_DBE_ERR = 12047, 937 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_PARITY_ERR = 12048, 938 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR = 12049, 939 NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSP_CNT_ERR = 12050, 940 NVSWITCH_ERR_HW_NPORT_EGRESS_RBRSP_CNT_ERR = 12051, 941 NVSWITCH_ERR_HW_NPORT_EGRESS_LAST, /* NOTE: Must be last */ 942 943 /* NPORT: Fstate errors */ 944 NVSWITCH_ERR_HW_NPORT_FSTATE = 13000, 945 NVSWITCH_ERR_HW_NPORT_FSTATE_TAGPOOLBUFERR = 13001, 946 NVSWITCH_ERR_HW_NPORT_FSTATE_CRUMBSTOREBUFERR = 13002, 947 NVSWITCH_ERR_HW_NPORT_FSTATE_SINGLEBITECCLIMITERR_CRUMBSTORE = 13003, 948 NVSWITCH_ERR_HW_NPORT_FSTATE_UNCORRECTABLEECCERR_CRUMBSTORE = 13004, 949 NVSWITCH_ERR_HW_NPORT_FSTATE_SINGLEBITECCLIMITERR_TAGSTORE = 13005, 950 NVSWITCH_ERR_HW_NPORT_FSTATE_UNCORRECTABLEECCERR_TAGSTORE = 13006, 951 NVSWITCH_ERR_HW_NPORT_FSTATE_SINGLEBITECCLIMITERR_FLUSHREQSTORE = 13007, 952 NVSWITCH_ERR_HW_NPORT_FSTATE_UNCORRECTABLEECCERR_FLUSHREQSTORE = 13008, 953 NVSWITCH_ERR_HW_NPORT_FSTATE_LAST, /* NOTE: Must be last */ 954 955 /* NPORT: Tstate errors */ 956 NVSWITCH_ERR_HW_NPORT_TSTATE = 14000, 957 NVSWITCH_ERR_HW_NPORT_TSTATE_TAGPOOLBUFERR = 14001, 958 NVSWITCH_ERR_HW_NPORT_TSTATE_CRUMBSTOREBUFERR = 14002, 959 NVSWITCH_ERR_HW_NPORT_TSTATE_SINGLEBITECCLIMITERR_CRUMBSTORE = 14003, 960 NVSWITCH_ERR_HW_NPORT_TSTATE_UNCORRECTABLEECCERR_CRUMBSTORE = 14004, 961 NVSWITCH_ERR_HW_NPORT_TSTATE_SINGLEBITECCLIMITERR_TAGSTORE = 14005, 962 NVSWITCH_ERR_HW_NPORT_TSTATE_UNCORRECTABLEECCERR_TAGSTORE = 14006, 963 NVSWITCH_ERR_HW_NPORT_TSTATE_TAGPOOL_ECC_LIMIT_ERR = 14007, 964 NVSWITCH_ERR_HW_NPORT_TSTATE_TAGPOOL_ECC_DBE_ERR = 14008, 965 NVSWITCH_ERR_HW_NPORT_TSTATE_CRUMBSTORE_ECC_LIMIT_ERR = 14009, 966 NVSWITCH_ERR_HW_NPORT_TSTATE_CRUMBSTORE_ECC_DBE_ERR = 14010, 967 NVSWITCH_ERR_HW_NPORT_TSTATE_COL_CRUMBSTOREBUFERR = 14011, 968 NVSWITCH_ERR_HW_NPORT_TSTATE_COL_CRUMBSTORE_ECC_LIMIT_ERR = 14012, 969 NVSWITCH_ERR_HW_NPORT_TSTATE_COL_CRUMBSTORE_ECC_DBE_ERR = 14013, 970 NVSWITCH_ERR_HW_NPORT_TSTATE_TD_TID_RAMBUFERR = 14014, 971 NVSWITCH_ERR_HW_NPORT_TSTATE_TD_TID_RAM_ECC_LIMIT_ERR = 14015, 972 NVSWITCH_ERR_HW_NPORT_TSTATE_TD_TID_RAM_ECC_DBE_ERR = 14016, 973 NVSWITCH_ERR_HW_NPORT_TSTATE_ATO_ERR = 14017, 974 NVSWITCH_ERR_HW_NPORT_TSTATE_CAMRSP_ERR = 14018, 975 NVSWITCH_ERR_HW_NPORT_TSTATE_LAST, /* NOTE: Must be last */ 976 977 /* NPORT: Route errors */ 978 NVSWITCH_ERR_HW_NPORT_ROUTE = 15000, 979 NVSWITCH_ERR_HW_NPORT_ROUTE_ROUTEBUFERR = 15001, 980 NVSWITCH_ERR_HW_NPORT_ROUTE_NOPORTDEFINEDERR = 15002, 981 NVSWITCH_ERR_HW_NPORT_ROUTE_INVALIDROUTEPOLICYERR = 15003, 982 NVSWITCH_ERR_HW_NPORT_ROUTE_ECCLIMITERR = 15004, 983 NVSWITCH_ERR_HW_NPORT_ROUTE_UNCORRECTABLEECCERR = 15005, 984 NVSWITCH_ERR_HW_NPORT_ROUTE_TRANSDONERESVERR = 15006, 985 NVSWITCH_ERR_HW_NPORT_ROUTE_PACKET_HEADER = 15007, 986 NVSWITCH_ERR_HW_NPORT_ROUTE_GLT_ECC_LIMIT_ERR = 15008, 987 NVSWITCH_ERR_HW_NPORT_ROUTE_GLT_ECC_DBE_ERR = 15009, 988 NVSWITCH_ERR_HW_NPORT_ROUTE_PDCTRLPARERR = 15010, 989 NVSWITCH_ERR_HW_NPORT_ROUTE_NVS_ECC_LIMIT_ERR = 15011, 990 NVSWITCH_ERR_HW_NPORT_ROUTE_NVS_ECC_DBE_ERR = 15012, 991 NVSWITCH_ERR_HW_NPORT_ROUTE_CDTPARERR = 15013, 992 NVSWITCH_ERR_HW_NPORT_ROUTE_MCRID_ECC_LIMIT_ERR = 15014, 993 NVSWITCH_ERR_HW_NPORT_ROUTE_MCRID_ECC_DBE_ERR = 15015, 994 NVSWITCH_ERR_HW_NPORT_ROUTE_EXTMCRID_ECC_LIMIT_ERR = 15016, 995 NVSWITCH_ERR_HW_NPORT_ROUTE_EXTMCRID_ECC_DBE_ERR = 15017, 996 NVSWITCH_ERR_HW_NPORT_ROUTE_RAM_ECC_LIMIT_ERR = 15018, 997 NVSWITCH_ERR_HW_NPORT_ROUTE_RAM_ECC_DBE_ERR = 15019, 998 NVSWITCH_ERR_HW_NPORT_ROUTE_INVALID_MCRID_ERR = 15020, 999 NVSWITCH_ERR_HW_NPORT_ROUTE_LAST, /* NOTE: Must be last */ 1000 1001 /* NPORT: Nport errors */ 1002 NVSWITCH_ERR_HW_NPORT = 16000, 1003 NVSWITCH_ERR_HW_NPORT_DATAPOISONED = 16001, 1004 NVSWITCH_ERR_HW_NPORT_UCINTERNAL = 16002, 1005 NVSWITCH_ERR_HW_NPORT_CINTERNAL = 16003, 1006 NVSWITCH_ERR_HW_NPORT_LAST, /* NOTE: Must be last */ 1007 1008 /* NVLCTRL: NVCTRL errors */ 1009 NVSWITCH_ERR_HW_NVLCTRL = 17000, 1010 NVSWITCH_ERR_HW_NVLCTRL_INGRESSECCSOFTLIMITERR = 17001, 1011 NVSWITCH_ERR_HW_NVLCTRL_INGRESSECCHDRDOUBLEBITERR = 17002, 1012 NVSWITCH_ERR_HW_NVLCTRL_INGRESSECCDATADOUBLEBITERR = 17003, 1013 NVSWITCH_ERR_HW_NVLCTRL_INGRESSBUFFERERR = 17004, 1014 NVSWITCH_ERR_HW_NVLCTRL_EGRESSECCSOFTLIMITERR = 17005, 1015 NVSWITCH_ERR_HW_NVLCTRL_EGRESSECCHDRDOUBLEBITERR = 17006, 1016 NVSWITCH_ERR_HW_NVLCTRL_EGRESSECCDATADOUBLEBITERR = 17007, 1017 NVSWITCH_ERR_HW_NVLCTRL_EGRESSBUFFERERR = 17008, 1018 NVSWITCH_ERR_HW_NVLCTRL_LAST, /* NOTE: Must be last */ 1019 1020 /* Nport: Nvlipt errors */ 1021 NVSWITCH_ERR_HW_NVLIPT = 18000, 1022 NVSWITCH_ERR_HW_NVLIPT_DLPROTOCOL = 18001, 1023 NVSWITCH_ERR_HW_NVLIPT_DATAPOISONED = 18002, 1024 NVSWITCH_ERR_HW_NVLIPT_FLOWCONTROL = 18003, 1025 NVSWITCH_ERR_HW_NVLIPT_RESPONSETIMEOUT = 18004, 1026 NVSWITCH_ERR_HW_NVLIPT_TARGETERROR = 18005, 1027 NVSWITCH_ERR_HW_NVLIPT_UNEXPECTEDRESPONSE = 18006, 1028 NVSWITCH_ERR_HW_NVLIPT_RECEIVEROVERFLOW = 18007, 1029 NVSWITCH_ERR_HW_NVLIPT_MALFORMEDPACKET = 18008, 1030 NVSWITCH_ERR_HW_NVLIPT_STOMPEDPACKETRECEIVED = 18009, 1031 NVSWITCH_ERR_HW_NVLIPT_UNSUPPORTEDREQUEST = 18010, 1032 NVSWITCH_ERR_HW_NVLIPT_UCINTERNAL = 18011, 1033 NVSWITCH_ERR_HW_NVLIPT_PHYRECEIVER = 18012, 1034 NVSWITCH_ERR_HW_NVLIPT_BADAN0PKT = 18013, 1035 NVSWITCH_ERR_HW_NVLIPT_REPLAYTIMEOUT = 18014, 1036 NVSWITCH_ERR_HW_NVLIPT_ADVISORYERROR = 18015, 1037 NVSWITCH_ERR_HW_NVLIPT_CINTERNAL = 18016, 1038 NVSWITCH_ERR_HW_NVLIPT_HEADEROVERFLOW = 18017, 1039 NVSWITCH_ERR_HW_NVLIPT_RSTSEQ_PHYARB_TIMEOUT = 18018, 1040 NVSWITCH_ERR_HW_NVLIPT_RSTSEQ_PLL_TIMEOUT = 18019, 1041 NVSWITCH_ERR_HW_NVLIPT_CLKCTL_ILLEGAL_REQUEST = 18020, 1042 NVSWITCH_ERR_HW_NVLIPT_LAST, /* NOTE: Must be last */ 1043 1044 /* Nport: Nvltlc TX/RX errors */ 1045 NVSWITCH_ERR_HW_NVLTLC = 19000, 1046 NVSWITCH_ERR_HW_NVLTLC_TXHDRCREDITOVFERR = 19001, 1047 NVSWITCH_ERR_HW_NVLTLC_TXDATACREDITOVFERR = 19002, 1048 NVSWITCH_ERR_HW_NVLTLC_TXDLCREDITOVFERR = 19003, 1049 NVSWITCH_ERR_HW_NVLTLC_TXDLCREDITPARITYERR = 19004, 1050 NVSWITCH_ERR_HW_NVLTLC_TXRAMHDRPARITYERR = 19005, 1051 NVSWITCH_ERR_HW_NVLTLC_TXRAMDATAPARITYERR = 19006, 1052 NVSWITCH_ERR_HW_NVLTLC_TXUNSUPVCOVFERR = 19007, 1053 NVSWITCH_ERR_HW_NVLTLC_TXSTOMPDET = 19008, 1054 NVSWITCH_ERR_HW_NVLTLC_TXPOISONDET = 19009, 1055 NVSWITCH_ERR_HW_NVLTLC_TARGETERR = 19010, 1056 NVSWITCH_ERR_HW_NVLTLC_TX_PACKET_HEADER = 19011, 1057 NVSWITCH_ERR_HW_NVLTLC_UNSUPPORTEDREQUESTERR = 19012, 1058 NVSWITCH_ERR_HW_NVLTLC_RXDLHDRPARITYERR = 19013, 1059 NVSWITCH_ERR_HW_NVLTLC_RXDLDATAPARITYERR = 19014, 1060 NVSWITCH_ERR_HW_NVLTLC_RXDLCTRLPARITYERR = 19015, 1061 NVSWITCH_ERR_HW_NVLTLC_RXRAMDATAPARITYERR = 19016, 1062 NVSWITCH_ERR_HW_NVLTLC_RXRAMHDRPARITYERR = 19017, 1063 NVSWITCH_ERR_HW_NVLTLC_RXINVALIDAEERR = 19018, 1064 NVSWITCH_ERR_HW_NVLTLC_RXINVALIDBEERR = 19019, 1065 NVSWITCH_ERR_HW_NVLTLC_RXINVALIDADDRALIGNERR = 19020, 1066 NVSWITCH_ERR_HW_NVLTLC_RXPKTLENERR = 19021, 1067 NVSWITCH_ERR_HW_NVLTLC_RSVCMDENCERR = 19022, 1068 NVSWITCH_ERR_HW_NVLTLC_RSVDATLENENCERR = 19023, 1069 NVSWITCH_ERR_HW_NVLTLC_RSVADDRTYPEERR = 19024, 1070 NVSWITCH_ERR_HW_NVLTLC_RSVRSPSTATUSERR = 19025, 1071 NVSWITCH_ERR_HW_NVLTLC_RSVPKTSTATUSERR = 19026, 1072 NVSWITCH_ERR_HW_NVLTLC_RSVCACHEATTRPROBEREQERR = 19027, 1073 NVSWITCH_ERR_HW_NVLTLC_RSVCACHEATTRPROBERSPERR = 19028, 1074 NVSWITCH_ERR_HW_NVLTLC_DATLENGTATOMICREQMAXERR = 19029, 1075 NVSWITCH_ERR_HW_NVLTLC_DATLENGTRMWREQMAXERR = 19030, 1076 NVSWITCH_ERR_HW_NVLTLC_DATLENLTATRRSPMINERR = 19031, 1077 NVSWITCH_ERR_HW_NVLTLC_INVALIDCACHEATTRPOERR = 19032, 1078 NVSWITCH_ERR_HW_NVLTLC_INVALIDCRERR = 19033, 1079 NVSWITCH_ERR_HW_NVLTLC_RXRESPSTATUSTARGETERR = 19034, 1080 NVSWITCH_ERR_HW_NVLTLC_RXRESPSTATUSUNSUPPORTEDREQUESTERR = 19035, 1081 NVSWITCH_ERR_HW_NVLTLC_RXHDROVFERR = 19036, 1082 NVSWITCH_ERR_HW_NVLTLC_RXDATAOVFERR = 19037, 1083 NVSWITCH_ERR_HW_NVLTLC_STOMPDETERR = 19038, 1084 NVSWITCH_ERR_HW_NVLTLC_RXPOISONERR = 19039, 1085 NVSWITCH_ERR_HW_NVLTLC_CORRECTABLEINTERNALERR = 19040, 1086 NVSWITCH_ERR_HW_NVLTLC_RXUNSUPVCOVFERR = 19041, 1087 NVSWITCH_ERR_HW_NVLTLC_RXUNSUPNVLINKCREDITRELERR = 19042, 1088 NVSWITCH_ERR_HW_NVLTLC_RXUNSUPNCISOCCREDITRELERR = 19043, 1089 NVSWITCH_ERR_HW_NVLTLC_RX_PACKET_HEADER = 19044, 1090 NVSWITCH_ERR_HW_NVLTLC_RX_ERR_HEADER = 19045, 1091 NVSWITCH_ERR_HW_NVLTLC_TX_SYS_NCISOC_PARITY_ERR = 19046, 1092 NVSWITCH_ERR_HW_NVLTLC_TX_SYS_NCISOC_HDR_ECC_DBE_ERR = 19047, 1093 NVSWITCH_ERR_HW_NVLTLC_TX_SYS_NCISOC_DAT_ECC_DBE_ERR = 19048, 1094 NVSWITCH_ERR_HW_NVLTLC_TX_SYS_NCISOC_ECC_LIMIT_ERR = 19049, 1095 NVSWITCH_ERR_HW_NVLTLC_TX_SYS_TXRSPSTATUS_HW_ERR = 19050, 1096 NVSWITCH_ERR_HW_NVLTLC_TX_SYS_TXRSPSTATUS_UR_ERR = 19051, 1097 NVSWITCH_ERR_HW_NVLTLC_TX_SYS_TXRSPSTATUS_PRIV_ERR = 19052, 1098 NVSWITCH_ERR_HW_NVLTLC_RX_SYS_NCISOC_PARITY_ERR = 19053, 1099 NVSWITCH_ERR_HW_NVLTLC_RX_SYS_HDR_RAM_ECC_DBE_ERR = 19054, 1100 NVSWITCH_ERR_HW_NVLTLC_RX_SYS_HDR_RAM_ECC_LIMIT_ERR = 19055, 1101 NVSWITCH_ERR_HW_NVLTLC_RX_SYS_DAT0_RAM_ECC_DBE_ERR = 19056, 1102 NVSWITCH_ERR_HW_NVLTLC_RX_SYS_DAT0_RAM_ECC_LIMIT_ERR = 19057, 1103 NVSWITCH_ERR_HW_NVLTLC_RX_SYS_DAT1_RAM_ECC_DBE_ERR = 19058, 1104 NVSWITCH_ERR_HW_NVLTLC_RX_SYS_DAT1_RAM_ECC_LIMIT_ERR = 19059, 1105 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_CREQ_RAM_HDR_ECC_DBE_ERR = 19060, 1106 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_CREQ_RAM_DAT_ECC_DBE_ERR = 19061, 1107 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_CREQ_RAM_ECC_LIMIT_ERR = 19062, 1108 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_RSP_RAM_HDR_ECC_DBE_ERR = 19063, 1109 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_RSP_RAM_DAT_ECC_DBE_ERR = 19064, 1110 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_RSP_RAM_ECC_LIMIT_ERR = 19065, 1111 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_COM_RAM_HDR_ECC_DBE_ERR = 19066, 1112 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_COM_RAM_DAT_ECC_DBE_ERR = 19067, 1113 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_COM_RAM_ECC_LIMIT_ERR = 19068, 1114 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_RSP1_RAM_HDR_ECC_DBE_ERR = 19069, 1115 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_RSP1_RAM_DAT_ECC_DBE_ERR = 19070, 1116 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_RSP1_RAM_ECC_LIMIT_ERR = 19071, 1117 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC0 = 19072, 1118 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC1 = 19073, 1119 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC2 = 19074, 1120 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC3 = 19075, 1121 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC4 = 19076, 1122 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC5 = 19077, 1123 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC6 = 19078, 1124 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC7 = 19079, 1125 NVSWITCH_ERR_HW_NVLTLC_RX_LNK_RXRSPSTATUS_HW_ERR = 19080, 1126 NVSWITCH_ERR_HW_NVLTLC_RX_LNK_RXRSPSTATUS_UR_ERR = 19081, 1127 NVSWITCH_ERR_HW_NVLTLC_RX_LNK_RXRSPSTATUS_PRIV_ERR = 19082, 1128 NVSWITCH_ERR_HW_NVLTLC_RX_LNK_INVALID_COLLAPSED_RESPONSE_ERR = 19083, 1129 NVSWITCH_ERR_HW_NVLTLC_RX_LNK_AN1_HEARTBEAT_TIMEOUT_ERR = 19084, 1130 NVSWITCH_ERR_HW_NVLTLC_LAST, /* NOTE: Must be last */ 1131 1132 /* DLPL: errors ( SL1 errors too) */ 1133 NVSWITCH_ERR_HW_DLPL = 20000, 1134 NVSWITCH_ERR_HW_DLPL_TX_REPLAY = 20001, 1135 NVSWITCH_ERR_HW_DLPL_TX_RECOVERY_SHORT = 20002, 1136 NVSWITCH_ERR_HW_DLPL_TX_RECOVERY_LONG = 20003, 1137 NVSWITCH_ERR_HW_DLPL_TX_FAULT_RAM = 20004, 1138 NVSWITCH_ERR_HW_DLPL_TX_FAULT_INTERFACE = 20005, 1139 NVSWITCH_ERR_HW_DLPL_TX_FAULT_SUBLINK_CHANGE = 20006, 1140 NVSWITCH_ERR_HW_DLPL_RX_FAULT_SUBLINK_CHANGE = 20007, 1141 NVSWITCH_ERR_HW_DLPL_RX_FAULT_DL_PROTOCOL = 20008, 1142 NVSWITCH_ERR_HW_DLPL_RX_SHORT_ERROR_RATE = 20009, 1143 NVSWITCH_ERR_HW_DLPL_RX_LONG_ERROR_RATE = 20010, 1144 NVSWITCH_ERR_HW_DLPL_RX_ILA_TRIGGER = 20011, 1145 NVSWITCH_ERR_HW_DLPL_RX_CRC_COUNTER = 20012, 1146 NVSWITCH_ERR_HW_DLPL_LTSSM_FAULT = 20013, 1147 NVSWITCH_ERR_HW_DLPL_LTSSM_PROTOCOL = 20014, 1148 NVSWITCH_ERR_HW_DLPL_MINION_REQUEST = 20015, 1149 NVSWITCH_ERR_HW_DLPL_FIFO_DRAIN_ERR = 20016, 1150 NVSWITCH_ERR_HW_DLPL_CONST_DET_ERR = 20017, 1151 NVSWITCH_ERR_HW_DLPL_OFF2SAFE_LINK_DET_ERR = 20018, 1152 NVSWITCH_ERR_HW_DLPL_SAFE2NO_LINK_DET_ERR = 20019, 1153 NVSWITCH_ERR_HW_DLPL_SCRAM_LOCK_ERR = 20020, 1154 NVSWITCH_ERR_HW_DLPL_SYM_LOCK_ERR = 20021, 1155 NVSWITCH_ERR_HW_DLPL_SYM_ALIGN_END_ERR = 20022, 1156 NVSWITCH_ERR_HW_DLPL_FIFO_SKEW_ERR = 20023, 1157 NVSWITCH_ERR_HW_DLPL_TRAIN2SAFE_LINK_DET_ERR = 20024, 1158 NVSWITCH_ERR_HW_DLPL_HS2SAFE_LINK_DET_ERR = 20025, 1159 NVSWITCH_ERR_HW_DLPL_FENCE_ERR = 20026, 1160 NVSWITCH_ERR_HW_DLPL_SAFE_NO_LD_ERR = 20027, 1161 NVSWITCH_ERR_HW_DLPL_E2SAFE_LD_ERR = 20028, 1162 NVSWITCH_ERR_HW_DLPL_RC_RXPWR_ERR = 20029, 1163 NVSWITCH_ERR_HW_DLPL_RC_TXPWR_ERR = 20030, 1164 NVSWITCH_ERR_HW_DLPL_RC_DEADLINE_ERR = 20031, 1165 NVSWITCH_ERR_HW_DLPL_TX_HS2LP_ERR = 20032, 1166 NVSWITCH_ERR_HW_DLPL_RX_HS2LP_ERR = 20033, 1167 NVSWITCH_ERR_HW_DLPL_LTSSM_FAULT_UP = 20034, 1168 NVSWITCH_ERR_HW_DLPL_LTSSM_FAULT_DOWN = 20035, 1169 NVSWITCH_ERR_HW_DLPL_PHY_A = 20036, 1170 NVSWITCH_ERR_HW_DLPL_TX_PL_ERROR = 20037, 1171 NVSWITCH_ERR_HW_DLPL_RX_PL_ERROR = 20038, 1172 NVSWITCH_ERR_HW_DLPL_LAST, /* NOTE: Must be last */ 1173 1174 /* AFS: errors */ 1175 NVSWITCH_ERR_HW_AFS = 21000, 1176 NVSWITCH_ERR_HW_AFS_UC_INGRESS_CREDIT_OVERFLOW = 21001, 1177 NVSWITCH_ERR_HW_AFS_UC_INGRESS_CREDIT_UNDERFLOW = 21002, 1178 NVSWITCH_ERR_HW_AFS_UC_EGRESS_CREDIT_OVERFLOW = 21003, 1179 NVSWITCH_ERR_HW_AFS_UC_EGRESS_CREDIT_UNDERFLOW = 21004, 1180 NVSWITCH_ERR_HW_AFS_UC_INGRESS_NON_BURSTY_PKT_DETECTED = 21005, 1181 NVSWITCH_ERR_HW_AFS_UC_INGRESS_NON_STICKY_PKT_DETECTED = 21006, 1182 NVSWITCH_ERR_HW_AFS_UC_INGRESS_BURST_GT_17_DATA_VC_DETECTED = 21007, 1183 NVSWITCH_ERR_HW_AFS_UC_INGRESS_BURST_GT_1_NONDATA_VC_DETECTED = 21008, 1184 NVSWITCH_ERR_HW_AFS_UC_INVALID_DST = 21009, 1185 NVSWITCH_ERR_HW_AFS_UC_PKT_MISROUTE = 21010, 1186 NVSWITCH_ERR_HW_AFS_LAST, /* NOTE: Must be last */ 1187 1188 /* MINION: errors */ 1189 NVSWITCH_ERR_HW_MINION = 22000, 1190 NVSWITCH_ERR_HW_MINION_UCODE_IMEM = 22001, 1191 NVSWITCH_ERR_HW_MINION_UCODE_DMEM = 22002, 1192 NVSWITCH_ERR_HW_MINION_HALT = 22003, 1193 NVSWITCH_ERR_HW_MINION_BOOT_ERROR = 22004, 1194 NVSWITCH_ERR_HW_MINION_TIMEOUT = 22005, 1195 NVSWITCH_ERR_HW_MINION_DLCMD_FAULT = 22006, 1196 NVSWITCH_ERR_HW_MINION_DLCMD_TIMEOUT = 22007, 1197 NVSWITCH_ERR_HW_MINION_DLCMD_FAIL = 22008, 1198 NVSWITCH_ERR_HW_MINION_FATAL_INTR = 22009, 1199 NVSWITCH_ERR_HW_MINION_WATCHDOG = 22010, 1200 NVSWITCH_ERR_HW_MINION_EXTERR = 22011, 1201 NVSWITCH_ERR_HW_MINION_FATAL_LINK_INTR = 22012, 1202 NVSWITCH_ERR_HW_MINION_NONFATAL = 22013, 1203 NVSWITCH_ERR_HW_MINION_LAST, /* NOTE: Must be last */ 1204 1205 /* NXBAR errors */ 1206 NVSWITCH_ERR_HW_NXBAR = 23000, 1207 NVSWITCH_ERR_HW_NXBAR_TILE_INGRESS_BUFFER_OVERFLOW = 23001, 1208 NVSWITCH_ERR_HW_NXBAR_TILE_INGRESS_BUFFER_UNDERFLOW = 23002, 1209 NVSWITCH_ERR_HW_NXBAR_TILE_EGRESS_CREDIT_OVERFLOW = 23003, 1210 NVSWITCH_ERR_HW_NXBAR_TILE_EGRESS_CREDIT_UNDERFLOW = 23004, 1211 NVSWITCH_ERR_HW_NXBAR_TILE_INGRESS_NON_BURSTY_PKT = 23005, 1212 NVSWITCH_ERR_HW_NXBAR_TILE_INGRESS_NON_STICKY_PKT = 23006, 1213 NVSWITCH_ERR_HW_NXBAR_TILE_INGRESS_BURST_GT_9_DATA_VC = 23007, 1214 NVSWITCH_ERR_HW_NXBAR_TILE_INGRESS_PKT_INVALID_DST = 23008, 1215 NVSWITCH_ERR_HW_NXBAR_TILE_INGRESS_PKT_PARITY_ERROR = 23009, 1216 NVSWITCH_ERR_HW_NXBAR_TILEOUT_INGRESS_BUFFER_OVERFLOW = 23010, 1217 NVSWITCH_ERR_HW_NXBAR_TILEOUT_INGRESS_BUFFER_UNDERFLOW = 23011, 1218 NVSWITCH_ERR_HW_NXBAR_TILEOUT_EGRESS_CREDIT_OVERFLOW = 23012, 1219 NVSWITCH_ERR_HW_NXBAR_TILEOUT_EGRESS_CREDIT_UNDERFLOW = 23013, 1220 NVSWITCH_ERR_HW_NXBAR_TILEOUT_INGRESS_NON_BURSTY_PKT = 23014, 1221 NVSWITCH_ERR_HW_NXBAR_TILEOUT_INGRESS_NON_STICKY_PKT = 23015, 1222 NVSWITCH_ERR_HW_NXBAR_TILEOUT_INGRESS_BURST_GT_9_DATA_VC = 23016, 1223 NVSWITCH_ERR_HW_NXBAR_TILEOUT_EGRESS_CDT_PARITY_ERROR = 23017, 1224 NVSWITCH_ERR_HW_NXBAR_LAST, /* NOTE: Must be last */ 1225 1226 /* NPORT: SOURCETRACK errors */ 1227 NVSWITCH_ERR_HW_NPORT_SOURCETRACK = 24000, 1228 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR = 24001, 1229 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR = 24002, 1230 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR = 24003, 1231 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR = 24004, 1232 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR = 24005, 1233 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR = 24006, 1234 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_SOURCETRACK_TIME_OUT_ERR = 24007, 1235 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_DUP_CREQ_TCEN0_TAG_ERR = 24008, 1236 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_INVALID_TCEN0_RSP_ERR = 24009, 1237 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_INVALID_TCEN1_RSP_ERR = 24010, 1238 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_LAST, /* NOTE: Must be last */ 1239 1240 /* NVLIPT_LNK errors */ 1241 NVSWITCH_ERR_HW_NVLIPT_LNK = 25000, 1242 NVSWITCH_ERR_HW_NVLIPT_LNK_ILLEGALLINKSTATEREQUEST = 25001, 1243 NVSWITCH_ERR_HW_NVLIPT_LNK_FAILEDMINIONREQUEST = 25002, 1244 NVSWITCH_ERR_HW_NVLIPT_LNK_RESERVEDREQUESTVALUE = 25003, 1245 NVSWITCH_ERR_HW_NVLIPT_LNK_LINKSTATEWRITEWHILEBUSY = 25004, 1246 NVSWITCH_ERR_HW_NVLIPT_LNK_LINK_STATE_REQUEST_TIMEOUT = 25005, 1247 NVSWITCH_ERR_HW_NVLIPT_LNK_WRITE_TO_LOCKED_SYSTEM_REG_ERR = 25006, 1248 NVSWITCH_ERR_HW_NVLIPT_LNK_SLEEPWHILEACTIVELINK = 25007, 1249 NVSWITCH_ERR_HW_NVLIPT_LNK_RSTSEQ_PHYCTL_TIMEOUT = 25008, 1250 NVSWITCH_ERR_HW_NVLIPT_LNK_RSTSEQ_CLKCTL_TIMEOUT = 25009, 1251 NVSWITCH_ERR_HW_NVLIPT_LNK_ALI_TRAINING_FAIL = 25010, 1252 NVSWITCH_ERR_HW_NVLIPT_LNK_LAST, /* Note: Must be last */ 1253 1254 /* SOE errors */ 1255 NVSWITCH_ERR_HW_SOE = 26000, 1256 NVSWITCH_ERR_HW_SOE_RESET = 26001, 1257 NVSWITCH_ERR_HW_SOE_BOOTSTRAP = 26002, 1258 NVSWITCH_ERR_HW_SOE_COMMAND_QUEUE = 26003, 1259 NVSWITCH_ERR_HW_SOE_TIMEOUT = 26004, 1260 NVSWITCH_ERR_HW_SOE_SHUTDOWN = 26005, 1261 NVSWITCH_ERR_HW_SOE_HALT = 26006, 1262 NVSWITCH_ERR_HW_SOE_EXTERR = 26007, 1263 NVSWITCH_ERR_HW_SOE_WATCHDOG = 26008, 1264 NVSWITCH_ERR_HW_SOE_LAST, /* Note: Must be last */ 1265 1266 /* CCI errors */ 1267 NVSWITCH_ERR_HW_CCI = 27000, 1268 NVSWITCH_ERR_HW_CCI_RESET = 27001, 1269 NVSWITCH_ERR_HW_CCI_INIT = 27002, 1270 NVSWITCH_ERR_HW_CCI_TIMEOUT = 27003, 1271 NVSWITCH_ERR_HW_CCI_SHUTDOWN = 27004, 1272 NVSWITCH_ERR_HW_CCI_MODULE = 27005, 1273 NVSWITCH_ERR_HW_CCI_MODULE_BOOT = 27006, 1274 NVSWITCH_ERR_HW_CCI_MODULE_RECOVERY = 27007, 1275 NVSWITCH_ERR_HW_CCI_LAST, /* Note: Must be last */ 1276 1277 /* OSFP Therm Errors */ 1278 NVSWITCH_ERR_HW_OSFP_THERM = 28000, 1279 NVSWITCH_ERR_HW_OSFP_THERM_WARN_ACTIVATED = 28001, 1280 NVSWITCH_ERR_HW_OSFP_THERM_WARN_DEACTIVATED = 28002, 1281 NVSWITCH_ERR_HW_OSFP_THERM_OVERT_ACTIVATED = 28003, 1282 NVSWITCH_ERR_HW_OSFP_THERM_OVERT_DEACTIVATED = 28004, 1283 NVSWITCH_ERR_HW_OSFP_THERM_HEARTBEAT_SHUTDOWN = 28005, 1284 NVSWITCH_ERR_HW_OSFP_THERM_LAST, /* Note: Must be last */ 1285 1286 /* NPORT: Multicast Tstate errors */ 1287 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE = 29000, 1288 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_LIMIT_ERR = 29001, 1289 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_DBE_ERR = 29002, 1290 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_LIMIT_ERR = 29003, 1291 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_DBE_ERR = 29004, 1292 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_BUF_OVERWRITE_ERR = 29005, 1293 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_MCTO_ERR = 29006, 1294 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_LAST, /* Note: Must be last */ 1295 1296 /* NPORT: Reduction Tstate errors */ 1297 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE = 30000, 1298 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_LIMIT_ERR = 30001, 1299 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_DBE_ERR = 30002, 1300 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_LIMIT_ERR = 30003, 1301 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_DBE_ERR = 30004, 1302 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_BUF_OVERWRITE_ERR = 30005, 1303 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_RTO_ERR = 30006, 1304 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_LAST, /* Note: Must be last */ 1305 1306 /* Please update nvswitch_translate_hw_errors with a newly added error class. */ 1307 NVSWITCH_ERR_LAST 1308 /* See enum modification guidelines at the top of this file */ 1309 } NVSWITCH_ERR_TYPE; 1310 1311 typedef enum nvswitch_pri_error_instance 1312 { 1313 NVSWITCH_PBUS_PRI_SQUASH = 0, 1314 NVSWITCH_PBUS_PRI_FECSERR, 1315 NVSWITCH_PBUS_PRI_TIMEOUT, 1316 NVSWITCH_PPRIV_WRITE_SYS, 1317 NVSWITCH_PPRIV_WRITE_PRT 1318 } NVSWITCH_PRI_ERROR_INSTANCE; 1319 1320 #define NVSWITCH_ERROR_MAX_DESCRPTION_LEN 70 1321 #define NVSWITCH_RAW_ERROR_DATA_SIZE 16 1322 1323 typedef struct nvswitch_error 1324 { 1325 NvU32 error_value; /* NVSWITCH_ERR_* */ 1326 NvU32 error_src; /* NVSWITCH_ERROR_SRC_* */ 1327 NvU32 instance; /* Used for link# or subengine instance */ 1328 NvU32 subinstance; /* Used for lane# or similar */ 1329 NV_DECLARE_ALIGNED(NvU64 time, 8); /* Platform time (nsec) */ 1330 NvBool error_resolved; /* If an error is correctable, set to true. */ 1331 NvU32 error_data[NVSWITCH_RAW_ERROR_DATA_SIZE]; /* Data from NVSWITCH_REPORT_DATA */ 1332 NvU32 error_data_size; /* Size of error_data */ 1333 NvU8 error_description[NVSWITCH_ERROR_MAX_DESCRPTION_LEN]; /* Short description of error */ 1334 } NVSWITCH_ERROR; 1335 1336 #define NVSWITCH_ERROR_COUNT_SIZE 64 1337 1338 typedef struct nvswitch_get_errors 1339 { 1340 NvU32 errorType; 1341 NvU64 errorIndex; 1342 NvU64 nextErrorIndex; 1343 NvU32 errorCount; 1344 NVSWITCH_ERROR error[NVSWITCH_ERROR_COUNT_SIZE]; 1345 } NVSWITCH_GET_ERRORS_PARAMS; 1346 1347 /* 1348 * CTRL_NVSWITCH_GET_PORT_EVENTS 1349 * 1350 * Control for querying port up and port down event information 1351 * 1352 * Parameters: 1353 * 1354 * portEventIndex [IN/OUT] 1355 * On input: The index of the first port event at which to start reading out of the driver. 1356 * 1357 * On output: The index of the first port event that wasn't reported through the 'port event' array 1358 * in this call to CTRL_NVSWITCH_GET_PORT_EVENTS. 1359 * 1360 * nextPortEventIndex[OUT] 1361 * The index that will be assigned to the next port event to occur. 1362 * Users of the GET_PORT_EVENTS control call may set 'portEventIndex' to this field on initialization 1363 * to bypass port events that have already occurred without making multiple control calls. 1364 * 1365 * portEventCount [OUT] 1366 * Number of port events returned by the call. Currently, portEventCount is limited 1367 * by NVSWITCH_PORT_EVENT_COUNT_SIZE. In order to query all the port events, a 1368 * client needs to keep calling the control till portEventCount is zero. 1369 * 1370 * bOverflow [OUT] 1371 * True when the port event log is overflowed and no longer contains all the port 1372 * events that have occurred, false otherwise. 1373 * 1374 * portEvent [OUT] 1375 * The port event entires. 1376 */ 1377 #define NVSWITCH_PORT_EVENT_COUNT_SIZE 64 1378 #define NVSWITCH_PORT_EVENT_TYPE_UP 0 1379 #define NVSWITCH_PORT_EVENT_TYPE_DOWN 1 1380 #define NVSWITCH_PORT_EVENT_TYPE_INVALID 2 1381 1382 typedef struct 1383 { 1384 NvU8 port_event_type; /* NVSWITCH_PORT_EVENT_TYPE* */ 1385 NvU32 link_id; /* Link # that event occurred on */ 1386 NV_DECLARE_ALIGNED(NvU64 time, 8); /* Platform time (nsec) when event occurred */ 1387 } NVSWITCH_PORT_EVENT; 1388 1389 typedef struct nvswitch_get_port_events 1390 { 1391 NvU64 portEventIndex; 1392 NvU64 nextPortEventIndex; 1393 NvU32 portEventCount; 1394 NvBool bOverflow; 1395 NVSWITCH_PORT_EVENT portEvent[NVSWITCH_PORT_EVENT_COUNT_SIZE]; 1396 } NVSWITCH_GET_PORT_EVENTS_PARAMS; 1397 1398 /* 1399 * CTRL_NVSWITCH_GET_INTERNAL_LATENCY 1400 * 1401 * Control for querying latency bins. 1402 * 1403 * Parameters: 1404 * vc_selector [IN] 1405 * A valid VC number returned by NVSWITCH_GET_INFO. 1406 * 1407 * elapsed_time_msec [OUT] 1408 * Elapsed time since the latency bins were queried. 1409 * egressHistogram [OUT] 1410 * Latency bin data/histogram format. The data will be available for the 1411 * enabled/supported ports returned by NVSWITCH_GET_INFO. 1412 */ 1413 1414 #define NVSWITCH_MAX_PORTS 64 1415 1416 /* TODO: describe the format */ 1417 typedef struct nvswitch_internal_latency_bins 1418 { 1419 NV_DECLARE_ALIGNED(NvU64 low, 8); 1420 NV_DECLARE_ALIGNED(NvU64 medium, 8); 1421 NV_DECLARE_ALIGNED(NvU64 high, 8); 1422 NV_DECLARE_ALIGNED(NvU64 panic, 8); 1423 NV_DECLARE_ALIGNED(NvU64 count, 8); 1424 } NVSWITCH_INTERNAL_LATENCY_BINS; 1425 1426 typedef struct nvswitch_get_internal_latency 1427 { 1428 NvU32 vc_selector; 1429 NV_DECLARE_ALIGNED(NvU64 elapsed_time_msec, 8); 1430 NVSWITCH_INTERNAL_LATENCY_BINS egressHistogram[NVSWITCH_MAX_PORTS]; 1431 } NVSWITCH_GET_INTERNAL_LATENCY; 1432 1433 /* 1434 * CTRL_NVSWITCH_SET_LATENCY_BINS 1435 * 1436 * Control for setting latency bins. 1437 * 1438 * Parameters: 1439 * NVSWITCH_LATENCY_BIN [IN] 1440 * Latency bin thresholds. The thresholds would be only applied to the 1441 * enabled ports and the supported VCs by those ports. 1442 * NVSWITCH_GET_INFO can be used to query enabled ports and supported VCs. 1443 */ 1444 1445 #define NVSWITCH_MAX_VCS 8 1446 1447 /* TODO: describe the format */ 1448 typedef struct nvswitch_latency_bin 1449 { 1450 NvU32 lowThreshold; /* in nsec */ 1451 NvU32 medThreshold; /* in nsec */ 1452 NvU32 hiThreshold; /* in nsec */ 1453 1454 } NVSWITCH_LATENCY_BIN; 1455 1456 typedef struct nvswitch_set_latency_bins 1457 { 1458 NVSWITCH_LATENCY_BIN bin[NVSWITCH_MAX_VCS]; 1459 1460 } NVSWITCH_SET_LATENCY_BINS; 1461 1462 /* 1463 * CTRL_NVSWITCH_SET_SWITCH_PORT_CONFIG 1464 * 1465 * Control for setting device port configurations. 1466 * 1467 * Parameters: 1468 * portNum [IN] 1469 * A valid port number present in the port masks returned by 1470 * NVSWITCH_GET_INFO. 1471 * type [IN] 1472 * A connection type. See NVSWITCH_CONNECTION_TYPE. 1473 * requesterLinkID [IN] 1474 * An unique port ID in the fabric. 1475 * requesterLan [IN] 1476 * A Lan Id. 1477 * count [IN] 1478 * Endpoint Count 1479 * acCoupled [IN] 1480 * Set true, if the port is AC coupled. 1481 * enableVC1 [IN] 1482 * Set true, if VC1 should be enabled for the port. 1483 * trunkSrcMask [IN] 1484 * Mask of source trunk ports. 1485 */ 1486 1487 typedef enum nvswitch_connection_type 1488 { 1489 CONNECT_ACCESS_GPU = 0, 1490 CONNECT_ACCESS_CPU, 1491 CONNECT_TRUNK_SWITCH, 1492 CONNECT_ACCESS_SWITCH 1493 /* See enum modification guidelines at the top of this file */ 1494 } NVSWITCH_CONNECTION_TYPE; 1495 1496 typedef enum nvswitch_connection_count 1497 { 1498 CONNECT_COUNT_512 = 0, 1499 CONNECT_COUNT_1024, 1500 CONNECT_COUNT_2048 1501 /* See enum modification guidelines at the top of this file */ 1502 } NVSWITCH_CONNECTION_COUNT; 1503 1504 typedef struct nvswitch_set_switch_port_config 1505 { 1506 NvU32 portNum; 1507 NvU32 type; 1508 NvU32 requesterLinkID; 1509 NvU32 requesterLanID; 1510 NvU32 count; 1511 NvBool acCoupled; 1512 NvBool enableVC1; 1513 NvU64 trunkSrcMask; 1514 1515 } NVSWITCH_SET_SWITCH_PORT_CONFIG; 1516 1517 /* 1518 * CTRL_NVSWITCH_SET_GANGED_LINK_TABLE 1519 * 1520 * Control for setting ganged link tables. 1521 * This interface is only supported on architectures that report 1522 * _GET_INFO_INDEX_ARCH == SV10. All others will return an error. 1523 * 1524 * Parameters: 1525 * linkMask [IN] 1526 * A valid link/port mask returned by the port masks returned by 1527 * NVSWITCH_GET_INFO. 1528 * entries [IN] 1529 * The Ganged link entires. (TODO: Describe format) 1530 */ 1531 1532 #define NVSWITCH_GANGED_LINK_TABLE_ENTRIES_MAX 256 1533 1534 typedef struct nvswitch_set_ganged_link_table 1535 { 1536 NvU32 link_mask; 1537 NvU32 entries[NVSWITCH_GANGED_LINK_TABLE_ENTRIES_MAX]; 1538 1539 } NVSWITCH_SET_GANGED_LINK_TABLE; 1540 1541 /* 1542 * CTRL_NVSWITCH_GET_NVLIPT_COUNTER 1543 * 1544 * Control for querying NVLIPT counters. 1545 * 1546 * Parameters: 1547 * liptCounter [OUT] 1548 * Port's TX/RX traffic data. The data will be available for the 1549 * enabled/supported ports returned by NVSWITCH_GET_INFO. 1550 */ 1551 1552 typedef struct nvswitch_nvlipt_counter 1553 { 1554 NV_DECLARE_ALIGNED(NvU64 txCounter0, 8); 1555 NV_DECLARE_ALIGNED(NvU64 txCounter1, 8); 1556 NV_DECLARE_ALIGNED(NvU64 rxCounter0, 8); 1557 NV_DECLARE_ALIGNED(NvU64 rxCounter1, 8); 1558 1559 } NVSWITCH_NVLIPT_COUNTER; 1560 1561 typedef struct nvswitch_get_nvlipt_counters 1562 { 1563 NVSWITCH_NVLIPT_COUNTER liptCounter[NVSWITCH_MAX_PORTS]; 1564 1565 } NVSWITCH_GET_NVLIPT_COUNTERS; 1566 1567 /* 1568 * CTRL_NVSWITCH_SET_NVLIPT_COUNTER_CONFIG 1569 * 1570 * Control to set NVLIPT counter configuration. 1571 * 1572 * Parameters: 1573 * linkMask [IN] 1574 * A valid link/port mask returned by the port masks returned by 1575 * NVSWITCH_GET_INFO. 1576 * tx0/tx1/rx0/rx1 [IN] 1577 * TX/RX link configurations. 1578 */ 1579 1580 /* TODO: describe format */ 1581 typedef struct nvlipt_counter_config 1582 { 1583 NvU32 ctrl_0; 1584 NvU32 ctrl_1; 1585 NvU32 req_filter; 1586 NvU32 rsp_filter; 1587 NvU32 misc_filter; 1588 NV_DECLARE_ALIGNED(NvU64 addr_filter, 8); 1589 NV_DECLARE_ALIGNED(NvU64 addr_mask, 8); 1590 1591 } NVLIPT_COUNTER_CONFIG; 1592 1593 typedef struct nvswitch_set_nvlipt_counter_config 1594 { 1595 NV_DECLARE_ALIGNED(NvU64 link_mask, 8); 1596 NVLIPT_COUNTER_CONFIG tx0; 1597 NVLIPT_COUNTER_CONFIG tx1; 1598 NVLIPT_COUNTER_CONFIG rx0; 1599 NVLIPT_COUNTER_CONFIG rx1; 1600 1601 } NVSWITCH_SET_NVLIPT_COUNTER_CONFIG; 1602 1603 /* 1604 * CTRL_NVSWITCH_GET_NVLIPT_COUNTER_CONFIG 1605 * 1606 * Control to query NVLIPT counter configuration. 1607 * 1608 * Parameters: 1609 * link [IN] 1610 * A valid link/port returned by the port masks returned by 1611 * NVSWITCH_GET_INFO. 1612 * 1613 * tx0/tx1/rx0/rx1 [OUT] 1614 * TX/RX link configurations for the provide port. 1615 */ 1616 1617 typedef struct nvswitch_get_nvlipt_counter_config 1618 { 1619 NvU32 link; 1620 NVLIPT_COUNTER_CONFIG tx0; 1621 NVLIPT_COUNTER_CONFIG tx1; 1622 NVLIPT_COUNTER_CONFIG rx0; 1623 NVLIPT_COUNTER_CONFIG rx1; 1624 1625 } NVSWITCH_GET_NVLIPT_COUNTER_CONFIG; 1626 1627 /* 1628 * CTRL_NVSWITCH_GET_INGRESS_REQLINKID 1629 * 1630 * Control to query the ingress requestor link id. 1631 * 1632 * Parameters: 1633 * portNum [IN] 1634 * A valid port number present in the port masks returned by 1635 * NVSWITCH_GET_INFO 1636 * 1637 * requesterLinkID [OUT] 1638 * Ingress requestor link id for the provided port. 1639 */ 1640 1641 typedef struct nvswitch_get_ingress_reqlinkid_params 1642 { 1643 NvU32 portNum; 1644 NvU32 requesterLinkID; 1645 1646 } NVSWITCH_GET_INGRESS_REQLINKID_PARAMS; 1647 1648 /* 1649 * CTRL_NVSWITCH_UNREGISTER_LINK 1650 * 1651 * Control to unregister the request link (port). This ensures that the black- 1652 * listed link will not be initialized or trained by the driver. 1653 * 1654 * Parameters: 1655 * portNum [IN] 1656 * A valid port number present in the port masks returned by 1657 * NVSWITCH_GET_INFO 1658 */ 1659 1660 typedef struct nvswitch_unregister_link_params 1661 { 1662 NvU32 portNum; 1663 1664 } NVSWITCH_UNREGISTER_LINK_PARAMS; 1665 1666 /* 1667 * CTRL_RESET_AND_DRAIN_LINKS 1668 * 1669 * Control to reset and drain the links. Resets NVLinks and ensures to drain 1670 * backed up traffic. 1671 * 1672 * Parameters: 1673 * linkMask [IN] 1674 * A mask of link(s) to be reset. 1675 * For SV10, the linkMask must contain at least a link-pair (even-odd links). 1676 * 1677 * Returns: 1678 * NVL_SUCCESS if there were no errors 1679 * -NVL_BAD_PARAMS if input parameters are wrong. 1680 * -NVL_ERR_INVALID_STATE if other errors are present and a full-chip reset is required. 1681 * -NVL_INITIALIZATION_TOTAL_FAILURE if NPORT initialization failed and a retry is required. 1682 */ 1683 1684 typedef struct nvswitch_reset_and_drain_links_params 1685 { 1686 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 1687 1688 } NVSWITCH_RESET_AND_DRAIN_LINKS_PARAMS; 1689 1690 /* 1691 * CTRL_NVSWITCH_GET_NVLINK_STATUS 1692 * 1693 * enabledLinkMask 1694 * This field specifies the mask of available links on this subdevice. 1695 * linkInfo 1696 * This structure stores the per-link status of different NVLink 1697 * parameters. The link is identified using an index. 1698 * 1699 * Possible status values returned are: 1700 * NV_OK 1701 * NV_ERR_INVALID_PARAM_STRUCT 1702 * NV_ERR_INVALID_ARGUMENT 1703 */ 1704 1705 /* 1706 * NVSWITCH_NVLINK_DEVICE_INFO 1707 * 1708 * This structure stores information about the device to which this link is 1709 * associated 1710 * 1711 * deviceIdFlags 1712 * Bitmask that specifies which IDs are valid for the device 1713 * Refer NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_* for possible values 1714 * If NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI is set, PCI 1715 * information is valid 1716 * If NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID is set, UUID is 1717 * valid 1718 * domain, bus, device, function, pciDeviceId 1719 * PCI information for the device 1720 * deviceType 1721 * Type of the device 1722 * See NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_* for possible values 1723 * deviceUUID 1724 * This field specifies the device UUID of the device. Useful for 1725 * identifying the device (or version) 1726 */ 1727 1728 typedef struct 1729 { 1730 // ID Flags 1731 NvU32 deviceIdFlags; 1732 1733 // PCI Information 1734 NvU32 domain; 1735 NvU16 bus; 1736 NvU16 device; 1737 NvU16 function; 1738 NvU32 pciDeviceId; 1739 1740 // Device Type 1741 NV_DECLARE_ALIGNED(NvU64 deviceType, 8); 1742 1743 // Device UUID 1744 NvU8 deviceUUID[16]; 1745 } NVSWITCH_NVLINK_DEVICE_INFO; 1746 1747 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS 31:0 1748 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE (0x00000000) 1749 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI (0x00000001) 1750 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID (0x00000002) 1751 1752 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE (0x00000000) 1753 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU (0x00000001) 1754 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU (0x00000002) 1755 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH (0x00000003) 1756 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA (0x00000004) 1757 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE (0x000000FF) 1758 1759 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID (0xFFFFFFFF) 1760 1761 /* 1762 * NVSWITCH_NVLINK_CAPS_* 1763 * 1764 * SUPPORTED 1765 * Set if NVLink is present and supported on this subdevice, NV_FALSE 1766 * otherwise. This field is used for *global* caps only and NOT for 1767 * per-link caps 1768 * P2P_SUPPORTED 1769 * Set if P2P over NVLink is supported on this subdevice, NV_FALSE 1770 * otherwise. 1771 * SYSMEM_ACCESS 1772 * Set if sysmem can be accessed over NVLink on this subdevice, NV_FALSE 1773 * otherwise. 1774 * PEER_ATOMICS 1775 * Set if P2P atomics are supported over NVLink on this subdevice, NV_FALSE 1776 * otherwise. 1777 * SYSMEM_ATOMICS 1778 * Set if sysmem atomic transcations are supported over NVLink on this 1779 * subdevice, NV_FALSE otherwise. 1780 * PEX_TUNNELING 1781 * Set if PEX tunneling over NVLink is supported on this subdevice, 1782 * NV_FALSE otherwise. 1783 * SLI_BRIDGE 1784 * GLOBAL: Set if SLI over NVLink is supported on this subdevice, NV_FALSE 1785 * otherwise. 1786 * LINK: Set if SLI over NVLink is supported on a link, NV_FALSE 1787 * otherwise. 1788 * SLI_BRIDGE_SENSABLE 1789 * GLOBAL: Set if the subdevice is capable of sensing SLI bridges, NV_FALSE 1790 * otherwise. 1791 * LINK: Set if the link is capable of sensing an SLI bridge, NV_FALSE 1792 * otherwise. 1793 * POWER_STATE_L0 1794 * Set if L0 is a supported power state on this subdevice/link, NV_FALSE 1795 * otherwise. 1796 * POWER_STATE_L1 1797 * Set if L1 is a supported power state on this subdevice/link, NV_FALSE 1798 * otherwise. 1799 * POWER_STATE_L2 1800 * Set if L2 is a supported power state on this subdevice/link, NV_FALSE 1801 * otherwise. 1802 * POWER_STATE_L3 1803 * Set if L3 is a supported power state on this subdevice/link, NV_FALSE 1804 * otherwise. 1805 * VALID 1806 * Set if this link is supported on this subdevice, NV_FALSE otherwise. 1807 * This field is used for *per-link* caps only and NOT for global caps. 1808 * 1809 */ 1810 1811 /* caps format is byte_index:bit_mask */ 1812 #define NVSWITCH_NVLINK_CAPS_SUPPORTED 0:0x01 1813 #define NVSWITCH_NVLINK_CAPS_P2P_SUPPORTED 0:0x02 1814 #define NVSWITCH_NVLINK_CAPS_SYSMEM_ACCESS 0:0x04 1815 #define NVSWITCH_NVLINK_CAPS_P2P_ATOMICS 0:0x08 1816 #define NVSWITCH_NVLINK_CAPS_SYSMEM_ATOMICS 0:0x10 1817 #define NVSWITCH_NVLINK_CAPS_PEX_TUNNELING 0:0x20 1818 #define NVSWITCH_NVLINK_CAPS_SLI_BRIDGE 0:0x40 1819 #define NVSWITCH_NVLINK_CAPS_SLI_BRIDGE_SENSABLE 0:0x80 1820 #define NVSWITCH_NVLINK_CAPS_POWER_STATE_L0 1:0x01 1821 #define NVSWITCH_NVLINK_CAPS_POWER_STATE_L1 1:0x02 1822 #define NVSWITCH_NVLINK_CAPS_POWER_STATE_L2 1:0x04 1823 #define NVSWITCH_NVLINK_CAPS_POWER_STATE_L3 1:0x08 1824 #define NVSWITCH_NVLINK_CAPS_VALID 1:0x10 1825 1826 /* 1827 * Size in bytes of nvlink caps table. This value should be one greater 1828 * than the largest byte_index value above. 1829 */ 1830 #define NVSWITCH_NVLINK_CAPS_TBL_SIZE 2 1831 1832 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_INVALID (0x00000000) 1833 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_1_0 (0x00000001) 1834 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_2_0 (0x00000002) 1835 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_2_2 (0x00000004) 1836 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_3_0 (0x00000005) 1837 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_3_1 (0x00000006) 1838 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_4_0 (0x00000007) 1839 1840 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000) 1841 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001) 1842 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002) 1843 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_2_2 (0x00000004) 1844 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_3_0 (0x00000005) 1845 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_3_1 (0x00000006) 1846 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_4_0 (0x00000007) 1847 1848 1849 /* 1850 * NVSWITCH_NVLINK_LINK_STATUS_INFO 1851 * 1852 * This structure stores the per-link status of different NVLink parameters. 1853 * 1854 * capsTbl 1855 * This is bit field for getting different global caps. The individual 1856 * bitfields are specified by NVSWITCH_NVLINK_CAPS_* 1857 * phyType 1858 * This field specifies the type of PHY (NVHS or GRS) being used for this 1859 * link. 1860 * subLinkWidth 1861 * This field specifies the no. of lanes per sublink. 1862 * linkState 1863 * This field specifies the current state of the link. See 1864 * NVSWITCH_GET_NVLINK_STATUS_LINK_STATE_* for possible values. 1865 * linkPowerState 1866 * This field specifies the current power state of the link. See 1867 * NVSWITCH_NVLINK_STATUS_LINK_POWER_STATE_* for possible values. 1868 * rxSublinkStatus 1869 * This field specifies the current state of RX sublink. See 1870 * NVSWITCH_GET_NVLINK_STATUS_SUBLINK_RX_STATE_* for possible values. 1871 * txSublinkStatus 1872 * This field specifies the current state of TX sublink. See 1873 * NVSWITCH_GET_NVLINK_STATUS_SUBLINK_TX_STATE_* for possible values. 1874 * nvlinkVersion 1875 * This field specifies the NVLink version supported by the link. 1876 * nciVersion 1877 * This field specifies the NCI version supported by the link. 1878 * phyVersion 1879 * This field specifies the version of PHY being used by the link. 1880 * nvlinkCommonClockSpeed 1881 * This field gives the value of nvlink common clock. 1882 * nvlinkRefClkSpeed 1883 * This field gives the value of nvlink refclk clock. 1884 * nvlinkRefClkType 1885 * This field specifies whether refclk is taken from NVHS reflck or PEX 1886 * refclk for the current GPU. See NVSWITCH_NVLINK_REFCLK_TYPE_INVALID* 1887 * for possible values. 1888 * nvlinkLinkClock 1889 * This field gives the actual clock/speed at which links is running. 1890 * connected 1891 * This field specifies if any device is connected on the other end of the 1892 * link 1893 * loopProperty 1894 * This field specifies if the link is a loopback/loopout link. See 1895 * NVSWITCH_NVLINK_STATUS_LOOP_PROPERTY_* for possible values. 1896 * laneRxdetStatusMask 1897 * This field reports the per-lane RX Detect status provided by MINION. 1898 * remoteDeviceLinkNumber 1899 * This field specifies the link number on the remote end of the link 1900 * remoteDeviceInfo 1901 * This field stores the device information for the remote end of the link 1902 * 1903 */ 1904 1905 typedef struct 1906 { 1907 // Top level capablilites 1908 NvU32 capsTbl; 1909 1910 NvU8 phyType; 1911 NvU8 subLinkWidth; 1912 1913 // Link and sublink states 1914 NvU32 linkState; 1915 NvU32 linkPowerState; 1916 NvU8 rxSublinkStatus; 1917 NvU8 txSublinkStatus; 1918 1919 // Indicates that lane reveral is in effect on this link. 1920 NvBool bLaneReversal; 1921 1922 NvU8 nvlinkVersion; 1923 NvU8 nciVersion; 1924 NvU8 phyVersion; 1925 1926 // Clock information 1927 1928 // These are being deprecated, please use HW Consistent terminology below 1929 NvU32 nvlinkLinkClockKHz; 1930 NvU32 nvlinkCommonClockSpeedKHz; 1931 NvU32 nvlinkRefClkSpeedKHz; 1932 NvU32 nvlinkCommonClockSpeedMhz; 1933 1934 // HW consistent terminology 1935 NvU32 nvlinkLineRateMbps; 1936 NvU32 nvlinkLinkDataRateKiBps; 1937 NvU32 nvlinkLinkClockMhz; 1938 NvU32 nvlinkRefClkSpeedMhz; 1939 NvU8 nvlinkRefClkType; 1940 1941 // Connection information 1942 NvBool connected; 1943 NvU8 loopProperty; 1944 NvU8 remoteDeviceLinkNumber; 1945 NvU8 localDeviceLinkNumber; 1946 1947 // 1948 // Added as part of NvLink 3.0 1949 // Note: SID has link info appended to it when provided by minion 1950 // 1951 NV_DECLARE_ALIGNED(NvU64 remoteLinkSid, 8); 1952 NV_DECLARE_ALIGNED(NvU64 localLinkSid, 8); 1953 1954 // LR10+ only 1955 NvU32 laneRxdetStatusMask; 1956 1957 // LS10+ only 1958 NvBool bIsRepeaterMode; 1959 1960 NVSWITCH_NVLINK_DEVICE_INFO remoteDeviceInfo; 1961 NVSWITCH_NVLINK_DEVICE_INFO localDeviceInfo; 1962 } NVSWITCH_NVLINK_LINK_STATUS_INFO; 1963 1964 /* NVLink link states */ 1965 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_INIT (0x00000000) 1966 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_HWPCFG (0x0000000c) 1967 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_HWCFG (0x00000001) 1968 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_SWCFG (0x00000002) 1969 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_ACTIVE (0x00000003) 1970 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_FAULT (0x00000004) 1971 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_SLEEP (0x00000005) 1972 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_RECOVERY (0x00000006) 1973 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_INVALID (0xFFFFFFFF) 1974 1975 /* NVLink link power states */ 1976 #define NVSWITCH_NVLINK_STATUS_LINK_POWER_STATE_L0 (0x00000000) 1977 #define NVSWITCH_NVLINK_STATUS_LINK_POWER_STATE_L1 (0x00000001) 1978 #define NVSWITCH_NVLINK_STATUS_LINK_POWER_STATE_INVALID (0xFFFFFFFF) 1979 1980 /* NVLink Tx sublink states */ 1981 #define NVSWITCH_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 (0x00000000) 1982 #define NVSWITCH_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE (0x00000004) 1983 #define NVSWITCH_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING (0x00000005) 1984 #define NVSWITCH_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE (0x00000006) 1985 #define NVSWITCH_NVLINK_STATUS_SUBLINK_RX_STATE_OFF (0x00000007) 1986 #define NVSWITCH_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID (0x000000FF) 1987 1988 /* NVLink Rx sublink states */ 1989 #define NVSWITCH_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 (0x00000000) 1990 #define NVSWITCH_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE (0x00000004) 1991 #define NVSWITCH_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING (0x00000005) 1992 #define NVSWITCH_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE (0x00000006) 1993 #define NVSWITCH_NVLINK_STATUS_SUBLINK_TX_STATE_OFF (0x00000007) 1994 #define NVSWITCH_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID (0x000000FF) 1995 1996 #define NVSWITCH_NVLINK_STATUS_PHY_NVHS (0x00000001) 1997 #define NVSWITCH_NVLINK_STATUS_PHY_GRS (0x00000002) 1998 #define NVSWITCH_NVLINK_STATUS_PHY_INVALID (0x000000FF) 1999 2000 /* Version information */ 2001 #define NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_1_0 (0x00000001) 2002 #define NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_2_0 (0x00000002) 2003 #define NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_2_2 (0x00000004) 2004 #define NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_3_0 (0x00000005) 2005 #define NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_3_1 (0x00000006) 2006 #define NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_4_0 (0x00000007) 2007 #define NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_INVALID (0x000000FF) 2008 2009 #define NVSWITCH_NVLINK_STATUS_NCI_VERSION_1_0 (0x00000001) 2010 #define NVSWITCH_NVLINK_STATUS_NCI_VERSION_2_0 (0x00000002) 2011 #define NVSWITCH_NVLINK_STATUS_NCI_VERSION_2_2 (0x00000004) 2012 #define NVSWITCH_NVLINK_STATUS_NCI_VERSION_3_0 (0x00000005) 2013 #define NVSWITCH_NVLINK_STATUS_NCI_VERSION_3_1 (0x00000006) 2014 #define NVSWITCH_NVLINK_STATUS_NCI_VERSION_4_0 (0x00000007) 2015 #define NVSWITCH_NVLINK_STATUS_NCI_VERSION_INVALID (0x000000FF) 2016 2017 #define NVSWITCH_NVLINK_STATUS_NVHS_VERSION_1_0 (0x00000001) 2018 #define NVSWITCH_NVLINK_STATUS_NVHS_VERSION_INVALID (0x000000FF) 2019 2020 #define NVSWITCH_NVLINK_STATUS_GRS_VERSION_1_0 (0x00000001) 2021 #define NVSWITCH_NVLINK_STATUS_GRS_VERSION_INVALID (0x000000FF) 2022 2023 /* Connection properties */ 2024 #define NVSWITCH_NVLINK_STATUS_CONNECTED_TRUE (0x00000001) 2025 #define NVSWITCH_NVLINK_STATUS_CONNECTED_FALSE (0x00000000) 2026 2027 #define NVSWITCH_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK (0x00000001) 2028 #define NVSWITCH_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT (0x00000002) 2029 #define NVSWITCH_NVLINK_STATUS_LOOP_PROPERTY_NONE (0x00000000) 2030 2031 #define NVSWITCH_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID (0x000000FF) 2032 2033 #define NVSWITCH_NVLINK_MAX_LINKS 64 2034 2035 /* NVLink REFCLK types */ 2036 #define NVSWITCH_NVLINK_REFCLK_TYPE_INVALID (0x00) 2037 #define NVSWITCH_NVLINK_REFCLK_TYPE_NVHS (0x01) 2038 #define NVSWITCH_NVLINK_REFCLK_TYPE_PEX (0x02) 2039 2040 typedef struct 2041 { 2042 NV_DECLARE_ALIGNED(NvU64 enabledLinkMask, 8); 2043 NVSWITCH_NVLINK_LINK_STATUS_INFO linkInfo[NVSWITCH_NVLINK_MAX_LINKS]; 2044 } NVSWITCH_GET_NVLINK_STATUS_PARAMS; 2045 2046 /* List of supported capability type */ 2047 #define NVSWITCH_CAP_FABRIC_MANAGEMENT 0 2048 2049 /* 2050 * Max supported capabilities count. 2051 */ 2052 #define NVSWITCH_CAP_COUNT 1 2053 2054 /* 2055 * CTRL_NVSWITCH_ACQUIRE_CAPABILITY 2056 * 2057 * Upon success, user mode would acquire the requested capability 2058 * to perform privilege operations. This IOCTL will acquire one 2059 * capability at a time. 2060 * 2061 * Parameters: 2062 * capDescriptor [IN] 2063 * The OS file descriptor or handle representing the capability. 2064 * cap [IN] 2065 * The requested capability. One of the NVSWITCH_CAP_*. 2066 */ 2067 typedef struct 2068 { 2069 /* input parameters */ 2070 NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); 2071 NvU32 cap; 2072 2073 2074 } NVSWITCH_ACQUIRE_CAPABILITY_PARAMS; 2075 2076 /* 2077 * CTRL_NVSWITCH_GET_TEMPERATURE 2078 * 2079 * Control to query temperature of Nvswitch sensors. 2080 * 2081 * The Temperatures are returned in FXP 24.8(NvTemp) format. 2082 * 2083 * Parameters: 2084 * channelMask [IN] 2085 * Mask of all the thermal channels queried. 2086 * temperature [OUT] 2087 * Temperature of the channel. 2088 * status [OUT] 2089 * Return status of the channel. 2090 */ 2091 2092 #define NVSWITCH_NUM_MAX_CHANNELS 16 2093 2094 typedef struct 2095 { 2096 NvU32 channelMask; 2097 NvTemp temperature[NVSWITCH_NUM_MAX_CHANNELS]; 2098 NvS32 status[NVSWITCH_NUM_MAX_CHANNELS]; 2099 } NVSWITCH_CTRL_GET_TEMPERATURE_PARAMS; 2100 2101 #define NVSWITCH_CTRL_THERMAL_EVENT_ID_WARN 0 2102 #define NVSWITCH_CTRL_THERMAL_EVENT_ID_OVERT 1 2103 2104 typedef struct 2105 { 2106 NvU32 thermalEventId; 2107 NvTemp temperatureLimit; 2108 } NVSWITCH_CTRL_GET_TEMPERATURE_LIMIT_PARAMS; 2109 2110 /* 2111 * Limerock thermal channels 2112 */ 2113 #define NVSWITCH_THERM_CHANNEL_LR10_TSENSE_MAX 0x00 2114 #define NVSWITCH_THERM_CHANNEL_LR10_TSENSE_OFFSET_MAX 0x01 2115 #define NVSWITCH_THERM_CHANNEL_LR10_TDIODE 0x02 2116 #define NVSWITCH_THERM_CHANNEL_LR10_TDIODE_OFFSET 0x03 2117 #define NVSWITCH_NUM_CHANNELS_LR10 4 2118 2119 /* 2120 * Laguna Seca thermal channels 2121 */ 2122 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_MAX 0x00 2123 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_OFFSET_MAX 0x01 2124 #define NVSWITCH_THERM_CHANNEL_LS10_TDIODE 0x02 2125 #define NVSWITCH_THERM_CHANNEL_LS10_TDIODE_OFFSET 0x03 2126 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_0 0x04 2127 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_1 0x05 2128 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_2 0x06 2129 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_3 0x07 2130 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_4 0x08 2131 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_5 0x09 2132 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_6 0x0A 2133 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_7 0x0B 2134 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_8 0x0C 2135 #define NVSWITCH_NUM_CHANNELS_LS10 13 2136 2137 /* 2138 * CTRL_NVSWITCH_GET_THROUGHPUT_COUNTERS 2139 * 2140 * Control for querying NVLINK throughput counters. 2141 * 2142 * Parameters: 2143 * counterMask [IN] 2144 * A mask of counter types. 2145 * One of the NVSWITCH_THROUGHPUT_COUNTERS_TYPE_* macros 2146 * linkMask [IN] 2147 * A mask of desired link(s) 2148 * counters [OUT] 2149 * Fetched counter values 2150 */ 2151 2152 /* NVLink throughput counter types */ 2153 2154 /* Nvlink throughput counters reading data flits in TX */ 2155 #define NVSWITCH_THROUGHPUT_COUNTERS_TYPE_DATA_TX (0x00000001) 2156 2157 /* Nvlink throughput counters reading data flits in RX */ 2158 #define NVSWITCH_THROUGHPUT_COUNTERS_TYPE_DATA_RX (0x00000002) 2159 2160 /* Nvlink throughput counters reading all flits in TX */ 2161 #define NVSWITCH_THROUGHPUT_COUNTERS_TYPE_RAW_TX (0x00000004) 2162 2163 /* Nvlink throughput counters reading all flits in RX */ 2164 #define NVSWITCH_THROUGHPUT_COUNTERS_TYPE_RAW_RX (0x00000008) 2165 2166 #define NVSWITCH_THROUGHPUT_COUNTERS_TYPE_MAX 4 2167 2168 typedef struct nvswitch_throughput_values 2169 { 2170 NvU64 values[NVSWITCH_THROUGHPUT_COUNTERS_TYPE_MAX]; 2171 2172 } NVSWITCH_THROUGHPUT_COUNTER_VALUES; 2173 2174 typedef struct nvswitch_get_throughput_counters 2175 { 2176 NvU16 counterMask; 2177 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 2178 NVSWITCH_THROUGHPUT_COUNTER_VALUES counters[NVSWITCH_MAX_PORTS]; 2179 2180 } NVSWITCH_GET_THROUGHPUT_COUNTERS_PARAMS; 2181 2182 /* 2183 * CTRL_NVSWITCH_GET_BIOS_INFO 2184 * 2185 * Control call to get VBIOS information. 2186 * 2187 * Parameters: 2188 * version [OUT] 2189 * Vbios version in hex value. 2190 */ 2191 typedef struct nvswitch_get_bios_info 2192 { 2193 NvU64 version; 2194 } NVSWITCH_GET_BIOS_INFO_PARAMS; 2195 2196 #define NVSWITCH_INFOROM_VERSION_LEN 16 2197 /* 2198 * CTRL_NVSWITCH_GET_INFOROM_VERSION 2199 * 2200 * Control call to get INFOROM information. 2201 * 2202 * Parameters: 2203 * version [OUT] 2204 * Inforom version in char value. 2205 */ 2206 typedef struct nvswitch_get_inforom_version 2207 { 2208 NvU8 version[NVSWITCH_INFOROM_VERSION_LEN]; 2209 } NVSWITCH_GET_INFOROM_VERSION_PARAMS; 2210 2211 /* 2212 * CTRL_NVSWITCH_BLACKLIST_DEVICE 2213 * 2214 * Control to Blacklist a device. A blacklisted device will have 2215 * interrupts disabled, and opens/ioctls will fail. If a device is 2216 * blacklisted OOB then the setting is persistent. If a device is 2217 * blacklisted by the OS (such as module parameter) then the setting 2218 * persists for the OS until the config file is changed and the driver 2219 * reloaded. If a device is blacklisted by ioctl then the setting does 2220 * not persist across driver unload/reload. 2221 * 2222 * See BLACKLIST_REASON enum definition in interface/ioctl_common_nvswitch.h 2223 * 2224 * Parameters: 2225 * deviceReason [IN] 2226 * The reason the device is blacklisted 2227 */ 2228 typedef struct nvswitch_blacklist_device 2229 { 2230 NVSWITCH_DEVICE_BLACKLIST_REASON deviceReason; 2231 } NVSWITCH_BLACKLIST_DEVICE_PARAMS; 2232 2233 /* 2234 * CTRL_NVSWITCH_SET_FM_DRIVER_STATE 2235 * 2236 * Control to set the FM driver state for a device (heartbeat). 2237 * 2238 * Driver Fabric State is intended to reflect the state of the driver and 2239 * fabric manager. Once FM sets the Driver State to CONFIGURED, it is 2240 * expected the FM will send heartbeat updates. If the heartbeat is not 2241 * received before the session timeout, then the driver reports status 2242 * as MANAGER_TIMEOUT. See also control device ioctl CTRL_NVSWITCH_GET_DEVICES_V2. 2243 * 2244 * See DRIVER_FABRIC_STATE enum definition in interface/ioctl_common_nvswitch.h 2245 * 2246 * Parameters: 2247 * driverState [IN] 2248 * The driver state for the device 2249 */ 2250 typedef struct nvswitch_set_fm_driver_state 2251 { 2252 NVSWITCH_DRIVER_FABRIC_STATE driverState; 2253 } NVSWITCH_SET_FM_DRIVER_STATE_PARAMS; 2254 2255 /* 2256 * CTRL_NVSWITCH_SET_DEVICE_FABRIC_STATE 2257 * 2258 * Control to set the device fabric state 2259 * 2260 * Device Fabric State reflects the fabric state of the nvswitch device. 2261 * FM sets the Device Fabric State to CONFIGURED once FM is managing the 2262 * device. 2263 * 2264 * See DEVICE_FABRIC_STATE enum definition in interface/ioctl_common_nvswitch.h 2265 * 2266 * Parameters: 2267 * deviceState [IN] 2268 * The device fabric state 2269 */ 2270 typedef struct nvswitch_set_device_fabric_state 2271 { 2272 NVSWITCH_DEVICE_FABRIC_STATE deviceState; 2273 } NVSWITCH_SET_DEVICE_FABRIC_STATE_PARAMS; 2274 2275 /* 2276 * CTRL_NVSWITCH_SET_FM_HEARTBEAT_TIMEOUT 2277 * 2278 * Control to set the FM session heartbeat timeout for a device 2279 * 2280 * If a device is managed by FM, and if a heartbeat is not received 2281 * by the FM_HEARTBEAT_TIMEOUT, then the driver reports Driver 2282 * Fabric State as MANAGER_TIMEOUT. 2283 * 2284 * NVSWITCH_DEFAULT_FM_HEARTBEAT_TIMEOUT_MSEC is the default timeout 2285 * 2286 * Parameters: 2287 * fmTimeout [IN] 2288 * The FM timeout value for the device, in milliseconds 2289 */ 2290 typedef struct nvswitch_set_fm_heartbeat_timeout 2291 { 2292 NvU32 fmTimeout; 2293 } NVSWITCH_SET_FM_HEARTBEAT_TIMEOUT_PARAMS; 2294 #define NVSWITCH_DEFAULT_FM_HEARTBEAT_TIMEOUT_MSEC (10*1000) 2295 2296 /* 2297 * CTRL_NVSWITCH_SET_LINK_ERROR_STATE_INFO 2298 * 2299 * Control to set bitmask info of the 2300 * link training error 2301 * 2302 * Parameters: 2303 * attemptedTrainingMask0 [IN] 2304 * Bitmask of links that have been 2305 * attempted to train. 2306 * trainingErrorMask0 [IN] 2307 * Bitmaks of links that have an error 2308 * during training. 2309 */ 2310 typedef struct nvswitch_set_training_error_info 2311 { 2312 NvU64 attemptedTrainingMask0; 2313 NvU64 trainingErrorMask0; 2314 } NVSWITCH_SET_TRAINING_ERROR_INFO_PARAMS; 2315 2316 #define NVSWITCH_DEVICE_EVENT_FATAL 0 2317 #define NVSWITCH_DEVICE_EVENT_NONFATAL 1 2318 #define NVSWITCH_DEVICE_EVENT_PORT_UP 2 2319 #define NVSWITCH_DEVICE_EVENT_PORT_DOWN 3 2320 #define NVSWITCH_DEVICE_EVENT_FABRIC_STATE 4 2321 #define NVSWITCH_DEVICE_EVENT_INBAND_DATA 5 2322 #define NVSWITCH_DEVICE_EVENT_COUNT 6 2323 #define NVSWITCH_REGISTER_EVENTS_MAX_EVENT_IDS (500) 2324 2325 /* 2326 * CTRL_NVSWITCH_REGISTER_EVENTS 2327 * 2328 * Control to register event IDs with an OS descriptor 2329 * 2330 * This control allows for clients to register one or more event IDs 2331 * with an OS descriptor. After registering event IDs, clients may poll 2332 * the OS descriptor for the registered event. 2333 * 2334 * Subsequent calls to register_event will overwrite currently registered 2335 * event IDs. This allows the client to switch event polling as and when required. 2336 * Explicit unregister_events control call isn't necessary when the 2337 * client wishes to change the event types currently being monitored. 2338 * 2339 * On Linux, only a single event ID can be registered to each 2340 * OS descriptor at a time. Calling this control with 2341 * numEvents > 1 on Linux will cause an error to be returned. 2342 * 2343 * On Windows, the osDescriptor field should be a valid 2344 * Windows EVENT handle. 2345 * 2346 * osDescriptor is unused on other operating systems. 2347 * 2348 * Parameters: 2349 * eventIds [IN] 2350 * A buffer of event IDs to register for 2351 * numEvents [IN] 2352 * Number of valid elements in eventIds 2353 * osDescriptor [IN] 2354 * OS event handle (Windows only) 2355 */ 2356 typedef struct nvswitch_register_events 2357 { 2358 NvU32 eventIds[NVSWITCH_REGISTER_EVENTS_MAX_EVENT_IDS]; 2359 NvU32 numEvents; 2360 void *osDescriptor; 2361 } NVSWITCH_REGISTER_EVENTS_PARAMS; 2362 2363 /* 2364 * CTRL_NVSWITCH_UNREGISTER_EVENTS 2365 * 2366 * Control to unregister all event IDs from an OS descriptor 2367 * 2368 * This control unregisters all registered event IDs associated 2369 * with an OS descriptor. 2370 * 2371 * On Windows, the osDescriptor field should be a valid 2372 * Windows EVENT handle. 2373 * 2374 * osDescriptor is unused on other operating systems. 2375 * 2376 * Parameters: 2377 * osDescriptor [IN] 2378 * OS event handle (Windows only) 2379 */ 2380 typedef struct nvswitch_unregister_events 2381 { 2382 void *osDescriptor; 2383 } NVSWITCH_UNREGISTER_EVENTS_PARAMS; 2384 2385 /* 2386 * CTRL_NVSWITCH_GET_FATAL_ERROR_SCOPE 2387 * 2388 * Control to query if a fatal error is occurred on a port or device 2389 * 2390 * Parameters: 2391 * device [OUT] 2392 * Set to NV_TRUE if the nvswitch device encountered a fatal error 2393 * port [OUT] 2394 * An array of booleans indicating which ports 2395 * encountered a fatal error 2396 */ 2397 typedef struct nvswitch_get_fatal_error_scope_params 2398 { 2399 NvBool device; 2400 NvBool port[NVSWITCH_MAX_PORTS]; 2401 } NVSWITCH_GET_FATAL_ERROR_SCOPE_PARAMS; 2402 2403 /* 2404 * CTRL_NVSWITCH_SET_MC_RID_TABLE 2405 * 2406 * Control for programming an ingress multicast RID table entry. 2407 * This interface is only supported on LS10 architecture. All others will 2408 * return an error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 2409 * 2410 * Parameters: 2411 * portNum [IN] 2412 * A valid port number present in the port masks returned by 2413 * NVSWITCH_GET_INFO 2414 * index [IN] 2415 * Index within the multicast RID table to be programmed. This is 2416 * equivalent to MCID. 2417 * extendedTable [IN] 2418 * boolean: Set the requested entry in the extended table 2419 * else set the requested entry in the main table 2420 * ports [IN] 2421 * The list of ports. For each multicast request, the address hash 2422 * selects the multicast port string, and hardware multicasts to ports 2423 * in that string. 2424 * vcHop [IN] 2425 * Array of VC hop values for each port. 2426 * mcSize [IN] 2427 * Number of ports in the multicast group (must be a nonzero value). 2428 * Must be the number of ports in the main table, plus the extended table 2429 * if that is used. 2430 * Must be the same for all spray groups. 2431 * Caller is responsible for ensuring the above conditions, as the driver 2432 * provides only minimal range checking. 2433 * numSprayGroups [IN] 2434 * Number of groups to spray over. This must be a nonzero value. 2435 * portsPerSprayGroup [IN] 2436 * Array, number of ports contained in each spray group. 2437 * Note these must all be the same size unless an extended entry 2438 * is used, 2439 * _and_ numSprayGroups is the same for both the main entry and extended 2440 * entry, 2441 * _and_ the sum of ports in the main and extended groups equals 2442 * mcSize for each spray group. 2443 * FM is responsible for providing the correct value. Driver provides only 2444 * minimal range checking. 2445 * replicaOffset [IN] 2446 * Array, offsets within each spray group to the primary replica port for the group. 2447 * The caller should specify mcSize primaryReplicas. 2448 * replicaValid [IN] 2449 * boolean: Array, set the primary replica according to the replicaOffset array. 2450 * else let hardware choose a default primary replica port 2451 * extendedPtr [IN] 2452 * pointer to the extended table to append to the multicast table entry 2453 * can only be valid in the main table entries 2454 * extendedValid [IN] 2455 * boolean: Use the extended index to append to the main table string. 2456 * else the main string specifies the complete operation for its MCID 2457 * noDynRsp [IN] 2458 * boolean: no dynamic alt selection on MC responses. This field has no meaning in 2459 * the extended table 2460 * entryValid 2461 * boolean: flag this entry in the MC RID table as valid 2462 */ 2463 2464 #define NVSWITCH_MC_MAX_PORTS 64 2465 #define NVSWITCH_MC_MAX_SPRAYGROUPS 16 2466 2467 #define NVSWITCH_MC_VCHOP_PASS 0 2468 #define NVSWITCH_MC_VCHOP_INVERT 1 2469 #define NVSWITCH_MC_VCHOP_FORCE0 2 2470 #define NVSWITCH_MC_VCHOP_FORCE1 3 2471 2472 typedef struct nvswitch_set_mc_rid_table_params 2473 { 2474 NvU32 portNum; 2475 NvU32 index; 2476 NvBool extendedTable; 2477 NvU32 ports[NVSWITCH_MC_MAX_PORTS]; 2478 NvU8 vcHop[NVSWITCH_MC_MAX_PORTS]; 2479 NvU32 mcSize; 2480 NvU32 numSprayGroups; 2481 NvU32 portsPerSprayGroup[NVSWITCH_MC_MAX_SPRAYGROUPS]; 2482 NvU32 replicaOffset[NVSWITCH_MC_MAX_SPRAYGROUPS]; 2483 NvBool replicaValid[NVSWITCH_MC_MAX_SPRAYGROUPS]; 2484 NvU32 extendedPtr; 2485 NvBool extendedValid; 2486 NvBool noDynRsp; 2487 NvBool entryValid; 2488 } NVSWITCH_SET_MC_RID_TABLE_PARAMS; 2489 2490 /* 2491 * CTRL_NVSWITCH_GET_MC_RID_TABLE 2492 * 2493 * Control for reading an ingress multicast RID table entry. 2494 * This interface is only supported on LS10 architecture. All others will 2495 * return an error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 2496 * 2497 * Parameters: 2498 * portNum [IN] 2499 * A valid port number present in the port masks returned by 2500 * NVSWITCH_GET_INFO 2501 * index [IN] 2502 * Index within the multicast RID table to be retrieved. This is 2503 * equivalent to MCID. 2504 * extendedTable [IN] 2505 * boolean: Get the requested entry from the extended table. 2506 * Else get the requested entry from the main table. 2507 * ports [OUT] 2508 * The list of ports. Port order within spray groups is not guaranteed 2509 * to be preserved. 2510 * vcHop [OUT] 2511 * Array containing VC hop values for each entry in the ports array. 2512 * mcSize [OUT] 2513 * Number of ports in the multicast group. 2514 * numSprayGroups [OUT] 2515 * Number of groups to spray over. 2516 * portsPerSprayGroup [OUT] 2517 * Array, each element contains the number of ports within each corresponding 2518 * spray group. 2519 * replicaOffset [OUT] 2520 * Array, offsets within each spray group to the primary replica port 2521 * for the group. 2522 * replicaValid [OUT] 2523 * boolean: Array, specifies whether each entry in the replicaOffset 2524 * array is valid. 2525 * extendedPtr [OUT] 2526 * Pointer to the extended table appended to the main table entry. 2527 * Only valid for main table entries. 2528 * extendedValid [OUT] 2529 * boolean: Whether the extendedPtr is valid. 2530 * noDynRsp [IN] 2531 * boolean: no dynamic alt selection on MC responses. 2532 * This field has no meaning in the extended table. 2533 * entryValid 2534 * boolean: Whether this entry in the MC RID table is valid 2535 */ 2536 2537 typedef struct nvswitch_get_mc_rid_table_params 2538 { 2539 NvU32 portNum; 2540 NvU32 index; 2541 NvBool extendedTable; 2542 NvU32 ports[NVSWITCH_MC_MAX_PORTS]; 2543 NvU8 vcHop[NVSWITCH_MC_MAX_PORTS]; 2544 NvU32 mcSize; 2545 NvU32 numSprayGroups; 2546 NvU32 portsPerSprayGroup[NVSWITCH_MC_MAX_SPRAYGROUPS]; 2547 NvU32 replicaOffset[NVSWITCH_MC_MAX_SPRAYGROUPS]; 2548 NvBool replicaValid[NVSWITCH_MC_MAX_SPRAYGROUPS]; 2549 NvU32 extendedPtr; 2550 NvBool extendedValid; 2551 NvBool noDynRsp; 2552 NvBool entryValid; 2553 } NVSWITCH_GET_MC_RID_TABLE_PARAMS; 2554 2555 #define NVSWITCH_I2C_SMBUS_CMD_QUICK 0 2556 #define NVSWITCH_I2C_SMBUS_CMD_BYTE 1 2557 #define NVSWITCH_I2C_SMBUS_CMD_BYTE_DATA 2 2558 #define NVSWITCH_I2C_SMBUS_CMD_WORD_DATA 3 2559 2560 /* 2561 * NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW 2562 * 2563 * This structure provides data for the SMBUS Byte command. 2564 * 2565 * message [IN/OUT] 2566 * 8 Bit data message to read or write. 2567 */ 2568 typedef struct 2569 { 2570 NvU8 message; 2571 } NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW; 2572 2573 /* 2574 * NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_BYTE_DATA_RW 2575 * 2576 * This structure provides data for the SMBUS Byte Data command. 2577 * 2578 * cmd [IN] 2579 * SMBUS input command. 2580 * message [IN/OUT] 2581 * 8 Bit data message to read or write. 2582 */ 2583 typedef struct 2584 { 2585 NvU8 cmd; 2586 NvU8 message; 2587 } NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_BYTE_DATA_RW; 2588 2589 /* 2590 * NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_WORD_DATA_RW 2591 * 2592 * This structure provides data for the SMBUS Word Data command. 2593 * 2594 * cmd [IN] 2595 * SMBUS input command. 2596 * message [IN/OUT] 2597 * 16 Bit data message to read or write. 2598 */ 2599 typedef struct 2600 { 2601 NvU8 cmd; 2602 NvU16 message; 2603 } NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_WORD_DATA_RW; 2604 2605 typedef union 2606 { 2607 NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW smbusByte; 2608 NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_BYTE_DATA_RW smbusByteData; 2609 NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_WORD_DATA_RW smbusWordData; 2610 } NVSWITCH_I2C_TRANSACTION_DATA; 2611 2612 /* 2613 * CTRL_NVSWITCH_I2C_SMBUS_COMMAND 2614 * 2615 * Control to issue SMBUS I2C transaction to an I2C device 2616 * 2617 * Parameters: 2618 * deviceAddr [IN] 2619 * The I2C Slave address to issue a transaction to. This is the unshifted, 2620 * normal 7-bit address. For example, the input would be address 0x50 for 2621 * device 0xA0. 2622 * port [IN] 2623 * The logical port/bus in which the I2C transaction is requested. 2624 * cmdType [IN] 2625 * The desired SMBUS command type. See NVSWITCH_I2C_SMBUS_CMD_*. 2626 * bRead [IN] 2627 * This field must be specified to indicate whether the 2628 * command is a write (FALSE) or a read (TRUE). 2629 * transactionData [IN/OUT] 2630 * The NVSWITCH_I2C_TRANSACTION_DATA union to be filled out/read back 2631 * depending on the SMBUS command type. 2632 */ 2633 typedef struct nvswitch_i2c_smbus_command_params 2634 { 2635 NvU16 deviceAddr; 2636 NvU32 port; 2637 NvU8 cmdType; 2638 NvBool bRead; 2639 NVSWITCH_I2C_TRANSACTION_DATA transactionData; 2640 } NVSWITCH_I2C_SMBUS_COMMAND_PARAMS; 2641 2642 /* 2643 * APIs for getting NVLink counters 2644 */ 2645 2646 // These are the bitmask definitions for different counter types 2647 2648 #define NVSWITCH_NVLINK_COUNTER_INVALID 0x00000000 2649 2650 #define NVSWITCH_NVLINK_COUNTER_TL_TX0 0x00000001 2651 #define NVSWITCH_NVLINK_COUNTER_TL_TX1 0x00000002 2652 #define NVSWITCH_NVLINK_COUNTER_TL_RX0 0x00000004 2653 #define NVSWITCH_NVLINK_COUNTER_TL_RX1 0x00000008 2654 2655 #define NVSWITCH_NVLINK_LP_COUNTERS_DL 0x00000010 2656 2657 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT 0x00010000 2658 2659 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(i) (1 << (i + 17)) 2660 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE 8 2661 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 0x00020000 2662 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 0x00040000 2663 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 0x00080000 2664 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 0x00100000 2665 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 0x00200000 2666 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 0x00400000 2667 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 0x00800000 2668 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 0x01000000 2669 2670 #define NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_REPLAY 0x02000000 2671 #define NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_RECOVERY 0x04000000 2672 2673 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_REPLAY 0x08000000 2674 2675 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED 0x10000000 2676 2677 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_ECC_COUNTS 0x20000000 2678 2679 #define NVSWITCH_NVLINK_COUNTER_PHY_REFRESH_PASS 0x40000000 2680 #define NVSWITCH_NVLINK_COUNTER_PHY_REFRESH_FAIL 0x80000000 2681 2682 /* 2683 * Note that COUNTER_MAX_TYPES will need to be updated each time adding 2684 * a new counter type exceeds the existing value. 2685 * 2686 */ 2687 #define NVSWITCH_NVLINK_COUNTER_MAX_TYPES 32 2688 2689 /* 2690 * CTRL_NVSWITCH_GET_COUNTERS 2691 * This command gets the counts for different counter types. 2692 * 2693 * [in] linkId 2694 * This parameter specifies the TL link id/no for which we want to get 2695 * counters for. 2696 * 2697 * [in] counterMask 2698 * This parameter specifies the input mask for desired counter types. 2699 * 2700 * [out] bTx0TlCounterOverflow 2701 * This boolean is set to NV_TRUE if TX Counter 0 has rolled over. 2702 * 2703 * [out] bTx1TlCounterOverflow 2704 * This boolean is set to NV_TRUE if TX Counter 1 has rolled over. 2705 * 2706 * [out] bRx0TlCounterOverflow 2707 * This boolean is set to NV_TRUE if RX Counter 0 has rolled over. 2708 * 2709 * [out] bRx1TlCounterOverflow 2710 * This boolean is set to NV_TRUE if RX Counter 1 has rolled over. 2711 * 2712 * [out] nvlinkCounters 2713 * This array contains the error counts for each error type as requested from 2714 * the counterMask. The array indexes correspond to the mask bits one-to-one. 2715 */ 2716 2717 typedef struct 2718 { 2719 NvU8 linkId; 2720 NvU32 counterMask; 2721 NvBool bTx0TlCounterOverflow; 2722 NvBool bTx1TlCounterOverflow; 2723 NvBool bRx0TlCounterOverflow; 2724 NvBool bRx1TlCounterOverflow; 2725 NV_DECLARE_ALIGNED(NvU64 nvlinkCounters[NVSWITCH_NVLINK_COUNTER_MAX_TYPES], 8); 2726 } NVSWITCH_NVLINK_GET_COUNTERS_PARAMS; 2727 2728 /* 2729 * Structure to store the ECC error data. 2730 * valid 2731 * Is the lane valid or not 2732 * eccErrorValue 2733 * Value of the Error. 2734 * overflowed 2735 * If the error overflowed or not 2736 */ 2737 typedef struct 2738 { 2739 NvBool valid; 2740 NvU32 eccErrorValue; 2741 NvBool overflowed; 2742 } NVSWITCH_LANE_ERROR; 2743 2744 /* 2745 * Structure to store ECC error data for Links 2746 * errorLane array index corresponds to the lane number. 2747 * 2748 * errorLane[] 2749 * Stores the ECC error data per lane. 2750 */ 2751 typedef struct 2752 { 2753 NVSWITCH_LANE_ERROR errorLane[NVSWITCH_NVLINK_MAX_LANES]; 2754 NvU32 eccDecFailed; 2755 NvBool eccDecFailedOverflowed; 2756 } NVSWITCH_LINK_ECC_ERROR; 2757 2758 /* 2759 * CTRL_GET_NVLINK_ECC_ERRORS 2760 * 2761 * Control to get the values of ECC ERRORS 2762 * 2763 * Parameters: 2764 * linkMask [IN] 2765 * Links on which the ECC error data requested 2766 * A valid link/port mask returned by the port masks returned by 2767 * NVSWITCH_GET_INFO 2768 * errorLink[] [OUT] 2769 * Stores the ECC error related information for each link. 2770 * errorLink array index corresponds to the link Number. 2771 */ 2772 2773 typedef struct nvswitch_get_nvlink_ecc_errors 2774 { 2775 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 2776 NVSWITCH_LINK_ECC_ERROR errorLink[NVSWITCH_NVLINK_MAX_LINKS]; 2777 } NVSWITCH_GET_NVLINK_ECC_ERRORS_PARAMS; 2778 2779 /* 2780 * CTRL_NVSWITCH_CCI_CMIS_PRESENCE 2781 * 2782 * Control to get module presence bitmasks 2783 * 2784 * Parameters: 2785 * cagesMask [OUT] 2786 * Bitmask representing the CMIS module cages present 2787 * (associated with) the selected ASIC device 2788 * modulesMask [OUT] 2789 * Bitmask representing the CMIS modules currently present 2790 * (plugged in) on the selected ASIC device 2791 */ 2792 2793 typedef struct nvswitch_cci_cmis_presence_params 2794 { 2795 NvU32 cagesMask; 2796 NvU32 modulesMask; 2797 NvU32 reserved0; 2798 NvU32 reserved1; 2799 NvU32 reserved2; 2800 NvU32 reserved3; 2801 } NVSWITCH_CCI_CMIS_PRESENCE_PARAMS; 2802 2803 #define NVSWITCH_CCI_CMIS_NVLINK_MAPPING_ENCODED_VALUE(i) (7 + (i<<3)):(i<<3) 2804 #define NVSWITCH_CCI_CMIS_NVLINK_MAPPING_ENCODED_VALUE_LINK_ID 5:0 2805 #define NVSWITCH_CCI_CMIS_NVLINK_MAPPING_GET_OSFP_LANE_MASK(laneMask, linkId, eVal) \ 2806 do { \ 2807 NvU8 _byte, _lane; \ 2808 \ 2809 laneMask = 0; \ 2810 for (_lane = 0; _lane < 8; _lane++) \ 2811 { \ 2812 _byte = REF_VAL64(NVSWITCH_CCI_CMIS_NVLINK_MAPPING_ENCODED_VALUE(_lane), eVal); \ 2813 if (REF_VAL64(NVSWITCH_CCI_CMIS_NVLINK_MAPPING_ENCODED_VALUE_LINK_ID, _byte) == linkId) \ 2814 { \ 2815 laneMask |= NVBIT(_lane); \ 2816 } \ 2817 } \ 2818 } while (0); 2819 2820 /* 2821 * CTRL_NVSWITCH_CCI_CMIS_NVLINK_MAPPING 2822 * 2823 * Control to get cage to NVLink link mappings 2824 * 2825 * Provided macros should be used to extract fields from 2826 * encoded value. 2827 * 2828 * Parameters: 2829 * cageIndex [IN] 2830 * Target cage index (>=0 and <= 31) on the 2831 * selected ASIC device. 2832 * linkMask [OUT] 2833 * Mask of Nvlinks mapped to the given cage 2834 * encodedValue [OUT] 2835 * Value that encodes the following: 2836 * -Link Ids to OSFP lane number 2837 */ 2838 2839 typedef struct nvswitch_cci_cmis_nvlink_mapping_params 2840 { 2841 NvU8 cageIndex; 2842 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 2843 NV_DECLARE_ALIGNED(NvU64 encodedValue, 8); 2844 NvU32 reserved0; 2845 NvU32 reserved1; 2846 NvU32 reserved2; 2847 NvU32 reserved3; 2848 } NVSWITCH_CCI_CMIS_NVLINK_MAPPING_PARAMS; 2849 2850 #define NVSWITCH_CCI_CMIS_MEMORY_ACCESS_BUF_SIZE (128) 2851 2852 /* 2853 * CTRL_NVSWITCH_CCI_CMIS_MEMORY_ACCESS_READ 2854 * 2855 * Control for direct memory accesses to cages 2856 * 2857 * Parameters: 2858 * cageIndex [IN] 2859 * Target cage index (>=0 and <= 31) on the 2860 * selected ASIC device 2861 * bank [IN] 2862 * Target bank in module (if address >= 0x80) 2863 * page [IN] 2864 * Target page in module (if address >= 0x80) 2865 * address [IN] 2866 * Target byte address (offset) in module 2867 * count [IN] 2868 * Number of bytes to read (>=0 and <= 0x7F) 2869 * bSequenceLock [IN] 2870 * Allows clients to own the module for 2871 * CMIS read/write sequences. This must 2872 * be set to TRUE for all accesses within 2873 * the sequence. Setting it to FALSE will 2874 * release the lock. The lock will expire 2875 * and be released if the module is left idle 2876 * for greater than 10 seconds. 2877 * data[] [OUT] 2878 * 128 byte data buffer 2879 */ 2880 2881 typedef struct nvswitch_cci_cmis_memory_access_read_params 2882 { 2883 NvU8 cageIndex; 2884 NvU8 bank; 2885 NvU8 page; 2886 NvU8 address; 2887 NvU8 count; 2888 NvU8 data[NVSWITCH_CCI_CMIS_MEMORY_ACCESS_BUF_SIZE]; 2889 NvBool bSequenceLock; 2890 NvU8 reserved0[3]; 2891 NvU32 reserved1; 2892 NvU32 reserved2; 2893 NvU32 reserved3; 2894 } NVSWITCH_CCI_CMIS_MEMORY_ACCESS_READ_PARAMS; 2895 2896 /* 2897 * CTRL_NVSWITCH_CCI_CMIS_MEMORY_ACCESS_WRITE 2898 * 2899 * Control for direct memory accesses to cages 2900 * 2901 * Parameters: 2902 * cageIndex [IN] 2903 * Target cage index (>=0 and <= 31) on the 2904 * selected ASIC device 2905 * bank [IN] 2906 * Target bank in module (if address >= 0x80) 2907 * page [IN] 2908 * Target page in module (if address >= 0x80) 2909 * address [IN] 2910 * Target byte address (offset) in module 2911 * count [IN] 2912 * Number of bytes to write (>=0 and <= 0x7F) 2913 * bSequenceLock [IN] 2914 * Allows clients to own the module for 2915 * CMIS read/write sequences. This must 2916 * be set to TRUE for all accesses within 2917 * the sequence. Setting it to FALSE will 2918 * release the lock. The lock will expire 2919 * and be released if the module is left idle 2920 * for greater than 10 seconds. 2921 * data[] [IN] 2922 * 128 byte data buffer 2923 */ 2924 2925 typedef struct nvswitch_cci_cmis_memory_access_write_params 2926 { 2927 NvU8 cageIndex; 2928 NvU8 bank; 2929 NvU8 page; 2930 NvU8 address; 2931 NvU8 count; 2932 NvU8 data[NVSWITCH_CCI_CMIS_MEMORY_ACCESS_BUF_SIZE]; 2933 NvBool bSequenceLock; 2934 NvU8 reserved0[3]; 2935 NvU32 reserved1; 2936 NvU32 reserved2; 2937 NvU32 reserved3; 2938 } NVSWITCH_CCI_CMIS_MEMORY_ACCESS_WRITE_PARAMS; 2939 2940 #define NVSWITCH_CCI_CMIS_CAGE_BEZEL_MARKING_LEN 31 2941 2942 /* 2943 * CTRL_NVSWITCH_CCI_CMIS_CAGE_BEZEL_MARKING 2944 * 2945 * Control to get bezel information for a cage. 2946 * 2947 * Parameters: 2948 * cageIndex [IN] 2949 * Target cage index (>=0 and <= 31) on the 2950 * selected ASIC device. 2951 * bezelMarking [OUT] 2952 * 2953 */ 2954 2955 typedef struct nvswitch_cci_cmis_cage_bezel_marking_params 2956 { 2957 NvU8 cageIndex; 2958 char bezelMarking[NVSWITCH_CCI_CMIS_CAGE_BEZEL_MARKING_LEN + 1]; 2959 NvU32 reserved0; 2960 NvU32 reserved1; 2961 NvU32 reserved2; 2962 NvU32 reserved3; 2963 } NVSWITCH_CCI_CMIS_CAGE_BEZEL_MARKING_PARAMS; 2964 2965 #define NVSWITCH_CCI_XVCR_LANES 0x8 2966 2967 /* 2968 * 2969 * Structure to store cci grading values 2970 * 2971 * 2972 * This API is not supported on SV10. 2973 * 2974 * Parameters: 2975 * tx_init 2976 * TX-Input Initial Tuning grading. 2977 * rx_init 2978 * RX-Input Initial Tuning grading. 2979 * tx_maint 2980 * TX-Input Maintenance grading. 2981 * rx_maint 2982 * RX-Input Maintenance grading. 2983 */ 2984 typedef struct nvswitch_cci_grading_values 2985 { 2986 NvU8 tx_init[NVSWITCH_CCI_XVCR_LANES]; 2987 NvU8 rx_init[NVSWITCH_CCI_XVCR_LANES]; 2988 NvU8 tx_maint[NVSWITCH_CCI_XVCR_LANES]; 2989 NvU8 rx_maint[NVSWITCH_CCI_XVCR_LANES]; 2990 } NVSWITCH_CCI_GRADING_VALUES; 2991 2992 /* 2993 * CTRL_NVSWITCH_CCI_GET_GRADING_VALUES 2994 * 2995 * Control to get cci xvcr grading values 2996 * 2997 * 2998 * This API is not supported on SV10. 2999 * 3000 * Parameters: 3001 * link [IN] 3002 * Link number 3003 * laneMask [OUT] 3004 * Lane mask of valid indexes in the grading data 3005 * grading [OUT] 3006 * xvcr grading values 3007 */ 3008 typedef struct nvswitch_cci_get_grading_values_params 3009 { 3010 NvU32 linkId; 3011 NvU8 laneMask; 3012 NVSWITCH_CCI_GRADING_VALUES grading; 3013 } NVSWITCH_CCI_GET_GRADING_VALUES_PARAMS; 3014 3015 #define NVSWITCH_NVLINK_MAX_CORRECTABLE_ERROR_DAYS 5 3016 #define NVSWITCH_NVLINK_MAX_CORRECTABLE_ERROR_MONTHS 3 3017 3018 typedef struct 3019 { 3020 NvU32 lastUpdated; 3021 NvU32 flitCrcErrorsPerMinute; 3022 NvU32 laneCrcErrorsPerMinute[NVSWITCH_NVLINK_MAX_LANES]; 3023 } NVSWITCH_NVLINK_CORRECTABLE_ERROR_RATES; 3024 3025 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_COUNT_TX_NVHS 0 3026 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_COUNT_TX_RESERVED 1 3027 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_COUNT_TX_OTHER 2 3028 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_NUM_TX_LP_ENTER 3 3029 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_NUM_TX_LP_EXIT 4 3030 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_COUNT_TX_SLEEP 5 3031 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_MAX_COUNTERS 6 3032 /* 3033 * CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS 3034 * 3035 * Reads NVLINK low power counters for given linkId 3036 * 3037 * Parameters: 3038 * linkId [IN] 3039 * ID of the link to be queried 3040 * counterValidMask [IN,OUT] 3041 * Mask of valid counters 3042 * counterValues [OUT] 3043 * Low power counter values returned 3044 */ 3045 typedef struct nvswitch_get_nvlink_lp_counters_params 3046 { 3047 NvU32 linkId; 3048 NvU32 counterValidMask; 3049 NvU32 counterValues[CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_MAX_COUNTERS]; 3050 } NVSWITCH_GET_NVLINK_LP_COUNTERS_PARAMS; 3051 3052 /* 3053 * CTRL_NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES 3054 * 3055 * This command queries recent correctable error rates for the given link. 3056 * 3057 * The error rates specify the maximum number of errors per minute recorded 3058 * for the given link within a 24-hour period for daily maximums or a 30-day 3059 * period for monthly maximums. 3060 * 3061 * Parameters: 3062 * linkId [in] 3063 * NVLink link ID 3064 * dailyMaxCorrectableErrorRates[] [OUT] 3065 * NVLink daily max correctable error rate array 3066 * monthlyMaxCorrectableErrorRates[] [OUT] 3067 * NVLink monthly max correctable error rate array 3068 */ 3069 3070 typedef struct 3071 { 3072 NvU8 linkId; 3073 NVSWITCH_NVLINK_CORRECTABLE_ERROR_RATES dailyMaxCorrectableErrorRates[NVSWITCH_NVLINK_MAX_CORRECTABLE_ERROR_DAYS]; 3074 NVSWITCH_NVLINK_CORRECTABLE_ERROR_RATES monthlyMaxCorrectableErrorRates[NVSWITCH_NVLINK_MAX_CORRECTABLE_ERROR_MONTHS]; 3075 } NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS; 3076 3077 #define NVSWITCH_NVLINK_ERROR_READ_SIZE 128 //could not read the maximum size (721) of entries in one call 3078 3079 typedef enum 3080 { 3081 NVSWITCH_NVLINK_NO_ERROR = 0, 3082 3083 //DL RX Fatal Counts 3084 NVSWITCH_NVLINK_ERR_DL_RX_FAULT_DL_PROTOCOL_FATAL = 1000, 3085 NVSWITCH_NVLINK_ERR_DL_RX_FAULT_SUBLINK_CHANGE_FATAL, 3086 3087 //DL RX Correctable Accumulated Counts 3088 NVSWITCH_NVLINK_ERR_DL_RX_FLIT_CRC_CORR, 3089 NVSWITCH_NVLINK_ERR_DL_RX_LANE0_CRC_CORR, 3090 NVSWITCH_NVLINK_ERR_DL_RX_LANE1_CRC_CORR, 3091 NVSWITCH_NVLINK_ERR_DL_RX_LANE2_CRC_CORR, 3092 NVSWITCH_NVLINK_ERR_DL_RX_LANE3_CRC_CORR, 3093 NVSWITCH_NVLINK_ERR_DL_RX_LINK_REPLAY_EVENTS_CORR, 3094 3095 //DL TX Fatal Counts 3096 NVSWITCH_NVLINK_ERR_DL_TX_FAULT_RAM_FATAL, 3097 NVSWITCH_NVLINK_ERR_DL_TX_FAULT_INTERFACE_FATAL, 3098 NVSWITCH_NVLINK_ERR_DL_TX_FAULT_SUBLINK_CHANGE_FATAL, 3099 3100 //DL TX Correctable Accumulated Counts 3101 NVSWITCH_NVLINK_ERR_DL_TX_LINK_REPLAY_EVENTS_CORR, 3102 3103 //DL NA Fatal Counts 3104 NVSWITCH_NVLINK_ERR_DL_LTSSM_FAULT_UP_FATAL, 3105 NVSWITCH_NVLINK_ERR_DL_LTSSM_FAULT_DOWN_FATAL, 3106 3107 //DL NA Correctable Accumulated Counts 3108 NVSWITCH_NVLINK_ERR_DL_LINK_RECOVERY_EVENTS_CORR, 3109 3110 //TLC RX Fatal Counts 3111 NVSWITCH_NVLINK_ERR_TLC_RX_DL_HDR_PARITY_ERR_FATAL = 2000, 3112 NVSWITCH_NVLINK_ERR_TLC_RX_DL_DATA_PARITY_ERR_FATAL, 3113 NVSWITCH_NVLINK_ERR_TLC_RX_DL_CTRL_PARITY_ERR_FATAL, 3114 NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_AE_FATAL, 3115 NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_BE_FATAL, 3116 NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_ADDR_ALIGN_FATAL, 3117 NVSWITCH_NVLINK_ERR_TLC_RX_PKTLEN_ERR_FATAL, 3118 NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_PACKET_STATUS_ERR_FATAL, 3119 NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_CACHE_ATTR_PROBE_REQ_ERR_FATAL, 3120 NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_CACHE_ATTR_PROBE_RSP_ERR_FATAL, 3121 NVSWITCH_NVLINK_ERR_TLC_RX_DATLEN_GT_RMW_REQ_MAX_ERR_FATAL, 3122 NVSWITCH_NVLINK_ERR_TLC_RX_DATLEN_LT_ATR_RSP_MIN_ERR_FATAL, 3123 NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_CR_FATAL, 3124 NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_COLLAPSED_RESPONSE_FATAL, 3125 NVSWITCH_NVLINK_ERR_TLC_RX_HDR_OVERFLOW_FATAL, 3126 NVSWITCH_NVLINK_ERR_TLC_RX_DATA_OVERFLOW_FATAL, 3127 NVSWITCH_NVLINK_ERR_TLC_RX_STOMP_DETECTED_FATAL, 3128 NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_CMD_ENC_FATAL, 3129 NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_DAT_LEN_ENC_FATAL, 3130 NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_PO_FOR_CACHE_ATTR_FATAL, 3131 3132 //TLC RX Non-Fatal Counts 3133 NVSWITCH_NVLINK_ERR_TLC_RX_RSP_STATUS_HW_ERR_NONFATAL, 3134 NVSWITCH_NVLINK_ERR_TLC_RX_RSP_STATUS_UR_ERR_NONFATAL, 3135 NVSWITCH_NVLINK_ERR_TLC_RX_RSP_STATUS_PRIV_ERR_NONFATAL, 3136 NVSWITCH_NVLINK_ERR_TLC_RX_POISON_NONFATAL, 3137 NVSWITCH_NVLINK_ERR_TLC_RX_AN1_HEARTBEAT_TIMEOUT_NONFATAL, 3138 NVSWITCH_NVLINK_ERR_TLC_RX_ILLEGAL_PRI_WRITE_NONFATAL, 3139 3140 //TLC RX Fatal Counts addendum 3141 NVSWITCH_NVLINK_ERR_TLC_RX_HDR_RAM_ECC_DBE_FATAL, 3142 NVSWITCH_NVLINK_ERR_TLC_RX_DAT0_RAM_ECC_DBE_FATAL, 3143 NVSWITCH_NVLINK_ERR_TLC_RX_DAT1_RAM_ECC_DBE_FATAL, 3144 3145 //TLC TX Fatal Counts 3146 NVSWITCH_NVLINK_ERR_TLC_TX_DL_CREDIT_PARITY_ERR_FATAL, 3147 NVSWITCH_NVLINK_ERR_TLC_TX_NCISOC_HDR_ECC_DBE_FATAL, 3148 NVSWITCH_NVLINK_ERR_TLC_TX_NCISOC_PARITY_ERR_FATAL, 3149 3150 //TLC TX Non-Fatal Counts 3151 NVSWITCH_NVLINK_ERR_TLC_TX_ILLEGAL_PRI_WRITE_NONFATAL, 3152 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC0_NONFATAL, 3153 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC1_NONFATAL, 3154 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC2_NONFATAL, 3155 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC3_NONFATAL, 3156 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC4_NONFATAL, 3157 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC5_NONFATAL, 3158 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC6_NONFATAL, 3159 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC7_NONFATAL, 3160 NVSWITCH_NVLINK_ERR_TLC_TX_POISON_NONFATAL, 3161 NVSWITCH_NVLINK_ERR_TLC_TX_RSP_STATUS_HW_ERR_NONFATAL, 3162 NVSWITCH_NVLINK_ERR_TLC_TX_RSP_STATUS_UR_ERR_NONFATAL, 3163 NVSWITCH_NVLINK_ERR_TLC_TX_RSP_STATUS_PRIV_ERR_NONFATAL, 3164 NVSWITCH_NVLINK_ERR_TLC_TX_CREQ_DAT_RAM_ECC_DBE_NONFATAL, 3165 NVSWITCH_NVLINK_ERR_TLC_TX_RSP_DAT_RAM_ECC_DBE_NONFATAL, 3166 NVSWITCH_NVLINK_ERR_TLC_TX_COM_DAT_RAM_ECC_DBE_NONFATAL, 3167 NVSWITCH_NVLINK_ERR_TLC_TX_RSP1_DAT_RAM_ECC_DBE_FATAL, 3168 3169 //NVLIPT Fatal Counts 3170 NVSWITCH_NVLINK_ERR_NVLIPT_SLEEP_WHILE_ACTIVE_LINK_FATAL = 3000, 3171 NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_PHYCTL_TIMEOUT_FATAL, 3172 NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_CLKCTL_TIMEOUT_FATAL, 3173 NVSWITCH_NVLINK_ERR_NVLIPT_CLKCTL_ILLEGAL_REQUEST_FATAL, 3174 NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_PLL_TIMEOUT_FATAL, 3175 NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_PHYARB_TIMEOUT_FATAL, 3176 3177 //NVLIPT Non-Fatal Counts 3178 NVSWITCH_NVLINK_ERR_NVLIPT_ILLEGAL_LINK_STATE_REQUEST_NONFATAL, 3179 NVSWITCH_NVLINK_ERR_NVLIPT_FAILED_MINION_REQUEST_NONFATAL, 3180 NVSWITCH_NVLINK_ERR_NVLIPT_RESERVED_REQUEST_VALUE_NONFATAL, 3181 NVSWITCH_NVLINK_ERR_NVLIPT_LINK_STATE_WRITE_WHILE_BUSY_NONFATAL, 3182 NVSWITCH_NVLINK_ERR_NVLIPT_WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL, 3183 NVSWITCH_NVLINK_ERR_NVLIPT_LINK_STATE_REQUEST_TIMEOUT_NONFATAL, 3184 } NVSWITCH_NVLINK_ERROR_TYPE; 3185 3186 typedef struct 3187 { 3188 NvU8 instance; 3189 NvU32 error; //NVSWITCH_NVLINK_ERROR_TYPE 3190 NvU32 timeStamp; 3191 NvU64 count; 3192 } NVSWITCH_NVLINK_ERROR_ENTRY; 3193 3194 /* 3195 * CTRL_NVSWITCH_GET_NVLINK_ERROR_COUNTS 3196 * 3197 * Control to get the NVLINK errors from inforom cache 3198 * 3199 * Parameters: 3200 * errorIndex [IN/OUT] 3201 * On input: The index of the first NVLink error to retrieve from inforom cache 3202 * On output: The index of the first error to retrieve after the previous call. 3203 * errorCount [OUT] 3204 * Number of errors returned by the call. Currently, errorCount is limited 3205 * by NVSWITCH_NVLINK_ERROR_READ_SIZE. In order to query all the errors, a 3206 * client needs to keep calling the control till errorCount is zero. 3207 * errorLog[] [OUT] 3208 * NVLINK error array 3209 */ 3210 3211 typedef struct 3212 { 3213 NvU32 errorIndex; 3214 NvU32 errorCount; 3215 NVSWITCH_NVLINK_ERROR_ENTRY errorLog[NVSWITCH_NVLINK_ERROR_READ_SIZE]; 3216 } NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS; 3217 3218 #define NVSWITCH_ECC_ERRORS_MAX_READ_COUNT 128 3219 3220 typedef struct 3221 { 3222 NvU32 sxid; 3223 NvU8 linkId; 3224 NvU32 lastErrorTimestamp; 3225 NvBool bAddressValid; 3226 NvU32 address; 3227 NvU32 correctedCount; 3228 NvU32 uncorrectedCount; 3229 } NVSWITCH_ECC_ERROR_ENTRY; 3230 3231 /* 3232 * CTRL_NVSWITCH_GET_ECC_ERROR_COUNTS 3233 * 3234 * Control to get the ECC error counts and logs from inforom 3235 * 3236 * Parameters: 3237 * uncorrectedTotal [out] 3238 * uncorrected ECC errors count 3239 * correctedTotal [out] 3240 * corrected ECC errors count 3241 * errorCount [out] 3242 * recorded error log count in the array 3243 * errorLog[] [OUT] 3244 * ECC errors array 3245 */ 3246 3247 typedef struct 3248 { 3249 NvU64 uncorrectedTotal; 3250 NvU64 correctedTotal; 3251 NvU32 errorCount; 3252 NVSWITCH_ECC_ERROR_ENTRY errorLog[NVSWITCH_ECC_ERRORS_MAX_READ_COUNT]; 3253 } NVSWITCH_GET_ECC_ERROR_COUNTS_PARAMS; 3254 3255 #define NVSWITCH_SXID_ENTRIES_NUM 10 3256 3257 typedef struct 3258 { 3259 NvU32 sxid; 3260 NvU32 timestamp; 3261 } NVSWITCH_SXID_ENTRY; 3262 3263 /* 3264 * CTRL_NVSWITCH_GET_SXIDS 3265 * 3266 * Control to get the NVSwitch SXID errors from inforom cache 3267 * 3268 * Parameters: 3269 * sxidCount [OUT] 3270 * The total SXID error number 3271 * sxidFirst [OUT] 3272 * The array of the first NVSWITCH_SXID_ENTRIES_NUM (10) SXIDs 3273 * sxidLast [OUT] 3274 * The array of the last NVSWITCH_SXID_ENTRIES_NUM (10) SXIDs 3275 */ 3276 3277 typedef struct 3278 { 3279 NvU32 sxidCount; 3280 NVSWITCH_SXID_ENTRY sxidFirst[NVSWITCH_SXID_ENTRIES_NUM]; 3281 NVSWITCH_SXID_ENTRY sxidLast[NVSWITCH_SXID_ENTRIES_NUM]; 3282 } NVSWITCH_GET_SXIDS_PARAMS; 3283 3284 /* 3285 * CTRL_NVSWITCH_GET_SYS_INFO 3286 * 3287 * Control to get the NVSwitch system version information from inforom cache 3288 * 3289 * Parameters: 3290 * driverLo [OUT] 3291 * The driver version low 32 bits. Example: driverLo = 54531 (Driver 545.31) 3292 * driverHi [OUT] 3293 * The driver version high 16 bits 3294 * vbiosVersion [OUT] 3295 * The vbios version number. Example: vbiosVersion=0x96104100 (release 96.10.41.00) 3296 * vbiosVersionOem [OUT] 3297 * The vbios OEM version byte. 3298 * osType [OUT] 3299 * The OS type. Example: osType=0x05 (UNIX) 3300 * osVersion [OUT] 3301 * The OS version number. [BUILD[31:16]|MINOR[15:8]|MAJOR[7:0]] 3302 */ 3303 3304 typedef struct 3305 { 3306 NvU32 driverLo; 3307 NvU16 driverHi; 3308 NvU32 vbiosVersion; 3309 NvU8 vbiosVersionOem; 3310 NvU8 osType; 3311 NvU32 osVersion; 3312 } NVSWITCH_GET_SYS_INFO_PARAMS; 3313 3314 /* 3315 * CTRL_NVSWITCH_GET_TIME_INFO 3316 * 3317 * Control to get the NVSwitch time information from inforom cache 3318 * 3319 * Parameters: 3320 * timeStart [OUT] 3321 * The timestamp (EPOCH) when driver load onto the NVSwitch for the 1st time 3322 * timeEnd [OUT] 3323 * The timestamp (EPOCH) when the data was last flushed 3324 * timeRun [OUT] 3325 * The amount of time (in seconds) driver was loaded/running 3326 * time24Hours [OUT] 3327 * The timestamp (EPOCH) when the first 24 operational hours is hit 3328 * time100Hours [OUT] 3329 * The timestamp (EPOCH) when the first 100 operational hours is hit 3330 */ 3331 3332 typedef struct 3333 { 3334 NvU32 timeStart; 3335 NvU32 timeEnd; 3336 NvU32 timeRun; 3337 NvU32 time24Hours; 3338 NvU32 time100Hours; 3339 } NVSWITCH_GET_TIME_INFO_PARAMS; 3340 3341 #define NVSWITCH_TEMP_DAY_ENTRIES 5 3342 #define NVSWITCH_TEMP_WEEK_ENTRIES 5 3343 #define NVSWITCH_TEMP_MNT_ENTRIES 5 3344 #define NVSWITCH_TEMP_ALL_ENTRIES 5 3345 #define NVSWITCH_TEMP_SUM_HOUR_ENTRIES 23 3346 #define NVSWITCH_TEMP_SUM_DAY_ENTRIES 5 3347 #define NVSWITCH_TEMP_SUM_MNT_ENTRIES 3 3348 #define NVSWITCH_TEMP_HISTOGRAM_THLD_ENTRIES 20 3349 #define NVSWITCH_TEMP_HISTOGRAM_TIME_ENTRIES 21 3350 #define NVSWITCH_TEMP_HOURLY_MAX_ENTRIES 168 3351 3352 /* 3353 * NVSWITCH_TEMP_ENTRY 3354 * 3355 * This structure represents the NVSwitch TEMP with its timestamp. 3356 * 3357 * value 3358 * This parameter specifies the NVSwitch Temperature 3359 * (SFXP 9.7 format in Celsius). 3360 * 3361 * timestamp 3362 * This parameter specifies the timestamp (EPOCH) of the entry. 3363 */ 3364 typedef struct 3365 { 3366 NvU16 value; 3367 NvU32 timestamp; 3368 } NVSWITCH_TEMP_ENTRY; 3369 3370 /* 3371 * CTRL_NVSWITCH_GET_TEMP_DATA 3372 * 3373 * Control to get the NVSwitch device historical temperature information from inforom cache 3374 * 3375 * Parameters: 3376 * tempMaxDayIdx [OUT] 3377 * The current index to the maximum day temperature array 3378 * tempMaxDay[] [OUT] 3379 * The maximum temperature array for last NVSWITCH_TEMP_DAY_ENTRIES days 3380 * tempMaxWeekIdx [OUT] 3381 * The current index to the maximum week temperature array 3382 * tempMaxWeek[] [OUT] 3383 * The maximum temperature array for last NVSWITCH_TEMP_WEEK_ENTRIES weeks 3384 * tempMaxMntIdx [OUT] 3385 * The current index to the maximum month temperature array 3386 * tempMaxMnt[] [OUT] 3387 * The maximum temperature array for last NVSWITCH_TEMP_MNT_ENTRIES months 3388 * tempMaxAllIdx [OUT] 3389 * The current index to the maximum temperature array 3390 * tempMaxAll[] [OUT] 3391 * The maximum temperature array for the device 3392 * tempMinDayIdx [OUT] 3393 * The current index to the minimum day temperature array 3394 * tempMinDay[] [OUT] 3395 * The minimum temperature array for last NVSWITCH_TEMP_DAY_ENTRIES days 3396 * tempMinWeekIdx [OUT] 3397 * The current index to the minimum week temperature array 3398 * tempMinWeek[] [OUT] 3399 * The minimum temperature array for last NVSWITCH_TEMP_WEEK_ENTRIES weeks 3400 * tempMinMntIdx [OUT] 3401 * The current index to the minimum month temperature array 3402 * tempMinMnt[] [OUT] 3403 * The minimum temperature array for last NVSWITCH_TEMP_MNT_ENTRIES months 3404 * tempMinAllIdx [OUT] 3405 * The current index to the minimum temperature array 3406 * tempMinAll[] [OUT] 3407 * The minimum temperature array for the device 3408 * tempSumDelta [OUT] 3409 * The total sum of temperature change in 0.1C granularity 3410 * tempSumHour[] [OUT] 3411 * The moving average of temperature per hour, for last NVSWITCH_TEMP_SUM_HOUR_ENTRIES hours 3412 * tempSumDay[] [OUT] 3413 * The moving average of temperature per day, for last NVSWITCH_TEMP_SUM_DAY_ENTRIES days 3414 * tempSumMnt[] [OUT] 3415 * The moving average of temperature per month, for last NVSWITCH_TEMP_SUM_MNT_ENTRIES months 3416 * tempHistogramThld[] [OUT] 3417 * The histogram of temperature crossing various thresholds (5/10/15/.../95/100) 3418 * tempHistogramTime[] [OUT] 3419 * The histogram of time was in various temperature ranges (0..5/5..10/.../100..) 3420 * tempHourlyMaxSample[] [OUT] 3421 * The maximum hourly temperature array for the device 3422 */ 3423 3424 typedef struct 3425 { 3426 NvU32 tempMaxDayIdx; 3427 NVSWITCH_TEMP_ENTRY tempMaxDay[NVSWITCH_TEMP_DAY_ENTRIES]; 3428 NvU32 tempMaxWeekIdx; 3429 NVSWITCH_TEMP_ENTRY tempMaxWeek[NVSWITCH_TEMP_WEEK_ENTRIES]; 3430 NvU32 tempMaxMntIdx; 3431 NVSWITCH_TEMP_ENTRY tempMaxMnt[NVSWITCH_TEMP_MNT_ENTRIES]; 3432 NvU32 tempMaxAllIdx; 3433 NVSWITCH_TEMP_ENTRY tempMaxAll[NVSWITCH_TEMP_ALL_ENTRIES]; 3434 NvU32 tempMinDayIdx; 3435 NVSWITCH_TEMP_ENTRY tempMinDay[NVSWITCH_TEMP_DAY_ENTRIES]; 3436 NvU32 tempMinWeekIdx; 3437 NVSWITCH_TEMP_ENTRY tempMinWeek[NVSWITCH_TEMP_WEEK_ENTRIES]; 3438 NvU32 tempMinMntIdx; 3439 NVSWITCH_TEMP_ENTRY tempMinMnt[NVSWITCH_TEMP_MNT_ENTRIES]; 3440 NvU32 tempMinAllIdx; 3441 NVSWITCH_TEMP_ENTRY tempMinAll[NVSWITCH_TEMP_ALL_ENTRIES]; 3442 NvU32 tempSumDelta; 3443 NvU32 tempSumHour[NVSWITCH_TEMP_SUM_HOUR_ENTRIES]; 3444 NvU32 tempSumDay[NVSWITCH_TEMP_SUM_DAY_ENTRIES]; 3445 NvU32 tempSumMnt[NVSWITCH_TEMP_SUM_MNT_ENTRIES]; 3446 NvU32 tempHistogramThld[NVSWITCH_TEMP_HISTOGRAM_THLD_ENTRIES]; 3447 NvU32 tempHistogramTime[NVSWITCH_TEMP_HISTOGRAM_TIME_ENTRIES]; 3448 NVSWITCH_TEMP_ENTRY tempHourlyMaxSample[NVSWITCH_TEMP_HOURLY_MAX_ENTRIES]; 3449 } NVSWITCH_GET_TEMP_DATA_PARAMS; 3450 3451 #define NVSWITCH_TEMP_COMPRESS_BUFFER_ENTRIES 1096 3452 #define NVSWITCH_NUM_COMPRESSION_PERIODS 8 3453 3454 /* 3455 * CTRL_NVSWITCH_GET_TEMP_DATA 3456 * 3457 * Control to get the NVSwitch device temperature information from inforom cache 3458 * 3459 * Parameters: 3460 * compressionPeriodIdx [OUT] 3461 * The current index to the sample period array 3462 * compressionPeriod[] [OUT] 3463 * The samples period array (seconds) 3464 * tempCompressionBuffer[] [OUT] 3465 * The temperature array sampling at a specific period in compressionPeriod[] 3466 */ 3467 3468 typedef struct 3469 { 3470 NvU32 compressionPeriodIdx; 3471 NvU32 compressionPeriod[NVSWITCH_NUM_COMPRESSION_PERIODS]; 3472 NVSWITCH_TEMP_ENTRY tempCompressionBuffer[NVSWITCH_TEMP_COMPRESS_BUFFER_ENTRIES]; 3473 } NVSWITCH_GET_TEMP_SAMPLES_PARAMS; 3474 3475 /* 3476 * CTRL_NVSWITCH_GET_FOM_VALUES 3477 * This command gives the FOM values to MODS 3478 * 3479 * [in] linkId 3480 * Link number on which the FOM values are requested 3481 * [out] numLanes 3482 * This field specifies the no. of lanes per link 3483 * [out] figureOfMetritValues 3484 * This field contains the FOM values per lane 3485 */ 3486 3487 typedef struct nvswitch_get_fom_values_params 3488 { 3489 NvU32 linkId; 3490 NvU8 numLanes; 3491 NvU16 figureOfMeritValues[NVSWITCH_NVLINK_MAX_LANES]; 3492 } NVSWITCH_GET_FOM_VALUES_PARAMS; 3493 3494 /* 3495 * CTRL_NVSWITCH_SET_RESIDENCY_BINS 3496 * 3497 * Control for setting residency bins. 3498 * 3499 * Parameters: 3500 * [in] table_select 3501 * Which table to return. 3502 * [in] NVSWITCH_RESIDENCY_BIN 3503 * Residency thresholds. The thresholds would be only applied to the 3504 * enabled ports. 3505 * NVSWITCH_GET_INFO can be used to query enabled ports. 3506 */ 3507 3508 typedef struct nvswitch_residency_bin 3509 { 3510 NvU32 lowThreshold; /* in nsec */ 3511 NvU32 hiThreshold; /* in nsec */ 3512 3513 } NVSWITCH_RESIDENCY_THRESHOLDS; 3514 3515 #define NVSWITCH_TABLE_SELECT_MULTICAST 0 3516 #define NVSWITCH_TABLE_SELECT_REDUCTION 1 3517 3518 typedef struct nvswitch_set_residency_bins 3519 { 3520 NvU32 table_select; // NVSWITCH_TABLE_SELECT_MULTICAST/_REDUCTION 3521 NVSWITCH_RESIDENCY_THRESHOLDS bin; 3522 3523 } NVSWITCH_SET_RESIDENCY_BINS; 3524 3525 /* 3526 * CTRL_NVSWITCH_GET_RESIDENCY_BINS 3527 * 3528 * Control for querying multicast & reduction residency histogram. 3529 * 3530 * Parameters: 3531 * [in] linkId 3532 * Link number on which the residency histogram is requested 3533 * [in] table_select 3534 * Which table to return. 3535 * 3536 * [in] bin 3537 * Residency thresholds. 3538 * [out] residency 3539 * Residency data/histogram format. The data will be available for the 3540 * enabled/supported ports returned by NVSWITCH_GET_INFO. 3541 */ 3542 3543 typedef struct nvswitch_residency_bins 3544 { 3545 NV_DECLARE_ALIGNED(NvU64 low, 8); 3546 NV_DECLARE_ALIGNED(NvU64 medium, 8); 3547 NV_DECLARE_ALIGNED(NvU64 high, 8); 3548 } NVSWITCH_RESIDENCY_BINS; 3549 3550 #define NVSWITCH_RESIDENCY_SIZE 128 3551 3552 typedef struct nvswitch_get_residency_bins 3553 { 3554 NvU32 link; 3555 NvU32 table_select; // NVSWITCH_TABLE_SELECT_MULTICAST/_REDUCTION 3556 NVSWITCH_RESIDENCY_THRESHOLDS bin; 3557 NVSWITCH_RESIDENCY_BINS residency[NVSWITCH_RESIDENCY_SIZE]; 3558 } NVSWITCH_GET_RESIDENCY_BINS; 3559 3560 /* 3561 * CTRL_NVSWITCH_GET_RB_STALL_BUSY 3562 * 3563 * Control for querying reduction buffer stall/busy counters. 3564 * 3565 * Parameters: 3566 * [in] linkId 3567 * Link number on which the stall/busy counters are requested 3568 * [in] table_select 3569 * Which table to return. 3570 * 3571 * [out] stall_busy 3572 * Reduction buffer stall/busy counters. The data will be available for the 3573 * enabled/supported ports returned by NVSWITCH_GET_INFO. 3574 */ 3575 3576 typedef struct nvswitch_stall_busy 3577 { 3578 NV_DECLARE_ALIGNED(NvU64 time, 8); // in ns 3579 NV_DECLARE_ALIGNED(NvU64 stall, 8); 3580 NV_DECLARE_ALIGNED(NvU64 busy, 8); 3581 } NVSWITCH_STALL_BUSY; 3582 3583 typedef struct nvswitch_get_rd_stall_busy 3584 { 3585 NvU32 link; 3586 NvU32 table_select; // NVSWITCH_TABLE_SELECT_MULTICAST/_REDUCTION 3587 NVSWITCH_STALL_BUSY vc0; 3588 NVSWITCH_STALL_BUSY vc1; 3589 } NVSWITCH_GET_RB_STALL_BUSY; 3590 3591 /* 3592 * CTRL_NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR 3593 * 3594 * Control for querying multicast ID error vector 3595 * 3596 * Parameters: 3597 * [in] link 3598 * Link number on which the error vector is requested 3599 * 3600 * [out] error_vector[] 3601 * Bit vector of multicast IDs that are in error. 3602 */ 3603 3604 #define NVSWITCH_MC_ID_ERROR_VECTOR_COUNT 128 3605 3606 typedef struct nvswitch_get_multicast_id_error_vector 3607 { 3608 NvU32 link; 3609 NvU32 error_vector[NVSWITCH_MC_ID_ERROR_VECTOR_COUNT / 32]; 3610 } NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR; 3611 3612 /* 3613 * CTRL_NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR 3614 * 3615 * Control for clearing multicast ID error vector 3616 * 3617 * Parameters: 3618 * [in] link 3619 * Link number on which the error vector clear is requested 3620 * 3621 * [in] error_vector[] 3622 * Bit vector of multicast IDs to clear error. 3623 */ 3624 3625 typedef struct nvswitch_clear_multicast_id_error_vector 3626 { 3627 NvU32 link; 3628 NvU32 error_vector[NVSWITCH_MC_ID_ERROR_VECTOR_COUNT / 32]; 3629 } NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR; 3630 3631 /* 3632 * NVSWITCH_NVLINK_ERR_INFO 3633 * Error information per link 3634 * 3635 * Parameters: 3636 * TLErrlog 3637 * Returns the error mask for NVLINK TL errors 3638 * Used in Pascal 3639 * 3640 * TLIntrEn 3641 * Returns the intr enable mask for NVLINK TL errors 3642 * Used in Pascal 3643 * 3644 * TLCTxErrStatus0 3645 * Returns the TLC Tx Error Mask 0 3646 * Used in Volta 3647 * 3648 * TLCRxErrStatus0 3649 * Returns the TLC Rx Error Mask 0 3650 * Used in Volta 3651 * 3652 * TLCRxErrStatus1 3653 * Returns the TLC Rx Error Mask 1 3654 * Used in Volta 3655 * 3656 * TLCTxErrLogEn0 3657 * Returns the TLC Tx Error Log En 0 3658 * Used in Volta 3659 * 3660 * TLCRxErrLogEn0 3661 * Returns the TLC Rx Error Log En 0 3662 * Used in Volta 3663 * 3664 * TLCRxErrLogEn1 3665 * Returns the TLC Rx Error Log En 1 3666 * Used in Volta 3667 * 3668 * MIFTxErrStatus0 3669 * Returns the MIF Rx Error Mask 0 3670 * Used in Volta 3671 * 3672 * MIFRxErrStatus0 3673 * Returns the MIF Tx Error Mask 0 3674 * Used in Volta 3675 * 3676 * DLSpeedStatusTx 3677 * Returns the NVLINK DL speed status for sublink Tx 3678 * 3679 * DLSpeedStatusRx 3680 * Returns the NVLINK DL speed status for sublink Rx 3681 * 3682 * bExcessErrorDL 3683 * Returns true for excessive error rate interrupt from DL 3684 */ 3685 typedef struct 3686 { 3687 NvU32 TLErrlog; 3688 NvU32 TLIntrEn; 3689 NvU32 TLCTxErrStatus0; 3690 NvU32 TLCRxErrStatus0; 3691 NvU32 TLCRxErrStatus1; 3692 NvU32 TLCTxErrLogEn0; 3693 NvU32 TLCRxErrLogEn0; 3694 NvU32 TLCRxErrLogEn1; 3695 NvU32 MIFTxErrStatus0; 3696 NvU32 MIFRxErrStatus0; 3697 NvU32 DLSpeedStatusTx; 3698 NvU32 DLSpeedStatusRx; 3699 NvBool bExcessErrorDL; 3700 } NVSWITCH_NVLINK_ERR_INFO; 3701 3702 /* 3703 * CTRL_NVSWITCH_GET_ERR_INFO 3704 * This command is used to query the NVLINK error information 3705 * 3706 * Possible status values returned are: 3707 * NV_OK 3708 * NV_ERR_NOT_SUPPORTED 3709 */ 3710 3711 /* 3712 * NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS 3713 * 3714 * linkMask 3715 * Returns the mask of links enabled 3716 * 3717 * linkErrInfo 3718 * Returns the error information for all the links 3719 */ 3720 typedef struct 3721 { 3722 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 3723 NVSWITCH_NVLINK_ERR_INFO linkErrInfo[NVSWITCH_NVLINK_MAX_LINKS]; 3724 } NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS; 3725 3726 #define NVSWITCH_INBAND_DATA_SIZE 5120 3727 3728 /* 3729 * CTRL_NVSWITCH_INBAND_SEND_DATA 3730 * 3731 * Control call used for sending data over inband. 3732 * 3733 * Parameters: 3734 * 3735 * dataSize[IN] 3736 * Valid data in the buffer 3737 * 3738 * linkId[IN] 3739 * Link number on which the data needs to be sent 3740 * 3741 * buffer[IN] 3742 * Data which needs to be sent on the other side 3743 * 3744 * dataSent [OUT] 3745 * Bytes of data which were sent to the other side 3746 */ 3747 typedef struct nvswitch_inband_send_data_params 3748 { 3749 /* input parameters */ 3750 NvU32 dataSize; 3751 NvU32 linkId; 3752 NvU8 buffer[NVSWITCH_INBAND_DATA_SIZE]; 3753 3754 /* output parameters */ 3755 NvU32 dataSent; 3756 } NVSWITCH_INBAND_SEND_DATA_PARAMS; 3757 3758 /* 3759 * CTRL_NVSWITCH_INBAND_READ_DATA 3760 * 3761 * Control call used for reading data received over inband 3762 * 3763 * Parameters: 3764 * 3765 * linkId[IN] 3766 * Link number on which the data needs to be read. 3767 * 3768 * dataSize[OUT] 3769 * Valid data in the buffer 3770 * 3771 * buffer[OUT] 3772 * Data which needs to be read from the other side 3773 */ 3774 typedef struct nvswitch_inband_read_data_params 3775 { 3776 /* input parameters */ 3777 NvU32 linkId; 3778 3779 /* output parameters */ 3780 NvU32 dataSize; 3781 NvU8 buffer[NVSWITCH_INBAND_DATA_SIZE]; 3782 } NVSWITCH_INBAND_READ_DATA_PARAMS; 3783 3784 /* 3785 * CTRL_NVSWITCH_INBAND_FLUSH_DATA 3786 * 3787 * Flushing all the pending data for the corresponding link. 3788 * Messages would be stored in a queue. If flush is send all the 3789 * pending messages which are there for that linkId will be deleted. 3790 * 3791 * Parameters: 3792 * 3793 * linkMask[IN] 3794 * Mask of Links on which the data needs to be flushed. 3795 */ 3796 typedef struct nvswitch_inband_flush_data_params 3797 { 3798 /* input parameters */ 3799 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 3800 3801 /* output parameters */ 3802 } NVSWITCH_INBAND_FLUSH_DATA_PARAMS; 3803 3804 /* 3805 * CTRL_NVSWITCH_INBAND_PENDING_DATA_STATS 3806 * 3807 * Control call to check which links have pending data 3808 * 3809 * Parameters: 3810 * 3811 * linkMask[OUT] 3812 * Mask of the links which has data on it. 3813 */ 3814 typedef struct nvswitch_inband_pending_data_stats_params 3815 { 3816 /* output parameters */ 3817 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 3818 } NVSWITCH_INBAND_PENDING_DATA_STATS_PARAMS; 3819 3820 /* 3821 * CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 3822 * 3823 * Control for querying the board part number 3824 * 3825 * Parameters: 3826 * [out] data[] 3827 * Byte vector of the board part number. 3828 */ 3829 3830 #define NVSWITCH_BOARD_PART_NUMBER_SIZE_IN_BYTES 20 3831 3832 typedef struct nvswitch_get_board_part_number_vector 3833 { 3834 NvU8 data[NVSWITCH_BOARD_PART_NUMBER_SIZE_IN_BYTES]; 3835 } NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR; 3836 3837 #define NVSWITCH_GET_SW_INFO_COUNT_MAX 32 3838 3839 typedef enum nvswitch_get_sw_info_index 3840 { 3841 NVSWITCH_GET_SW_INFO_INDEX_INFOROM_NVL_SUPPORTED = 0x0, 3842 NVSWITCH_GET_SW_INFO_INDEX_INFOROM_BBX_SUPPORTED 3843 } NVSWITCH_GET_SW_INFO_INDEX; 3844 3845 typedef struct nvswitch_get_sw_info_params 3846 { 3847 NvU32 count; 3848 NvU32 index[NVSWITCH_GET_SW_INFO_COUNT_MAX]; 3849 NvU32 info[NVSWITCH_GET_SW_INFO_COUNT_MAX]; 3850 } NVSWITCH_GET_SW_INFO_PARAMS; 3851 3852 /* 3853 * CTRL_NVSWITCH_CLEAR_COUNTERS 3854 * This command clears/resets the counters for the specified types. 3855 * 3856 * [in] linkMask 3857 * This parameter specifies for which links we want to clear the 3858 * counters. 3859 * 3860 * [in] counterMask 3861 * This parameter specifies the input mask for desired counters to be 3862 * cleared. Note that all counters cannot be cleared. 3863 * 3864 * NOTE: Bug# 2098529: On Turing all DL errors and LP counters are cleared 3865 * together. They cannot be cleared individually per error type. RM 3866 * would possibly move to a new API on Ampere and beyond 3867 */ 3868 3869 typedef struct 3870 { 3871 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 3872 NvU32 counterMask; 3873 } NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS; 3874 3875 /* 3876 * NVSWITCH_CTRL_I2C_DEVICE_INFO 3877 * 3878 * This structure describes the basic I2C Device information. 3879 * 3880 * type 3881 * This field return the type of device NVSWITCH_I2C_DEVICE_<xyz> 3882 * i2cAddress 3883 * This field contains the 7 bit/10 bit address of the I2C device. 3884 * i2cLogicalPort 3885 * This field contains the Logical port of the I2C device. 3886 */ 3887 3888 typedef enum 3889 { 3890 NVSWITCH_I2C_PORT_I2CA = 0, 3891 NVSWITCH_I2C_PORT_I2CB, 3892 NVSWITCH_I2C_PORT_I2CC, 3893 NVSWITCH_I2C_PORT_I2CD 3894 } NVSWITCH_I2C_PORT_TYPE; 3895 3896 typedef enum 3897 { 3898 NVSWITCH_I2C_DEVICE_UNKNOWN = 0, 3899 3900 // OSFP Devices 3901 NVSWITCH_I2C_DEVICE_CMIS4_MODULE = 0xB0, 3902 NVSWITCH_I2C_DEVICE_CMIS4_MUX_PCA9847 = 0xB1, 3903 3904 NVSWITCH_I2C_DEVICE_SKIP = 0xFF 3905 3906 } NVSWITCH_I2C_DEVICE_TYPE; 3907 3908 typedef struct 3909 { 3910 NVSWITCH_I2C_DEVICE_TYPE type; 3911 NvU32 i2cAddress; 3912 NVSWITCH_I2C_PORT_TYPE i2cPortLogical; 3913 } NVSWITCH_CTRL_I2C_DEVICE_INFO; 3914 3915 /* Maximum number of I2C devices in DCB */ 3916 #define NVSWITCH_CTRL_I2C_MAX_DEVICES 32 3917 3918 /* 3919 * CTRL_NVSWITCH_I2C_TABLE_GET_DEV_INFO 3920 * 3921 * RM Control to get I2C device info from the DCB I2C Devices Table. 3922 * 3923 * i2cDevCount 3924 * The value of this parameter will give the number of valid 3925 * I2C devices returned in structure. 3926 * 3927 * i2cDevInfo[] 3928 * For each device the control call will report the device info 3929 * 3930 */ 3931 typedef struct 3932 { 3933 NvU8 i2cDevCount; 3934 NVSWITCH_CTRL_I2C_DEVICE_INFO i2cDevInfo[NVSWITCH_CTRL_I2C_MAX_DEVICES]; 3935 } NVSWITCH_CTRL_I2C_GET_DEV_INFO_PARAMS; 3936 3937 //! Maximum size of index. 3938 #define NVSWITCH_CTRL_I2C_INDEX_LENGTH_MAX 4 3939 3940 /*! Set if the command should begin with a START. For a transactional 3941 * interface (highly recommended), this should always be _SEND. 3942 */ 3943 #define NVSWITCH_CTRL_I2C_FLAGS_START 0:0 3944 #define NVSWITCH_CTRL_I2C_FLAGS_START_NONE 0 3945 #define NVSWITCH_CTRL_I2C_FLAGS_START_SEND 1 3946 3947 /*! 3948 * Indicate whether to send a repeated start between the index and 3949 * message phrases. 3950 * 3951 * This flag will send a restart between each index and message. This should 3952 * be set for reads, but rarely (if ever) for writes. 3953 * 3954 * A RESTART is required when switching directions; this is called a combined 3955 * format. These are typically used in indexed read commands, where an index 3956 * is written to the device to indicate what register(s) to read, and then 3957 * the register is read. Almost always, indexed writes do not require a 3958 * restart, though some devices will accept them. However, this flag should 3959 * be used for writes in the rare case where a restart should be sent between 3960 * the last index and the message. 3961 */ 3962 #define NVSWITCH_CTRL_I2C_FLAGS_RESTART 1:1 3963 #define NVSWITCH_CTRL_I2C_FLAGS_RESTART_NONE 0 3964 #define NVSWITCH_CTRL_I2C_FLAGS_RESTART_SEND 1 3965 3966 /*! Set if the command should conclude with a STOP. For a transactional 3967 * interface (highly recommended), this should always be _SEND. 3968 */ 3969 #define NVSWITCH_CTRL_I2C_FLAGS_STOP 2:2 3970 #define NVSWITCH_CTRL_I2C_FLAGS_STOP_NONE 0 3971 #define NVSWITCH_CTRL_I2C_FLAGS_STOP_SEND 1 3972 3973 /*! The slave addressing mode: 7-bit (most common) or 10-bit. It is possible 3974 * but not recommended to send no address at all using _NONE. 3975 */ 3976 #define NVSWITCH_CTRL_I2C_FLAGS_ADDRESS_MODE 4:3 3977 #define NVSWITCH_CTRL_I2C_FLAGS_ADDRESS_MODE_NO_ADDRESS 0 3978 #define NVSWITCH_CTRL_I2C_FLAGS_ADDRESS_MODE_7BIT 1 3979 #define NVSWITCH_CTRL_I2C_FLAGS_ADDRESS_MODE_10BIT 2 3980 3981 //! The length of the index. If length is 0, no index will be sent. 3982 #define NVSWITCH_CTRL_I2C_FLAGS_INDEX_LENGTH 7:5 3983 #define NVSWITCH_CTRL_I2C_FLAGS_INDEX_LENGTH_ZERO 0 3984 #define NVSWITCH_CTRL_I2C_FLAGS_INDEX_LENGTH_ONE 1 3985 #define NVSWITCH_CTRL_I2C_FLAGS_INDEX_LENGTH_TWO 2 3986 #define NVSWITCH_CTRL_I2C_FLAGS_INDEX_LENGTH_THREE 3 3987 #define NVSWITCH_CTRL_I2C_FLAGS_INDEX_LENGTH_MAXIMUM NVSWITCH_CTRL_I2C_INDEX_LENGTH_MAX 3988 3989 /*! The flavor to use: software bit-bang or hardware controller. The hardware 3990 * controller is faster, but is not necessarily available or capable. 3991 */ 3992 #define NVSWITCH_CTRL_I2C_FLAGS_FLAVOR 8:8 3993 #define NVSWITCH_CTRL_I2C_FLAGS_FLAVOR_HW 0 3994 #define NVSWITCH_CTRL_I2C_FLAGS_FLAVOR_SW 1 3995 3996 /*! The target speed at which to drive the transaction at. 3997 * 3998 * Note: The lib reserves the right to lower the speed mode if the I2C master 3999 * implementation cannot handle the speed given. 4000 */ 4001 #define NVSWITCH_CTRL_I2C_FLAGS_SPEED_MODE 11:9 4002 #define NVSWITCH_CTRL_I2C_FLAGS_SPEED_MODE_DEFAULT 0x00000000 4003 #define NVSWITCH_CTRL_I2C_FLAGS_SPEED_MODE_100KHZ 0x00000003 4004 #define NVSWITCH_CTRL_I2C_FLAGS_SPEED_MODE_200KHZ 0x00000004 4005 #define NVSWITCH_CTRL_I2C_FLAGS_SPEED_MODE_300KHZ 0x00000005 4006 #define NVSWITCH_CTRL_I2C_FLAGS_SPEED_MODE_400KHZ 0x00000006 4007 #define NVSWITCH_CTRL_I2C_FLAGS_SPEED_MODE_1000KHZ 0x00000007 4008 4009 /* 4010 * NVSWITCH_CTRL_I2C_FLAGS_TRANSACTION_MODE 4011 * A client uses this field to specify a transaction mode. 4012 * Possible values are: 4013 * NVSWITCH_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL 4014 * The default, this value indicates to use the normal I2C transaction 4015 * mode which will involve read/write operations depending on client's 4016 * needs. 4017 * NVSWITCH_CTRL_I2C_FLAGS_TRANSACTION_MODE_PING 4018 * This value specifies that the device only needs to be pinged. No need 4019 * of performing a complete read/write transaction. This will address 4020 * the device to be pinged but not send any data. On receiving an ACK, 4021 * we will get a confirmation on the device's availability. 4022 * PING requires that: 4023 * _START = _SEND 4024 * _RESTART = _NONE 4025 * _STOP = _SEND 4026 * _ADDRESS_MODE != _NO_ADDRESS 4027 * _INDEX_LENGTH = _ZERO 4028 * messageLength = 0 4029 */ 4030 #define NVSWITCH_CTRL_I2C_FLAGS_TRANSACTION_MODE 12:12 4031 #define NVSWITCH_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL (0x00000000) 4032 #define NVSWITCH_CTRL_I2C_FLAGS_TRANSACTION_MODE_PING (0x00000001) 4033 4034 /*! 4035 * Block Reads/Writes: There are two different protocols for reading/writing >2 4036 * byte sets of data to/from a slave device. The SMBus specification section 4037 * 5.5.7 defines "Block Reads/Writes" in which the first byte of the payload 4038 * specifies the size of the data to be read/written s.t. payload_size = 4039 * data_size + 1. However, many other devices depend on the master to already 4040 * know the size of the data being accessed (i.e. SW written with knowledge of 4041 * the device's I2C register spec) and skip this overhead. This second behavior 4042 * is actually the default behavior of all the lib's I2C interfaces. 4043 * 4044 * Setting this bit will enable the block protocol for reads and writes for size 4045 * >2. 4046 */ 4047 #define NVSWITCH_CTRL_I2C_FLAGS_BLOCK_PROTOCOL 17:17 4048 #define NVSWITCH_CTRL_I2C_FLAGS_BLOCK_PROTOCOL_DISABLED 0x00000000 4049 #define NVSWITCH_CTRL_I2C_FLAGS_BLOCK_PROTOCOL_ENABLED 0x00000001 4050 4051 /*! 4052 * NVSWITCH_CTRL_I2C_FLAGS_RESERVED 4053 * A client must leave this field as 0, as it is reserved for future use. 4054 */ 4055 #define NVSWITCH_CTRL_I2C_FLAGS_RESERVED 31:18 4056 4057 #define NVSWITCH_CTRL_I2C_MESSAGE_LENGTH_MAX 256 4058 4059 typedef enum 4060 { 4061 NVSWITCH_I2C_ACQUIRER_NONE = 0, 4062 NVSWITCH_I2C_ACQUIRER_UNKNOWN, 4063 NVSWITCH_I2C_ACQUIRER_IOCTL, // e.g. MODS 4064 NVSWITCH_I2C_ACQUIRER_EXTERNAL, // e.g. Linux Direct 4065 NVSWITCH_I2C_ACQUIRER_CCI_INITIALIZE, // CCI Init/Startup 4066 NVSWITCH_I2C_ACQUIRER_CCI_TRAIN, // Cable training 4067 NVSWITCH_I2C_ACQUIRER_CCI_UX, // User interface e.g. LEDs 4068 NVSWITCH_I2C_ACQUIRER_CCI_SERVICE, // e.g. ISR 4069 NVSWITCH_I2C_ACQUIRER_CCI_SMBPBI, // OOB path 4070 4071 } NVSWITCH_I2C_ACQUIRER; 4072 4073 /* 4074 * CTRL_NVSWITCH_I2C_INDEXED 4075 * 4076 * Perform a basic I2C transaction synchronously. 4077 * 4078 * portId 4079 * This field must be specified by the client to indicate the logical 4080 * port/bus for which the transaction is requested. 4081 * 4082 * bIsRead 4083 * This field must be specified by the client to indicate whether the 4084 * command is a write (FALSE) or a read (TRUE). 4085 * 4086 * flags 4087 * This parameter specifies optional flags used to control certain modal 4088 * features such as target speed and addressing mode. The currently 4089 * defined fields are described previously; see NVSWITCH_CTRL_I2C_FLAGS_*. 4090 * 4091 * acquirer 4092 * The ID of the client that is trying to take control of the I2C module. 4093 * 4094 * address 4095 * The address of the I2C slave. The address should be shifted left by 4096 * one. For example, the I2C address 0x50, often used for reading EDIDs, 4097 * would be stored here as 0xA0. This matches the position within the 4098 * byte sent by the master, as the last bit is reserved to specify the 4099 * read or write direction. 4100 * 4101 * index 4102 * This parameter, required of the client if index is one or more, 4103 * specifies the index to be written. The buffer should be arranged such 4104 * that index[0] will be the first byte sent. 4105 * 4106 * messageLength 4107 * This parameter, required of the client, specifies the number of bytes to 4108 * read or write from the slave after the index is written. 4109 * 4110 * message 4111 * This parameter, required of the client, specifies the data to be written 4112 * to the slave. The buffer should be arranged such that message[0] will 4113 * be the first byte read or written. If the transaction is a read, then 4114 * it will follow the combined format described in the I2C specification. 4115 * If the transaction is a write, the message will immediately follow the 4116 * index without a restart. 4117 * 4118 */ 4119 typedef struct 4120 { 4121 NvU8 port; 4122 NvU8 bIsRead; 4123 NvU16 address; 4124 NvU32 flags; 4125 NvU32 acquirer; 4126 4127 NvU8 index[NVSWITCH_CTRL_I2C_INDEX_LENGTH_MAX]; 4128 4129 NvU32 messageLength; 4130 NvU8 message[NVSWITCH_CTRL_I2C_MESSAGE_LENGTH_MAX]; 4131 } NVSWITCH_CTRL_I2C_INDEXED_PARAMS; 4132 4133 /* 4134 * Structure to store register values required to debug ALI training failures 4135 * 4136 * dlstatMn00 4137 * DLSTAT MN00 register value (subcode and code) 4138 * dlstatUc01 4139 * DLSTAT UC01 register value 4140 * dlstatLinkIntr 4141 * NV_MINION_NVLINK_LINK_INTR (subcode, code and state) 4142 */ 4143 typedef struct nvswitch_minion_ali_debug_registers 4144 { 4145 NvU32 dlstatMn00; 4146 NvU32 dlstatUc01; 4147 NvU32 dlstatLinkIntr; 4148 } NVSWITCH_MINION_ALI_DEBUG_REGISTERS; 4149 4150 /* 4151 * CTRL_NVSWITCH_CCI_GET_PORTS_CPLD_INFO 4152 * 4153 * Retrieve information about the Ports CPLD 4154 * 4155 * Parameters: 4156 * 4157 * versionMajor[OUT] 4158 * Major number of CPLD version 4159 * versionMinor[OUT] 4160 * Minor number of CPLD version 4161 */ 4162 typedef struct nvswitch_cci_get_ports_cpld_info_params 4163 { 4164 NvU8 versionMajor; 4165 NvU8 versionMinor; 4166 } NVSWITCH_CCI_GET_PORTS_CPLD_INFO_PARAMS; 4167 4168 #define NVSWITCH_CCI_FW_FLAGS_PRESENT 0:0 4169 #define NVSWITCH_CCI_FW_FLAGS_PRESENT_NO 0 4170 #define NVSWITCH_CCI_FW_FLAGS_PRESENT_YES 1 4171 #define NVSWITCH_CCI_FW_FLAGS_ACTIVE 1:1 4172 #define NVSWITCH_CCI_FW_FLAGS_ACTIVE_NO 0 4173 #define NVSWITCH_CCI_FW_FLAGS_ACTIVE_YES 1 4174 #define NVSWITCH_CCI_FW_FLAGS_COMMITED 2:2 4175 #define NVSWITCH_CCI_FW_FLAGS_COMMITED_NO 0 4176 #define NVSWITCH_CCI_FW_FLAGS_COMMITED_YES 1 4177 #define NVSWITCH_CCI_FW_FLAGS_EMPTY 3:3 4178 #define NVSWITCH_CCI_FW_FLAGS_EMPTY_NO 0 4179 #define NVSWITCH_CCI_FW_FLAGS_EMPTY_YES 1 4180 4181 #define NVSWITCH_CCI_FW_IMAGE_A 0x0 4182 #define NVSWITCH_CCI_FW_IMAGE_B 0x1 4183 #define NVSWITCH_CCI_FW_IMAGE_FACTORY 0x2 4184 #define NVSWITCH_CCI_FW_IMAGE_COUNT 0x3 4185 4186 /* 4187 * Structure to store FW revision parameters 4188 * 4189 * Parameters: 4190 * status 4191 * FW status flags 4192 * image 4193 * Firmware Image A/B/Factory. 4194 * major 4195 * FW major revision. 4196 * minor 4197 * FW minor revision. 4198 * build 4199 * FW build number. 4200 */ 4201 typedef struct nvswitch_cci_get_fw_revisions 4202 { 4203 NvU8 flags; 4204 NvU8 major; 4205 NvU8 minor; 4206 NvU16 build; 4207 } NVSWITCH_CCI_GET_FW_REVISIONS; 4208 4209 /* 4210 * CTRL_NVSWITCH_CCI_GET_FW_REVISIONS 4211 * 4212 * Control to get cci firmware revisions of the transreciever. 4213 * 4214 * This API is not supported on SV10. 4215 * 4216 * Parameters: 4217 * link [IN] 4218 * Link number 4219 * revisions [OUT] 4220 * Stores the CCI FW revision params 4221 */ 4222 typedef struct nvswitch_cci_get_fw_revision_params 4223 { 4224 NvU32 linkId; 4225 NVSWITCH_CCI_GET_FW_REVISIONS revisions[NVSWITCH_CCI_FW_IMAGE_COUNT]; 4226 } NVSWITCH_CCI_GET_FW_REVISION_PARAMS; 4227 4228 /* 4229 * CTRL_NVSWITCH_CCI_SET_LOCATE_LED 4230 * 4231 * Control to turn on/off the LOCATE LED on a module cage. 4232 * This command will override the current LED state. 4233 * 4234 * Parameters: 4235 * cageIndex [IN] 4236 * Target cage index (>=0 and <= 31) on the 4237 * selected ASIC device. 4238 * portNum [IN] 4239 * Target port (0 or 1) on the seleted 4240 * cage. 4241 * bSetLocateOn [IN] 4242 * Turn on/off LED. NV_TRUE == ON, NV_FALSE == OFF 4243 */ 4244 typedef struct nvswitch_cci_set_locate_led_params 4245 { 4246 NvU8 cageIndex; 4247 NvU8 portNum; 4248 NvBool bSetLocateOn; 4249 } NVSWITCH_CCI_SET_LOCATE_LED_PARAMS; 4250 4251 /* 4252 * CTRL_NVSWITCH_GET_SOE_HEARTBEAT 4253 * 4254 * Retrieve SOE Heartbeat status 4255 * 4256 * Parameters: 4257 * 4258 * timestampNs[OUT] 4259 * PTIMER timestamp of the SOE Heartbeat GPIO reading 4260 * gpioVal[OUT] 4261 * Current SOE Heartbeat GPIO value 4262 */ 4263 typedef struct nvswitch_get_soe_heartbeat_params 4264 { 4265 NvU64 timestampNs; 4266 NvU32 gpioVal; 4267 } NVSWITCH_GET_SOE_HEARTBEAT_PARAMS; 4268 4269 /* 4270 * CTRL_NVSWITCH_SET_CONTINUOUS_ALI 4271 * 4272 * Enable/disable continuous ALI for all CCI managed links. 4273 * This also enables/disables hot plug. 4274 * 4275 * Continuous ALI is enabled by default. 4276 * 4277 * Parameters: 4278 * bEnable [IN] 4279 */ 4280 4281 typedef struct 4282 { 4283 NvBool bEnable; 4284 } NVSWITCH_SET_CONTINUOUS_ALI_PARAMS; 4285 4286 /* 4287 * CTRL_NVSWITCH_REQUEST_ALI 4288 * 4289 * Request link training for links specified in the mask. 4290 * NVswitch must be in non-continuous ALI mode. Reset 4291 * and drain will always be performed along with ALI. ALI 4292 * requests for links that are currently being trained will be 4293 * dropped. This is an asynchronous request. 4294 * 4295 * Parameters: 4296 * linkMaskTrain [IN] 4297 */ 4298 4299 typedef struct 4300 { 4301 // TODO: not used, remove later 4302 NvU64 linkMaskForcedResetAndDrain; 4303 NvU64 linkMaskTrain; 4304 } NVSWITCH_REQUEST_ALI_PARAMS; 4305 4306 /* 4307 * CTRL_NVSWITCH_REGISTER_READ/WRITE 4308 * 4309 * This provides direct access to the MMIO space. 4310 */ 4311 4312 typedef struct 4313 { 4314 NvU32 engine; // REGISTER_RW_ENGINE_* 4315 NvU32 instance; // engine instance 4316 NvU32 offset; // Register offset within device/instance 4317 NvU32 val; // out: register value read 4318 } NVSWITCH_REGISTER_READ; 4319 4320 typedef struct 4321 { 4322 NvU32 engine; // REGISTER_RW_ENGINE_* 4323 NvU32 instance; // engine instance 4324 NvBool bcast; // Unicast or broadcast 4325 NvU32 offset; // Register offset within engine/instance 4326 NvU32 val; // in: register value to write 4327 } NVSWITCH_REGISTER_WRITE; 4328 4329 4330 typedef struct 4331 { 4332 NvU8 thresholdMan; 4333 NvU8 thresholdExp; 4334 NvU8 timescaleMan; 4335 NvU8 timescaleExp; 4336 NvBool bInterruptEn; 4337 NvBool bInterruptTrigerred; 4338 NvU32 flags; 4339 } NVSWITCH_NVLINK_ERROR_THRESHOLD_VALUES; 4340 4341 #define NVSWITCH_NVLINK_ERROR_THRESHOLD_RESET 0x1 4342 4343 /* 4344 * CTRL_NVSWITCH_SET_NVLINK_ERROR_THRESHOLD 4345 * 4346 * Set the Nvlink Error Rate Threshold. 4347 * 4348 * Parameters: 4349 * linkMask [IN] 4350 * A valid link mask for which we need to set the Error Threshold 4351 * 4352 * errorThreshold [IN] 4353 * Threshold values, interrupt enable/disable and flags 4354 */ 4355 4356 typedef struct 4357 { 4358 NV_DECLARE_ALIGNED(NvU64 link_mask, 8); 4359 NVSWITCH_NVLINK_ERROR_THRESHOLD_VALUES errorThreshold[NVSWITCH_NVLINK_MAX_LINKS]; 4360 } NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS; 4361 4362 /* 4363 * CTRL_NVSWITCH_GET_NVLINK_ERROR_THRESHOLD 4364 * 4365 * Control to query NVLIPT counter configuration. 4366 * 4367 * Parameters: 4368 * linkMask [IN] 4369 * A valid link mask for which we need to get the Error Threshold 4370 * 4371 * errorThreshold [OUT] 4372 * Threshold values, interrupt enable/disable and flags 4373 */ 4374 4375 typedef struct 4376 { 4377 NV_DECLARE_ALIGNED(NvU64 link_mask, 8); 4378 NVSWITCH_NVLINK_ERROR_THRESHOLD_VALUES errorThreshold[NVSWITCH_NVLINK_MAX_LINKS]; 4379 } NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS; 4380 4381 /* 4382 * CTRL_NVSWITCH_GET_NVLINK_L1_CAPABILITY 4383 * 4384 * Control to query NvLink L1 Threshold capability. 4385 * 4386 * Parameters: 4387 * linkMask [IN] 4388 * A valid link mask for which we need to get the L1 Threshold 4389 * 4390 * l1Capable [OUT] 4391 * An array of links that are capable of supporting L1 Thresholds 4392 */ 4393 typedef struct 4394 { 4395 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 4396 NvBool l1Capable[NVSWITCH_NVLINK_MAX_LINKS]; 4397 } NVSWITCH_GET_NVLINK_L1_CAPABILITY_PARAMS; 4398 4399 /* 4400 * CTRL_NVSWITCH_GET_NVLINK_L1_THRESHOLD 4401 * 4402 * Control to query NvLink L1 Thresholds. 4403 * 4404 * Parameters: 4405 * linkMask [IN] 4406 * A valid link mask for which we need to get the L1 Threshold 4407 * 4408 * l1Threshold [OUT] 4409 * L1 Threshold values in units of 100us 4410 */ 4411 typedef struct 4412 { 4413 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 4414 NvU32 l1Threshold[NVSWITCH_NVLINK_MAX_LINKS]; 4415 } NVSWITCH_GET_NVLINK_L1_THRESHOLD_PARAMS; 4416 4417 #define NVSWITCH_SET_NVLINK_L1_THRESHOLD_MIN 0x1 4418 #define NVSWITCH_SET_NVLINK_L1_THRESHOLD_MAX 0x1fff 4419 #define NVSWITCH_SET_NVLINK_L1_THRESHOLD_DEFAULT 0xffffffff 4420 4421 /* 4422 * CTRL_NVSWITCH_SET_NVLINK_L1_THRESHOLD 4423 * 4424 * Control to set NvLink L1 Thresholds. 4425 * 4426 * Parameters: 4427 * linkMask [IN] 4428 * A valid link mask for which we need to get the L1 Threshold 4429 * 4430 * l1Threshold [IN] 4431 * L1 Threshold values in units of 100us 4432 */ 4433 typedef struct 4434 { 4435 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 4436 NvU32 l1Threshold[NVSWITCH_NVLINK_MAX_LINKS]; 4437 } NVSWITCH_SET_NVLINK_L1_THRESHOLD_PARAMS; 4438 4439 /* 4440 * CTRL_NVSWITCH_FSPRPC_GET_CAPS 4441 * 4442 * Control to query FSP capabilities 4443 * 4444 * Parameters: 4445 * commandNvdmType [OUT] 4446 * NVDM type of the command RPC 4447 * responseNvdmType [OUT] 4448 * NVDM type of the RPC response 4449 * errorCode [OUT] 4450 * Error code of the RPC 4451 * pRspPayload [OUT] 4452 * Payload of the response 4453 */ 4454 typedef struct 4455 { 4456 NvU32 commandNvdmType; 4457 NvU32 responseNvdmType; 4458 NvU32 errorCode; 4459 } NVSWITCH_FSPRPC_GET_CAPS_PARAMS; 4460 4461 typedef enum nvswitch_device_tnvl_mode 4462 { 4463 NVSWITCH_DEVICE_TNVL_MODE_DISABLED = 0, // TNVL mode is disabled 4464 NVSWITCH_DEVICE_TNVL_MODE_ENABLED, // TNVL mode is enabled 4465 NVSWITCH_DEVICE_TNVL_MODE_FAILURE, // TNVL mode is enabled but in failure state 4466 NVSWITCH_DEVICE_TNVL_MODE_LOCKED, // TNVL mode is enabled and locked 4467 NVSWITCH_DEVICE_TNVL_MODE_COUNT 4468 } NVSWITCH_DEVICE_TNVL_MODE; 4469 4470 /* 4471 * CTRL_NVSWITCH_SET_DEVICE_TNVL_LOCK 4472 * 4473 * Control to set Trusted NVLink(TNVL) lock 4474 * 4475 * FM sets the TNVL lock after Fabric State is CONFIGURED 4476 * 4477 * Parameters: 4478 * tnvlStatus [OUT] 4479 * TNVL mode status of the device 4480 */ 4481 typedef struct nvswitch_set_device_tnvl_lock_params 4482 { 4483 NVSWITCH_DEVICE_TNVL_MODE tnvlStatus; 4484 } NVSWITCH_SET_DEVICE_TNVL_LOCK_PARAMS; 4485 4486 /* 4487 * CTRL_NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN 4488 * 4489 * Control to query NvSwitch session attestation certificate chain 4490 * 4491 * Parameters: 4492 * 4493 * attestationCertChain: [OUT] 4494 * Attestation certificate chain for the NvSwitch queried 4495 * 4496 * attestationCertChainSize: [OUT] 4497 * Actual size of attestation cert chain data 4498 */ 4499 4500 #define NVSWITCH_ATTESTATION_CERT_CHAIN_MAX_SIZE 0x1400 4501 4502 typedef struct nvswitch_get_attestation_certificate_chain_params 4503 { 4504 NvU8 attestationCertChain[NVSWITCH_ATTESTATION_CERT_CHAIN_MAX_SIZE]; 4505 NvU32 attestationCertChainSize; 4506 } NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS; 4507 4508 /* 4509 * CTRL_NVSWITCH_GET_ATTESTATION_REPORT 4510 * 4511 * Control to query NvSwitch attestation report. 4512 * 4513 * Parameters: 4514 * nonce: [IN] 4515 * nonce 4516 * attestationReport: [OUT] 4517 * Attestation report of the NvSwitch queried 4518 * attestationReportSize: [OUT] 4519 * Actual size of the report 4520 */ 4521 4522 #define NVSWITCH_NONCE_SIZE 0x20 4523 #define NVSWITCH_ATTESTATION_REPORT_MAX_SIZE 0x2000 4524 4525 typedef struct nvswitch_get_attestation_report_params 4526 { 4527 NvU8 nonce[NVSWITCH_NONCE_SIZE]; 4528 NvU8 attestationReport[NVSWITCH_ATTESTATION_REPORT_MAX_SIZE]; 4529 NvU32 attestationReportSize; 4530 } NVSWITCH_GET_ATTESTATION_REPORT_PARAMS; 4531 4532 /* 4533 * CTRL_NVSWITCH_GET_TNVL_STATUS 4534 * 4535 * Control to query Trusted NVLink(TNVL) status 4536 * 4537 * Parameters : 4538 * status: [OUT] 4539 * TNVL mode status 4540 */ 4541 typedef struct nvswitch_get_tnvl_status_params 4542 { 4543 NVSWITCH_DEVICE_TNVL_MODE status; 4544 } NVSWITCH_GET_TNVL_STATUS_PARAMS; 4545 4546 #define REGISTER_RW_ENGINE_RAW 0x00 4547 4548 #define REGISTER_RW_ENGINE_CLKS 0x10 4549 #define REGISTER_RW_ENGINE_FUSE 0x11 4550 #define REGISTER_RW_ENGINE_JTAG 0x12 4551 #define REGISTER_RW_ENGINE_PMGR 0x13 4552 #define REGISTER_RW_ENGINE_SAW 0x14 4553 #define REGISTER_RW_ENGINE_XP3G 0x15 4554 #define REGISTER_RW_ENGINE_XVE 0x16 4555 #define REGISTER_RW_ENGINE_SOE 0x17 4556 #define REGISTER_RW_ENGINE_SMR 0x18 4557 #define REGISTER_RW_ENGINE_SE 0x19 4558 #define REGISTER_RW_ENGINE_CLKS_SYS 0x1A 4559 #define REGISTER_RW_ENGINE_CLKS_SYSB 0x1B 4560 #define REGISTER_RW_ENGINE_CLKS_P0 0x1C 4561 #define REGISTER_RW_ENGINE_XPL 0x1D 4562 #define REGISTER_RW_ENGINE_XTL 0x1E 4563 4564 #define REGISTER_RW_ENGINE_SIOCTRL 0x20 4565 #define REGISTER_RW_ENGINE_MINION 0x21 4566 #define REGISTER_RW_ENGINE_NVLIPT 0x22 4567 #define REGISTER_RW_ENGINE_NVLTLC 0x23 4568 #define REGISTER_RW_ENGINE_NVLTLC_MULTICAST 0x24 4569 #define REGISTER_RW_ENGINE_DLPL 0x25 4570 #define REGISTER_RW_ENGINE_NVLW 0x26 4571 #define REGISTER_RW_ENGINE_NVLIPT_LNK 0x27 4572 #define REGISTER_RW_ENGINE_NVLIPT_LNK_MULTICAST 0x28 4573 #define REGISTER_RW_ENGINE_NVLDL 0x29 4574 #define REGISTER_RW_ENGINE_NVLDL_MULTICAST 0x2a 4575 #define REGISTER_RW_ENGINE_PLL 0x2b 4576 4577 #define REGISTER_RW_ENGINE_NPG 0x30 4578 #define REGISTER_RW_ENGINE_NPORT 0x31 4579 #define REGISTER_RW_ENGINE_NPORT_MULTICAST 0x32 4580 4581 #define REGISTER_RW_ENGINE_SWX 0x40 4582 #define REGISTER_RW_ENGINE_AFS 0x41 4583 #define REGISTER_RW_ENGINE_NXBAR 0x42 4584 #define REGISTER_RW_ENGINE_TILE 0x43 4585 #define REGISTER_RW_ENGINE_TILE_MULTICAST 0x44 4586 #define REGISTER_RW_ENGINE_TILEOUT 0x45 4587 #define REGISTER_RW_ENGINE_TILEOUT_MULTICAST 0x46 4588 4589 /* 4590 * CTRL call command list. 4591 * 4592 * Linux driver supports only 8-bit commands. 4593 * 4594 * See struct control call command modification guidelines at the top 4595 * of this file. 4596 */ 4597 #define CTRL_NVSWITCH_GET_INFO 0x01 4598 #define CTRL_NVSWITCH_SET_SWITCH_PORT_CONFIG 0x02 4599 #define CTRL_NVSWITCH_SET_INGRESS_REQUEST_TABLE 0x03 4600 #define CTRL_NVSWITCH_SET_INGRESS_REQUEST_VALID 0x04 4601 #define CTRL_NVSWITCH_SET_INGRESS_RESPONSE_TABLE 0x05 4602 #define CTRL_NVSWITCH_SET_GANGED_LINK_TABLE 0x06 4603 #define CTRL_NVSWITCH_GET_INTERNAL_LATENCY 0x07 4604 #define CTRL_NVSWITCH_SET_LATENCY_BINS 0x08 4605 #define CTRL_NVSWITCH_GET_NVLIPT_COUNTERS 0x09 4606 #define CTRL_NVSWITCH_SET_NVLIPT_COUNTER_CONFIG 0x0A 4607 #define CTRL_NVSWITCH_GET_NVLIPT_COUNTER_CONFIG 0x0B 4608 #define CTRL_NVSWITCH_GET_ERRORS 0x0C 4609 #define CTRL_NVSWITCH_SET_REMAP_POLICY 0x0D 4610 #define CTRL_NVSWITCH_SET_ROUTING_ID 0x0E 4611 #define CTRL_NVSWITCH_SET_ROUTING_LAN 0x0F 4612 #define CTRL_NVSWITCH_GET_INGRESS_REQUEST_TABLE 0x10 4613 #define CTRL_NVSWITCH_GET_INGRESS_RESPONSE_TABLE 0x11 4614 #define CTRL_NVSWITCH_GET_INGRESS_REQLINKID 0x12 4615 #define CTRL_NVSWITCH_UNREGISTER_LINK 0x13 4616 #define CTRL_NVSWITCH_RESET_AND_DRAIN_LINKS 0x14 4617 #define CTRL_NVSWITCH_GET_ROUTING_LAN 0x15 4618 #define CTRL_NVSWITCH_SET_ROUTING_LAN_VALID 0x16 4619 #define CTRL_NVSWITCH_GET_NVLINK_STATUS 0x17 4620 #define CTRL_NVSWITCH_ACQUIRE_CAPABILITY 0x18 4621 #define CTRL_NVSWITCH_GET_ROUTING_ID 0x19 4622 #define CTRL_NVSWITCH_SET_ROUTING_ID_VALID 0x1A 4623 #define CTRL_NVSWITCH_GET_TEMPERATURE 0x1B 4624 #define CTRL_NVSWITCH_GET_REMAP_POLICY 0x1C 4625 #define CTRL_NVSWITCH_SET_REMAP_POLICY_VALID 0x1D 4626 #define CTRL_NVSWITCH_GET_THROUGHPUT_COUNTERS 0x1E 4627 #define CTRL_NVSWITCH_GET_BIOS_INFO 0x1F 4628 #define CTRL_NVSWITCH_BLACKLIST_DEVICE 0x20 4629 #define CTRL_NVSWITCH_SET_FM_DRIVER_STATE 0x21 4630 #define CTRL_NVSWITCH_SET_DEVICE_FABRIC_STATE 0x22 4631 #define CTRL_NVSWITCH_SET_FM_HEARTBEAT_TIMEOUT 0x23 4632 #define CTRL_NVSWITCH_REGISTER_EVENTS 0x24 4633 #define CTRL_NVSWITCH_UNREGISTER_EVENTS 0x25 4634 #define CTRL_NVSWITCH_SET_TRAINING_ERROR_INFO 0x26 4635 #define CTRL_NVSWITCH_GET_FATAL_ERROR_SCOPE 0x27 4636 #define CTRL_NVSWITCH_SET_MC_RID_TABLE 0x28 4637 #define CTRL_NVSWITCH_GET_MC_RID_TABLE 0x29 4638 #define CTRL_NVSWITCH_GET_COUNTERS 0x2A 4639 #define CTRL_NVSWITCH_GET_NVLINK_ECC_ERRORS 0x2B 4640 #define CTRL_NVSWITCH_I2C_SMBUS_COMMAND 0x2C 4641 #define CTRL_NVSWITCH_GET_TEMPERATURE_LIMIT 0x2D 4642 #define CTRL_NVSWITCH_GET_NVLINK_MAX_ERROR_RATES 0x2E 4643 #define CTRL_NVSWITCH_GET_NVLINK_ERROR_COUNTS 0x2F 4644 #define CTRL_NVSWITCH_GET_ECC_ERROR_COUNTS 0x30 4645 #define CTRL_NVSWITCH_GET_SXIDS 0x31 4646 #define CTRL_NVSWITCH_GET_FOM_VALUES 0x32 4647 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS 0x33 4648 #define CTRL_NVSWITCH_SET_RESIDENCY_BINS 0x34 4649 #define CTRL_NVSWITCH_GET_RESIDENCY_BINS 0x35 4650 #define CTRL_NVSWITCH_GET_RB_STALL_BUSY 0x36 4651 #define CTRL_NVSWITCH_CCI_CMIS_PRESENCE 0x37 4652 #define CTRL_NVSWITCH_CCI_CMIS_NVLINK_MAPPING 0x38 4653 #define CTRL_NVSWITCH_CCI_CMIS_MEMORY_ACCESS_READ 0x39 4654 #define CTRL_NVSWITCH_CCI_CMIS_MEMORY_ACCESS_WRITE 0x3A 4655 #define CTRL_NVSWITCH_CCI_CMIS_CAGE_BEZEL_MARKING 0x3B 4656 #define CTRL_NVSWITCH_CCI_GET_GRADING_VALUES 0x3C 4657 #define CTRL_NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR 0x3D 4658 #define CTRL_NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR 0x3E 4659 #define CTRL_NVSWITCH_INBAND_SEND_DATA 0x43 4660 #define CTRL_NVSWITCH_INBAND_READ_DATA 0x44 4661 #define CTRL_NVSWITCH_INBAND_FLUSH_DATA 0x45 4662 #define CTRL_NVSWITCH_INBAND_PENDING_DATA_STATS 0x46 4663 #define CTRL_NVSWITCH_GET_SW_INFO 0x47 4664 #define CTRL_NVSWITCH_RESERVED_6 0x48 4665 #define CTRL_NVSWITCH_RESERVED_7 0x49 4666 #define CTRL_NVSWITCH_CCI_GET_PORTS_CPLD_INFO 0x4A 4667 #define CTRL_NVSWITCH_CCI_GET_FW_REVISIONS 0x4B 4668 #define CTRL_NVSWITCH_CCI_SET_LOCATE_LED 0x4C 4669 #define CTRL_NVSWITCH_REGISTER_READ 0x4D 4670 #define CTRL_NVSWITCH_REGISTER_WRITE 0x4E 4671 #define CTRL_NVSWITCH_GET_INFOROM_VERSION 0x4F 4672 #define CTRL_NVSWITCH_GET_ERR_INFO 0x50 4673 #define CTRL_NVSWITCH_CLEAR_COUNTERS 0x51 4674 #define CTRL_NVSWITCH_SET_NVLINK_ERROR_THRESHOLD 0x52 4675 #define CTRL_NVSWITCH_GET_NVLINK_ERROR_THRESHOLD 0x53 4676 #define CTRL_NVSWITCH_GET_VOLTAGE 0x54 4677 #define CTRL_NVSWITCH_GET_SOE_HEARTBEAT 0x55 4678 #define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x56 4679 #define CTRL_NVSWITCH_GET_POWER 0x57 4680 #define CTRL_NVSWITCH_GET_PORT_EVENTS 0x58 4681 #define CTRL_NVSWITCH_GET_SYS_INFO 0x59 4682 #define CTRL_NVSWITCH_GET_TIME_INFO 0x60 4683 #define CTRL_NVSWITCH_GET_TEMP_DATA 0x61 4684 #define CTRL_NVSWITCH_GET_TEMP_SAMPLES 0x62 4685 #define CTRL_NVSWITCH_SET_CONTINUOUS_ALI 0x63 4686 #define CTRL_NVSWITCH_REQUEST_ALI 0x64 4687 #define CTRL_NVSWITCH_GET_NVLINK_L1_CAPABILITY 0x65 4688 #define CTRL_NVSWITCH_GET_NVLINK_L1_THRESHOLD 0x66 4689 #define CTRL_NVSWITCH_SET_NVLINK_L1_THRESHOLD 0x67 4690 #define CTRL_NVSWITCH_FSPRPC_GET_CAPS 0x68 4691 #define CTRL_NVSWITCH_SET_DEVICE_TNVL_LOCK 0x69 4692 #define CTRL_NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN 0x6A 4693 #define CTRL_NVSWITCH_GET_ATTESTATION_REPORT 0x6B 4694 #define CTRL_NVSWITCH_GET_TNVL_STATUS 0x6C 4695 4696 #ifdef __cplusplus 4697 } 4698 #endif 4699 4700 #endif // _CTRL_DEVICE_NVSWITCH_H_ 4701