1 //***************************************************************************** 2 // 3 // SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 4 // SPDX-License-Identifier: MIT 5 // 6 // Permission is hereby granted, free of charge, to any person obtaining a 7 // copy of this software and associated documentation files (the "Software"), 8 // to deal in the Software without restriction, including without limitation 9 // the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 // and/or sell copies of the Software, and to permit persons to whom the 11 // Software is furnished to do so, subject to the following conditions: 12 // 13 // The above copyright notice and this permission notice shall be included in 14 // all copies or substantial portions of the Software. 15 // 16 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 // THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 // FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 // DEALINGS IN THE SOFTWARE. 23 // 24 // File: displayid.h 25 // 26 // Purpose: the template for DisplayID parsing (future replacement for EDID) 27 // 28 //***************************************************************************** 29 30 31 #ifndef __DISPLAYID_H_ 32 #define __DISPLAYID_H_ 33 34 #include "nvtiming.h" 35 36 // The structures below must be tightly packed, in order to correctly 37 // overlay on the EDID DisplayID extension block bytes. Both MSVC and 38 // gcc support the pack() pragma for this. 39 40 #if defined(__GNUC__) || defined(_MSC_VER) 41 # define __SUPPORTS_PACK_PRAGMA 1 42 #else 43 # error "unrecognized compiler: displayid structures must be tightly packed" 44 #endif 45 46 #ifdef __SUPPORTS_PACK_PRAGMA 47 #pragma pack(1) 48 #endif 49 50 typedef struct _tagDISPLAYID_SECTION 51 { 52 NvU8 version; // displayid version 53 NvU8 section_bytes; // length of this displayID section excluding mandatory bytes [0, 251] 54 55 NvU8 product_type; // NVT_DISPLAYID_PROD_X 56 NvU8 extension_count; 57 58 NvU8 data[NVT_DISPLAYID_SECTION_MAX_SIZE]; // data blocks. Note, the length of this structure may 59 // exceed valid memory, as DisplayID has variable length 60 61 } DISPLAYID_SECTION; 62 63 #define NVT_DISPLAYID_VER_1_1 0x101 64 65 #define NVT_DISPLAYID_PROD_EXTENSION 0 // Extension (product type not declared) 66 #define NVT_DISPLAYID_PROD_TEST 1 // Test Structure/Test Equipment 67 #define NVT_DISPLAYID_PROD_DISPLAY_PANEL 2 // Display Panel, LCD, or PDP module, etc. 68 #define NVT_DISPLAYID_PROD_STANDALONE_MONITOR 3 // Standalone display device, desktop monitor, TV monitor 69 #define NVT_DISPLAYID_PROD_RECEIVER 4 // Television receiver or display product capable of RF signals 70 #define NVT_DISPLAYID_PROD_REPEATER 5 // Repeater/translator that is not intended as display device 71 #define NVT_DISPLAYID_PROD_DIRECT_DRIVE 6 // Direct Drive monitor 72 #define NVT_DISPLAYID_PROD_MAX_NUMBER 6 // max product number 73 74 75 typedef struct _tagDISPLAYID_DATA_BLOCK_HEADER 76 { 77 NvU8 type; // identification 78 NvU8 revision; 79 NvU8 data_bytes; // number of payload bytes [0, 248] 80 81 } DISPLAYID_DATA_BLOCK_HEADER; 82 83 #define NVT_DISPLAYID_BLOCK_TYPE_PRODUCT_IDENTITY 0 // Product Identification block 84 #define NVT_DISPLAYID_BLOCK_TYPE_DISPLAY_PARAM 1 // Display Parameters block 85 #define NVT_DISPLAYID_BLOCK_TYPE_COLOR_CHAR 2 // Color Characteristics block 86 #define NVT_DISPLAYID_BLOCK_TYPE_TIMING_1 3 // Type 1 Detailed Timing block 87 #define NVT_DISPLAYID_BLOCK_TYPE_TIMING_2 4 // Type 2 Detailed Timing block 88 #define NVT_DISPLAYID_BLOCK_TYPE_TIMING_3 5 // Type 3 Short Timing block 89 #define NVT_DISPLAYID_BLOCK_TYPE_TIMING_4 6 // Type 4 DMT ID Timing block 90 #define NVT_DISPLAYID_BLOCK_TYPE_TIMING_VESA 7 // VESA Standard Timing block 91 #define NVT_DISPLAYID_BLOCK_TYPE_TIMING_CEA 8 // CEA Standard Timing block 92 #define NVT_DISPLAYID_BLOCK_TYPE_RANGE_LIMITS 9 // Video Timing Range Limits block 93 #define NVT_DISPLAYID_BLOCK_TYPE_SERIAL_NUMBER 10 // Product Serial Number block 94 #define NVT_DISPLAYID_BLOCK_TYPE_ASCII_STRING 11 // General Purpose ASCII String block 95 #define NVT_DISPLAYID_BLOCK_TYPE_DEVICE_DATA 12 // Display Device Data block 96 #define NVT_DISPLAYID_BLOCK_TYPE_INTERFACE_POWER 13 // Interface Power Sequencing block 97 #define NVT_DISPLAYID_BLOCK_TYPE_TRANSFER_CHAR 14 // Transfer Characteristics block 98 #define NVT_DISPLAYID_BLOCK_TYPE_DISPLAY_INTERFACE 15 // Display Interface Data Block 99 #define NVT_DISPLAYID_BLOCK_TYPE_STEREO 16 // Stereo Data Block 100 #define NVT_DISPLAYID_BLOCK_TYPE_TIMING_5 17 // Type V Timing Short Descriptor 101 #define NVT_DISPLAYID_BLOCK_TYPE_TILEDDISPLAY 18 // Tiled Display Data Block 102 #define NVT_DISPLAYID_BLOCK_TYPE_DISPLAY_INTERFACE_FEATURES 0X26 // DisplayID2.0 Display Interface Features Data Block // 103 #define NVT_DISPLAYID_BLOCK_TYPE_CTA_DATA 0x81 // DIsplay ID data block 104 #define NVT_DISPLAYID_BLOCK_TYPE_VENDOR_SPEC 0x7F // Vendor Specific Data Block 105 106 #define NVT_DISPLAYID_PRODUCT_IDENTITY_MIN_LEN 12 107 #define NVT_DISPLAYID_PRODUCT_IDENTITY_MAX_STRING_LEN 0xE9 108 109 typedef struct _tagDISPLAYID_PROD_IDENTIFICATION_BLOCK 110 { 111 DISPLAYID_DATA_BLOCK_HEADER header; 112 113 NvU8 vendor[3]; 114 NvU16 product_code; 115 NvU32 serial_number; 116 NvU8 model_tag; 117 NvU8 model_year; 118 NvU8 productid_string_size; 119 120 NvU8 productid_string[NVT_DISPLAYID_PRODUCT_IDENTITY_MAX_STRING_LEN]; 121 } DISPLAYID_PROD_IDENTIFICATION_BLOCK; 122 123 typedef struct _tagDISPLAYID_DISPLAY_PARAM_BLOCK 124 { 125 DISPLAYID_DATA_BLOCK_HEADER header; 126 NvU16 horizontal_image_size; 127 NvU16 vertical_image_size; 128 NvU16 horizontal_pixel_count; 129 NvU16 vertical_pixel_count; 130 131 NvU8 feature; 132 133 NvU8 transfer_char_gamma; 134 NvU8 aspect_ratio; 135 NvU8 color_bit_depth; 136 } DISPLAYID_DISPLAY_PARAM_BLOCK; 137 138 #define NVT_DISPLAYID_DISPLAY_PARAM_BLOCK_LEN 0x0C 139 140 #define NVT_DISPLAYID_DISPLAY_PARAM_SUPPORT_AUDIO 7:7 141 #define NVT_DISPLAYID_DISPLAY_PARAM_SEPARATE_AUDIO 6:6 142 #define NVT_DISPLAYID_DISPLAY_PARAM_AUDIO_INPUT_OVERRIDE 5:5 143 #define NVT_DISPLAYID_DISPLAY_PARAM_POWER_MANAGEMENT 4:4 144 #define NVT_DISPLAYID_DISPLAY_PARAM_FIXED_TIMING 3:3 145 #define NVT_DISPLAYID_DISPLAY_PARAM_FIXED_PIXEL_FORMAT 2:2 146 #define NVT_DISPLAYID_DISPLAY_PARAM_DEINTERLACING 0:0 147 148 #define NVT_DISPLAYID_DISPLAY_PARAM_DEPTH_OVERALL 7:4 149 #define NVT_DISPLAYID_DISPLAY_PARAM_DEPTH_NATIVE 3:0 150 151 typedef struct _tagDISPLAYID_COLOR_POINT 152 { 153 NvU8 color_x_bits_low; 154 NvU8 color_bits_mid; 155 NvU8 color_y_bits_high; 156 } DISPLAYID_COLOR_POINT; 157 158 #define NVT_DISPLAYID_COLOR_POINT_Y 7:4 159 #define NVT_DISPLAYID_COLOR_POINT_X 3:0 160 161 #define NVT_DISPLAYID_COLOR_MAX_POINTS 22 162 163 typedef struct _tagDISPLAYID_COLOR_CHAR_BLOCK 164 { 165 DISPLAYID_DATA_BLOCK_HEADER header; 166 167 // Color Characteristics Information 168 NvU8 point_info; 169 170 DISPLAYID_COLOR_POINT points[NVT_DISPLAYID_COLOR_MAX_POINTS]; 171 } DISPLAYID_COLOR_CHAR_BLOCK; 172 173 #define NVT_DISPLAYID_COLOR_PRIMARIES 6:4 174 #define NVT_DISPLAYID_COLOR_WHITE_POINTS 3:0 175 #define NVT_DISPLAYID_COLOR_TEMPORAL 7:7 176 177 // the following fields apply to Timing Descriptors 1-3 (Not all of them are 178 // used per descriptor, but the format is the same 179 #define NVT_DISPLAYID_TIMING_PREFERRED 7:7 180 #define NVT_DISPLAYID_TIMING_3D_STEREO 6:5 181 #define NVT_DISPLAYID_TIMING_3D_STEREO_MONO 0 182 #define NVT_DISPLAYID_TIMING_3D_STEREO_STEREO 1 183 #define NVT_DISPLAYID_TIMING_3D_STEREO_EITHER 2 184 #define NVT_DISPLAYID_TIMING_INTERLACE 4:4 185 #define NVT_DISPLAYID_TIMING_ASPECT_RATIO 2:0 186 #define NVT_DISPLAYID_TIMING_ASPECT_RATIO_1_1 0 187 #define NVT_DISPLAYID_TIMING_ASPECT_RATIO_5_4 1 188 #define NVT_DISPLAYID_TIMING_ASPECT_RATIO_4_3 2 189 #define NVT_DISPLAYID_TIMING_ASPECT_RATIO_15_9 3 190 #define NVT_DISPLAYID_TIMING_ASPECT_RATIO_16_9 4 191 #define NVT_DISPLAYID_TIMING_ASPECT_RATIO_16_10 5 192 193 typedef struct _tag_DISPLAYID_TIMING_1_DESCRIPTOR 194 { 195 NvU8 pixel_clock_low_minus_0_01MHz; 196 NvU8 pixel_clock_mid; 197 NvU8 pixel_clock_high; 198 199 struct 200 { 201 NvU8 aspect_ratio : 3; 202 NvU8 rsvd : 1; 203 NvU8 interface_frame_scanning_type : 1; 204 NvU8 stereo_support : 2; 205 NvU8 is_preferred_detailed_timing : 1; 206 }options; 207 208 struct 209 { 210 NvU8 active_image_pixels_low_minus_1; 211 NvU8 active_image_pixels_high; 212 NvU8 blank_pixels_low_minus_1; 213 NvU8 blank_pixels_high; 214 NvU8 front_porch_low_minus_1; 215 NvU8 front_porch_high : 7; 216 NvU8 sync_polarity : 1; 217 NvU8 sync_width_low_minus_1; 218 NvU8 sync_width_high; 219 }horizontal; 220 221 struct 222 { 223 NvU8 active_image_lines_low_minus_1; 224 NvU8 active_image_lines_high; 225 NvU8 blank_lines_low_minus_1; 226 NvU8 blank_lines_high; 227 NvU8 front_porch_lines_low_minus_1; 228 NvU8 front_porch_lines_high : 7; 229 NvU8 sync_polarity : 1; 230 NvU8 sync_width_lines_low_minus_1; 231 NvU8 sync_width_lines_high; 232 }vertical; 233 234 } DISPLAYID_TIMING_1_DESCRIPTOR; 235 236 #define NVT_DISPLAYID_TIMING_1_MAX_DESCRIPTORS 12 237 238 typedef struct _tagDISPLAYID_TIMING_1_BLOCK 239 { 240 DISPLAYID_DATA_BLOCK_HEADER header; 241 DISPLAYID_TIMING_1_DESCRIPTOR descriptors[NVT_DISPLAYID_TIMING_1_MAX_DESCRIPTORS]; 242 } DISPLAYID_TIMING_1_BLOCK; 243 244 #define NVT_DISPLAYID_TIMING_1_POLARITY_SHIFT 15 245 #define NVT_DISPLAYID_CHAR_WIDTH_IN_PIXELS 8 246 247 typedef struct _tag_DISPLAYID_TIMING_2_DESCRIPTOR 248 { 249 NvU8 pixel_clock_low_minus_0_01MHz; 250 NvU8 pixel_clock_mid; 251 NvU8 pixel_clock_high; 252 253 struct 254 { 255 NvU8 rsvd : 2; 256 NvU8 vsync_polarity : 1; 257 NvU8 hsync_polarity : 1; 258 NvU8 interface_frame_scanning_type : 1; 259 NvU8 stereo_support : 2; 260 NvU8 is_preferred_detailed_timing : 1; 261 }options; 262 263 struct 264 { 265 NvU8 active_image_in_char_minus_1; 266 NvU8 active_image_in_char_high : 1; 267 NvU8 blank_in_char_minus_1 : 7; 268 NvU8 sync_width_in_char_minus_1 : 4; 269 NvU8 front_porch_in_char_minus_1 : 4; 270 }horizontal; 271 272 struct 273 { 274 NvU8 active_image_lines_low_minus_1; 275 NvU8 active_image_lines_high : 4; 276 NvU8 reserved : 4; 277 NvU8 blank_lines_minus_1; 278 NvU8 sync_width_lines_minus_1 : 4; 279 NvU8 front_porch_lines_minus_1 : 4; 280 }vertical; 281 282 } DISPLAYID_TIMING_2_DESCRIPTOR; 283 284 #define NVT_DISPLAYID_TIMING_2_HORIZ_BLANK_PIXEL 7:1 285 #define NVT_DISPLAYID_TIMING_2_HORIZ_ACTIVE_PIXEL_HIGH 0:0 286 #define NVT_DISPLAYID_TIMING_2_HORIZ_OFFSET 7:4 287 #define NVT_DISPLAYID_TIMING_2_HORIZ_SYNC 3:0 288 #define NVT_DISPLAYID_TIMING_2_VERT_ACTIVE_PIXEL_HIGH 3:0 289 #define NVT_DISPLAYID_TIMING_2_VERT_OFFSET 7:4 290 #define NVT_DISPLAYID_TIMING_2_VERT_SYNC 3:0 291 292 #define NVT_DISPLAYID_TIMING_2_MAX_DESCRIPTORS 22 293 294 typedef struct _tagDISPLAYID_TIMING_2_BLOCK 295 { 296 DISPLAYID_DATA_BLOCK_HEADER header; 297 DISPLAYID_TIMING_2_DESCRIPTOR descriptors[NVT_DISPLAYID_TIMING_2_MAX_DESCRIPTORS]; 298 } DISPLAYID_TIMING_2_BLOCK; 299 300 typedef struct _TAG_DISPLAYID_TIMING_3_DESCRIPTOR 301 { 302 NvU8 optns; 303 NvU8 horizontal_active_pixels; 304 NvU8 transfer; 305 } DISPLAYID_TIMING_3_DESCRIPTOR; 306 307 #define NVT_DISPLAYID_TIMING_3_FORMULA 6:4 308 #define NVT_DISPLAYID_TIMING_3_FORMULA_STANDARD 0 309 #define NVT_DISPLAYID_TIMING_3_FORMULA_REDUCED_BLANKING 1 310 #define NVT_DISPLAYID_TIMING_3_ASPECT_RATIO 3:0 311 #define NVT_DISPLAYID_TIMING_3_ASPECT_RATIO_1_1 0 312 #define NVT_DISPLAYID_TIMING_3_ASPECT_RATIO_5_4 1 313 #define NVT_DISPLAYID_TIMING_3_ASPECT_RATIO_4_3 2 314 #define NVT_DISPLAYID_TIMING_3_ASPECT_RATIO_15_9 3 315 #define NVT_DISPLAYID_TIMING_3_ASPECT_RATIO_16_9 4 316 #define NVT_DISPLAYID_TIMING_3_ASPECT_RATIO_16_10 5 317 #define NVT_DISPLAYID_TIMING_3_INTERLACE 7:7 318 #define NVT_DISPLAYID_TIMING_3_REFRESH_RATE 6:0 319 320 #define NVT_DISPLAYID_TIMING_3_MAX_DESCRIPTORS 82 321 322 typedef struct _tagDISPLAYID_TIMING_3_BLOCK 323 { 324 DISPLAYID_DATA_BLOCK_HEADER header; 325 DISPLAYID_TIMING_3_DESCRIPTOR descriptors[NVT_DISPLAYID_TIMING_3_MAX_DESCRIPTORS]; 326 } DISPLAYID_TIMING_3_BLOCK; 327 328 #define NVT_DISPLAYID_TIMING_4_MAX_CODES NVT_DISPLAYID_DATABLOCK_MAX_PAYLOAD_LEN 329 330 typedef struct _tagDISPLAYID_TIMING_4_BLOCK 331 { 332 DISPLAYID_DATA_BLOCK_HEADER header; 333 NvU8 timing_codes[NVT_DISPLAYID_TIMING_4_MAX_CODES]; 334 } DISPLAYID_TIMING_4_BLOCK; 335 336 #define NVT_DISPLAYID_TIMING_5_STEREO_SUPPORT_MASK 0x60 337 #define NVT_DISPLAYID_TIMING_5_FRACTIONAL_RR_SUPPORT_MASK 0x10 338 #define NVT_DISPLAYID_TIMING_5_FORMULA_SUPPORT_MASK 3 339 340 typedef struct _TAG_DISPLAYID_TIMING_5_DESCRIPTOR 341 { 342 NvU8 optns; 343 NvU8 rsvd; 344 NvU8 horizontal_active_pixels_low; 345 NvU8 horizontal_active_pixels_high; 346 NvU8 vertical_active_pixels_low; 347 NvU8 vertical_active_pixels_high; 348 NvU8 refresh_rate; 349 } DISPLAYID_TIMING_5_DESCRIPTOR; 350 351 #define NVT_DISPLAYID_TIMING_5_MAX_DESCRIPTORS 53 352 353 typedef struct _tagDISPLAYID_TIMING_5_BLOCK 354 { 355 DISPLAYID_DATA_BLOCK_HEADER header; 356 DISPLAYID_TIMING_5_DESCRIPTOR descriptors[NVT_DISPLAYID_TIMING_5_MAX_DESCRIPTORS]; 357 } DISPLAYID_TIMING_5_BLOCK; 358 359 #define DISPLAYID_TIMING_VESA_BLOCK_SIZE 0x0A 360 #define DISPLAYID_TIMING_CEA_BLOCK_SIZE 0x08 361 362 typedef struct _tagDISPLAYID_TIMING_MODE_BLOCK 363 { 364 DISPLAYID_DATA_BLOCK_HEADER header; 365 NvU8 timing_modes[DISPLAYID_TIMING_VESA_BLOCK_SIZE]; 366 } DISPLAYID_TIMING_MODE_BLOCK; 367 368 369 typedef struct _tagDISPLAYID_RANGE_LIMITS_BLOCK 370 { 371 DISPLAYID_DATA_BLOCK_HEADER header; 372 NvU8 pixel_clock_min[3]; 373 NvU8 pixel_clock_max[3]; 374 NvU8 horizontal_frequency_min; 375 NvU8 horizontal_frequency_max; 376 NvU16 horizontal_blanking_min; 377 NvU8 vertical_refresh_rate_min; 378 NvU8 vertical_refresh_rate_max; 379 NvU16 vertical_blanking_min; 380 381 NvU8 optns; 382 } DISPLAYID_RANGE_LIMITS_BLOCK; 383 384 #define DISPLAYID_RANGE_LIMITS_BLOCK_LEN 0xF 385 386 #define NVT_DISPLAYID_RANGE_LIMITS_INTERLACE 7:7 387 #define NVT_DISPLAYID_RANGE_LIMITS_CVT_STANDARD 6:6 388 #define NVT_DISPLAYID_RANGE_LIMITS_CVT_REDUCED 5:5 389 #define NVT_DISPLAYID_RANGE_LIMITS_DFD 4:4 390 391 typedef struct _tagDISPLAYID_ASCII_STRING_BLOCK 392 { 393 DISPLAYID_DATA_BLOCK_HEADER header; 394 NvU8 data[NVT_DISPLAYID_DATABLOCK_MAX_PAYLOAD_LEN]; 395 } DISPLAYID_ASCII_STRING_BLOCK; 396 397 typedef struct _tagDISPLAYID_DEVICE_DATA_BLOCK 398 { 399 DISPLAYID_DATA_BLOCK_HEADER header; 400 401 NvU8 technology; 402 NvU8 operating_mode; 403 NvU16 horizontal_pixel_count; 404 NvU16 vertical_pixel_count; 405 NvU8 aspect_ratio; 406 NvU8 orientation; 407 408 NvU8 subpixel_info; 409 NvU8 horizontal_pitch; 410 NvU8 vertical_pitch; 411 412 NvU8 color_bit_depth; 413 NvU8 response_time; 414 415 } DISPLAYID_DEVICE_DATA_BLOCK; 416 417 #define DISPLAYID_DEVICE_DATA_BLOCK_LEN 0xD 418 419 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_CRT_MONOCHROME 0x00 420 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_CRT_STANDARD 0x01 421 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_CRT_OTHER 0x02 422 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_LCD_PASSIVE_MATRIX_TN 0x10 423 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_LCD_PASSIVE_MATRIX_CHOL_LC 0x11 424 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_LCD_PASSIVE_MATRIX_FERRO_LC 0x12 425 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_LCD_PASSIVE_MATRIX_OTHER 0x13 426 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_LCD_ACTIVE_MATRIX_TN 0x14 427 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_LCD_ACTIVE_MATRIX_IPS 0x15 428 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_LCD_ACTIVE_MATRIX_VA 0x16 429 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_LCD_ACTIVE_MATRIX_OCB 0x17 430 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_LCD_ACTIVE_MATRIX_FERRO 0x18 431 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_LCD_OTHER 0x1F 432 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_PLASMA_DC 0x20 433 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_PLASMA_AC 0x21 434 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_ELECTROLUM 0x30 435 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_INORGANIC_LED 0x40 436 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_ORGANIC_LED 0x50 437 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_FED 0x60 438 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_ELECTROPHORETIC 0x70 439 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_ELECTROCHROMIC 0x80 440 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_ELECTROMECHANICAL 0x90 441 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_ELECTROWETTING 0xA0 442 #define NVT_DISPLAYID_DEVICE_TECHNOLOGY_OTHER 0xF0 443 444 // Display Device operating mode info 445 #define NVT_DISPLAYID_DEVICE_OPERATING_MODE 7:4 446 #define NVT_DISPLAYID_DEVICE_OPERATING_MODE_REFLECTIVE_NO_ILLUM 0x0 447 #define NVT_DISPLAYID_DEVICE_OPERATING_MODE_REFLECTIVE_ILLUM 0x1 448 #define NVT_DISPLAYID_DEVICE_OPERATING_MODE_REFLECTIVE_ILLUM_DEF 0x2 449 #define NVT_DISPLAYID_DEVICE_OPERATING_MODE_TRANSMISSIVE_NO_ILLUM 0x3 450 #define NVT_DISPLAYID_DEVICE_OPERATING_MODE_TRANSMISSIVE_ILLUM 0x4 451 #define NVT_DISPLAYID_DEVICE_OPERATING_MODE_TRANSMISSIVE_ILLUM_DEF 0x5 452 #define NVT_DISPLAYID_DEVICE_OPERATING_MODE_EMISSIVE 0x6 453 #define NVT_DISPLAYID_DEVICE_OPERATING_MODE_TRANSFLECTIVE_REF 0x7 454 #define NVT_DISPLAYID_DEVICE_OPERATING_MODE_TRANSFLECTIVE_TRANS 0x8 455 #define NVT_DISPLAYID_DEVICE_OPERATING_MODE_TRANSPARENT_AMB 0x9 456 #define NVT_DISPLAYID_DEVICE_OPERATING_MODE_TRANSPARENT_EMIS 0xA 457 #define NVT_DISPLAYID_DEVICE_OPERATING_MODE_PROJECTION_REF 0xB 458 #define NVT_DISPLAYID_DEVICE_OPERATING_MODE_PROJECTION_TRANS 0xC 459 #define NVT_DISPLAYID_DEVICE_OPERATING_MODE_PROJECTION_EMIS 0xD 460 #define NVT_DISPLAYID_DEVICE_BACKLIGHT 3:3 461 #define NVT_DISPLAYID_DEVICE_INTENSITY 2:2 462 463 // Display Device aspect ratio/orientation info 464 #define NVT_DISPLAYID_DEVICE_ORIENTATION 7:6 465 #define NVT_DISPLAYID_DEVICE_ORIENTATION_LANDSCAPE 0 466 #define NVT_DISPLAYID_DEVICE_ORIENTATION_PORTRAIT 1 467 #define NVT_DISPLAYID_DEVICE_ORIENTATION_NOT_FIXED 2 468 #define NVT_DISPLAYID_DEVICE_ORIENTATION_UNDEFINED 3 469 #define NVT_DISPLAYID_DEVICE_ROTATION 5:4 470 #define NVT_DISPLAYID_DEVICE_ROTATION_NONE 0 471 #define NVT_DISPLAYID_DEVICE_ROTATION_CLOCKWISE 1 472 #define NVT_DISPLAYID_DEVICE_ROTATION_COUNTERCLOCKWISE 2 473 #define NVT_DISPLAYID_DEVICE_ROTATION_BOTH 3 474 #define NVT_DISPLAYID_DEVICE_ZERO_PIXEL 3:2 475 #define NVT_DISPLAYID_DEVICE_ZERO_PIXEL_UPPER_LEFT 0 476 #define NVT_DISPLAYID_DEVICE_ZERO_PIXEL_UPPER_RIGHT 1 477 #define NVT_DISPLAYID_DEVICE_ZERO_PIXEL_LOWER_LEFT 2 478 #define NVT_DISPLAYID_DEVICE_ZERO_PIXEL_LOWER RIGHT 3 479 #define NVT_DISPLAYID_DEVICE_SCAN 1:0 480 #define NVT_DISPLAYID_DEVICE_SCAN_UNDEFINED 0 481 #define NVT_DISPLAYID_DEVICE_SCAN_FAST_LONG 1 482 #define NVT_DISPLAYID_DEVICE_SCAN_FAST_SHORT 2 483 484 // Display Device Color Depth information 485 #define NVT_DISPLAYID_DEVICE_COLOR_DEPTH 3:0 486 487 // Display Device Response Time information 488 #define NVT_DISPLAYID_DEVICE_WHITE_BLACK 7:7 489 #define NVT_DISPLAYID_DEVICE_RESPONSE_TIME 6:0 490 491 #define NVT_DISPLAYID_SUBPIXEL_UNDEFINED 0 492 #define NVT_DISPLAYID_SUBPIXEL_RGB_VERTICAL 1 493 #define NVT_DISPLAYID_SUBPIXEL_RGB_HORIZONTAL 2 494 #define NVT_DISPLAYID_SUBPIXEL_VERTICAL_STR 3 495 #define NVT_DISPLAYID_SUBPIXEL_HORIZONTAL_STR 4 496 #define NVT_DISPLAYID_SUBPIXEL_QUAD_RED_TOP_LEFT 5 497 #define NVT_DISPLAYID_SUBPIXEL_QUAD_RED_BOTTOM_LEFT 6 498 #define NVT_DISPLAYID_SUBPIXEL_DELTA_RGB 7 499 #define NVT_DISPLAYID_SUBPIXEL_MOSAIC 8 500 #define NVT_DISPLAYID_SUBPIXEL_QUAD_INC_WHITE 9 501 #define NVT_DISPLAYID_SUBPIXEL_FIVE 10 502 #define NVT_DISPLAYID_SUBPIXEL_SIX 11 503 #define NVT_DISPLAYID_SUBPIXEL_PENTILE 12 504 505 typedef struct _tagDISPLAYID_INTERFACE_POWER_BLOCK 506 { 507 DISPLAYID_DATA_BLOCK_HEADER header; 508 NvU8 power_sequence_T1; 509 NvU8 power_sequence_T2; 510 NvU8 power_sequence_T3; 511 NvU8 power_sequence_T4_min; 512 NvU8 power_sequence_T5_min; 513 NvU8 power_sequence_T6_min; 514 } DISPLAYID_INTERFACE_POWER_BLOCK; 515 516 #define DISPLAYID_INTERFACE_POWER_BLOCK_LEN 0x6 517 518 #define NVT_DISPLAYID_POWER_T1_MIN 7:4 519 #define NVT_DISPLAYID_POWER_T1_MAX 3:0 520 #define NVT_DISPLAYID_POWER_T2 5:0 521 #define NVT_DISPLAYID_POWER_T3 5:0 522 #define NVT_DISPLAYID_POWER_T4_MIN 6:0 523 #define NVT_DISPLAYID_POWER_T5_MIN 5:0 524 #define NVT_DISPLAYID_POWER_T6_MIN 5:0 525 526 typedef struct _tagDISPLAYID_TRANSFER_CHAR_BLOCK 527 { 528 DISPLAYID_DATA_BLOCK_HEADER header; 529 NvU8 info; 530 NvU8 samples; 531 NvU8 curve_data[NVT_DISPLAYID_DATABLOCK_MAX_PAYLOAD_LEN - 2]; 532 } DISPLAYID_TRANSFER_CHAR_BLOCK; 533 534 typedef struct _tagDISPLAYID_INTERFACE_DATA_BLOCK 535 { 536 DISPLAYID_DATA_BLOCK_HEADER header; 537 NvU8 info; 538 539 NvU8 version; 540 NvU8 color_depth_rgb; 541 NvU8 color_depth_ycbcr444; 542 NvU8 color_depth_ycbcr422; 543 NvU8 content_protection; 544 NvU8 content_protection_version; 545 546 NvU8 spread; 547 548 NvU8 interface_attribute_1; 549 NvU8 interface_attribute_2; 550 } DISPLAYID_INTERFACE_DATA_BLOCK; 551 552 #define DISPLAYID_INTERFACE_DATA_BLOCK_LEN 0xA 553 554 #define NVT_DISPLAYID_INTERFACE_TYPE 7:4 555 556 // Interface Codes (note exception for Analog Interface) 557 #define NVT_DISPLAYID_INTERFACE_TYPE_ANALOG 0 558 #define NVT_DISPLAYID_INTERFACE_TYPE_LVDS 1 559 #define NVT_DISPLAYID_INTERFACE_TYPE_TMDS 2 560 #define NVT_DISPLAYID_INTERFACE_TYPE_RSDS 3 561 #define NVT_DISPLAYID_INTERFACE_TYPE_DVI_D 4 562 #define NVT_DISPLAYID_INTERFACE_TYPE_DVI_I_ANALOG 5 563 #define NVT_DISPLAYID_INTERFACE_TYPE_DVI_I_DIGITAL 6 564 #define NVT_DISPLAYID_INTERFACE_TYPE_HDMI_A 7 565 #define NVT_DISPLAYID_INTERFACE_TYPE_HDMI_B 8 566 #define NVT_DISPLAYID_INTERFACE_TYPE_MDDI 9 567 #define NVT_DISPLAYID_INTERFACE_TYPE_DISPLAYPORT 10 568 #define NVT_DISPLAYID_INTERFACE_TYPE_PROPRIETARY 11 569 570 // Analog Interface Subtype codes 571 #define NVT_DISPLAYID_INTERFACE_TYPE_ANALOG_VGA 0 572 #define NVT_DISPLAYID_INTERFACE_TYPE_ANALOG_VESA_NAVI_V 1 573 #define NVT_DISPLAYID_INTERFACE_TYPE_ANALOG_VESA_NAVI_D 2 574 575 #define NVT_DISPLAYID_INTERFACE_NUMLINKS 3:0 576 #define NVT_DISPLAYID_INTERFACE_CONTENT 2:0 577 #define NVT_DISPLAYID_INTERFACE_CONTENT_NONE 0 578 #define NVT_DISPLAYID_INTERFACE_CONTENT_HDCP 1 579 #define NVT_DISPLAYID_INTERFACE_CONTENT_DTCP 2 580 #define NVT_DISPLAYID_INTERFACE_CONTENT_DPCP 3 581 #define NVT_DISPLAYID_INTERFACE_SPREAD_TYPE 7:6 582 #define NVT_DISPLAYID_INTERFACE_SPREAD_TYPE_NONE 0 583 #define NVT_DISPLAYID_INTERFACE_SPREAD_TYPE_DOWN 1 584 #define NVT_DISPLAYID_INTERFACE_SPREAD_TYPE_CENTER 2 585 #define NVT_DISPLAYID_INTERFACE_SPREAD_PER 3:0 586 587 #define NVT_DISPLAYID_INTERFACE_RGB16 5:5 588 #define NVT_DISPLAYID_INTERFACE_RGB14 4:4 589 #define NVT_DISPLAYID_INTERFACE_RGB12 3:3 590 #define NVT_DISPLAYID_INTERFACE_RGB10 2:2 591 #define NVT_DISPLAYID_INTERFACE_RGB8 1:1 592 #define NVT_DISPLAYID_INTERFACE_RGB6 0:0 593 594 #define NVT_DISPLAYID_INTERFACE_YCBCR444_16 5:5 595 #define NVT_DISPLAYID_INTERFACE_YCBCR444_14 4:4 596 #define NVT_DISPLAYID_INTERFACE_YCBCR444_12 3:3 597 #define NVT_DISPLAYID_INTERFACE_YCBCR444_10 2:2 598 #define NVT_DISPLAYID_INTERFACE_YCBCR444_8 1:1 599 #define NVT_DISPLAYID_INTERFACE_YCBCR444_6 0:0 600 601 #define NVT_DISPLAYID_INTERFACE_YCBCR422_16 4:4 602 #define NVT_DISPLAYID_INTERFACE_YCBCR422_14 3:3 603 #define NVT_DISPLAYID_INTERFACE_YCBCR422_12 2:2 604 #define NVT_DISPLAYID_INTERFACE_YCBCR422_10 1:1 605 #define NVT_DISPLAYID_INTERFACE_YCBCR422_8 0:0 606 607 // LVDS specific settings 608 #define NVT_DISPLAYID_LVDS_COLOR 4:4 609 #define NVT_DISPLAYID_LVDS_2_8 3:3 610 #define NVT_DISPLAYID_LVDS_12 2:2 611 #define NVT_DISPLAYID_LVDS_5 1:1 612 #define NVT_DISPLAYID_LVDS_3_3 0:0 613 614 #define NVT_DISPLAYID_INTERFACE_DE 2:2 615 #define NVT_DISPLAYID_INTERFACE_POLARITY 1:1 616 #define NVT_DISPLAYID_INTERFACE_STROBE 0:0 617 618 typedef struct _tagDISPLAYID_STEREO_INTERFACE_METHOD_BLOCK 619 { 620 DISPLAYID_DATA_BLOCK_HEADER header; 621 NvU8 stereo_bytes; 622 NvU8 stereo_code; 623 NvU8 timing_sub_block[NVT_DISPLAYID_DATABLOCK_MAX_PAYLOAD_LEN]; 624 } DISPLAYID_STEREO_INTERFACE_METHOD_BLOCK; 625 626 #define NVT_DISPLAYID_STEREO_FIELD_SEQUENTIAL 0x0 627 #define NVT_DISPLAYID_STEREO_SIDE_BY_SIDE 0x1 628 #define NVT_DISPLAYID_STEREO_PIXEL_INTERLEAVED 0x2 629 #define NVT_DISPLAYID_STEREO_DUAL_INTERFACE 0x3 630 #define NVT_DISPLAYID_STEREO_MULTIVIEW 0x4 631 #define NVT_DISPLAYID_STEREO_PROPRIETARY 0xFF 632 633 #define NVT_DISPLAYID_STEREO_MIRRORING 2:1 634 #define NVT_DISPLAYID_STEREO_POLARITY 0:0 635 636 typedef struct _tagDISPLAYID_TILED_DISPLAY_BLOCK 637 { 638 DISPLAYID_DATA_BLOCK_HEADER header; 639 struct 640 { 641 NvU8 single_tile_behavior:3; // 0x03 642 NvU8 multi_tile_behavior:2; // 0x03 643 NvU8 rsvd :1; // 0x03 644 NvU8 has_bezel_info :1; // 0x03 645 NvU8 single_enclosure :1; // 0x03 646 } capability; 647 struct 648 { 649 NvU8 row :4; // 0x04 650 NvU8 col :4; // 0x04 651 } topology_low; 652 struct 653 { 654 NvU8 y :4; // 0x05 655 NvU8 x :4; // 0x05 656 } location_low; 657 struct 658 { 659 NvU8 y :1; // 0x06 660 NvU8 reserved1 :1; // 0x06 661 NvU8 x :1; // 0x06 662 NvU8 reserved2 :1; // 0x06 663 NvU8 row :1; // 0x06 664 NvU8 reserved3 :1; // 0x06 665 NvU8 col :1; // 0x06 666 NvU8 reserved4 :1; // 0x06 667 } topo_loc_high; 668 struct 669 { 670 NvU8 width_low; // 0x07 671 NvU8 width_high; // 0x08 672 NvU8 height_low; // 0x09 673 NvU8 height_high; // 0X0A 674 } native_resolution; 675 struct 676 { 677 NvU8 pixel_density; // 0x0B 678 NvU8 top; // 0x0C 679 NvU8 bottom; // 0x0D 680 NvU8 right; // 0x0E 681 NvU8 left; // 0x0F 682 } bezel_info; 683 struct 684 { 685 NvU8 vendor_id[3]; // 0x10 ~ 0x12 686 NvU8 product_id[2]; // 0x13 ~ 0x14 687 NvU8 serial_number[4]; // 0x15 ~ 0x18 688 } topology_id; 689 } DISPLAYID_TILED_DISPLAY_BLOCK; 690 691 typedef struct _tagDISPLAYID_INTERFACE_FEATURES_DATA_BLOCK 692 { 693 DISPLAYID_DATA_BLOCK_HEADER header; 694 NvU8 supported_color_depth_rgb; 695 NvU8 supported_color_depth_ycbcr444; 696 NvU8 supported_color_depth_ycbcr422; 697 NvU8 supported_color_depth_ycbcr420; 698 NvU8 minimum_pixel_rate_ycbcr420; 699 NvU8 supported_audio_capability; 700 NvU8 supported_colorspace_eotf_combination_1; 701 NvU8 supported_colorspace_eotf_combination_2; 702 NvU8 additional_supported_colorspace_eotf_total; 703 NvU8 additional_supported_colorspace_eotf[NVT_DISPLAYID_DISPLAY_INTERFACE_FEATURES_MAX_ADDITIONAL_SUPPORTED_COLORSPACE_EOTF]; 704 } DISPLAYID_INTERFACE_FEATURES_DATA_BLOCK; 705 706 #define DISPLAYID_INTERFACE_FEATURES_DATA_BLOCK_MAX_LEN sizeof(DISPLAYID_INTERFACE_FEATURES_DATA_BLOCK) 707 708 #define NVT_DISPLAYID_INTERFACE_FEATURES_RGB16 5:5 709 #define NVT_DISPLAYID_INTERFACE_FEATURES_RGB14 4:4 710 #define NVT_DISPLAYID_INTERFACE_FEATURES_RGB12 3:3 711 #define NVT_DISPLAYID_INTERFACE_FEATURES_RGB10 2:2 712 #define NVT_DISPLAYID_INTERFACE_FEATURES_RGB8 1:1 713 #define NVT_DISPLAYID_INTERFACE_FEATURES_RGB6 0:0 714 715 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR444_16 5:5 716 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR444_14 4:4 717 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR444_12 3:3 718 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR444_10 2:2 719 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR444_8 1:1 720 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR444_6 0:0 721 722 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR422_16 4:4 723 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR422_14 3:3 724 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR422_12 2:2 725 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR422_10 1:1 726 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR422_8 0:0 727 728 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR420_16 4:4 729 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR420_14 3:3 730 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR420_12 2:2 731 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR420_10 1:1 732 #define NVT_DISPLAYID_INTERFACE_FEATURES_YCBCR420_8 0:0 733 734 #define NVT_DISPLAYID_INTERFACE_FEATURES_AUDIO_SUPPORTED_32KHZ 7:7 735 #define NVT_DISPLAYID_INTERFACE_FEATURES_AUDIO_SUPPORTED_44_1KHZ 6:6 736 #define NVT_DISPLAYID_INTERFACE_FEATURES_AUDIO_SUPPORTED_48KHZ 5:5 737 738 #define NVT_DISPLAYID_INTERFACE_FEATURES_COLORSPACE_BT2020_EOTF_SMPTE_ST2084 6:6 739 #define NVT_DISPLAYID_INTERFACE_FEATURES_COLORSPACE_BT2020_EOTF_BT2020 5:5 740 #define NVT_DISPLAYID_INTERFACE_FEATURES_COLORSPACE_DCI_P3_EOTF_DCI_P3 4:4 741 #define NVT_DISPLAYID_INTERFACE_FEATURES_COLORSPACE_ADOBE_RGB_EOTF_ADOBE_RGB 3:3 742 #define NVT_DISPLAYID_INTERFACE_FEATURES_COLORSPACE_BT709_EOTF_BT1886 2:2 743 #define NVT_DISPLAYID_INTERFACE_FEATURES_COLORSPACE_BT601_EOTF_BT601 1:1 744 #define NVT_DISPLAYID_INTERFACE_FEATURES_COLORSPACE_SRGB_EOTF_SRGB 0:0 745 746 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_COLORSPACE_EOTF_TOTAL 2:0 747 748 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_COLORSPACE 7:4 749 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_COLORSPACE_NOT_DEFINED 0 750 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_COLORSPACE_SRGB 1 751 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_COLORSPACE_BT601 2 752 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_COLORSPACE_BT709 3 753 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_COLORSPACE_ADOBE_RGB 4 754 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_COLORSPACE_DCI_P3 5 755 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_COLORSPACE_BT2020 6 756 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_COLORSPACE_CUSTOM 7 757 758 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_EOTF 3:0 759 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_EOTF_NOT_DEFINED 0 760 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_EOTF_SRGB 1 761 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_EOTF_BT601 2 762 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_EOTF_BT709 3 763 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_EOTF_ADOBE_RGB 4 764 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_EOTF_DCI_P3 5 765 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_EOTF_BT2020 6 766 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_EOTF_GAMMA 7 767 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_EOTF_SMPTE_ST2084 8 768 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_EOTF_HYBRID_LOG 9 769 #define NVT_DISPLAYID_INTERFACE_FEATURES_ADDITIONAL_SUPPORTED_EOTF_CUSTOM 10 770 771 772 #ifdef __SUPPORTS_PACK_PRAGMA 773 #pragma pack() 774 #endif 775 776 #endif // __DISPLAYID_H_ 777