1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /*! 25 * @brief Defines for simplifying SW accesses to the dev_ctrl interrupt tree. 26 * These are generic defines ued in addition to architecure-specific 27 * defines in dev_vm_addendum.h 28 * 29 */ 30 31 // 32 // Notes on the terms used below: 33 // Subtree: The HW tree is a 64-way tree that consists of 2 TOP level interrupt 34 // registers, 32 bits each. Each of these 64 is referred to as a subtree. 35 // Leaf: Each of these 64 subtrees are associated with a pair of LEAF registers 36 // giving us a total of 128 LEAF registers. 37 // GPU vector: The 128 LEAF registers give us a total of (128*32) GPU vectors 38 // giving us a total of 4096 GPU vectors 39 // 40 41 // 42 // Given a subtree index, the below macros give us the index of the TOP level 43 // register and the bit within the TOP level register to program for that 44 // subtree. 45 // 46 #define NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(i) (((NvU32)(i)) / 32) 47 #define NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i) (((NvU32)(i)) % 32) 48 49 // 50 // Given a subtree index, the below macros give us the two LEAF register indices 51 // that correspond to that subtree. 52 // 53 #define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(i) (((NvU32)(i)) * 2) 54 #define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(i) ((((NvU32)(i)) * 2) + 1) 55 56 #define NV_CTRL_INTR_LEAF_IDX_TO_SUBTREE(i) (((NvU32)(i)) / 2) 57 58 // 59 // Given a LEAF register index, the below macros give us the range of GPU 60 // interrupt vectors that correspond to those leafs. 61 // 62 #define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_START(i) (((NvU32)(i)) * 32) 63 #define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_END(i) ((((NvU32)(i)) * 32) + 31) 64 65 // 66 // Given a GPU interrupt vector, the below macros give us the index of the 67 // LEAF register and the bit within the LEAF register to program for that 68 // GPU interrupt vector. 69 // 70 #define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i) (((NvU32)(i)) / 32) 71 #define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(i) (((NvU32)(i)) % 32) 72 73 // 74 // Given a GPU interrupt vector, the below macro gives us the subtree in which 75 // it belongs. 76 // 77 #define NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(i) \ 78 ((NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2) 79 80 // First index of doorbell which is controlled by VF 81 #define NV_CTRL_INTR_GPU_DOORBELL_INDEX_VF_START 2048 82 83 // The max number of leaf registers we expect 84 #define NV_MAX_INTR_LEAVES 16 85 86 // In SW, this specifies an invalid interrupt vector 87 #define NV_INTR_VECTOR_INVALID (NV_U32_MAX) 88