1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef _DPCD_H_ 25 #define _DPCD_H_ 26 27 #define NV_DPCD_CAP_LEGACY_BASE (0x00000000) 28 29 #define NV_DPCD_REV (0x00000000) /* R-XUR */ 30 #define NV_DPCD_REV_MAJOR 7:4 /* R-XUF */ 31 #define NV_DPCD_REV_MAJOR_1 (0x00000001) /* R-XUV */ 32 #define NV_DPCD_REV_MINOR 3:0 /* R-XUF */ 33 #define NV_DPCD_REV_MINOR_0 (0x00000000) /* R-XUV */ 34 #define NV_DPCD_REV_MINOR_1 (0x00000001) /* R-XUV */ 35 #define NV_DPCD_REV_MINOR_2 (0x00000002) /* R-XUV */ 36 #define NV_DPCD_REV_MINOR_4 (0x00000004) /* R-XUV */ 37 38 #define NV_DPCD_MAX_LINK_BANDWIDTH (0x00000001) /* R-XUR */ 39 #define NV_DPCD_MAX_LINK_BANDWIDTH_VAL 4:0 /* R-XUF */ 40 #define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_1_62_GBPS (0x00000006) /* R-XUV */ 41 #define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_2_70_GBPS (0x0000000a) /* R-XUV */ 42 #define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_5_40_GBPS (0x00000014) /* R-XUV */ 43 44 #define NV_DPCD_MAX_LANE_COUNT (0x00000002) /* R-XUR */ 45 #define NV_DPCD_MAX_LANE_COUNT_LANE 4:0 /* R-XUF */ 46 #define NV_DPCD_MAX_LANE_COUNT_LANE_1 (0x00000001) /* R-XUV */ 47 #define NV_DPCD_MAX_LANE_COUNT_LANE_2 (0x00000002) /* R-XUV */ 48 #define NV_DPCD_MAX_LANE_COUNT_LANE_4 (0x00000004) /* R-XUV */ 49 #define NV_DPCD_MAX_LANE_COUNT_LANE_8 (0x00000008) /* R-XUV */ 50 #define NV_DPCD_MAX_LANE_COUNT_POST_LT_ADJ_REQ_SUPPORT 5:5 /* R-XUF */ 51 #define NV_DPCD_MAX_LANE_COUNT_POST_LT_ADJ_REQ_SUPPORT_NO (0x00000000) /* R-XUV */ 52 #define NV_DPCD_MAX_LANE_COUNT_POST_LT_ADJ_REQ_SUPPORT_YES (0x00000001) /* R-XUV */ 53 #define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING 7:7 /* R-XUF */ 54 #define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_NO (0x00000000) /* R-XUV */ 55 #define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (0x00000001) /* R-XUV */ 56 #define NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED 6:6 /* R-XUF */ 57 #define NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_NO (0x00000000) /* R-XUV */ 58 #define NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES (0x00000001) /* R-XUV */ 59 60 #define NV_DPCD_MAX_DOWNSPREAD (0x00000003) /* R-XUR */ 61 #define NV_DPCD_MAX_DOWNSPREAD_VAL 0:0 /* R-XUF */ 62 #define NV_DPCD_MAX_DOWNSPREAD_VAL_NONE (0x00000000) /* R-XUV */ 63 #define NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT (0x00000001) /* R-XUV */ 64 #define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT 6:6 /* R-XUF */ 65 #define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_FALSE (0x00000000) /* R-XUV */ 66 #define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_TRUE (0x00000001) /* R-XUV */ 67 68 // NORP = Number of Receiver Ports = Value + 1 69 #define NV_DPCD_NORP (0x00000004) /* R-XUR */ 70 #define NV_DPCD_NORP_VAL 0:0 /* R-XUF */ 71 #define NV_DPCD_NORP_VAL_ONE (0x00000000) /* R-XUV */ 72 #define NV_DPCD_NORP_VAL_TWO (0x00000001) /* R-XUV */ 73 #define NV_DPCD_NORP_VAL_SST_MAX (0x00000001) /* R-XUV */ 74 #define NV_DPCD_NORP_DP_PWR_CAP_5V 5:5 /* R-XUF */ 75 #define NV_DPCD_NORP_DP_PWR_CAP_12V 6:6 /* R-XUF */ 76 #define NV_DPCD_NORP_DP_PWR_CAP_18V 7:7 /* R-XUF */ 77 78 #define NV_DPCD_DOWNSTREAMPORT (0x00000005) /* R-XUR */ 79 #define NV_DPCD_DOWNSTREAMPORT_PRESENT 0:0 /* R-XUF */ 80 #define NV_DPCD_DOWNSTREAMPORT_PRESENT_NO (0x00000000) /* R-XUV */ 81 #define NV_DPCD_DOWNSTREAMPORT_PRESENT_YES (0x00000001) /* R-XUV */ 82 #define NV_DPCD_DOWNSTREAMPORT_TYPE 2:1 /* R-XUF */ 83 #define NV_DPCD_DOWNSTREAMPORT_TYPE_DISPLAYPORT (0x00000000) /* R-XUV */ 84 #define NV_DPCD_DOWNSTREAMPORT_TYPE_ANALOG (0x00000001) /* R-XUV */ 85 #define NV_DPCD_DOWNSTREAMPORT_TYPE_HDMI_DVI (0x00000002) /* R-XUV */ 86 #define NV_DPCD_DOWNSTREAMPORT_TYPE_OTHERS (0x00000003) /* R-XUV */ 87 #define NV_DPCD_DOWNSTREAMPORT_FORMAT_CONVERSION 3:3 /* R-XUF */ 88 #define NV_DPCD_DOWNSTREAMPORT_FORMAT_CONVERSION_NO (0x00000000) /* R-XUV */ 89 #define NV_DPCD_DOWNSTREAMPORT_FORMAT_CONVERSION_YES (0x00000001) /* R-XUV */ 90 #define NV_DPCD_DOWNSTREAMPORT_DETAILED_CAP_INFO_AVAILABLE 4:4 /* R-XUF */ 91 #define NV_DPCD_DOWNSTREAMPORT_DETAILED_CAP_INFO_AVAILABLE_NO (0x00000000) /* R-XUV */ 92 #define NV_DPCD_DOWNSTREAMPORT_DETAILED_CAP_INFO_AVAILABLE_YES (0x00000001) /* R-XUV */ 93 94 #define NV_DPCD_MAIN_LINK_CHANNEL_CODING (0x00000006) /* R-XUR */ 95 #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B 0:0 /* R-XUF */ 96 #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B_NO (0x00000000) /* R-XUV */ 97 #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B_YES (0x00000001) /* R-XUV */ 98 #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B 1:1 /* R-XUF */ 99 #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B_NO (0x00000000) /* R-XUV */ 100 #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B_YES (0x00000001) /* R-XUV */ 101 102 #define NV_DPCD_DOWN_STREAM_PORT (0x00000007) /* R-XUR */ 103 #define NV_DPCD_DOWN_STREAM_PORT_COUNT 3:0 /* R-XUF */ 104 #define NV_DPCD_DOWN_STREAM_PORT_MSA_TIMING_PAR_IGNORED 6:6 /* R-XUF */ 105 #define NV_DPCD_DOWN_STREAM_PORT_MSA_TIMING_PAR_IGNORED_NO (0x00000000) /* R-XUV */ 106 #define NV_DPCD_DOWN_STREAM_PORT_MSA_TIMING_PAR_IGNORED_YES (0x00000001) /* R-XUV */ 107 #define NV_DPCD_DOWN_STREAM_PORT_OUI_SUPPORT 7:7 /* R-XUF */ 108 #define NV_DPCD_DOWN_STREAM_PORT_OUI_SUPPORT_NO (0x00000000) /* R-XUV */ 109 #define NV_DPCD_DOWN_STREAM_PORT_OUI_SUPPORT_YES (0x00000001) /* R-XUV */ 110 111 #define NV_DPCD_RECEIVE_PORT0_CAP_0 (0x00000008) /* R-XUR */ 112 #define NV_DPCD_RECEIVE_PORT1_CAP_0 (0x0000000A) /* R-XUR */ 113 #define NV_DPCD_RECEIVE_PORTX_CAP_0_LOCAL_EDID 1:1 /* R-XUF */ 114 #define NV_DPCD_RECEIVE_PORTX_CAP_0_LOCAL_EDID_NO (0x00000000) /* R-XUV */ 115 #define NV_DPCD_RECEIVE_PORTX_CAP_0_LOCAL_EDID_YES (0x00000001) /* R-XUV */ 116 #define NV_DPCD_RECEIVE_PORTX_CAP_0_ASSO_TO_PRECEDING_PORT 2:2 /* R-XUF */ 117 #define NV_DPCD_RECEIVE_PORTX_CAP_0_ASSO_TO_PRECEDING_PORT_NO (0x00000000) /* R-XUV */ 118 #define NV_DPCD_RECEIVE_PORTX_CAP_0_ASSO_TO_PRECEDING_PORT_YES (0x00000001) /* R-XUV */ 119 120 #define NV_DPCD_RECEIVE_PORT0_CAP_1 (0x00000009) /* R-XUR */ 121 #define NV_DPCD_RECEIVE_PORT1_CAP_1 (0x0000000B) /* R-XUR */ 122 #define NV_DPCD_RECEIVE_PORTX_CAP_1_BUFFER_SIZE 7:0 /* R-XUF */ 123 124 #define NV_DPCD_I2C_CTRL_CAP (0x0000000C) /* R-XUR */ 125 #define NV_DPCD_I2C_CTRL_CAP_SPEED 7:0 /* R-XUF */ 126 #define NV_DPCD_I2C_CTRL_CAP_SPEED_1K (0x00000001) /* R-XUV */ 127 #define NV_DPCD_I2C_CTRL_CAP_SPEED_5K (0x00000002) /* R-XUV */ 128 #define NV_DPCD_I2C_CTRL_CAP_SPEED_10K (0x00000004) /* R-XUV */ 129 #define NV_DPCD_I2C_CTRL_CAP_SPEED_100K (0x00000008) /* R-XUV */ 130 #define NV_DPCD_I2C_CTRL_CAP_SPEED_400K (0x00000010) /* R-XUV */ 131 #define NV_DPCD_I2C_CTRL_CAP_SPEED_1M (0x00000020) /* R-XUV */ 132 133 #define NV_DPCD_EDP_CONFIG_CAP (0x0000000D) /* R-XUR */ 134 #define NV_DPCD_EDP_CONFIG_CAP_ALTERNATE_SCRAMBLER_RESET 0:0 /* R-XUF */ 135 #define NV_DPCD_EDP_CONFIG_CAP_ALTERNATE_SCRAMBLER_RESET_NO (0x00000000) /* R-XUV */ 136 #define NV_DPCD_EDP_CONFIG_CAP_ALTERNATE_SCRAMBLER_RESET_YES (0x00000001) /* R-XUV */ 137 #define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE 1:1 /* R-XUF */ 138 #define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_NO (0x00000000) /* R-XUV */ 139 #define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES (0x00000001) /* R-XUV */ 140 #define NV_DPCD_EDP_CONFIG_CAP_INVERTED_TRAINING_BIT 2:2 /* R-XUF */ 141 #define NV_DPCD_EDP_CONFIG_CAP_INVERTED_TRAINING_BIT_NO (0x00000000) /* R-XUV */ 142 #define NV_DPCD_EDP_CONFIG_CAP_INVERTED_TRAINING_BIT_YES (0x00000001) /* R-XUV */ 143 #define NV_DPCD_EDP_CONFIG_CAP_DISPLAY_CONTROL_CAPABLE 3:3 /* R-XUF */ 144 #define NV_DPCD_EDP_CONFIG_CAP_DISPLAY_CONTROL_CAPABLE_NO (0x00000000) /* R-XUV */ 145 #define NV_DPCD_EDP_CONFIG_CAP_DISPLAY_CONTROL_CAPABLE_YES (0x00000001) /* R-XUV */ 146 147 #define NV_DPCD_TRAINING_AUX_RD_INTERVAL (0x0000000E) /* R-XUR */ 148 #define NV_DPCD_TRAINING_AUX_RD_INTERVAL_VAL 6:0 /* R-XUF */ 149 #define NV_DPCD_TRAINING_AUX_RD_INTERVAL_VAL_DEFAULT (0x00000000) /* R-XUV */ 150 #define NV_DPCD_TRAINING_AUX_RD_INTERVAL_VAL_4MS (0x00000001) /* R-XUV */ 151 #define NV_DPCD_TRAINING_AUX_RD_INTERVAL_VAL_8MS (0x00000002) /* R-XUV */ 152 #define NV_DPCD_TRAINING_AUX_RD_INTERVAL_VAL_12MS (0x00000003) /* R-XUV */ 153 #define NV_DPCD_TRAINING_AUX_RD_INTERVAL_VAL_16MS (0x00000004) /* R-XUV */ 154 155 #define NV_DPCD_ADAPTER_CAP (0x0000000F) /* R-XUR */ 156 #define NV_DPCD_ADAPTER_CAP_FORCE_LOAD_SENSE 0:0 /* R-XUF */ 157 #define NV_DPCD_ADAPTER_CAP_FORCE_LOAD_SENSE_NO (0x00000000) /* R-XUV */ 158 #define NV_DPCD_ADAPTER_CAP_FORCE_LOAD_SENSE_YES (0x00000001) /* R-XUV */ 159 #define NV_DPCD_ADAPTER_CAP_ALT_I2C_PATTERN 1:1 /* R-XUF */ 160 #define NV_DPCD_ADAPTER_CAP_ALT_I2C_PATTERN_NO (0x00000000) /* R-XUV */ 161 #define NV_DPCD_ADAPTER_CAP_ALT_I2C_PATTERN_YES (0x00000001) /* R-XUV */ 162 163 #define NV_DPCD_SUPPORTED_LINK_RATES(i) (0x00000010+(i)*2) /* R--2A */ 164 #define NV_DPCD_SUPPORTED_LINK_RATES__SIZE (0x00000008) /* R---S */ 165 166 // 00010h-0001Fh: RESERVED. Reads all 0s 167 168 #define NV_DPCD_SINK_VIDEO_FALLBACK_FORMATS (0x00000020) /* R-XUR */ 169 #define NV_DPCD_SINK_VIDEO_FALLBACK_FORMATS_1024_768 0:0 /* R-XUF */ 170 #define NV_DPCD_SINK_VIDEO_FALLBACK_FORMATS_1024_768_NO (0X00000000) /* R-XUF */ 171 #define NV_DPCD_SINK_VIDEO_FALLBACK_FORMATS_1024_768_YES (0X00000001) /* R-XUF */ 172 #define NV_DPCD_SINK_VIDEO_FALLBACK_FORMATS_1280_720 1:1 /* R-XUV */ 173 #define NV_DPCD_SINK_VIDEO_FALLBACK_FORMATS_1280_720_NO (0X00000000) /* R-XUF */ 174 #define NV_DPCD_SINK_VIDEO_FALLBACK_FORMATS_1280_720_YES (0X00000001) /* R-XUF */ 175 #define NV_DPCD_SINK_VIDEO_FALLBACK_FORMATS_1920_1080 2:2 /* R-XUV */ 176 #define NV_DPCD_SINK_VIDEO_FALLBACK_FORMATS_1920_1080_NO (0X00000000) /* R-XUF */ 177 #define NV_DPCD_SINK_VIDEO_FALLBACK_FORMATS_1920_1080_YES (0X00000001) /* R-XUF */ 178 179 #define NV_DPCD_MSTM (0x00000021) /* R-XUR */ 180 #define NV_DPCD_MSTM_CAP 0:0 /* R-XUF */ 181 #define NV_DPCD_MSTM_CAP_NO (0x00000000) /* R-XUV */ 182 #define NV_DPCD_MSTM_CAP_YES (0x00000001) /* R-XUV */ 183 184 #define NV_DPCD_NUMBER_OF_AUDIO_ENDPOINTS (0x00000022) /* R-XUR */ 185 #define NV_DPCD_NUMBER_OF_AUDIO_ENDPOINTS_VALUE 7:0 /* R-XUF */ 186 187 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY (0x00000023) /* R-XUR */ 188 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_AG_FACTOR 3:0 /* R-XUF */ 189 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_AG_FACTOR_3MS (0x00000000) /* R-XUV */ 190 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_AG_FACTOR_2MS (0x00000001) /* R-XUV */ 191 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_AG_FACTOR_1MS (0x00000002) /* R-XUV */ 192 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_AG_FACTOR_500US (0x00000003) /* R-XUV */ 193 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_AG_FACTOR_200US (0x00000004) /* R-XUV */ 194 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_AG_FACTOR_100US (0x00000005) /* R-XUV */ 195 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_AG_FACTOR_10US (0x00000006) /* R-XUV */ 196 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_AG_FACTOR_1US (0x00000007) /* R-XUV */ 197 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_AG_FACTOR_DEFAULT NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_AG_FACTOR_2MS 198 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_VG_FACTOR 7:4 /* R-XUF */ 199 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_VG_FACTOR_3MS (0x00000000) /* R-XUV */ 200 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_VG_FACTOR_2MS (0x00000001) /* R-XUV */ 201 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_VG_FACTOR_1MS (0x00000002) /* R-XUV */ 202 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_VG_FACTOR_500US (0x00000003) /* R-XUV */ 203 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_VG_FACTOR_200US (0x00000004) /* R-XUV */ 204 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_VG_FACTOR_100US (0x00000005) /* R-XUV */ 205 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_VG_FACTOR_DEFAULT NV_DPCD_AV_SYNC_DATA_BLOCK_AV_GRANULARITY_VG_FACTOR_2MS 206 207 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AUD_DEC_LAT_0 (0x00000024) /* R-XUR */ 208 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AUD_DEC_LAT_1 (0x00000025) /* R-XUR */ 209 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AUD_PP_LAT_0 (0x00000026) /* R-XUR */ 210 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AUD_PP_LAT_1 (0x00000027) /* R-XUR */ 211 #define NV_DPCD_AV_SYNC_DATA_BLOCK_VID_INTER_LAT (0x00000028) /* R-XUR */ 212 #define NV_DPCD_AV_SYNC_DATA_BLOCK_VID_PROG_LAT (0x00000029) /* R-XUR */ 213 #define NV_DPCD_AV_SYNC_DATA_BLOCK_REP_LAT (0x0000002A) /* R-XUR */ 214 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AUD_DEL_INS_0 (0x0000002B) /* R-XUR */ 215 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AUD_DEL_INS_1 (0x0000002C) /* R-XUR */ 216 #define NV_DPCD_AV_SYNC_DATA_BLOCK_AUD_DEL_INS_2 (0x0000002D) /* R-XUR */ 217 218 // 0002Eh - 0002Fh: RESERVED. Reads all 0s 219 220 #define NV_DPCD_GUID (0x00000030) /* R-XUR */ 221 222 // 00040h - 00053h: RESERVED. Reads all 0s 223 224 #define NV_DPCD_RX_GTC_VALUE(i) (0x00000054+(i)) /* R--1A */ 225 #define NV_DPCD_RX_GTC_VALUE__SIZE 4 /* R---S */ 226 227 #define NV_DPCD_RX_GTC_REQ (0x00000058) /* R-XUR */ 228 #define NV_DPCD_RX_GTC_REQ_RX_GTC_MSTR_REQ 0:0 /* R-XUF */ 229 #define NV_DPCD_RX_GTC_REQ_RX_GTC_MSTR_REQ_NO (0x00000000) /* R-XUV */ 230 #define NV_DPCD_RX_GTC_REQ_RX_GTC_MSTR_REQ_YES (0x00000001) /* R-XUV */ 231 #define NV_DPCD_RX_GTC_REQ_TX_GTC_VALUE_PHASE_SKEW_EN 1:1 /* R-XUF */ 232 #define NV_DPCD_RX_GTC_REQ_TX_GTC_VALUE_PHASE_SKEW_EN_NO (0x00000000) /* R-XUV */ 233 #define NV_DPCD_RX_GTC_REQ_TX_GTC_VALUE_PHASE_SKEW_EN_YES (0x00000001) /* R-XUV */ 234 235 #define NV_DPCD_RX_GTC_FREQ_LOCK (0x00000059) /* R-XUR */ 236 #define NV_DPCD_RX_GTC_FREQ_LOCK_DONE 0:0 /* R-XUF */ 237 #define NV_DPCD_RX_GTC_FREQ_LOCK_DONE_NO (0x00000000) /* R-XUV */ 238 #define NV_DPCD_RX_GTC_FREQ_LOCK_DONE_YES (0x00000001) /* R-XUV */ 239 240 // 0005Ah - 0006Fh: RESERVED Read all 0s 241 242 #define NV_DPCD_EDP_PSR_VERSION (0x00000070) /* R-XUR */ 243 244 #define NV_DPCD_EDP_PSR_CAP (0x00000071) /* R-XUR */ 245 #define NV_DPCD_EDP_PSR_CAP_LT_NEEDED 0:0 /* R-XUF */ 246 #define NV_DPCD_EDP_PSR_CAP_LT_NEEDED_YES (0x00000000) /* R-XUV */ 247 #define NV_DPCD_EDP_PSR_CAP_LT_NEEDED_NO (0x00000001) /* R-XUV */ 248 #define NV_DPCD_EDP_PSR_CAP_SETUP_TIME 3:1 /* R-XUF */ 249 #define NV_DPCD_EDP_PSR_CAP_SETUP_TIME_330US (0x00000000) /* R-XUV */ 250 #define NV_DPCD_EDP_PSR_CAP_SETUP_TIME_275US (0x00000001) /* R-XUV */ 251 #define NV_DPCD_EDP_PSR_CAP_SETUP_TIME_220US (0x00000002) /* R-XUV */ 252 #define NV_DPCD_EDP_PSR_CAP_SETUP_TIME_165US (0x00000003) /* R-XUV */ 253 #define NV_DPCD_EDP_PSR_CAP_SETUP_TIME_110US (0x00000004) /* R-XUV */ 254 #define NV_DPCD_EDP_PSR_CAP_SETUP_TIME_55US (0x00000005) /* R-XUV */ 255 #define NV_DPCD_EDP_PSR_CAP_SETUP_TIME_0US (0x00000006) /* R-XUV */ 256 #define NV_DPCD_EDP_PSR_CAP_Y_COORD_NEEDED 4:4 /* R-XUF */ 257 #define NV_DPCD_EDP_PSR_CAP_Y_COORD_NEEDED_NO (0x00000000) /* R-XUF */ 258 #define NV_DPCD_EDP_PSR_CAP_Y_COORD_NEEDED_YES (0x00000001) /* R-XUF */ 259 #define NV_DPCD_EDP_PSR_CAP_GRAN_REQUIRED 5:5 /* R-XUF */ 260 #define NV_DPCD_EDP_PSR_CAP_GRAN_REQUIRED_NO (0x00000000) /* R-XUF */ 261 #define NV_DPCD_EDP_PSR_CAP_GRAN_REQUIRED_YES (0x00000001) /* R-XUF*/ 262 263 #define NV_DPCD_EDP_PSR2_X_GRANULARITY_L (0x00000072) /* R-XUR */ 264 #define NV_DPCD_EDP_PSR2_X_GRANULARITY_H (0x00000073) /* R-XUR */ 265 #define NV_DPCD_EDP_PSR2_Y_GRANULARITY (0x00000074) /* R-XUR */ 266 267 // 00072h - 0007Fh: RESERVED Read all 0s 268 269 /* 270 * When DETAILED_CAP_INFO_AVAILABLE = 0, 1 byte info per port. 271 * When DETAILED_CAP_INFO_AVAILABLE = 1, 4 bytes info per port. 272 * DETAILED_CAP_INFO_AVAILABLE located at 0x05h (DOWNSTREAMPORT_PRESENT), bit 5 273 * 274 * Byte 0 definition. 275 */ 276 277 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT(i) (0x00000080+(i)*4) /* R--1A */ 278 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT__SIZE 4 /* R---S */ 279 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_TX_TYPE 2:0 /* R-XUF */ 280 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_TX_TYPE_DISPLAYPORT (0x00000000) /* R-XUV */ 281 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_TX_TYPE_ANALOG (0x00000001) /* R-XUV */ 282 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_TX_TYPE_DVI (0x00000002) /* R-XUV */ 283 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_TX_TYPE_HDMI (0x00000003) /* R-XUV */ 284 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_TX_TYPE_OTHERS_NO_EDID (0x00000004) /* R-XUV */ 285 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_TX_TYPE_DP_PLUSPLUS (0x00000005) /* R-XUV */ 286 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_HPD 3:3 /* R-XUF */ 287 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_HPD_NOT_AWARE (0x00000000) /* R-XUV */ 288 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_HPD_AWARE (0x00000001) /* R-XUV */ 289 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_NON_EDID_ATTR 7:4 /* R-XUF */ 290 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_NON_EDID_480I_60HZ (0x00000001) /* R-XUV */ // 720x480i 291 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_NON_EDID_480I_50HZ (0x00000002) /* R-XUV */ // 720x480i 292 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_NON_EDID_1080I_60HZ (0x00000003) /* R-XUV */ 293 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_NON_EDID_1080I_50HZ (0x00000004) /* R-XUV */ 294 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_NON_EDID_720P_60HZ (0x00000005) /* R-XUV */ 295 #define NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_NON_EDID_720P_50HZ (0x00000007) /* R-XUV */ 296 297 /* 298 * Byte 1, Reserved for DisplayPort. 299 */ 300 301 #define NV_DPCD_DETAILED_CAP_INFO_ONE(i) (0x00000081+(i)*4) /* R--1A */ 302 #define NV_DPCD_DETAILED_CAP_INFO__SIZE NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT__SIZE 303 #define NV_DPCD_DETAILED_CAP_INFO_ONE__SIZE 4 /* R---S */ 304 // For Analog VGA Donwstream Port. Maximum Pixel Rate in Mpixels per sec divided by 8 305 #define NV_DPCD_DETAILED_CAP_INFO_VGA_MAX_PIXEL_RATE 7:0 /* R-XUF */ 306 /* 307 * For DVI/HDMI/DP++ Downstream Port, Maximum TMDS clock rate supported in Mbps divided by 2.5 308 * e.g. 66 (0x42) for 165 MHz, 90 (0x5a) for 225 MHz 309 */ 310 #define NV_DPCD_DETAILED_CAP_INFO_TMDS_MAX_CLOCK_RATE 7:0 /* R-XUF */ 311 312 // Byte 2, for VGA/DVI/HDMI/DP++ Downstream Port, reserved for DisplayPort. 313 #define NV_DPCD_DETAILED_CAP_INFO_TWO(i) (0x00000082+(i)*4) /* R--1A */ 314 #define NV_DPCD_DETAILED_CAP_INFO_TWO__SIZE 4 /* R---S */ 315 #define NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF 1:0 /* R-XUF */ 316 #define NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_8BPC (0x00000000) /* R-XUV */ 317 #define NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_10BPC (0x00000001) /* R-XUV */ 318 #define NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_12BPC (0x00000002) /* R-XUV */ 319 #define NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_16BPC (0x00000003) /* R-XUV */ 320 #define NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT 4:2 /* R-XUF */ 321 #define NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_ZERO (0x00000000) /* R-XUV */ 322 #define NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_9G (0x00000001) /* R-XUV */ 323 #define NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_18G (0x00000002) /* R-XUV */ 324 #define NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_24G (0x00000003) /* R-XUV */ 325 #define NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_32G (0x00000004) /* R-XUV */ 326 #define NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_40G (0x00000005) /* R-XUV */ 327 #define NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_48G (0x00000006) /* R-XUV */ 328 #define NV_DPCD_DETAILED_CAP_INFO_SRC_CONTROL_MODE_SUPPORT 5:5 /* R-XUF */ 329 #define NV_DPCD_DETAILED_CAP_INFO_SRC_CONTROL_MODE_SUPPORT_NO (0x00000000) /* R-XUV */ 330 #define NV_DPCD_DETAILED_CAP_INFO_SRC_CONTROL_MODE_SUPPORT_YES (0x00000001) /* R-XUV */ 331 #define NV_DPCD_DETAILED_CAP_INFO_CONCURRENT_LT_SUPPORT 6:6 /* R-XUF */ 332 #define NV_DPCD_DETAILED_CAP_INFO_CONCURRENT_LT_SUPPORT_NO (0x00000000) /* R-XUV */ 333 #define NV_DPCD_DETAILED_CAP_INFO_CONCURRENT_LT_SUPPORT_YES (0x00000001) /* R-XUV */ 334 335 #define NV_MAX_BPC_8 8 336 #define NV_MAX_BPC_10 10 337 #define NV_MAX_BPC_12 12 338 #define NV_MAX_BPC_16 16 339 340 // Byte 3, Reserved for DisplayPort and VGA 341 #define NV_DPCD_DETAILED_CAP_INFO_THREE(i) (0x00000083+(i)*4) /* R--1A */ 342 #define NV_DPCD_DETAILED_CAP_INFO_THREE__SIZE 4 /* R---S */ 343 // For DVI 344 #define NV_DPCD_DETAILED_CAP_INFO_DVI_DUAL_LINK 1:1 /* R-XUF */ 345 #define NV_DPCD_DETAILED_CAP_INFO_DVI_DUAL_LINK_NO (0x00000000) /* R-XUV */ 346 #define NV_DPCD_DETAILED_CAP_INFO_DVI_DUAL_LINK_YES (0x00000001) /* R-XUV */ 347 #define NV_DPCD_DETAILED_CAP_INFO_DVI_HIGH_COLOR_DEPTH 2:2 /* R-XUF */ 348 #define NV_DPCD_DETAILED_CAP_INFO_DVI_HIGH_COLOR_DEPTH_NO (0x00000000) /* R-XUV */ 349 #define NV_DPCD_DETAILED_CAP_INFO_DVI_HIGH_COLOR_DEPTH_YES (0x00000001) /* R-XUV */ 350 // For HDMI and DP++ 351 #define NV_DPCD_DETAILED_CAP_INFO_FRAME_SEQ_TO_FRAME_PACK 0:0 /* R-XUF */ 352 #define NV_DPCD_DETAILED_CAP_INFO_FRAME_SEQ_TO_FRAME_PACK_NO (0x00000000) /* R-XUV */ 353 #define NV_DPCD_DETAILED_CAP_INFO_FRAME_SEQ_TO_FRAME_PACK_YES (0x00000001) /* R-XUV */ 354 // For HDMI-PCon 355 #define NV_DPCD_DETAILED_CAP_YCBCR422_PASS_THRU_SUPPORTED 1:1 /* R-XUF */ 356 #define NV_DPCD_DETAILED_CAP_YCBCR422_PASS_THRU_SUPPORTED_NO (0x00000000) /* R-XUV */ 357 #define NV_DPCD_DETAILED_CAP_YCBCR422_PASS_THRU_SUPPORTED_YES (0x00000001) /* R-XUV */ 358 #define NV_DPCD_DETAILED_CAP_YCBCR420_PASS_THRU_SUPPORTED 2:2 /* R-XUF */ 359 #define NV_DPCD_DETAILED_CAP_YCBCR420_PASS_THRU_SUPPORTED_NO (0x00000000) /* R-XUV */ 360 #define NV_DPCD_DETAILED_CAP_YCBCR420_PASS_THRU_SUPPORTED_YES (0x00000001) /* R-XUV */ 361 #define NV_DPCD_DETAILED_CAP_CONV_YCBCR444_TO_YCBCR422_SUPPORTED 3:3 /* R-XUF */ 362 #define NV_DPCD_DETAILED_CAP_CONV_YCBCR444_TO_YCBCR422_SUPPORTED_NO (0x00000000) /* R-XUV */ 363 #define NV_DPCD_DETAILED_CAP_CONV_YCBCR444_TO_YCBCR422_SUPPORTED_YES (0x00000001) /* R-XUV */ 364 #define NV_DPCD_DETAILED_CAP_CONV_YCBCR444_TO_YCBCR420_SUPPORTED 4:4 /* R-XUF */ 365 #define NV_DPCD_DETAILED_CAP_CONV_YCBCR444_TO_YCBCR420_SUPPORTED_NO (0x00000000) /* R-XUV */ 366 #define NV_DPCD_DETAILED_CAP_CONV_YCBCR444_TO_YCBCR420_SUPPORTED_YES (0x00000001) /* R-XUV */ 367 #define NV_DPCD_DETAILED_CAP_CONV_RGB601_TO_YCBCR601_SUPPORTED 5:5 /* R-XUF */ 368 #define NV_DPCD_DETAILED_CAP_CONV_RGB601_TO_YCBCR601_SUPPORTED_NO (0x00000000) /* R-XUV */ 369 #define NV_DPCD_DETAILED_CAP_CONV_RGB601_TO_YCBCR601_SUPPORTED_YES (0x00000001) /* R-XUV */ 370 #define NV_DPCD_DETAILED_CAP_CONV_RGB709_TO_YCBCR709_SUPPORTED 6:6 /* R-XUF */ 371 #define NV_DPCD_DETAILED_CAP_CONV_RGB709_TO_YCBCR709_SUPPORTED_NO (0x00000000) /* R-XUV */ 372 #define NV_DPCD_DETAILED_CAP_CONV_RGB709_TO_YCBCR709_SUPPORTED_YES (0x00000001) /* R-XUV */ 373 #define NV_DPCD_DETAILED_CAP_CONV_RGBBT2020_TO_YCBCRBT2020_SUPPORTED 7:7 /* R-XUF */ 374 #define NV_DPCD_DETAILED_CAP_CONV_RGBBT2020_TO_YCBCRBT2020_SUPPORTED_NO (0x00000000) /* R-XUV */ 375 #define NV_DPCD_DETAILED_CAP_CONV_RGBBT2020_TO_YCBCRBT2020_SUPPORTED_YES (0x00000001) /* R-XUV */ 376 377 /* 378 00090h - 000FFh: RESERVED for supporting up to 127 Downstream devices per Branch device. Read all 0s 379 Note: When DETAILED_CAP_INFO_AVAILABLE bit is set to 1, the maximum 380 number of Downstream ports will be limited to 32. 381 */ 382 383 #define NV_DPCD_LINK_BANDWIDTH_SET (0x00000100) /* RWXUR */ 384 #define NV_DPCD_LINK_BANDWIDTH_SET_VAL 7:0 /* RWXUF */ 385 #define NV_DPCD_LINK_BANDWIDTH_SET_VAL_1_62_GPBS (0x00000006) /* RWXUV */ 386 #define NV_DPCD_LINK_BANDWIDTH_SET_VAL_2_70_GPBS (0x0000000a) /* RWXUV */ 387 #define NV_DPCD_LINK_BANDWIDTH_SET_VAL_5_40_GPBS (0x00000014) /* RWXUV */ 388 389 #define NV_DPCD_LANE_COUNT_SET (0x00000101) /* RWXUR */ 390 #define NV_DPCD_LANE_COUNT_SET_LANE 4:0 /* RWXUF */ 391 #define NV_DPCD_LANE_COUNT_SET_LANE_1 (0x00000001) /* RWXUV */ 392 #define NV_DPCD_LANE_COUNT_SET_LANE_2 (0x00000002) /* RWXUV */ 393 #define NV_DPCD_LANE_COUNT_SET_LANE_4 (0x00000004) /* RWXUV */ 394 #define NV_DPCD_LANE_COUNT_SET_POST_LT_ADJ_REQ_GRANTED 5:5 /* RWXUF */ 395 #define NV_DPCD_LANE_COUNT_SET_POST_LT_ADJ_REQ_GRANTED_NO (0x00000000) /* RWXUV */ 396 #define NV_DPCD_LANE_COUNT_SET_POST_LT_ADJ_REQ_GRANTED_YES (0x00000001) /* RWXUV */ 397 #define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING 7:7 /* RWXUF */ 398 #define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_FALSE (0x00000000) /* RWXUV */ 399 #define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_TRUE (0x00000001) /* RWXUV */ 400 401 #define NV_DPCD_TRAINING_PATTERN_SET (0x00000102) /* RWXUR */ 402 #define NV_DPCD_TRAINING_PATTERN_SET_TPS 1:0 /* RWXUF */ 403 #define NV_DPCD_TRAINING_PATTERN_SET_TPS_NONE (0x00000000) /* RWXUV */ 404 #define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1 (0x00000001) /* RWXUV */ 405 #define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP2 (0x00000002) /* RWXUV */ 406 #define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP3 (0x00000003) /* RWXUV */ 407 #define NV_DPCD_TRAINING_PATTERN_SET_LQPS 3:2 /* R-XUF */ 408 #define NV_DPCD_TRAINING_PATTERN_SET_LQPS_NO (0x00000000) /* R-XUV */ 409 #define NV_DPCD_TRAINING_PATTERN_SET_LQPS_D10_2_TP (0x00000001) /* R-XUV */ 410 #define NV_DPCD_TRAINING_PATTERN_SET_LQPS_SYM_ERR_RATE_TP (0x00000002) /* R-XUV */ 411 #define NV_DPCD_TRAINING_PATTERN_SET_LQPS_PRBS7 (0x00000003) /* R-XUV */ 412 #define NV_DPCD_TRAINING_PATTERN_SET_RECOVERED_CLOCK_OUT_EN 4:4 /* RWXUF */ 413 #define NV_DPCD_TRAINING_PATTERN_SET_RECOVERED_CLOCK_OUT_EN_NO (0x00000000) /* RWXUV */ 414 #define NV_DPCD_TRAINING_PATTERN_SET_RECOVERED_CLOCK_OUT_EN_YES (0x00000001) /* RWXUV */ 415 #define NV_DPCD_TRAINING_PATTERN_SET_SCRAMBLING_DISABLED 5:5 /* RWXUF */ 416 #define NV_DPCD_TRAINING_PATTERN_SET_SCRAMBLING_DISABLED_FALSE (0x00000000) /* RWXUV */ 417 #define NV_DPCD_TRAINING_PATTERN_SET_SCRAMBLING_DISABLED_TRUE (0x00000001) /* RWXUV */ 418 #define NV_DPCD_TRAINING_PATTERN_SET_SYM_ERR_SEL 7:6 /* RWXUF */ 419 #define NV_DPCD_TRAINING_PATTERN_SET_SYM_ERR_SEL_DISPARITY_ILLEGAL_SYMBOL_ERROR (0x00000000) /* RWXUV */ 420 #define NV_DPCD_TRAINING_PATTERN_SET_SYM_ERR_SEL_DISPARITY_ERROR (0x00000001) /* RWXUV */ 421 #define NV_DPCD_TRAINING_PATTERN_SET_SYM_ERR_SEL_ILLEGAL_SYMBOL_ERROR (0x00000002) /* RWXUV */ 422 423 #define NV_DPCD_TRAINING_LANE_SET(i) (0x00000103+(i)) /* RW-1A */ 424 #define NV_DPCD_TRAINING_LANE_SET__SIZE 4 /* RW--S */ 425 #define NV_DPCD_TRAINING_LANE_SET_VOLTAGE_SWING 1:0 /* RWXUF */ 426 #define NV_DPCD_TRAINING_LANE_SET_VOLTAGE_SWING_MAX_REACHED 2:2 /* RWXUF */ 427 #define NV_DPCD_TRAINING_LANE_SET_VOLTAGE_SWING_MAX_REACHED_TRUE (0x00000001) /* RWXUV */ 428 #define NV_DPCD_TRAINING_LANE_SET_PREEMPHASIS 4:3 /* RWXUF */ 429 #define NV_DPCD_TRAINING_LANE_SET_PREEMPHASIS_MAX_REACHED 5:5 /* RWXUF */ 430 #define NV_DPCD_TRAINING_LANE_SET_PREEMPHASIS_MAX_REACHED_TRUE (0x00000001) /* RWXUV */ 431 #define NV_DPCD_TRAINING_LANE0_SET (0x00000103) /* RWXUR */ 432 433 #define NV_DPCD_MAX_VOLTAGE_SWING (0x00000003) /* RWXUV */ 434 #define NV_DPCD_MAX_VOLTAGE_PREEMPHASIS (0x00000003) /* RWXUV */ 435 436 #define NV_DPCD_TRAINING_LANE1_SET (0x00000104) /* RWXUR */ 437 #define NV_DPCD_TRAINING_LANE2_SET (0x00000105) /* RWXUR */ 438 #define NV_DPCD_TRAINING_LANE3_SET (0x00000106) /* RWXUR */ 439 #define NV_DPCD_TRAINING_LANEX_SET_DRIVE_CURRENT 1:0 /* RWXUF */ 440 #define NV_DPCD_TRAINING_LANEX_SET_DRIVE_CURRENT_MAX_REACHED 2:2 /* RWXUF */ 441 #define NV_DPCD_TRAINING_LANEX_SET_DRIVE_CURRENT_MAX_REACHED_TRUE (0x00000001) /* RWXUV */ 442 #define NV_DPCD_TRAINING_LANEX_SET_PREEMPHASIS 4:3 /* RWXUF */ 443 #define NV_DPCD_TRAINING_LANEX_SET_PREEMPHASIS_MAX_REACHED 5:5 /* RWXUF */ 444 #define NV_DPCD_TRAINING_LANEX_SET_PREEMPHASIS_MAX_REACHED_TRUE (0x00000001) /* RWXUV */ 445 446 #define NV_DPCD_DOWNSPREAD_CTRL (0x00000107) /* RWXUR */ 447 #define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP 4:4 /* RWXUF */ 448 #define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE (0x00000000) /* RWXUV */ 449 #define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LESS_THAN_0_5 (0x00000001) /* RWXUV */ 450 #define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED 7:7 /* RWXUF */ 451 #define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED_FALSE (0x00000000) /* RWXUV */ 452 #define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED_TRUE (0x00000001) /* RWXUV */ 453 454 #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET (0x00000108) /* RWXUR */ 455 #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B_10B 0:0 /* RWXUF */ 456 #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B_10B_FALSE (0x00000000) /* RWXUV */ 457 #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B_10B_TRUE (0x00000001) /* RWXUV */ 458 #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_128B_132B 1:1 /* RWXUF */ 459 #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_128B_132B_FALSE (0x00000000) /* RWXUV */ 460 #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_128B_132B_TRUE (0x00000001) /* RWXUV */ 461 462 #define NV_DPCD_I2C_CTRL_SET (0x00000109) /* RWXUR */ 463 #define NV_DPCD_I2C_CTRL_SET_SPEED 7:0 /* RWXUF */ 464 #define NV_DPCD_I2C_CTRL_SET_SPEED_DEFAULT (0x00000000) /* RWXUV */ 465 #define NV_DPCD_I2C_CTRL_SET_SPEED_1K (0x00000001) /* RWXUV */ 466 #define NV_DPCD_I2C_CTRL_SET_SPEED_5K (0x00000002) /* RWXUV */ 467 #define NV_DPCD_I2C_CTRL_SET_SPEED_10K (0x00000004) /* RWXUV */ 468 #define NV_DPCD_I2C_CTRL_SET_SPEED_100K (0x00000008) /* RWXUV */ 469 #define NV_DPCD_I2C_CTRL_SET_SPEED_400K (0x00000010) /* RWXUV */ 470 #define NV_DPCD_I2C_CTRL_SET_SPEED_1M (0x00000020) /* RWXUV */ 471 472 #define NV_DPCD_EDP_CONFIG_SET (0x0000010A) /* RWXUR */ 473 #define NV_DPCD_EDP_CONFIG_SET_ALTERNATE_SCRAMBLER_RESET 0:0 /* RWXUF */ 474 #define NV_DPCD_EDP_CONFIG_SET_ALTERNATE_SCRAMBLER_RESET_DISABLE (0x00000000) /* RWXUV */ 475 #define NV_DPCD_EDP_CONFIG_SET_ALTERNATE_SCRAMBLER_RESET_ENABLE (0x00000001) /* RWXUV */ 476 #define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE 1:1 /* RWXUF */ 477 #define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_DISABLE (0x00000000) /* RWXUV */ 478 #define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_ENABLE (0x00000001) /* RWXUV */ 479 #define NV_DPCD_EDP_CONFIG_SET_INVERTED_TRAINING_BIT 2:2 /* RWXUF */ 480 #define NV_DPCD_EDP_CONFIG_SET_INVERTED_TRAINING_BIT_DISABLE (0x00000000) /* RWXUV */ 481 #define NV_DPCD_EDP_CONFIG_SET_INVERTED_TRAINING_BIT_ENABLE (0x00000001) /* RWXUV */ 482 #define NV_DPCD_EDP_CONFIG_SET_PANEL_SELF_TEST 7:7 /* RWXUF */ 483 #define NV_DPCD_EDP_CONFIG_SET_PANEL_SELF_TEST_DISABLE (0x00000000) /* RWXUV */ 484 #define NV_DPCD_EDP_CONFIG_SET_PANEL_SELF_TEST_ENABLE (0x00000001) /* RWXUV */ 485 486 #define NV_DPCD_LINK_QUAL_LANE_SET(i) (0x0000010B+(i)) /* RW-1A */ 487 #define NV_DPCD_LINK_QUAL_LANE_SET__SIZE 4 /* RW--S */ 488 #define NV_DPCD_LINK_QUAL_LANE_SET_LQS 2:0 /* RWXUF */ 489 #define NV_DPCD_LINK_QUAL_LANE_SET_LQS_NO (0x00000000) /* RWXUV */ 490 #define NV_DPCD_LINK_QUAL_LANE_SET_LQS_D10_2 (0x00000001) /* RWXUV */ 491 #define NV_DPCD_LINK_QUAL_LANE_SET_LQS_SYM_ERR_MEASUREMENT_CNT (0x00000002) /* RWXUV */ 492 #define NV_DPCD_LINK_QUAL_LANE_SET_LQS_PRBS7 (0x00000003) /* RWXUV */ 493 #define NV_DPCD_LINK_QUAL_LANE_SET_LQS_80_BIT_CUSTOM (0x00000004) /* RWXUV */ 494 #define NV_DPCD_LINK_QUAL_LANE_SET_LQS_HBR2 (0x00000005) /* RWXUV */ 495 496 #define NV_DPCD_TRAINING_LANE0_1_SET2 (0x0000010F) /* RWXUR */ 497 #define NV_DPCD_TRAINING_LANE2_3_SET2 (0x00000110) /* RWXUR */ 498 #define NV_DPCD_LANEX_XPLUS1_TRAINING_LANEX_SET2_POST_CURSOR2 1:0 /* RWXUF */ 499 #define NV_DPCD_LANEX_XPLUS1_TRAINING_LANEX_SET2_POST_CURSOR2_MAX_REACHED 2:2 /* RWXUF */ 500 #define NV_DPCD_LANEX_XPLUS1_TRAINING_LANEX_SET2_POST_CURSOR2_MAX_REACHED_TRUE (0x00000001) /* RWXUV */ 501 #define NV_DPCD_LANEX_XPLUS1_TRAINING_LANEXPLUS1_SET2_POST_CURSOR2 5:4 /* RWXUF */ 502 #define NV_DPCD_LANEX_XPLUS1_TRAINING_LANEXPLUS1_SET2_POST_CURSOR2_MAX_REACHED 6:6 /* RWXUF */ 503 #define NV_DPCD_LANEX_XPLUS1_TRAINING_LANEXPLUS1_SET2_POST_CURSOR2_MAX_REACHED_TRUE (0x00000001) /* RWXUV */ 504 505 #define NV_DPCD_MSTM_CTRL (0x00000111) /* RWXUR */ 506 #define NV_DPCD_MSTM_CTRL_EN 0:0 /* RWXUF */ 507 #define NV_DPCD_MSTM_CTRL_EN_NO (0x00000000) /* RWXUV */ 508 #define NV_DPCD_MSTM_CTRL_EN_YES (0x00000001) /* RWXUV */ 509 #define NV_DPCD_MSTM_CTRL_UP_REQ_EN 1:1 /* RWXUF */ 510 #define NV_DPCD_MSTM_CTRL_UP_REQ_EN_NO (0x00000000) /* RWXUV */ 511 #define NV_DPCD_MSTM_CTRL_UP_REQ_EN_YES (0x00000001) /* RWXUV */ 512 #define NV_DPCD_MSTM_CTRL_UPSTREAM_IS_SRC 2:2 /* RWXUF */ 513 #define NV_DPCD_MSTM_CTRL_UPSTREAM_IS_SRC_NO (0x00000000) /* RWXUV */ 514 #define NV_DPCD_MSTM_CTRL_UPSTREAM_IS_SRC_YES (0x00000001) /* RWXUV */ 515 516 #define NV_DPCD_AUDIO_DELAY(i) (0x00000112+(i)) /* RW-1A */ 517 #define NV_DPCD_AUDIO_DELAY__SIZE 3 /* NNNNS */ 518 519 #define NV_DPCD_LINK_RATE_SET (0x00000115) /* RWXUR */ 520 #define NV_DPCD_LINK_RATE_SET_VAL 2:0 /* RWXUF */ 521 522 // 00115h - 00117h: RESERVED. Reads all 0s 523 524 #define NV_DPCD_UPSTREAM_DEV_DP_PWR (0x00000118) /* RWXUR */ 525 #define NV_DPCD_UPSTREAM_DEV_DP_PWR_NOT_NEEDED 0:0 /* RWXUF */ 526 #define NV_DPCD_UPSTREAM_DEV_DP_PWR_NOT_NEEDED_FALSE (0x00000000) /* RWXUV */ 527 #define NV_DPCD_UPSTREAM_DEV_DP_PWR_NOT_NEEDED_TRUE (0x00000001) /* RWXUV */ 528 529 #define NV_DPCD_EXTENDED_DPRX_WAKE_TIMEOUT (0x00000119) /* RWXUR */ 530 #define NV_DPCD_EXTENDED_DPRX_WAKE_TIMEOUT_PERIOD_GRANTED 0:0 /* RWXUF */ 531 #define NV_DPCD_EXTENDED_DPRX_WAKE_TIMEOUT_PERIOD_GRANTED_NO (0x00000000) /* RWXUV */ 532 #define NV_DPCD_EXTENDED_DPRX_WAKE_TIMEOUT_PERIOD_GRANTED_YES (0x00000001) /* RWXUV */ 533 534 // 0011Ah - 0011Fh: RESERVED. Reads all 0s 535 // 00126h - 00153h: RESERVED. Reads all 0s 536 537 #define NV_DPCD_TX_GTC_VALUE(i) (0x00000154+(i)) /* RW-1A */ 538 #define NV_DPCD_TX_GTC_VALUE__SIZE 4 /* R---S */ 539 540 #define NV_DPCD_RX_GTC_VALUE_PHASE_SKEW (0x00000158) /* RWXUR */ 541 #define NV_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN 0:0 /* RWXUF */ 542 #define NV_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN_NO (0x00000000) /* RWXUV */ 543 #define NV_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN_YES (0x00000001) /* RWXUV */ 544 545 #define NV_DPCD_TX_GTC_FREQ_LOCK (0x00000159) /* RWXUR */ 546 #define NV_DPCD_TX_GTC_FREQ_LOCK_DONE 0:0 /* RWXUF */ 547 #define NV_DPCD_TX_GTC_FREQ_LOCK_DONE_NO (0x00000000) /* RWXUV */ 548 #define NV_DPCD_TX_GTC_FREQ_LOCK_DONE_YES (0x00000001) /* RWXUV */ 549 550 // 0015Ah - 0016Fh: RESERVED. Read all 0s 551 552 #define NV_DPCD_EDP_PSR_CONFIG (0x00000170) /* RWXUR */ 553 #define NV_DPCD_EDP_PSR_CONFIG_SINK_ENABLE 0:0 /* RWXUF */ 554 #define NV_DPCD_EDP_PSR_CONFIG_SINK_ENABLE_NO (0x00000000) /* RWXUV */ 555 #define NV_DPCD_EDP_PSR_CONFIG_SINK_ENABLE_YES (0x00000001) /* RWXUV */ 556 #define NV_DPCD_EDP_PSR_CONFIG_SOURCE_LINK_ACTIVE 1:1 /* RWXUF */ 557 #define NV_DPCD_EDP_PSR_CONFIG_SOURCE_LINK_ACTIVE_NO (0x00000000) /* RWXUV */ 558 #define NV_DPCD_EDP_PSR_CONFIG_SOURCE_LINK_ACTIVE_YES (0x00000001) /* RWXUV */ 559 #define NV_DPCD_EDP_PSR_CONFIG_CRC_VERIFICATION_ACTIVE 2:2 /* RWXUF */ 560 #define NV_DPCD_EDP_PSR_CONFIG_CRC_VERIFICATION_ACTIVE_NO (0x00000000) /* RWXUV */ 561 #define NV_DPCD_EDP_PSR_CONFIG_CRC_VERIFICATION_ACTIVE_YES (0x00000001) /* RWXUV */ 562 #define NV_DPCD_EDP_PSR_CONFIG_FRAME_CAPTURE_INDICATION 3:3 /* RWXUF */ 563 #define NV_DPCD_EDP_PSR_CONFIG_FRAME_CAPTURE_INDICATION_IMM (0x00000000) /* RWXUV */ 564 #define NV_DPCD_EDP_PSR_CONFIG_FRAME_CAPTURE_INDICATION_SECOND (0x00000001) /* RWXUV */ 565 #define NV_DPCD_EDP_PSR_CONFIG_SU_LINE_CAPTURE_INDICATION 4:4 /* RWXUF */ 566 #define NV_DPCD_EDP_PSR_CONFIG_SU_LINE_CAPTURE_INDICATION_IMM (0x00000000) /* RWXUV */ 567 #define NV_DPCD_EDP_PSR_CONFIG_SU_LINE_CAPTURE_INDICATION_SECOND (0x00000001) /* RWXUV */ 568 #define NV_DPCD_EDP_PSR_CONFIG_HPD_IRQ_ON_CRC_ERROR 5:5 /* RWXUF */ 569 #define NV_DPCD_EDP_PSR_CONFIG_HPD_IRQ_ON_CRC_ERROR_NO (0x00000000) /* RWXUV */ 570 #define NV_DPCD_EDP_PSR_CONFIG_HPD_IRQ_ON_CRC_ERROR_YES (0x00000001) /* RWXUV */ 571 #define NV_DPCD_EDP_PSR_CONFIG_ENABLE_PSR2 6:6 /* RWXUF */ 572 #define NV_DPCD_EDP_PSR_CONFIG_ENABLE_PSR2_NO (0x00000000) /* RWXUV */ 573 #define NV_DPCD_EDP_PSR_CONFIG_ENABLE_PSR2_YES (0x00000001) /* RWXUV */ 574 575 // 00171h - 0019Fh: RESERVED. Read all 0s 576 577 578 #define NV_DPCD_ADAPTER_CTRL (0x000001A0) /* RWXUR */ 579 #define NV_DPCD_ADAPTER_CTRL_FORCE_LOAD_SENSE 0:0 /* RWXUF */ 580 #define NV_DPCD_ADAPTER_CTRL_FORCE_LOAD_SENSE_NO (0x00000000) /* RWXUV */ 581 #define NV_DPCD_ADAPTER_CTRL_FORCE_LOAD_SENSE_YES (0x00000001) /* RWXUV */ 582 583 #define NV_DPCD_BRANCH_DEV_CTRL (0x000001A1) /* RWXUR */ 584 #define NV_DPCD_BRANCH_DEV_CTRL_HOTPLUG_EVENT_TYPE 0:0 /* RWXUF */ 585 #define NV_DPCD_BRANCH_DEV_CTRL_HOTPLUG_EVENT_TYPE_LONGPULSE (0x00000000) /* RWXUV */ 586 #define NV_DPCD_BRANCH_DEV_CTRL_HOTPLUG_EVENT_TYPE_IRQ_HPD (0x00000001) /* RWXUV */ 587 #define NV_DPCD_BRANCH_DEV_CTRL_HOTPLUG_EVENT_TYPE_DEFAULT NV_DPCD_BRANCH_DEV_CTRL_HOTPLUG_EVENT_TYPE_LONGPULSE 588 589 // 001A2h - 0019Fh: RESERVED. Read all 0s 590 591 #define NV_DPCD_PAYLOAD_ALLOC_SET (0x000001C0) /* RWXUR */ 592 #define NV_DPCD_PAYLOAD_ALLOC_SET_PAYLOAD_ID 6:0 /* RWXUF */ 593 594 #define NV_DPCD_PAYLOAD_ALLOC_START_TIME_SLOT (0x000001C1) /* RWXUR */ 595 #define NV_DPCD_PAYLOAD_ALLOC_START_TIME_SLOT_VAL 5:0 /* RWXUF */ 596 597 #define NV_DPCD_PAYLOAD_ALLOC_TIME_SLOT_COUNT (0x000001C2) /* RWXUR */ 598 #define NV_DPCD_PAYLOAD_ALLOC_TIME_SLOT_COUNT_VAL 5:0 /* RWXUF */ 599 600 // 001C3h - 001FFh: RESERVED. Reads all 0s 601 602 #define NV_DPCD_SINK_COUNT (0x00000200) /* R-XUR */ 603 // Bits 7 and 5:0 = SINK_COUNT 604 #define NV_DPCD_SINK_COUNT_VAL_BIT_05_MASK (0x3F) 605 #define NV_DPCD_SINK_COUNT_VAL_BIT_7 (0x80) 606 #define NV_DPCD_SINK_COUNT_VAL(x) ((x & NV_DPCD_SINK_COUNT_VAL_BIT_05_MASK) \ 607 | ((x & NV_DPCD_SINK_COUNT_VAL_BIT_7) >> 1)) 608 #define NV_DPCD_SINK_COUNT_CP_READY 6:6 /* R-XUF */ 609 #define NV_DPCD_SINK_COUNT_CP_READY_NO (0x00000000) /* R-XUV */ 610 #define NV_DPCD_SINK_COUNT_CP_READY_YES (0x00000001) /* R-XUV */ 611 612 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR (0x00000201) /* RWXUR */ 613 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_REMOTE_CTRL 0:0 /* RWXUF */ 614 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_REMOTE_CTRL_NO (0x00000000) /* RWXUV */ 615 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_REMOTE_CTRL_YES (0x00000001) /* RWXUV */ 616 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST 1:1 /* RWXUF */ 617 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_NO (0x00000000) /* RWXUV */ 618 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_YES (0x00000001) /* RWXUV */ 619 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP 2:2 /* RWXUF */ 620 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_NO (0x00000000) /* RWXUV */ 621 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_YES (0x00000001) /* RWXUV */ 622 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_MCCS_IRQ 3:3 /* RWXUF */ 623 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_MCCS_IRQ_NO (0x00000000) /* RWXUV */ 624 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_MCCS_IRQ_YES (0x00000001) /* RWXUV */ 625 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_DOWN_REP_MSG_RDY 4:4 /* RWXUF */ 626 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_DOWN_REP_MSG_RDY_NO (0x00000000) /* RWXUV */ 627 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_DOWN_REP_MSG_RDY_YES (0x00000001) /* RWXUV */ 628 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_UP_REQ_MSG_RDY 5:5 /* RWXUF */ 629 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_UP_REQ_MSG_RDY_NO (0x00000000) /* RWXUV */ 630 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_UP_REQ_MSG_RDY_YES (0x00000001) /* RWXUV */ 631 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_SINK_SPECIFIC_IRQ 6:6 /* RWXUF */ 632 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_SINK_SPECIFIC_IRQ_NO (0x00000000) /* RWXUV */ 633 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_SINK_SPECIFIC_IRQ_YES (0x00000001) /* RWXUV */ 634 635 #define NV_DPCD_LANE0_1_STATUS (0x00000202) /* R-XUR */ 636 637 #define NV_DPCD_LANE2_3_STATUS (0x00000203) /* R-XUR */ 638 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEX_CR_DONE 0:0 /* R-XUF */ 639 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEX_CR_DONE_NO (0x00000000) /* R-XUV */ 640 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEX_CR_DONE_YES (0x00000001) /* R-XUV */ 641 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEX_CHN_EQ_DONE 1:1 /* R-XUF */ 642 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000) /* R-XUV */ 643 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001) /* R-XUV */ 644 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEX_SYMBOL_LOCKED 2:2 /* R-XUF */ 645 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000) /* R-XUV */ 646 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001) /* R-XUV */ 647 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEXPLUS1_CR_DONE 4:4 /* R-XUF */ 648 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000) /* R-XUV */ 649 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001) /* R-XUV */ 650 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEXPLUS1_CHN_EQ_DONE 5:5 /* R-XUF */ 651 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000) /* R-XUV */ 652 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001) /* R-XUV */ 653 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEXPLUS1_SYMBOL_LOCKED 6:6 /* R-XUF */ 654 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000) /* R-XUV */ 655 #define NV_DPCD_LANEX_XPLUS1_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001) /* R-XUV */ 656 657 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED (0x00000204) /* R-XUR */ 658 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_INTERLANE_ALIGN_DONE 0:0 /* R-XUF */ 659 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */ 660 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */ 661 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_POST_LT_ADJ_REQ_IN_PROGRESS 1:1 /* R-XUF */ 662 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_POST_LT_ADJ_REQ_IN_PROGRESS_NO (0x00000000) /* R-XUV */ 663 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_POST_LT_ADJ_REQ_IN_PROGRESS_YES (0x00000001) /* R-XUV */ 664 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_D0WNSTRM_PORT_STATUS_DONE 6:6 /* R-XUF */ 665 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_D0WNSTRM_PORT_STATUS_DONE_NO (0x00000000) /* R-XUV */ 666 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_D0WNSTRM_PORT_STATUS_DONE_YES (0x00000001) /* R-XUV */ 667 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED 7:7 /* R-XUF */ 668 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_NO (0x00000000) /* R-XUV */ 669 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_YES (0x00000001) /* R-XUV */ 670 671 #define NV_DPCD_SINK_STATUS (0x00000205) /* R-XUR */ 672 #define NV_DPCD_SINK_STATUS_RECEIVE_PORT_0_STATUS 0:0 /* R-XUF */ 673 #define NV_DPCD_SINK_STATUS_RECEIVE_PORT_0_STATUS_IN_SYNC_NO (0x00000000) /* R-XUV */ 674 #define NV_DPCD_SINK_STATUS_RECEIVE_PORT_0_STATUS_IN_SYNC_YES (0x00000001) /* R-XUV */ 675 #define NV_DPCD_SINK_STATUS_RECEIVE_PORT_1_STATUS 1:1 /* R-XUF */ 676 #define NV_DPCD_SINK_STATUS_RECEIVE_PORT_1_STATUS_IN_SYNC_NO (0x00000000) /* R-XUV */ 677 #define NV_DPCD_SINK_STATUS_RECEIVE_PORT_1_STATUS_IN_SYNC_YES (0x00000001) /* R-XUV */ 678 679 #define NV_DPCD_LANE0_1_ADJUST_REQ (0x00000206) /* R-XUR */ 680 #define NV_DPCD_LANE2_3_ADJUST_REQ (0x00000207) /* R-XUR */ 681 #define NV_DPCD_LANEX_XPLUS1_ADJUST_REQ_LANEX_DRIVE_CURRENT 1:0 /* R-XUF */ 682 #define NV_DPCD_LANEX_XPLUS1_ADJUST_REQ_LANEX_PREEMPHASIS 3:2 /* R-XUF */ 683 #define NV_DPCD_LANEX_XPLUS1_ADJUST_REQ_LANEXPLUS1_DRIVE_CURRENT 5:4 /* R-XUF */ 684 #define NV_DPCD_LANEX_XPLUS1_ADJUST_REQ_LANEXPLUS1_PREEMPHASIS 7:6 /* R-XUF */ 685 686 #define NV_DPCD_TRAINING_SCORE_LANE(i) (0x00000208+(i)) /* R--1A */ 687 #define NV_DPCD_TRAINING_SCORE_LANE__SIZE 4 /* R---S */ 688 689 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2 (0x0000020C) /* R-XUR */ 690 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE(i) i%4*2+1:i%4*2 691 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE0 1:0 /* R-XUF */ 692 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE1 3:2 /* R-XUF */ 693 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE2 5:4 /* R-XUF */ 694 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE3 7:6 /* R-XUF */ 695 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE4 1:0 /* R-XUF */ 696 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE5 3:2 /* R-XUF */ 697 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE6 5:4 /* R-XUF */ 698 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE7 7:6 /* R-XUF */ 699 700 #define NV_DPCD_EDP_LINK_CONFIG_STATUS (0x0000020c) /* RWXUR */ 701 #define NV_DPCD_EDP_LINK_CONFIG_STATUS_SET 0:0 /* R-XUF */ 702 #define NV_DPCD_EDP_LINK_CONFIG_STATUS_SET_LINK_BW (0x00000000) /* R-XUV */ 703 #define NV_DPCD_EDP_LINK_CONFIG_STATUS_SET_LINK_RATE (0x00000001) /* R-XUV */ 704 #define NV_DPCD_EDP_LINK_CONFIG_STATUS_VALID 1:1 /* R-XUF */ 705 #define NV_DPCD_EDP_LINK_CONFIG_STATUS_VALID_NO (0x00000000) /* R-XUV */ 706 #define NV_DPCD_EDP_LINK_CONFIG_STATUS_VALID_YES (0x00000001) /* R-XUV */ 707 708 // 0020Fh: RESERVED. Read all 0s 709 710 #define NV_DPCD_SYMBOL_ERROR_COUNT_LANEX_BYTE0(i) (0x00000210+(i)*2) /* R--1A */ 711 #define NV_DPCD_SYMBOL_ERROR_COUNT_LANEX_BYTE0__SIZE 4 /* R---S */ 712 #define NV_DPCD_SYMBOL_ERROR_COUNT_LANEX_BYTE0_VALUE 7:0 /* R-XUF */ 713 #define NV_DPCD_SYMBOL_ERROR_COUNT_LANEX_BYTE1(i) (0x00000211+(i)*2) /* R--1A */ 714 #define NV_DPCD_SYMBOL_ERROR_COUNT_LANEX_BYTE1__SIZE 4 /* R---S */ 715 #define NV_DPCD_SYMBOL_ERROR_COUNT_LANEX_BYTE1_VALUE 6:0 /* R-XUF */ 716 #define NV_DPCD_SYMBOL_ERROR_COUNT_LANEX_BYTE1_VALID 7:7 /* R-XUF */ 717 718 #define NV_DPCD_TEST_REQUEST (0x00000218) /* R-XUR */ 719 #define NV_DPCD_TEST_REQUEST_TEST_LINK_TRAINING 0:0 /* R-XUF */ 720 #define NV_DPCD_TEST_REQUEST_TEST_LINK_TRAINING_NO (0x00000000) /* R-XUV */ 721 #define NV_DPCD_TEST_REQUEST_TEST_LINK_TRAINING_YES (0x00000001) /* R-XUV */ 722 #define NV_DPCD_TEST_REQUEST_TEST_PATTERN 1:1 /* R-XUF */ 723 #define NV_DPCD_TEST_REQUEST_TEST_PATTERN_NO (0x00000000) /* R-XUV */ 724 #define NV_DPCD_TEST_REQUEST_TEST_PATTERN_YES (0x00000001) /* R-XUV */ 725 #define NV_DPCD_TEST_REQUEST_TEST_EDID_READ 2:2 /* R-XUF */ 726 #define NV_DPCD_TEST_REQUEST_TEST_EDID_READ_NO (0x00000000) /* R-XUV */ 727 #define NV_DPCD_TEST_REQUEST_TEST_EDID_READ_YES (0x00000001) /* R-XUV */ 728 #define NV_DPCD_TEST_REQUEST_TEST_PHY_TEST_PATTERN 3:3 /* R-XUF */ 729 #define NV_DPCD_TEST_REQUEST_TEST_PHY_TEST_PATTERN_NO (0x00000000) /* R-XUV */ 730 #define NV_DPCD_TEST_REQUEST_TEST_PHY_TEST_PATTERN_YES (0x00000001) /* R-XUV */ 731 #define NV_DPCD_TEST_REQUEST_PHY_TEST_CHANNEL_CODING 5:4 /* R-XUF */ 732 #define NV_DPCD_TEST_REQUEST_PHY_TEST_CHANNEL_CODING_8B10B (0x00000000) /* R-XUV */ 733 #define NV_DPCD_TEST_REQUEST_PHY_TEST_CHANNEL_CODING_128B132B (0x00000001) /* R-XUV */ 734 #define NV_DPCD_TEST_REQUEST_TEST_AUDIO_PATTERN_REQ 6:6 /* R-XUF */ 735 #define NV_DPCD_TEST_REQUEST_TEST_AUDIO_PATTERN_REQ_NO (0x00000000) /* R-XUV */ 736 #define NV_DPCD_TEST_REQUEST_TEST_AUDIO_PATTERN_REQ_YES (0x00000001) /* R-XUV */ 737 #define NV_DPCD_TEST_REQUEST_TEST_AUDIO_DISABLED_VIDEO 7:7 /* R-XUF */ 738 #define NV_DPCD_TEST_REQUEST_TEST_AUDIO_DISABLED_VIDEO_NO (0x00000000) /* R-XUV */ 739 #define NV_DPCD_TEST_REQUEST_TEST_AUDIO_DISABLED_VIDEO_YES (0x00000001) /* R-XUV */ 740 741 #define NV_DPCD_TEST_LINK_RATE (0x00000219) /* R-XUR */ 742 #define NV_DPCD_TEST_LINK_RATE_TYPE 7:0 /* R-XUF */ 743 #define NV_DPCD_TEST_LINK_RATE_TYPE_1_62G (0x00000006) /* R-XUV */ 744 #define NV_DPCD_TEST_LINK_RATE_TYPE_2_70G (0x0000000A) /* R-XUV */ 745 #define NV_DPCD_TEST_LINK_RATE_TYPE_5_40G (0x00000014) /* R-XUV */ 746 // 747 // For PHY Test 128b/132b channel coding (PHY_TEST_CHANNEL_CODING field in 748 // the TEST_REQUEST register (DPCD Address 00218h, bits 5:4) is programmed to 01b) 749 // 750 #define NV_DPCD_TEST_LINK_RATE_TYPE_UHBR10 (0x00000001) /* R-XUV */ 751 #define NV_DPCD_TEST_LINK_RATE_TYPE_UHBR20 (0x00000002) /* R-XUV */ 752 #define NV_DPCD_TEST_LINK_RATE_TYPE_UHBR135 (0x00000004) /* R-XUV */ 753 754 // 0021Ah - 0021Fh: RESERVED. Read all 0s 755 756 #define NV_DPCD_TEST_LANE_COUNT (0x00000220) /* R-XUR */ 757 #define NV_DPCD_TEST_LANE_COUNT_VALUE 4:0 /* R-XUF */ 758 759 #define NV_DPCD_TEST_PATTERN (0x00000221) /* R-XUR */ 760 #define NV_DPCD_TEST_PATTERN_TYPE 1:0 /* R-XUF */ 761 #define NV_DPCD_TEST_PATTERN_TYPE_NO (0x00000000) /* R-XUV */ 762 #define NV_DPCD_TEST_PATTERN_TYPE_COLOR_RAMPS (0x00000001) /* R-XUV */ 763 #define NV_DPCD_TEST_PATTERN_TYPE_BW_VERTICAL_LINES (0x00000002) /* R-XUV */ 764 #define NV_DPCD_TEST_PATTERN_TYPE_COLOR_SQUARES (0x00000003) /* R-XUV */ 765 766 #define NV_DPCD_TEST_H_TOTAL_HIGH_BYTE (0x00000222) /* R-XUR */ 767 #define NV_DPCD_TEST_H_TOTAL_LOW_BYTE (0x00000223) /* R-XUR */ 768 769 #define NV_DPCD_TEST_V_TOTAL_HIGH_BYTE (0x00000224) /* R-XUR */ 770 #define NV_DPCD_TEST_V_TOTAL_LOW_BYTE (0x00000225) /* R-XUR */ 771 772 #define NV_DPCD_TEST_H_START_HIGH_BYTE (0x00000226) /* R-XUR */ 773 #define NV_DPCD_TEST_H_START_LOW_BYTE (0x00000227) /* R-XUR */ 774 775 #define NV_DPCD_TEST_V_START_HIGH_BYTE (0x00000228) /* R-XUR */ 776 #define NV_DPCD_TEST_V_START_LOW_BYTE (0x00000229) /* R-XUR */ 777 778 #define NV_DPCD_TEST_HSYNC_HIGH_BYTE (0x0000022A) /* R-XUR */ 779 #define NV_DPCD_TEST_HSYNC_HIGH_BYTE_VALUE 6:0 /* R-XUF */ 780 #define NV_DPCD_TEST_HSYNC_HIGH_BYTE_POLARITY 7:7 /* R-XUF */ 781 #define NV_DPCD_TEST_HSYNC_LOW_BYTE (0x0000022B) /* R-XUR */ 782 783 #define NV_DPCD_TEST_VSYNC_HIGH_BYTE (0x0000022C) /* R-XUR */ 784 #define NV_DPCD_TEST_VSYNC_HIGH_BYTE_VALUE 6:0 /* R-XUF */ 785 #define NV_DPCD_TEST_VSYNC_HIGH_BYTE_POLARITY 7:7 /* R-XUF */ 786 #define NV_DPCD_TEST_VSYNC_LOW_BYTE (0x0000022D) /* R-XUR */ 787 788 #define NV_DPCD_TEST_H_WIDTH_HIGH_BYTE (0x0000022E) /* R-XUR */ 789 #define NV_DPCD_TEST_H_WIDTH_LOW_BYTE (0x0000022F) /* R-XUR */ 790 791 #define NV_DPCD_TEST_V_HEIGHT_HIGH_BYTE (0x00000230) /* R-XUR */ 792 #define NV_DPCD_TEST_V_HEIGHT_LOW_BYTE (0x00000231) /* R-XUR */ 793 794 #define NV_DPCD_TEST_MISC0 (0x00000232) /* R-XUR */ 795 #define NV_DPCD_TEST_MISC0_TEST_SYNC_CLOCK 0:0 /* R-XUF */ 796 #define NV_DPCD_TEST_MISC0_TEST_COLOR_FORMAT 2:1 /* R-XUF */ 797 #define NV_DPCD_TEST_MISC0_TEST_COLOR_FORMAT_RGB (0x00000000) /* R-XUV */ 798 #define NV_DPCD_TEST_MISC0_TEST_COLOR_FORMAT_4_2_2 (0x00000001) /* R-XUV */ 799 #define NV_DPCD_TEST_MISC0_TEST_COLOR_FORMAT_4_4_4 (0x00000002) /* R-XUV */ 800 #define NV_DPCD_TEST_MISC0_TEST_COLOR_FORMAT_RESERVED (0x00000003) /* R-XUV */ 801 #define NV_DPCD_TEST_MISC0_TEST_DYNAMIC_RANGE 3:3 /* R-XUF */ 802 #define NV_DPCD_TEST_MISC0_TEST_YCBCR_COEFF 4:4 /* R-XUF */ 803 #define NV_DPCD_TEST_MISC0_TEST_BIT_DEPTH 7:5 /* R-XUF */ 804 #define NV_DPCD_TEST_MISC0_TEST_BIT_DEPTH_6BITS (0x00000000) /* R-XUV */ 805 #define NV_DPCD_TEST_MISC0_TEST_BIT_DEPTH_8BITS (0x00000001) /* R-XUV */ 806 #define NV_DPCD_TEST_MISC0_TEST_BIT_DEPTH_10BITS (0x00000002) /* R-XUV */ 807 #define NV_DPCD_TEST_MISC0_TEST_BIT_DEPTH_12BITS (0x00000003) /* R-XUV */ 808 #define NV_DPCD_TEST_MISC0_TEST_BIT_DEPTH_16BITS (0x00000004) /* R-XUV */ 809 810 #define NV_DPCD_TEST_MISC1 (0x00000233) /* R-XUR */ 811 #define NV_DPCD_TEST_MISC1_TEST_REFRESH_DENOMINATOR 0:0 /* R-XUF */ 812 #define NV_DPCD_TEST_MISC1_TEST_INTERLACED 1:1 /* R-XUF */ 813 814 #define NV_DPCD_TEST_REFRESH_RATE_NUMERATOR (0x00000234) /* R-XUR */ 815 816 // 00235h - 0023Fh: RESERVED for test automation extensions. Reads all 0s 817 818 #define NV_DPCD_TEST_CRC_R_Cr_LOW_BYTE (0x00000240) /* R-XUR */ 819 #define NV_DPCD_TEST_CRC_R_Cr_HIGH_BYTE (0x00000241) /* R-XUR */ 820 821 #define NV_DPCD_TEST_CRC_G_Y_LOW_BYTE (0x00000242) /* R-XUR */ 822 #define NV_DPCD_TEST_CRC_G_Y_HIGH_BYTE (0x00000243) /* R-XUR */ 823 824 #define NV_DPCD_TEST_CRC_B_Cb_LOW_BYTE (0x00000244) /* R-XUR */ 825 #define NV_DPCD_TEST_CRC_B_Cb_HIGH_BYTE (0x00000245) /* R-XUR */ 826 827 #define NV_DPCD_TEST_SINK_MISC (0x00000246) /* R-XUR */ 828 #define NV_DPCD_TEST_SINK_TEST_CRC_COUNT 3:0 /* R-XUF */ 829 #define NV_DPCD_TEST_SINK_TEST_CRC_SUPPORTED 5:5 /* R-XUF */ 830 #define NV_DPCD_TEST_SINK_TEST_CRC_SUPPORTED_NO (0X00000000) /* R-XUV */ 831 #define NV_DPCD_TEST_SINK_TEST_CRC_SUPPORTED_YES (0X00000001) /* R-XUV */ 832 833 //00247h: RESERVED for test automation extensions. Reads all 0s 834 835 #define NV_DPCD_PHY_TEST_PATTERN (0x00000248) /* R-XUR */ 836 #define NV_DPCD_PHY_TEST_PATTERN_SEL_DP11 1:0 /* R-XUF */ 837 #define NV_DPCD_PHY_TEST_PATTERN_SEL_DP12 2:0 /* R-XUF */ 838 #define NV_DPCD_PHY_TEST_PATTERN_SEL_NO (0x00000000) /* R-XUV */ 839 #define NV_DPCD_PHY_TEST_PATTERN_SEL_D10_2 (0x00000001) /* R-XUV */ 840 #define NV_DPCD_PHY_TEST_PATTERN_SEL_SYM_ERR_MEASUREMENT_CNT (0x00000002) /* R-XUV */ 841 #define NV_DPCD_PHY_TEST_PATTERN_SEL_PRBS7 (0x00000003) /* R-XUV */ 842 #define NV_DPCD_PHY_TEST_PATTERN_SEL_80_BIT_CUSTOM (0x00000004) /* R-XUV */ 843 #define NV_DPCD_PHY_TEST_PATTERN_SEL_HBR2_COMPLIANCE_EYE (0x00000005) /* R-XUV */ 844 845 #define NV_DPCD_HBR2_COMPLIANCE_SCRAMBLER_RESET_LOW_BYTE (0x0000024A) /* R-XUV */ 846 #define NV_DPCD_HBR2_COMPLIANCE_SCRAMBLER_RESET_HIGH_BYTE (0x0000024B) /* R-XUV */ 847 848 // 0024Ch - 0024Fh RESERVED for test automation extensions. Reads all 0s 849 850 #define NV_DPCD_TEST_80BIT_CUSTOM_PATTERN(i) (0x00000250+(i)) /* R--1A */ 851 #define NV_DPCD_TEST_80BIT_CUSTOM_PATTERN__SIZE 10 /* R---S */ 852 853 // 0025Ah - 0025Fh: RESERVED for test automation extensions. Reads all 0s 854 855 #define NV_DPCD_TEST_RESPONSE (0x00000260) /* RWXUR */ 856 #define NV_DPCD_TEST_RESPONSE_TEST_ACK 0:0 /* RWXUF */ 857 #define NV_DPCD_TEST_RESPONSE_TEST_ACK_NO (0x00000000) /* RWXUV */ 858 #define NV_DPCD_TEST_RESPONSE_TEST_ACK_YES (0x00000001) /* RWXUV */ 859 #define NV_DPCD_TEST_RESPONSE_TEST_NACK 1:1 /* RWXUF */ 860 #define NV_DPCD_TEST_RESPONSE_TEST_NACK_NO (0x00000000) /* RWXUV */ 861 #define NV_DPCD_TEST_RESPONSE_TEST_NACK_YES (0x00000001) /* RWXUV */ 862 #define NV_DPCD_TEST_RESPONSE_TEST_EDID_CHKSUM_WRITE 2:2 /* RWXUF */ 863 #define NV_DPCD_TEST_RESPONSE_TEST_EDID_CHKSUM_WRITE_NO (0x00000000) /* RWXUV */ 864 #define NV_DPCD_TEST_RESPONSE_TEST_EDID_CHKSUM_WRITE_YES (0x00000001) /* RWXUV */ 865 866 #define NV_DPCD_TEST_EDID_CHKSUM (0x00000261) /* RWXUR */ 867 868 // 00263h - 0026Fh: RESERVED for test automation extensions Read all 0s. 869 870 #define NV_DPCD_TEST_SINK (0x00000270) /* RWXUR */ 871 #define NV_DPCD_TEST_SINK_START 0:0 /* RWXUF */ 872 #define NV_DPCD_TEST_SINK_START_NO (0x00000000) /* RWXUV */ 873 #define NV_DPCD_TEST_SINK_START_YES (0x00000001) /* RWXUV */ 874 #define NV_DPCD_TEST_SINK_PHY_SINK_TEST_LANE_SEL 5:4 /* RWXUF */ 875 #define NV_DPCD_TEST_SINK_PHY_SINK_TEST_LANE_EN 7:7 /* RWXUF */ 876 #define NV_DPCD_TEST_SINK_PHY_SINK_TEST_LANE_EN_DISABLE (0x00000000) /* RWXUV */ 877 #define NV_DPCD_TEST_SINK_PHY_SINK_TEST_LANE_EN_ENABLE (0x00000001) /* RWXUV */ 878 879 #define NV_DPCD_TEST_AUDIO_MODE (0x00000271) /* R-XUR */ 880 #define NV_DPCD_TEST_AUDIO_MODE_SAMPLING_RATE 3:0 /* R-XUF */ 881 #define NV_DPCD_TEST_AUDIO_MODE_SAMPLING_RATE_32_0KHZ (0x00000000) /* R-XUV */ 882 #define NV_DPCD_TEST_AUDIO_MODE_SAMPLING_RATE_44_1KHZ (0x00000001) /* R-XUV */ 883 #define NV_DPCD_TEST_AUDIO_MODE_SAMPLING_RATE_48_0KHZ (0x00000002) /* R-XUV */ 884 #define NV_DPCD_TEST_AUDIO_MODE_SAMPLING_RATE_88_2KHZ (0x00000003) /* R-XUV */ 885 #define NV_DPCD_TEST_AUDIO_MODE_SAMPLING_RATE_96_0KHZ (0x00000004) /* R-XUV */ 886 #define NV_DPCD_TEST_AUDIO_MODE_SAMPLING_RATE_176_4KHZ (0x00000005) /* R-XUV */ 887 #define NV_DPCD_TEST_AUDIO_MODE_SAMPLING_RATE_192_0KHZ (0x00000006) /* R-XUV */ 888 #define NV_DPCD_TEST_AUDIO_MODE_CHANNEL_COUNT 7:4 /* R-XUF */ 889 #define NV_DPCD_TEST_AUDIO_MODE_CHANNEL_COUNT_1 (0x00000000) /* R-XUV */ 890 #define NV_DPCD_TEST_AUDIO_MODE_CHANNEL_COUNT_2 (0x00000001) /* R-XUV */ 891 #define NV_DPCD_TEST_AUDIO_MODE_CHANNEL_COUNT_3 (0x00000002) /* R-XUV */ 892 #define NV_DPCD_TEST_AUDIO_MODE_CHANNEL_COUNT_4 (0x00000003) /* R-XUV */ 893 #define NV_DPCD_TEST_AUDIO_MODE_CHANNEL_COUNT_5 (0x00000004) /* R-XUV */ 894 #define NV_DPCD_TEST_AUDIO_MODE_CHANNEL_COUNT_6 (0x00000005) /* R-XUV */ 895 #define NV_DPCD_TEST_AUDIO_MODE_CHANNEL_COUNT_7 (0x00000006) /* R-XUV */ 896 #define NV_DPCD_TEST_AUDIO_MODE_CHANNEL_COUNT_8 (0x00000007) /* R-XUV */ 897 898 #define NV_DPCD_TEST_AUDIO_PATTERN (0x00000272) /* R-XUR */ 899 #define NV_DPCD_TEST_AUDIO_PATTERN_TYPE 7:0 /* R-XUF */ 900 #define NV_DPCD_TEST_AUDIO_PATTERN_TYPE_OP_DEFINED (0x00000000) /* R-XUV */ 901 #define NV_DPCD_TEST_AUDIO_PATTERN_TYPE_SAWTOOTH (0x00000001) /* R-XUV */ 902 903 #define NV_DPCD_TEST_AUDIO_PERIOD_CH(i) (0x00000273+(i)) /* R--1A */ 904 #define NV_DPCD_TEST_AUDIO_PERIOD_CH__SIZE 8 /* R---S */ 905 #define NV_DPCD_TEST_AUDIO_PERIOD_CH_SAMPLES 3:0 /* R-XUF */ 906 #define NV_DPCD_TEST_AUDIO_PERIOD_CH_SAMPLES_UNUSED (0x00000000) /* R-XUV */ 907 #define NV_DPCD_TEST_AUDIO_PERIOD_CH_SAMPLES_3 (0x00000001) /* R-XUV */ 908 #define NV_DPCD_TEST_AUDIO_PERIOD_CH_SAMPLES_6 (0x00000002) /* R-XUV */ 909 #define NV_DPCD_TEST_AUDIO_PERIOD_CH_SAMPLES_12 (0x00000003) /* R-XUV */ 910 #define NV_DPCD_TEST_AUDIO_PERIOD_CH_SAMPLES_24 (0x00000004) /* R-XUV */ 911 #define NV_DPCD_TEST_AUDIO_PERIOD_CH_SAMPLES_48 (0x00000005) /* R-XUV */ 912 #define NV_DPCD_TEST_AUDIO_PERIOD_CH_SAMPLES_96 (0x00000006) /* R-XUV */ 913 #define NV_DPCD_TEST_AUDIO_PERIOD_CH_SAMPLES_192 (0x00000007) /* R-XUV */ 914 #define NV_DPCD_TEST_AUDIO_PERIOD_CH_SAMPLES_384 (0x00000008) /* R-XUV */ 915 #define NV_DPCD_TEST_AUDIO_PERIOD_CH_SAMPLES_768 (0x00000009) /* R-XUV */ 916 #define NV_DPCD_TEST_AUDIO_PERIOD_CH_SAMPLES_1536 (0x0000000A) /* R-XUV */ 917 918 // 0027Bh - 0027Fh: RESERVED. Read all 0s 919 920 // For DP version 1.3 and above 921 #define NV_DPCD_FEC_STATUS (0x00000280) /* R-XUR */ 922 #define NV_DPCD_FEC_STATUS_DECODE_EN 0:0 /* R-XUF */ 923 #define NV_DPCD_FEC_STATUS_DECODE_EN_NOT_DETECTED (0x00000000) /* R-XUV */ 924 #define NV_DPCD_FEC_STATUS_DECODE_EN_DETECTED (0x00000001) /* R-XUV */ 925 #define NV_DPCD_FEC_STATUS_DECODE_DIS 1:1 /* R-XUF */ 926 #define NV_DPCD_FEC_STATUS_DECODE_DIS_NOT_DETECTED (0x00000000) /* R-XUV */ 927 #define NV_DPCD_FEC_STATUS_DECODE_DIS_DETECTED (0x00000001) /* R-XUV */ 928 929 930 // 00283h - 002BFh: RESERVED. Read all 0s. 931 932 #define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS (0x000002C0) /* R-XUR */ 933 #define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED 0:0 /* R-XUF */ 934 #define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED_NO (0x00000000) /* R-XUV */ 935 #define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED_YES (0x00000001) /* R-XUV */ 936 #define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED 1:1 /* R-XUF */ 937 #define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_NO (0x00000000) /* R-XUV */ 938 #define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_YES (0x00000001) /* R-XUV */ 939 940 #define NV_DPCD_VC_PAYLOAD_ID_SLOT(i) (0x000002C1+(i)) /* R--1A */ 941 #define NV_DPCD_VC_PAYLOAD_ID_SLOT__SIZE 63 /* R---S */ 942 943 // Source Device-Specific Field, Burst write for 00300h-0030Bh 944 // 6 hex digits: 0x300~0x302. 945 #define NV_DPCD_SOURCE_IEEE_OUI (0x00000300) /* RWXUR */ 946 #define NV_DPCD_OUI_NVIDIA_LITTLE_ENDIAN 0x4B0400 947 948 // 6 bytes: 0x303~0x308 949 #define NV_DPCD_SOURCE_DEV_ID_STRING(i) (0x00000303+(i)) /* RW-1A */ 950 #define NV_DPCD_SOURCE_DEV_ID_STRING__SIZE 6 /* RW--S */ 951 952 #define NV_DPCD_SOURCE_HARDWARE_REV (0x00000309) /* RWXUR */ 953 #define NV_DPCD_SOURCE_HARDWARE_REV_MINOR 3:0 /* RWXUF */ 954 #define NV_DPCD_SOURCE_HARDWARE_REV_MAJOR 7:4 /* RWXUF */ 955 956 #define NV_DPCD_SOURCE_SOFTWARE_REV_MAJOR (0x0000030A) /* RWXUR */ 957 #define NV_DPCD_SOURCE_SOFTWARE_REV_MINOR (0x0000030B) /* RWXUR */ 958 959 // Sink Device-Specific Field. Read Only 960 // 6 hex digits: 0x400~0x402 961 #define NV_DPCD_SINK_IEEE_OUI (0x00000400) /* R-XUR */ 962 963 // 6 bytes: 0x403~0x408 964 #define NV_DPCD_SINK_DEV_ID_STRING(i) (0x00000403+(i)) /* R--1A */ 965 #define NV_DPCD_SINK_DEV_ID_STRING__SIZE 6 /* R---S */ 966 967 #define NV_DPCD_SINK_HARDWARE_REV (0x00000409) /* R-XUR */ 968 #define NV_DPCD_SINK_HARDWARE_REV_MINOR 3:0 /* R-XUF */ 969 #define NV_DPCD_SINK_HARDWARE_REV_MAJOR 7:4 /* R-XUF */ 970 971 #define NV_DPCD_SINK_SOFTWARE_REV_MAJOR (0x0000040A) /* R-XUR */ 972 #define NV_DPCD_SINK_SOFTWARE_REV_MINOR (0x0000040B) /* R-XUR */ 973 974 // Branch Device-Specific Field 975 // 6 hex digits: 0x500~0x502 976 977 #define NV_DPCD_BRANCH_IEEE_OUI (0x00000500) /* R-XUR */ 978 979 // 6 bytes: 0x503~0x508 980 #define NV_DPCD_BRANCH_DEV_ID_STRING (0x00000503+(i)) /* R--1A */ 981 #define NV_DPCD_BRANCH_DEV_ID_STRING__SIZE 6 /* R---S */ 982 983 #define NV_DPCD_BRANCH_HARDWARE_REV (0x00000509) /* R-XUR */ 984 #define NV_DPCD_BRANCH_HARDWARE_REV_MINOR 3:0 /* R-XUF */ 985 #define NV_DPCD_BRANCH_HARDWARE_REV_MAJOR 7:4 /* R-XUF */ 986 987 #define NV_DPCD_BRANCH_SOFTWARE_REV_MAJOR (0x0000050A) /* R-XUR */ 988 #define NV_DPCD_BRANCH_SOFTWARE_REV_MINOR (0x0000050B) /* R-XUR */ 989 990 // Sink Control Field 991 #define NV_DPCD_SET_POWER (0x00000600) /* RWXUR */ 992 #define NV_DPCD_SET_POWER_VAL 2:0 /* RWXUF */ 993 #define NV_DPCD_SET_POWER_VAL_RESERVED (0x00000000) /* RWXUV */ 994 #define NV_DPCD_SET_POWER_VAL_D0_NORMAL (0x00000001) /* RWXUV */ 995 #define NV_DPCD_SET_POWER_VAL_D3_PWRDWN (0x00000002) /* RWXUV */ 996 #define NV_DPCD_SET_POWER_VAL_D3_AUX_ON (0x00000005) /* RWXUV */ 997 998 /* 999 * 00601h - 006FFh: RESERVED. Read all 0s 1000 */ 1001 1002 // * 00700h - 007FFh: RESERVED for eDP, see eDP v1.4 and above 1003 #define NV_DPCD_EDP_REV (0x00000700) /* R-XUR */ 1004 #define NV_DPCD_EDP_REV_VAL 7:0 /* R-XUF */ 1005 #define NV_DPCD_EDP_REV_VAL_1_1_OR_LOWER (0x00000000) /* R-XUV */ 1006 #define NV_DPCD_EDP_REV_VAL_1_2 (0x00000001) /* R-XUV */ 1007 #define NV_DPCD_EDP_REV_VAL_1_3 (0x00000002) /* R-XUV */ 1008 #define NV_DPCD_EDP_REV_VAL_1_4 (0x00000003) /* R-XUV */ 1009 #define NV_DPCD_EDP_REV_VAL_1_4A (0x00000004) /* R-XUV */ 1010 #define NV_DPCD_EDP_REV_VAL_1_4B (0x00000005) /* R-XUV */ 1011 #define NV_DPCD_EDP_REV_VAL_1_5 (0x00000006) /* R-XUV */ 1012 #define NV_DPCD_EDP_REV_VAL_1_5A (0x00000006) /* R-XUV */ 1013 #define NV_DPCD_EDP_GENERAL_CAP1 (0x00000701) /* R-XUR */ 1014 #define NV_DPCD_EDP_GENERAL_CAP1_TCON_BKLGHT_ADJUST_CAP 0:0 /* R-XUF */ 1015 #define NV_DPCD_EDP_GENERAL_CAP1_TCON_BKLGHT_ADJUST_CAP_YES (0x00000001) /* R-XUV */ 1016 #define NV_DPCD_EDP_GENERAL_CAP1_TCON_BKLGHT_ADJUST_CAP_NO (0x00000000) /* R-XUV */ 1017 #define NV_DPCD_EDP_GENERAL_CAP1_BKLGHT_PIN_EN_CAP 1:1 /* R-XUF */ 1018 #define NV_DPCD_EDP_GENERAL_CAP1_BKLGHT_PIN_EN_CAP_YES (0x00000001) /* R-XUV */ 1019 #define NV_DPCD_EDP_GENERAL_CAP1_BKLGHT_PIN_EN_CAP_NO (0x00000000) /* R-XUV */ 1020 #define NV_DPCD_EDP_GENERAL_CAP1_BKLGHT_AUX_EN_CAP 2:2 /* R-XUF */ 1021 #define NV_DPCD_EDP_GENERAL_CAP1_BKLGHT_AUX_EN_CAP_YES (0x00000001) /* R-XUV */ 1022 #define NV_DPCD_EDP_GENERAL_CAP1_BKLGHT_AUX_EN_CAP_NO (0x00000000) /* R-XUV */ 1023 #define NV_DPCD_EDP_GENERAL_CAP1_PANEL_SELF_TEST_PIN_EN_CAP 3:3 /* R-XUF */ 1024 #define NV_DPCD_EDP_GENERAL_CAP1_PANEL_SELF_TEST_PIN_EN_CAP_YES (0x00000001) /* R-XUV */ 1025 #define NV_DPCD_EDP_GENERAL_CAP1_PANEL_SELF_TEST_PIN_EN_CAP_NO (0x00000000) /* R-XUV */ 1026 #define NV_DPCD_EDP_GENERAL_CAP1_PANEL_SELF_TEST_AUX_EN_CAP 4:4 /* R-XUF */ 1027 #define NV_DPCD_EDP_GENERAL_CAP1_PANEL_SELF_TEST_AUX_EN_CAP_YES (0x00000001) /* R-XUV */ 1028 #define NV_DPCD_EDP_GENERAL_CAP1_PANEL_SELF_TEST_AUX_EN_CAP_NO (0x00000000) /* R-XUV */ 1029 #define NV_DPCD_EDP_GENERAL_CAP1_FRC_EN_CAP 5:5 /* R-XUF */ 1030 #define NV_DPCD_EDP_GENERAL_CAP1_FRC_EN_CAP_YES (0x00000001) /* R-XUV */ 1031 #define NV_DPCD_EDP_GENERAL_CAP1_FRC_EN_CAP_NO (0x00000000) /* R-XUV */ 1032 #define NV_DPCD_EDP_GENERAL_CAP1_COLOR_ENGINE_CAP 6:6 /* R-XUF */ 1033 #define NV_DPCD_EDP_GENERAL_CAP1_COLOR_ENGINE_CAP_YES (0x00000001) /* R-XUV */ 1034 #define NV_DPCD_EDP_GENERAL_CAP1_COLOR_ENGINE_CAP_NO (0x00000000) /* R-XUV */ 1035 #define NV_DPCD_EDP_GENERAL_CAP1_SET_POWER_CAP 7:7 /* R-XUF */ 1036 #define NV_DPCD_EDP_GENERAL_CAP1_SET_POWER_CAP_YES (0x00000001) /* R-XUV */ 1037 #define NV_DPCD_EDP_GENERAL_CAP1_SET_POWER_CAP_NO (0x00000000) /* R-XUV */ 1038 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP (0x00000702) /* R-XUR */ 1039 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_BRIGHT_PWM_PIN_CAP 0:0 /* R-XUF */ 1040 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_BRIGHT_PWM_PIN_CAP_YES (0x00000001) /* R-XUV */ 1041 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_BRIGHT_PWM_PIN_CAP_NO (0x00000000) /* R-XUV */ 1042 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_BRIGHT_AUX_SET_CAP 1:1 /* R-XUF */ 1043 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_BRIGHT_AUX_SET_CAP_YES (0x00000001) /* R-XUV */ 1044 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_BRIGHT_AUX_SET_CAP_NO (0x00000000) /* R-XUV */ 1045 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_BRIGHT_AUX_BYTE_CNT 2:2 /* R-XUF */ 1046 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_BRIGHT_AUX_BYTE_CNT_2B (0x00000001) /* R-XUV */ 1047 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_BRIGHT_AUX_BYTE_CNT_1B (0x00000000) /* R-XUV */ 1048 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_AUX_PWM_PRODUCT_CAP 3:3 /* R-XUF */ 1049 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_AUX_PWM_PRODUCT_CAP_YES (0x00000001) /* R-XUV */ 1050 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_AUX_PWM_PRODUCT_CAP_NO (0x00000000) /* R-XUV */ 1051 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_FREQ_PWM_PIN_PASSTHRU_CAP 4:4 /* R-XUF */ 1052 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_FREQ_PWM_PIN_PASSTHRU_CAP_YES (0x00000001) /* R-XUV */ 1053 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_FREQ_PWM_PIN_PASSTHRU_CAP_NO (0x00000000) /* R-XUV */ 1054 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_FREQ_AUX_SET_CAP 5:5 /* R-XUF */ 1055 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_FREQ_AUX_SET_CAP_YES (0x00000001) /* R-XUV */ 1056 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_FREQ_AUX_SET_CAP_NO (0x00000000) /* R-XUV */ 1057 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_DYNAMIC_BKLGHT_CAP 6:6 /* R-XUF */ 1058 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_DYNAMIC_BKLGHT_CAP_YES (0x00000001) /* R-XUV */ 1059 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_DYNAMIC_BKLGHT_CAP_NO (0x00000000) /* R-XUV */ 1060 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_VBLANK_BKLGHT_UPDATE_CAP 7:7 /* R-XUF */ 1061 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_VBLANK_BKLGHT_UPDATE_CAP_VBL (0x00000001) /* R-XUV */ 1062 #define NV_DPCD_EDP_BKLGHT_ADJUST_CAP_VBLANK_BKLGHT_UPDATE_CAP_IMM (0x00000000) /* R-XUV */ 1063 #define NV_DPCP_EDP_GENERAL_CAP2 (0x00000703) /* R-XUR */ 1064 #define NV_DPCD_EDP_GENERAL_CAP2_OVERDRIVE_ENGINE_CAP 0:0 /* R-XUF */ 1065 #define NV_DPCD_EDP_GENERAL_CAP2_OVERDRIVE_ENGINE_CAP_YES (0x00000001) /* R-XUV */ 1066 #define NV_DPCD_EDP_GENERAL_CAP2_OVERDRIVE_ENGINE_CAP_NO (0x00000000) /* R-XUV */ 1067 #define NV_DPCD_EDP_GENERAL_CAP2_BKLGHT_BRIGHT_BIT_ALIGNMENT 2:1 /* R-XUF */ 1068 #define NV_DPCD_EDP_GENERAL_CAP2_BKLGHT_BRIGHT_BIT_ALIGNMENT_NO (0x00000000) /* R-XUV */ 1069 #define NV_DPCD_EDP_GENERAL_CAP2_BKLGHT_BRIGHT_BIT_ALIGNMENT_MSB (0x00000001) /* R-XUV */ 1070 #define NV_DPCD_EDP_GENERAL_CAP2_BKLGHT_BRIGHT_BIT_ALIGNMENT_LSB (0x00000002) /* R-XUV */ 1071 #define NV_DPCD_EDP_GENERAL_CAP2_OVERDRIVE_CONTROL_CAP 3:3 /* R-XUF */ 1072 #define NV_DPCD_EDP_GENERAL_CAP2_OVERDRIVE_CONTROL_CAP_NO (0x00000000) /* R-XUV */ 1073 #define NV_DPCD_EDP_GENERAL_CAP2_OVERDRIVE_CONTROL_CAP_YES (0x00000001) /* R-XUV */ 1074 #define NV_DPCD_EDP_GENERAL_CAP2_PANEL_LUMINANCE_CONTROL_CAP 4:4 /* R-XUF */ 1075 #define NV_DPCD_EDP_GENERAL_CAP2_PANEL_LUMINANCE_CONTROL_CAP_NO (0x00000000) /* R-XUV */ 1076 #define NV_DPCD_EDP_GENERAL_CAP2_PANEL_LUMINANCE_CONTROL_CAP_YES (0x00000001) /* R-XUV */ 1077 #define NV_DPCD_EDP_GENERAL_CAP3 (0x00000704) /* R-XUV */ 1078 #define NV_DPCD_EDP_GENERAL_CAP3_X_REGION_CAP 3:0 /* R-XUF */ 1079 #define NV_DPCD_EDP_GENERAL_CAP3_X_REGION_CAP_NOT_SUPPORTED (0x00000000) /* R-XUV */ 1080 #define NV_DPCD_EDP_GENERAL_CAP3_Y_REGION_CAP 7:4 /* R-XUF */ 1081 #define NV_DPCD_EDP_GENERAL_CAP3_Y_REGION_CAP_NOT_SUPPORTED (0x00000000) /* R-XUV */ 1082 #define NV_DPCD_EDP_DISPLAY_CTL (0x00000720) /* RWXUR */ 1083 #define NV_DPCD_EDP_DISPLAY_CTL_BKLGHT_EN 0:0 /* RWXUF */ 1084 #define NV_DPCD_EDP_DISPLAY_CTL_BKLGHT_EN_INIT (0x00000000) /* RWXUV */ 1085 #define NV_DPCD_EDP_DISPLAY_CTL_BKLGHT_EN_ENABLED (0x00000001) /* RWXUV */ 1086 #define NV_DPCD_EDP_DISPLAY_CTL_BKLGHT_EN_DISABLED (0x00000000) /* RWXUV */ 1087 #define NV_DPCD_EDP_DISPLAY_CTL_BLACK_VIDEO_EN 1:1 /* RWXUF */ 1088 #define NV_DPCD_EDP_DISPLAY_CTL_BLACK_VIDEO_EN_INIT (0x00000000) /* RWXUV */ 1089 #define NV_DPCD_EDP_DISPLAY_CTL_BLACK_VIDEO_EN_ENABLED (0x00000001) /* RWXUV */ 1090 #define NV_DPCD_EDP_DISPLAY_CTL_BLACK_VIDEO_EN_DISABLED (0x00000000) /* RWXUV */ 1091 #define NV_DPCD_EDP_DISPLAY_CTL_FRC_EN 2:2 /* RWXUF */ 1092 #define NV_DPCD_EDP_DISPLAY_CTL_FRC_EN_2BIT (0x00000001) /* RWXUV */ 1093 #define NV_DPCD_EDP_DISPLAY_CTL_COLOR_ENGINE_EN 3:3 /* RWXUF */ 1094 #define NV_DPCD_EDP_DISPLAY_CTL_COLOR_ENGINE_EN_INIT (0x00000000) /* RWXUV */ 1095 #define NV_DPCD_EDP_DISPLAY_CTL_COLOR_ENGINE_EN_ENABLED (0x00000001) /* RWXUV */ 1096 #define NV_DPCD_EDP_DISPLAY_CTL_COLOR_ENGINE_EN_DISABLED (0x00000000) /* RWXUV */ 1097 #define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL 5:4 /* RWXUF */ 1098 #define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_AUTONOMOUS (0x00000000) /* RWXUV */ 1099 #define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_AUTONOMOUS_1 (0x00000001) /* RWXUV */ 1100 #define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_DISABLE (0x00000002) /* RWXUV */ 1101 #define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_ENABLE (0x00000003) /* RWXUV */ 1102 #define NV_DPCD_EDP_DISPLAY_CTL_VBLANK_BKLGHT_UPDATE_EN 7:7 /* RWXUF */ 1103 #define NV_DPCD_EDP_DISPLAY_CTL_VBLANK_BKLGHT_UPDATE_EN_ENABLED (0x00000001) /* RWXUV */ 1104 #define NV_DPCD_EDP_DISPLAY_CTL_VBLANK_BKLGHT_UPDATE_EN_DISABLED (0x00000000) /* RWXUV */ 1105 #define NV_DPCD_EDP_BKLGHT_MODE_SET (0x00000721) /* RWXUR */ 1106 #define NV_DPCD_EDP_BKLGHT_MODE_SET_BRIGHT_CTL_MODE 1:0 /* RWXUF */ 1107 #define NV_DPCD_EDP_BKLGHT_MODE_SET_BRIGHT_CTL_MODE_INIT (0x00000000) /* RWXUV */ 1108 #define NV_DPCD_EDP_BKLGHT_MODE_SET_BRIGHT_CTL_MODE_PWM_PIN (0x00000000) /* RWXUV */ 1109 #define NV_DPCD_EDP_BKLGHT_MODE_SET_BRIGHT_CTL_MODE_PRESET_LV (0x00000001) /* RWXUV */ 1110 #define NV_DPCD_EDP_BKLGHT_MODE_SET_BRIGHT_CTL_MODE_AUX (0x00000002) /* RWXUV */ 1111 #define NV_DPCD_EDP_BKLGHT_MODE_SET_BRIGHT_CTL_MODE_PWM_AND_AUX (0x00000003) /* RWXUV */ 1112 #define NV_DPCD_EDP_BKLGHT_MODE_SET_FREQ_PWM_PIN_PASSTHRU_EN 2:2 /* RWXUF */ 1113 #define NV_DPCD_EDP_BKLGHT_MODE_SET_FREQ_PWM_PIN_PASSTHRU_EN_INIT (0x00000000) /* RWXUV */ 1114 #define NV_DPCD_EDP_BKLGHT_MODE_SET_FREQ_PWM_PIN_PASSTHRU_EN_ENABLED (0x00000001) /* RWXUV */ 1115 #define NV_DPCD_EDP_BKLGHT_MODE_SET_FREQ_PWM_PIN_PASSTHRU_EN_DISABLED (0x00000000) /* RWXUV */ 1116 #define NV_DPCD_EDP_BKLGHT_MODE_SET_FREQ_AUX_SET_EN 3:3 /* RWXUF */ 1117 #define NV_DPCD_EDP_BKLGHT_MODE_SET_FREQ_AUX_SET_EN_INIT (0x00000000) /* RWXUV */ 1118 #define NV_DPCD_EDP_BKLGHT_MODE_SET_FREQ_AUX_SET_EN_ENABLED (0x00000001) /* RWXUV */ 1119 #define NV_DPCD_EDP_BKLGHT_MODE_SET_FREQ_AUX_SET_EN_DISABLED (0x00000000) /* RWXUV */ 1120 #define NV_DPCD_EDP_BKLGHT_MODE_SET_DYNAMIC_BKLGHT_EN 4:4 /* RWXUF */ 1121 #define NV_DPCD_EDP_BKLGHT_MODE_SET_DYNAMIC_BKLGHT_EN_INIT (0x00000000) /* RWXUV */ 1122 #define NV_DPCD_EDP_BKLGHT_MODE_SET_DYNAMIC_BKLGHT_EN_ENABLED (0x00000001) /* RWXUV */ 1123 #define NV_DPCD_EDP_BKLGHT_MODE_SET_DYNAMIC_BKLGHT_EN_DISABLED (0x00000000) /* RWXUV */ 1124 #define NV_DPCD_EDP_BKLGHT_MODE_SET_REGIONAL_BKLGHT_EN 5:5 /* RWXUF */ 1125 #define NV_DPCD_EDP_BKLGHT_MODE_SET_REGIONAL_BKLGHT_EN_INIT (0x00000000) /* RWXUV */ 1126 #define NV_DPCD_EDP_BKLGHT_MODE_SET_REGIONAL_BKLGHT_EN_ENABLED (0x00000001) /* RWXUV */ 1127 #define NV_DPCD_EDP_BKLGHT_MODE_SET_REGIONAL_BKLGHT_EN_DISABLED (0x00000000) /* RWXUV */ 1128 #define NV_DPCD_EDP_BKLGHT_MODE_SET_UPDATE_REGION_BRIGHTNESS 6:6 /* RWXUF */ 1129 #define NV_DPCD_EDP_BKLGHT_MODE_SET_UPDATE_REGION_BRIGHTNESS_ENABLED (0x00000001) /* RWXUV */ 1130 #define NV_DPCD_EDP_BKLGHT_MODE_SET_UPDATE_REGION_BRIGHTNESS_DISABLED (0x00000000) /* RWXUV */ 1131 #define NV_DPCD_EDP_BKLGHT_MODE_SET_PANEL_LUMINANCE_CONTROL_ENABLE 7:7 /* RWXUF */ 1132 #define NV_DPCD_EDP_BKLGHT_MODE_SET_PANEL_LUMINANCE_CONTROL_ENABLE_YES (0x00000001) /* RWXUV */ 1133 #define NV_DPCD_EDP_BKLGHT_MODE_SET_PANEL_LUMINANCE_CONTROL_ENABLE_NO (0x00000000) /* RWXUV */ 1134 #define NV_DPCD_EDP_BKLGHT_BRIGHTNESS_MSB (0x00000722) /* RWXUR */ 1135 #define NV_DPCD_EDP_BKLGHT_BRIGHTNESS_MSB_VAL 7:0 /* RWXUF */ 1136 #define NV_DPCD_EDP_BKLGHT_BRIGHTNESS_MSB_VAL_INIT (0x00000000) /* RWXUV */ 1137 #define NV_DPCD_EDP_BKLGHT_BRIGHTNESS_LSB (0x00000723) /* RWXUR */ 1138 #define NV_DPCD_EDP_BKLGHT_BRIGHTNESS_LSB_VAL 7:0 /* RWXUF */ 1139 #define NV_DPCD_EDP_BKLGHT_BRIGHTNESS_LSB_VAL_INIT (0x00000000) /* RWXUV */ 1140 #define NV_DPCD_EDP_PWMGEN_BIT_CNT (0x00000724) /* RWXUR */ 1141 #define NV_DPCD_EDP_PWMGEN_BIT_CNT_VAL 4:0 /* RWXUF */ 1142 #define NV_DPCD_EDP_PWMGEN_BIT_CNT_VAL_INIT (0x00000000) /* RWXUV */ 1143 #define NV_DPCD_EDP_PWMGEN_BIT_CNT_CAP_MIN (0x00000725) /* R-XUR */ 1144 #define NV_DPCD_EDP_PWMGEN_BIT_CNT_CAP_MIN_VAL 4:0 /* R-XUF */ 1145 #define NV_DPCD_EDP_PWMGEN_BIT_CNT_CAP_MIN_VAL_INIT (0x00000000) /* R-XUV */ 1146 #define NV_DPCD_EDP_PWMGEN_BIT_CNT_CAP_MAX (0x00000726) /* R-XUR */ 1147 #define NV_DPCD_EDP_PWMGEN_BIT_CNT_CAP_MAX_VAL 4:0 /* R-XUF */ 1148 #define NV_DPCD_EDP_PWMGEN_BIT_CNT_CAP_MAX_VAL_INIT (0x00000000) /* R-XUV */ 1149 #define NV_DPCD_EDP_BKLGHT_CTL_STATUS (0x00000727) /* R-XUR */ 1150 #define NV_DPCD_EDP_BKLGHT_CTL_STATUS_FAULT_CONDITION 0:0 /* R-XUF */ 1151 #define NV_DPCD_EDP_BKLGHT_CTL_STATUS_FAULT_CONDITION_INIT (0x00000000) /* R-XUV */ 1152 #define NV_DPCD_EDP_BKLGHT_CTL_STATUS_FAULT_CONDITION_FAULT (0x00000001) /* R-XUV */ 1153 #define NV_DPCD_EDP_BKLGHT_CTL_STATUS_FAULT_CONDITION_NORMAL (0x00000000) /* R-XUV */ 1154 #define NV_DPCD_EDP_BKLGHT_FREQ_SET (0x00000728) /* RWXUR */ 1155 #define NV_DPCD_EDP_BKLGHT_FREQ_SET_VAL 7:0 /* RWXUF */ 1156 #define NV_DPCD_EDP_BKLGHT_FREQ_SET_VAL_INIT (0x00000000) /* RWXUV */ 1157 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MIN_MSB (0x0000072A) /* R-XUR */ 1158 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MIN_MSB_VAL 7:0 /* R-XUF */ 1159 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MIN_MSB_VAL_INIT (0x00000000) /* R-XUV */ 1160 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MIN_MID (0x0000072B) /* R-XUR */ 1161 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MIN_MID_VAL 7:0 /* R-XUF */ 1162 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MIN_MID_VAL_INIT (0x00000000) /* R-XUV */ 1163 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MIN_LSB (0x0000072C) /* R-XUR */ 1164 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MIN_LSB_VAL 1:0 /* R-XUF */ 1165 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MIN_LSB_VAL_INIT (0x00000000) /* R-XUV */ 1166 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MAX_MSB (0x0000072D) /* R-XUR */ 1167 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MAX_MSB_VAL 7:0 /* R-XUF */ 1168 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MAX_MSB_VAL_INIT (0x00000000) /* R-XUV */ 1169 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MAX_MID (0x0000072E) /* R-XUR */ 1170 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MAX_MID_VAL 7:0 /* R-XUF */ 1171 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MAX_MID_VAL_INIT (0x00000000) /* R-XUV */ 1172 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MAX_LSB (0x0000072F) /* R-XUR */ 1173 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MAX_LSB_VAL 1:0 /* R-XUF */ 1174 #define NV_DPCD_EDP_BKLGHT_FREQ_CAP_MAX_LSB_VAL_INIT (0x00000000) /* R-XUV */ 1175 #define NV_DPCD_EDP_DBC_MINIMUM_BRIGHTNESS_SET (0x00000732) /* RWXUR */ 1176 #define NV_DPCD_EDP_DBC_MINIMUM_BRIGHTNESS_SET_VAL 4:0 /* RWXUF */ 1177 #define NV_DPCD_EDP_DBC_MINIMUM_BRIGHTNESS_SET_VAL_INIT (0x00000000) /* RWXUV */ 1178 #define NV_DPCD_EDP_DBC_MAXIMUM_BRIGHTNESS_SET (0x00000733) /* RWXUR */ 1179 #define NV_DPCD_EDP_DBC_MAXIMUM_BRIGHTNESS_CAP_VAL 4:0 /* RWXUF */ 1180 #define NV_DPCD_EDP_DBC_MAXIMUM_BRIGHTNESS_CAP_VAL_INIT (0x00000000) /* RWXUV */ 1181 #define NV_DPCD_PANEL_TARGET_LUMINANCE_LSB (0x00000734) /* RWXUR */ 1182 #define NV_DPCD_PANEL_TARGET_LUMINANCE_LSB_VAL 7:0 /* RWXUF */ 1183 #define NV_DPCD_PANEL_TARGET_LUMINANCE_LSB_VAL_INIT (0x00000000) /* RWXUV */ 1184 #define NV_DPCD_PANEL_TARGET_LUMINANCE_MID (0x00000735) /* RWXUR */ 1185 #define NV_DPCD_PANEL_TARGET_LUMINANCE_MID_VAL 7:0 /* RWXUF */ 1186 #define NV_DPCD_PANEL_TARGET_LUMINANCE_MID_VAL_INIT 0x00000000) /* RWXUV */ 1187 #define NV_DPCD_PANEL_TARGET_LUMINANCE_MSB (0x00000736) /* RWXUR */ 1188 #define NV_DPCD_PANEL_TARGET_LUMINANCE_MSB_VAL 7:0 /* RWXUF */ 1189 #define NV_DPCD_PANEL_TARGET_LUMINANCE_MSB_VAL_INIT 0x00000000) /* RWXUV */ 1190 #define NV_DPCD_EDP_REGIONAL_BKLGHT_BASE (0x00000740) /* RWXUR */ 1191 #define NV_DPCD_EDP_REGIONAL_BKLGHT_BASE_INDEX_OFFSET_VAL 7:0 /* RWXUF */ 1192 #define NV_DPCD_EDP_REGIONAL_BKLGHT_BASE_INDEX_OFFSET_VAL_INIT (0x00000000) /* RWXUV */ 1193 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_0 (0x00000741) /* RWXUR */ 1194 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_0_VAL 7:0 /* RWXUF */ 1195 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_0_VAL_INIT (0x00000000) /* RWXUV */ 1196 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_1 (0x00000742) /* RWXUR */ 1197 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_1_VAL 7:0 /* RWXUF */ 1198 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_1_VAL_INIT (0x00000000) /* RWXUV */ 1199 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_2 (0x00000743) /* RWXUR */ 1200 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_2_VAL 7:0 /* RWXUF */ 1201 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_2_VAL_INIT (0x00000000) /* RWXUV */ 1202 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_3 (0x00000744) /* RWXUR */ 1203 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_3_VAL 7:0 /* RWXUF */ 1204 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_3_VAL_INIT (0x00000000) /* RWXUV */ 1205 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_4 (0x00000745) /* RWXUR */ 1206 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_4_VAL 7:0 /* RWXUF */ 1207 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_4_VAL_INIT (0x00000000) /* RWXUV */ 1208 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_5 (0x00000746) /* RWXUR */ 1209 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_5_VAL 7:0 /* RWXUF */ 1210 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_5_VAL_INIT (0x00000000) /* RWXUV */ 1211 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_6 (0x00000747) /* RWXUR */ 1212 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_6_VAL 7:0 /* RWXUF */ 1213 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_6_VAL_INIT (0x00000000) /* RWXUV */ 1214 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_7 (0x00000748) /* RWXUR */ 1215 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_7_VAL 7:0 /* RWXUF */ 1216 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_7_VAL_INIT (0x00000000) /* RWXUV */ 1217 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_8 (0x00000749) /* RWXUR */ 1218 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_8_VAL 7:0 /* RWXUF */ 1219 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_8_VAL_INIT (0x00000000) /* RWXUV */ 1220 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_9 (0x0000074A) /* RWXUR */ 1221 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_9_VAL 7:0 /* RWXUF */ 1222 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_9_VAL_INIT (0x00000000) /* RWXUV */ 1223 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_10 (0x0000074B) /* RWXUR */ 1224 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_10_VAL 7:0 /* RWXUF */ 1225 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_10_VAL_INIT (0x00000000) /* RWXUV */ 1226 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_11 (0x0000074C) /* RWXUR */ 1227 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_11_VAL 7:0 /* RWXUF */ 1228 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_11_VAL_INIT (0x00000000) /* RWXUV */ 1229 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_12 (0x0000074D) /* RWXUR */ 1230 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_12_VAL 7:0 /* RWXUF */ 1231 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_12_VAL_INIT (0x00000000) /* RWXUV */ 1232 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_13 (0x0000074E) /* RWXUR */ 1233 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_13_VAL 7:0 /* RWXUF */ 1234 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_13_VAL_INIT (0x00000000) /* RWXUV */ 1235 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_14 (0x0000074F) /* RWXUR */ 1236 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_14_VAL 7:0 /* RWXUF */ 1237 #define NV_DPCD_EDP_REGIONAL_BACKLIGHT_BRIGHTNESS_14_VAL_INIT (0x00000000) /* RWXUV */ 1238 1239 /* 1240 * 00800h - 00FFFh: RESERVED. Read all 0s 1241 */ 1242 1243 // Sideband MSG Buffers 1244 #define NV_DPCD_MBOX_DOWN_REQ (0x00001000) /* RWXUR */ 1245 #define NV_DPCD_MBOX_UP_REP (0x00001200) /* RWXUR */ 1246 #define NV_DPCD_MBOX_DOWN_REP (0x00001400) /* R-XUR */ 1247 #define NV_DPCD_MBOX_UP_REQ (0x00001600) /* R-XUR */ 1248 1249 // 0x2000 & 0x2001 : RESERVED for USB-over-AUX 1250 1251 // ESI (Event Status Indicator) Field 1252 #define NV_DPCD_SINK_COUNT_ESI (0x00002002) /* R-XUR */ 1253 #define NV_DPCD_SINK_COUNT_ESI_SINK_COUNT 5:0 /* R-XUF */ 1254 #define NV_DPCD_SINK_COUNT_ESI_CP_READY 6:6 /* R-XUF */ 1255 #define NV_DPCD_SINK_COUNT_ESI_CP_READY_NO (0x00000000) /* R-XUV */ 1256 #define NV_DPCD_SINK_COUNT_ESI_CP_READY_YES (0x00000001) /* R-XUV */ 1257 1258 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0 (0x00002003) /* R-XUR */ 1259 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_REMOTE_CTRL 0:0 /* R-XUF */ 1260 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_REMOTE_CTRL_NO (0x00000000) /* R-XUV */ 1261 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_REMOTE_CTRL_YES (0x00000001) /* R-XUV */ 1262 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_AUTO_TEST 1:1 /* R-XUF */ 1263 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_AUTO_TEST_NO (0x00000000) /* R-XUV */ 1264 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_AUTO_TEST_YES (0x00000001) /* R-XUV */ 1265 // for eDP v1.4 & v1.4a only 1266 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_TOUCH_IRQ 1:1 /* R-XUF */ 1267 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_TOUCH_IRQ_NO (0x00000000) /* R-XUV */ 1268 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_TOUCH_IRQ_YES (0x00000001) /* R-XUV */ 1269 1270 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_CP 2:2 /* R-XUF */ 1271 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_CP_NO (0x00000000) /* R-XUV */ 1272 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_CP_YES (0x00000001) /* R-XUV */ 1273 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_MCCS_IRQ 3:3 /* R-XUF */ 1274 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_MCCS_IRQ_NO (0x00000000) /* R-XUV */ 1275 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_MCCS_IRQ_YES (0x00000001) /* R-XUV */ 1276 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_DOWN_REP_MSG_RDY 4:4 /* R-XUF */ 1277 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_DOWN_REP_MSG_RDY_NO (0x00000000) /* R-XUV */ 1278 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_DOWN_REP_MSG_RDY_YES (0x00000001) /* R-XUV */ 1279 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_UP_REQ_MSG_RDY 5:5 /* R-XUF */ 1280 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_UP_REQ_MSG_RDY_NO (0x00000000) /* R-XUV */ 1281 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_UP_REQ_MSG_RDY_YES (0x00000001) /* R-XUV */ 1282 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_SINK_SPECIFIC_IRQ 6:6 /* R-XUF */ 1283 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_SINK_SPECIFIC_IRQ_NO (0x00000000) /* R-XUV */ 1284 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI0_SINK_SPECIFIC_IRQ_YES (0x00000001) /* R-XUV */ 1285 1286 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI1 (0x00002004) /* R-XUR */ 1287 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI1_RX_GTC_MSTR_REQ_STATUS_CHANGE 0:0 /* R-XUF */ 1288 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI1_RX_GTC_MSTR_REQ_STATUS_CHANGE_NO (0x00000000) /* R-XUV */ 1289 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI1_RX_GTC_MSTR_REQ_STATUS_CHANGE_YES (0x00000001) /* R-XUV */ 1290 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI1_PANEL_REPLAY_ERROR_STATUS 3:3 /* R-XUF */ 1291 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI1_PANEL_REPLAY_ERROR_STATUS_NO (0x00000000) /* R-XUV */ 1292 #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI1_PANEL_REPLAY_ERROR_STATUS_YES (0x00000001) /* R-XUV */ 1293 1294 1295 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0 (0x00002005) /* R-XUR */ 1296 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_RX_CAP_CHANGED 0:0 /* R-XUF */ 1297 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_RX_CAP_CHANGED_NO (0x00000000) /* R-XUV */ 1298 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_RX_CAP_CHANGED_YES (0x00000001) /* R-XUV */ 1299 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_LINK_STATUS_CHANGED 1:1 /* R-XUF */ 1300 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_LINK_STATUS_CHANGED_NO (0x00000000) /* R-XUV */ 1301 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_LINK_STATUS_CHANGED_YES (0x00000001) /* R-XUV */ 1302 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_STREAM_STATUS_CHANGED 2:2 /* R-XUF */ 1303 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_STREAM_STATUS_CHANGED_NO (0x00000000) /* R-XUV */ 1304 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_STREAM_STATUS_CHANGED_YES (0x00000001) /* R-XUV */ 1305 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_HDMI_LINK_STATUS_CHANGED 3:3 /* R-XUF */ 1306 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_HDMI_LINK_STATUS_CHANGED_NO (0x00000000) /* R-XUV */ 1307 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_HDMI_LINK_STATUS_CHANGED_YES (0x00000001) /* R-XUV */ 1308 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_CONNECTED_OFF_ENTRY_REQ 4:4 /* R-XUF */ 1309 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_CONNECTED_OFF_ENTRY_REQ_NO (0x00000000) /* R-XUV */ 1310 #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_CONNECTED_OFF_ENTRY_REQ_YES (0x00000001) /* R-XUV */ 1311 1312 #define NV_DPCD_PANEL_SELF_REFRESH_ERR_STATUS (0x00002006) /* R-XUR */ 1313 #define NV_DPCD_PANEL_SELF_REFRESH_ERR_STATUS_LINK_CRC_ERR 0:0 /* R-XUF */ 1314 #define NV_DPCD_PANEL_SELF_REFRESH_ERR_STATUS_LINK_CRC_ERR_NO (0x00000000) /* R-XUV */ 1315 #define NV_DPCD_PANEL_SELF_REFRESH_ERR_STATUS_LINK_CRC_ERR_YES (0x00000001) /* R-XUV */ 1316 #define NV_DPCD_PANEL_SELF_REFRESH_ERR_STATUS_RFB_ERR 1:1 /* R-XUF */ 1317 #define NV_DPCD_PANEL_SELF_REFRESH_ERR_STATUS_RFB_ERR_NO (0x00000000) /* R-XUV */ 1318 #define NV_DPCD_PANEL_SELF_REFRESH_ERR_STATUS_RFB_ERR_YES (0x00000001) /* R-XUV */ 1319 #define NV_DPCD_PANEL_SELF_REFRESH_ERR_STATUS_VSC_SDP_ERR 2:2 /* R-XUF */ 1320 #define NV_DPCD_PANEL_SELF_REFRESH_ERR_STATUS_VSC_SDP_ERR_NO (0x00000000) /* R-XUV */ 1321 #define NV_DPCD_PANEL_SELF_REFRESH_ERR_STATUS_VSC_SDP_ERR_YES (0x00000001) /* R-XUV */ 1322 1323 #define NV_DPCD_PANEL_SELF_REFRESH_EVENT_STATUS (0x00002007) /* R-XUR */ 1324 #define NV_DPCD_PANEL_SELF_REFRESH_EVENT_STATUS_CAP_CHANGE 0:0 /* R-XUF */ 1325 #define NV_DPCD_PANEL_SELF_REFRESH_EVENT_STATUS_CAP_CHANGE_NO (0x00000000) /* R-XUV */ 1326 #define NV_DPCD_PANEL_SELF_REFRESH_EVENT_STATUS_CAP_CHANGE_YES (0x00000001) /* R-XUV */ 1327 1328 #define NV_DPCD_PANEL_SELF_REFRESH_STATUS (0x00002008) /* R-XUR */ 1329 #define NV_DPCD_PANEL_SELF_REFRESH_STATUS_VAL 2:0 /* R-XUF */ 1330 #define NV_DPCD_PANEL_SELF_REFRESH_STATUS_VAL_INACTIVE (0x00000000) /* R-XUV */ 1331 #define NV_DPCD_PANEL_SELF_REFRESH_STATUS_VAL_TRANSITION_TO_ACTIVE (0x00000001) /* R-XUV */ 1332 #define NV_DPCD_PANEL_SELF_REFRESH_STATUS_VAL_ACTIVE_DISP_FROM_RFB (0x00000002) /* R-XUV */ 1333 #define NV_DPCD_PANEL_SELF_REFRESH_STATUS_VAL_ACTIVE_SINK_DEV_TIMING (0x00000003) /* R-XUV */ 1334 #define NV_DPCD_PANEL_SELF_REFRESH_STATUS_VAL_TRANSITION_TO_INACTIVE (0x00000004) /* R-XUV */ 1335 #define NV_DPCD_PANEL_SELF_REFRESH_STATUS_VAL_RESERVED0 (0x00000005) /* R-XUV */ 1336 #define NV_DPCD_PANEL_SELF_REFRESH_STATUS_VAL_RESERVED1 (0x00000006) /* R-XUV */ 1337 #define NV_DPCD_PANEL_SELF_REFRESH_STATUS_VAL_SINK_DEV_INTERNAL_ERR (0x00000007) /* R-XUV */ 1338 1339 #define NV_DPCD_PANEL_SELF_REFRESH_DEBUG0 (0x00002009) /* R-XUR */ 1340 #define NV_DPCD_PANEL_SELF_REFRESH_DEBUG0_MAX_RESYNC_FRAME_CNT 3:0 /* R-XUF */ 1341 #define NV_DPCD_PANEL_SELF_REFRESH_DEBUG0_LAST_RESYNC_FRAME_CNT 7:4 /* R-XUF */ 1342 1343 #define NV_DPCD_PANEL_SELF_REFRESH_DEBUG1 (0x0000200A) /* R-XUR */ 1344 #define NV_DPCD_PANEL_SELF_REFRESH_LAST_SDP (0x0000200A) /* R-XUR */ 1345 #define NV_DPCD_PANEL_SELF_REFRESH_LAST_SDP_PSR_STATE_BIT 0:0 /* R-XUF */ 1346 #define NV_DPCD_PANEL_SELF_REFRESH_LAST_SDP_RFB_BIT 1:1 /* R-XUF */ 1347 #define NV_DPCD_PANEL_SELF_REFRESH_LAST_SDP_CRC_VALID_BIT 2:2 /* R-XUF */ 1348 #define NV_DPCD_PANEL_SELF_REFRESH_LAST_SDP_SU_VALID_BIT 3:3 /* R-XUF */ 1349 #define NV_DPCD_PANEL_SELF_REFRESH_LAST_SDP_SU_FIRST_LINE_RCVD 4:4 /* R-XUF */ 1350 #define NV_DPCD_PANEL_SELF_REFRESH_LAST_SDP_SU_LAST_LINE_RCVD 5:5 /* R-XUF */ 1351 #define NV_DPCD_PANEL_SELF_REFRESH_LAST_SDP_Y_CORD_VALID 6:6 /* R-XUF */ 1352 1353 // 0200Bh: RESERVED. Read all 0s 1354 1355 #define NV_DPCD_LANE0_1_STATUS_ESI (0x0000200C) /* R-XUR */ 1356 #define NV_DPCD_LANE2_3_STATUS_ESI (0x0000200D) /* R-XUR */ 1357 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEX_CR_DONE 0:0 /* R-XUF */ 1358 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEX_CR_DONE_NO (0x00000000) /* R-XUV */ 1359 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEX_CR_DONE_YES (0x00000001) /* R-XUV */ 1360 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEX_CHN_EQ_DONE 1:1 /* R-XUF */ 1361 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEX_CHN_EQ_DONE_NO (0x00000000) /* R-XUV */ 1362 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEX_CHN_EQ_DONE_YES (0x00000001) /* R-XUV */ 1363 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEX_SYMBOL_LOCKED 2:2 /* R-XUF */ 1364 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEX_SYMBOL_LOCKED_NO (0x00000000) /* R-XUV */ 1365 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEX_SYMBOL_LOCKED_YES (0x00000001) /* R-XUV */ 1366 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEXPLUS1_CR_DONE 4:4 /* R-XUF */ 1367 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEXPLUS1_CR_DONE_NO (0x00000000) /* R-XUV */ 1368 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEXPLUS1_CR_DONE_YES (0x00000001) /* R-XUV */ 1369 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEXPLUS1_CHN_EQ_DONE 5:5 /* R-XUF */ 1370 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000) /* R-XUV */ 1371 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001) /* R-XUV */ 1372 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEXPLUS1_SYMBOL_LOCKED 6:6 /* R-XUF */ 1373 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000) /* R-XUV */ 1374 #define NV_DPCD_LANEX_XPLUS1_STATUS_ESI_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001) /* R-XUV */ 1375 1376 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_ESI (0x0000200E) /* R-XUR */ 1377 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_ESI_INTERLANE_ALIGN_DONE 0:0 /* R-XUF */ 1378 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_ESI_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */ 1379 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_ESI_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */ 1380 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_ESI_DOWNSTRM_PORT_STATUS_DONE 6:6 /* R-XUF */ 1381 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_ESI_DOWNSTRM_PORT_STATUS_DONE_NO (0x00000000) /* R-XUV */ 1382 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_ESI_DOWNSTRM_PORT_STATUS_DONE_YES (0x00000001) /* R-XUV */ 1383 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_ESI_LINK_STATUS_UPDATED 7:7 /* R-XUF */ 1384 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_ESI_LINK_STATUS_UPDATED_NO (0x00000000) /* R-XUV */ 1385 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_ESI_LINK_STATUS_UPDATED_YES (0x00000001) /* R-XUV */ 1386 1387 #define NV_DPCD_SINK_STATUS_ESI (0x0000200F) /* R-XUR */ 1388 #define NV_DPCD_SINK_STATUS_ESI_RECEIVE_PORT_0_STATUS 0:0 /* R-XUF */ 1389 #define NV_DPCD_SINK_STATUS_ESI_RECEIVE_PORT_0_STATUS_IN_SYNC_NO (0x00000000) /* R-XUV */ 1390 #define NV_DPCD_SINK_STATUS_ESI_RECEIVE_PORT_0_STATUS_IN_SYNC_YES (0x00000001) /* R-XUV */ 1391 #define NV_DPCD_SINK_STATUS_ESI_RECEIVE_PORT_1_STATUS 1:1 /* R-XUF */ 1392 #define NV_DPCD_SINK_STATUS_ESI_RECEIVE_PORT_1_STATUS_IN_SYNC_NO (0x00000000) /* R-XUV */ 1393 #define NV_DPCD_SINK_STATUS_ESI_RECEIVE_PORT_1_STATUS_IN_SYNC_YES (0x00000001) /* R-XUV */ 1394 1395 // 0x00002010-0x0002025: RESERVED. Read all 0s 1396 #define NV_DPCD_OVERDRIVE_STATUS (0x00002026) /* R-XUR */ 1397 #define NV_DPCD_OVERDRIVE_STATUS_OVERDRIVE_ENGINE_STATUS 0:0 /* R-XUF */ 1398 #define NV_DPCD_OVERDRIVE_STATUS_OVERDRIVE_ENGINE_STATUS_NOT_ACTIVE (0x00000000) /* R-XUV */ 1399 #define NV_DPCD_OVERDRIVE_STATUS_OVERDRIVE_ENGINE_STATUS_ACTIVE (0x00000001) /* R-XUV */ 1400 // 0x00002027-0x00067FF: RESERVED. Read all 0s 1401 1402 #define NV_DPCD_HDCP_BKSV_OFFSET (0x00068000) /* R-XUR */ 1403 #define NV_DPCD_HDCP_RPRIME_OFFSET (0x00068005) /* R-XUR */ 1404 #define NV_DPCD_HDCP_AKSV_OFFSET (0x00068007) /* RWXUR */ 1405 #define NV_DPCD_HDCP_AN_OFFSET (0x0006800C) /* RWXUR */ 1406 #define NV_DPCD_HDCP_BKSV_S_OFFSET (0x00000300) /* RWXUV */ 1407 #define NV_DPCD_HDCP_RPRIME_S_OFFSET (0x00000305) /* RWXUV */ 1408 #define NV_DPCD_HDCP_AKSV_S_OFFSET (0x00000307) /* RWXUV */ 1409 #define NV_DPCD_HDCP_AN_S_OFFSET (0x0000030c) /* RWXUV */ 1410 #define NV_DPCD_HDCP_VPRIME_OFFSET (0x00068014) /* R-XUR */ 1411 #define NV_DPCD_HDCP_BCAPS_OFFSET (0x00068028) /* R-XUR */ 1412 #define NV_DPCD_HDCP_BCAPS_OFFSET_HDCP_CAPABLE 0:0 /* R-XUF */ 1413 #define NV_DPCD_HDCP_BCAPS_OFFSET_HDCP_CAPABLE_NO (0x00000000) /* R-XUV */ 1414 #define NV_DPCD_HDCP_BCAPS_OFFSET_HDCP_CAPABLE_YES (0x00000001) /* R-XUV */ 1415 #define NV_DPCD_HDCP_BCAPS_OFFSET_HDCP_REPEATER 1:1 /* R-XUF */ 1416 #define NV_DPCD_HDCP_BCAPS_OFFSET_HDCP_REPEATER_NO (0x00000000) /* R-XUV */ 1417 #define NV_DPCD_HDCP_BCAPS_OFFSET_HDCP_REPEATER_YES (0x00000001) /* R-XUV */ 1418 #define NV_DPCD_HDCP_BSTATUS_OFFSET (0x00068029) /* R-XUR */ 1419 #define NV_DPCD_HDCP_BSTATUS_REAUTHENTICATION_REQUESET 3:3 /* R-XUF */ 1420 #define NV_DPCD_HDCP_BSTATUS_REAUTHENTICATION_REQUESET_FALSE (0x00000000) /* R-XUV */ 1421 #define NV_DPCD_HDCP_BSTATUS_REAUTHENTICATION_REQUESET_TRUE (0x00000001) /* R-XUV */ 1422 #define NV_DPCD_HDCP_BSTATUS_LINK_INTEGRITY_FAILURE 2:2 /* R-XUF */ 1423 #define NV_DPCD_HDCP_BSTATUS_LINK_INTEGRITY_FAILURE_FALSE (0x00000000) /* R-XUV */ 1424 #define NV_DPCD_HDCP_BSTATUS_LINK_INTEGRITY_FAILURE_TRUE (0x00000001) /* R-XUV */ 1425 #define NV_DPCD_HDCP_BSTATUS_RPRIME_AVAILABLE 1:1 /* R-XUF */ 1426 #define NV_DPCD_HDCP_BSTATUS_RPRIME_AVAILABLE_FALSE (0x00000000) /* R-XUV */ 1427 #define NV_DPCD_HDCP_BSTATUS_RPRIME_AVAILABLE_TRUE (0x00000001) /* R-XUV */ 1428 #define NV_DPCD_HDCP_BSTATUS_READY 0:0 /* R-XUF */ 1429 #define NV_DPCD_HDCP_BSTATUS_READY_FALSE (0x00000000) /* R-XUV */ 1430 #define NV_DPCD_HDCP_BSTATUS_READY_TRUE (0x00000001) /* R-XUV */ 1431 #define NV_DPCD_HDCP_BINFO_OFFSET (0x0006802A) /* R-XUR */ 1432 #define NV_DPCD_HDCP_BINFO_OFFSET_DEVICE_COUNT 6:0 /* R-XUF */ 1433 #define NV_DPCD_HDCP_BINFO_OFFSET_MAX_DEVS_EXCEEDED 7:7 /* R-XUF */ 1434 #define NV_DPCD_HDCP_BINFO_OFFSET_MAX_DEVS_EXCEEDED_FALSE (0x00000000) /* R-XUV */ 1435 #define NV_DPCD_HDCP_BINFO_OFFSET_MAX_DEVS_EXCEEDED_TRUE (0x00000001) /* R-XUV */ 1436 #define NV_DPCD_HDCP_BINFO_OFFSET_DEPTH 10:8 /* R-XUF */ 1437 #define NV_DPCD_HDCP_BINFO_OFFSET_MAX_CASCADE_EXCEEDED 11:11 /* R-XUF */ 1438 #define NV_DPCD_HDCP_BINFO_OFFSET_MAX_CASCADE_EXCEEDED_FALSE (0x00000000) /* R-XUV */ 1439 #define NV_DPCD_HDCP_BINFO_OFFSET_MAX_CASCADE_EXCEEDED_TRUE (0x00000001) /* R-XUV */ 1440 1441 #define NV_DPCD_HDCP_KSV_FIFO_OFFSET (0x0006802C) /* R-XUR */ 1442 1443 #define NV_DPCD_HDCP_AINFO_OFFSET (0x0006803B) /* RWXUR */ 1444 #define NV_DPCD_HDCP_AINFO_OFFSET_REAUTHENTICATION_ENABLE_IRQ_HPD 0:0 /* RWXUF */ 1445 #define NV_DPCD_HDCP_AINFO_OFFSET_REAUTHENTICATION_ENABLE_IRQ_HPD_NO (0x00000000) /* RWXUV */ 1446 #define NV_DPCD_HDCP_AINFO_OFFSET_REAUTHENTICATION_ENABLE_IRQ_HPD_YES (0x00000001) /* RWXUV */ 1447 1448 // Eight-Lane DP Specific DPCD defines 1449 #define NV_DPCD_SL_TRAINING_LANE0_1_SET2(baseAddr) (baseAddr + 0x0000010E) /* RWXUR */ 1450 #define NV_DPCD_SL_TRAINING_LANE2_3_SET2(baseAddr) (baseAddr + 0x0000010F) /* RWXUR */ 1451 #define NV_DPCD_SL_LANE4_5_STATUS(baseAddr) (baseAddr + 0x00000202) /* R-XUR */ 1452 #define NV_DPCD_SL_LANE6_7_STATUS(baseAddr) (baseAddr + 0x00000203) /* R-XUR */ 1453 #define NV_DPCD_DUAL_DP_CAP (0x000003B0) /* RWXUR */ // Dual DP Capability Register 1454 #define NV_DPCD_DUAL_DP_CAP_DDC 0:0 /* RWXUF */ // Dual DP Capability 1455 #define NV_DPCD_DUAL_DP_CAP_DDC_DISABLE (0x00000000) /* RWXUV */ 1456 #define NV_DPCD_DUAL_DP_CAP_DDC_ENABLE (0x00000001) /* RWXUV */ 1457 #define NV_DPCD_DUAL_DP_CAP_DDCIC 1:1 /* RWXUF */ // DDCIC : Dual DP Column Interleave Mode Capability 1458 #define NV_DPCD_DUAL_DP_CAP_DDCIC_DISABLE (0x00000000) /* RWXUV */ 1459 #define NV_DPCD_DUAL_DP_CAP_DDCIC_ENABLE (0x00000001) /* RWXUV */ 1460 #define NV_DPCD_DUAL_DP_CAP_DDPSBSC 2:2 /* RWXUF */ // DDPSBSC : Dual DP Pixel Side-by-Side Mode Capability 1461 #define NV_DPCD_DUAL_DP_CAP_DDPSBSC_DISBALE (0x00000000) /* RWXUV */ 1462 #define NV_DPCD_DUAL_DP_CAP_DDPSBSC_ENABLE (0x00000001) /* RWXUV */ 1463 1464 #define NV_DPCD_DUAL_DP_BASE_ADDRESS 19:0 /* RWXUF */ 1465 #define NV_DPCD_DUAL_DP_COLUMN_WIDTH 15:0 /* RWXUF */ 1466 #define NV_DPCD_DUAL_DP_MAX_LANECOUNT 4:0 /* RWXUF */ 1467 #define NV_DPCD_DUAL_DP_MAX_LANECOUNT_1H 0x1 /* RWXUV */ 1468 #define NV_DPCD_DUAL_DP_MAX_LANECOUNT_2H 0x2 /* RWXUV */ 1469 #define NV_DPCD_DUAL_DP_MAX_LANECOUNT_4H 0x4 /* RWXUV */ 1470 #define NV_DPCD_DUAL_DP_MAX_LANECOUNT_8H 0x8 /* RWXUV */ 1471 1472 #define NV_DPCD_DUAL_DP_DUAL_LINK_CONTROL(baseAddr) (baseAddr + 0x00000110) /* RWXUR */ // Dual Link Control Register 1473 #define NV_DPCD_DUAL_DP_DUAL_LINK_CONTROL_PIX_MODE 1:0 /* RWXUF */ // PIX_MODE : Pixel mode select 1474 #define NV_DPCD_DUAL_DP_DUAL_LINK_CONTROL_PIX_MODE_SIDE_BY_SIDE (0x00000000) /* RWXUV */ // Side by side Mode enabled 1475 #define NV_DPCD_DUAL_DP_DUAL_LINK_CONTROL_PIX_MODE_COL_INTERLEAVE (0x00000001) /* RWXUV */ // Column Interleave Mode enabled 1476 #define NV_DPCD_DUAL_DP_DUAL_LINK_CONTROL_DD_ENABLE 7:7 /* RWXUF */ // DD_ENABLE: Enable Dual DP mode. 1477 #define NV_DPCD_DUAL_DP_DUAL_LINK_CONTROL_DD_ENABLE_TRUE (0x00000001) /* RWXUV */ 1478 #define NV_DPCD_DUAL_DP_DUAL_LINK_CONTROL_DD_ENABLE_FALSE (0x00000000) /* RWXUV */ 1479 1480 #define NV_DPCD_DUAL_DP_PIXEL_OVERLAP(baseAddr) (baseAddr + 0x00000111) /* RWXUR */ // PIXEL_OVERLAP Register 1481 #define NV_DPCD_DUAL_DP_PIXEL_OVERLAP_IGNORE_PIX_COUNT 6:0 /* RWXUF */ // Ignore Pix Count - Number of pixels to ignore 1482 1483 #define NV_DPCD_HDCP22_BCAPS_OFFSET (0x0006921D) /* R-XUR */ 1484 #define NV_DPCD_HDCP22_BCAPS_SIZE (0x00000003) /* R---S */ 1485 #define NV_DPCD_HDCP22_BCAPS_OFFSET_HDCP_REPEATER 0:0 /* R-XUF */ 1486 #define NV_DPCD_HDCP22_BCAPS_OFFSET_HDCP_REPEATER_NO (0x00000000) /* R-XUV */ 1487 #define NV_DPCD_HDCP22_BCAPS_OFFSET_HDCP_REPEATER_YES (0x00000001) /* R-XUV */ 1488 #define NV_DPCD_HDCP22_BCAPS_OFFSET_HDCP_CAPABLE 1:1 /* R-XUF */ 1489 #define NV_DPCD_HDCP22_BCAPS_OFFSET_HDCP_CAPABLE_NO (0x00000000) /* R-XUV */ 1490 #define NV_DPCD_HDCP22_BCAPS_OFFSET_HDCP_CAPABLE_YES (0x00000001) /* R-XUV */ 1491 #define NV_DPCD_HDCP22_BCAPS_OFFSET_RECEIVER_CAPABILITY_MASK 15:2 /* R-XUF */ 1492 #define NV_DPCD_HDCP22_BCAPS_OFFSET_RECEIVER_CAPABILITY_MASK_RESERVED (0x00000000) /* R-XUV */ 1493 #define NV_DPCD_HDCP22_BCAPS_OFFSET_VERSION 23:16 /* R-XUF */ 1494 #define NV_DPCD_HDCP22_BCAPS_OFFSET_VERSION_22 (0x00000002) /* R-XUV */ 1495 1496 #define NV_DPCD_HDCP22_BINFO_OFFSET (0x00069330) /* R-XUR */ 1497 #define NV_DPCD_HDCP22_BINFO_SIZE (0x00000002) /* R---S */ 1498 1499 #define NV_DPCD_HDCP22_RX_STATUS (0x00069493) /* R-XUR */ 1500 #define NV_DPCD_HDCP22_RX_STATUS_SIZE (0x00000001) /* R---S */ 1501 #define NV_DPCD_HDCP22_RX_STATUS_READY 0:0 /* R-XUF */ 1502 #define NV_DPCD_HDCP22_RX_STATUS_READY_YES (0x00000001) /* R-XUV */ 1503 #define NV_DPCD_HDCP22_RX_STATUS_READY_NO (0x00000000) /* R-XUV */ 1504 #define NV_DPCD_HDCP22_RX_STATUS_HPRIME_AVAILABLE 1:1 /* R-XUF */ 1505 #define NV_DPCD_HDCP22_RX_STATUS_HPRIME_AVAILABLE_YES (0x00000001) /* R-XUV */ 1506 #define NV_DPCD_HDCP22_RX_STATUS_HPRIME_AVAILABLE_NO (0x00000000) /* R-XUV */ 1507 #define NV_DPCD_HDCP22_RX_STATUS_PAIRING_AVAILABLE 2:2 /* R-XUF */ 1508 #define NV_DPCD_HDCP22_RX_STATUS_PAIRING_AVAILABLE_YES (0x00000001) /* R-XUV */ 1509 #define NV_DPCD_HDCP22_RX_STATUS_PAIRING_AVAILABLE_NO (0x00000000) /* R-XUV */ 1510 #define NV_DPCD_HDCP22_RX_STATUS_REAUTH_REQUEST 3:3 /* R-XUF */ 1511 #define NV_DPCD_HDCP22_RX_STATUS_REAUTH_REQUEST_YES (0x00000001) /* R-XUV */ 1512 #define NV_DPCD_HDCP22_RX_STATUS_REAUTH_REQUEST_NO (0x00000000) /* R-XUV */ 1513 #define NV_DPCD_HDCP22_RX_STATUS_LINK_INTEGRITY_FAILURE 4:4 /* R-XUF */ 1514 #define NV_DPCD_HDCP22_RX_STATUS_LINK_INTEGRITY_FAILURE_YES (0x00000001) /* R-XUV */ 1515 #define NV_DPCD_HDCP22_RX_STATUS_LINK_INTEGRITY_FAILURE_NO (0x00000000) /* R-XUV */ 1516 1517 #define NV_DPCD_HDCP22_RTX_OFFSET (0x00069000) /* RWXUR */ 1518 #define NV_DPCD_HDCP22_RTX_SIZE (0x00000008) /* R---S */ 1519 1520 #define NV_DPCD_HDCP22_TXCAPS_OFFSET (0x00069008) /* RWXUR */ 1521 #define NV_DPCD_HDCP22_TXCAPS_SIZE (0x00000003) /* R---S */ 1522 1523 #define NV_DPCD_HDCP22_CERTRX (0x0006900B) /* R-XUR */ 1524 #define NV_DPCD_HDCP22_CERTRX_SIZE (0x0000020A) /* R---S */ 1525 1526 #define NV_DPCD_HDCP22_RRX (0x00069215) /* R-XUR */ 1527 #define NV_DPCD_HDCP22_RRX_SIZE (0x00000008) /* R---S */ 1528 1529 #endif // #ifndef _DPCD_H_ 1530