1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 1997-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 // 25 // This file holds NVIDIA Resource Manager registry key definitions that are 26 // shared between Windows and Unix 27 // 28 29 #ifndef NVRM_REGISTRY_H 30 #define NVRM_REGISTRY_H 31 32 #include "nvtypes.h" 33 34 // 35 // Some shared defines with nvReg.h 36 // 37 #if defined(NV_UNIX) 38 #define NV4_REG_GLOBAL_BASE_KEY "" 39 #define NV4_REG_GLOBAL_BASE_PATH "_NV_" 40 #else 41 #define NV4_REG_GLOBAL_BASE_KEY HKEY_LOCAL_MACHINE 42 #define NV4_REG_GLOBAL_BASE_PATH "SOFTWARE\\NVIDIA Corporation\\Global" 43 #endif 44 #define NV4_REG_SUBKEY "NVidia" 45 #define NV4_REG_DISPLAY_DRIVER_SUBKEY "Display" 46 #define NV4_REG_RESOURCE_MANAGER_SUBKEY "System" 47 48 // 49 // Globally overrides the memory type used to store surfaces. 50 // Used by all parts of the driver and stored in the hardware-specific key. 51 // Mirrored from nvReg.h 52 // 53 #define NV_REG_STR_GLOBAL_SURFACE_OVERRIDE "GlobalSurfaceOverrides" 54 #define NV_REG_STR_GLOBAL_SURFACE_OVERRIDE_DISABLE (0x00000000) // Do not use global surface overrides 55 #define NV_REG_STR_GLOBAL_SURFACE_OVERRIDE_ENABLE (0x00000001) 56 #define NV_REG_STR_GLOBAL_SURFACE_OVERRIDE_RM_VALUE 1:0 57 #define NV_REG_STR_GLOBAL_SURFACE_OVERRIDE_RM_ENABLE 3:3 58 59 60 #define NV_REG_STR_RM_OVERRIDE_DEFAULT_TIMEOUT "RmDefaultTimeout" 61 // Type Dword 62 // Override default RM timeout. Measured in milliseconds. 63 // Not scaled for emulation 64 65 #define NV_REG_STR_RM_OVERRIDE_DEFAULT_TIMEOUT_FLAGS "RmDefaultTimeoutFlags" 66 #define NV_REG_STR_RM_OVERRIDE_DEFAULT_TIMEOUT_FLAGS_OSTIMER 4 67 #define NV_REG_STR_RM_OVERRIDE_DEFAULT_TIMEOUT_FLAGS_OSDELAY 8 68 // Type Dword 69 // Override default RM timeout flags to either OSDELAY or OSTIMER. 70 71 72 #define NV_REG_STR_SUPPRESS_CLASS_LIST "SuppressClassList" 73 // Type String 74 // A list of comma separated classes to suppress 75 // examples: 76 // 5097 77 // 4097, 5097 78 // etc 79 80 81 // 82 // Allow instance memory overrides. Some fields are chip specific 83 // and may not apply to all chips. Since there are many fields, 84 // this is spread across several DWORD registry keys. 85 // 86 // Type DWORD 87 // Encoding: 88 // DEFAULT RM determines 89 // COH Coherent system memory 90 // NCOH Non-coherent system memory 91 // VID Local video memory 92 // 93 #define NV_REG_STR_RM_INST_LOC "RMInstLoc" 94 #define NV_REG_STR_RM_INST_LOC_2 "RMInstLoc2" 95 #define NV_REG_STR_RM_INST_LOC_3 "RMInstLoc3" 96 #define NV_REG_STR_RM_INST_LOC_4 "RMInstLoc4" 97 98 #define NV_REG_STR_RM_INST_LOC_DEFAULT (0x00000000) 99 #define NV_REG_STR_RM_INST_LOC_COH (0x00000001) 100 #define NV_REG_STR_RM_INST_LOC_NCOH (0x00000002) 101 #define NV_REG_STR_RM_INST_LOC_VID (0x00000003) 102 103 #define NV_REG_STR_RM_INST_LOC_ALL_DEFAULT (0x00000000) 104 #define NV_REG_STR_RM_INST_LOC_ALL_COH (0x55555555) 105 #define NV_REG_STR_RM_INST_LOC_ALL_NCOH (0xAAAAAAAA) 106 #define NV_REG_STR_RM_INST_LOC_ALL_VID (0xFFFFFFFF) 107 108 // 109 // Allow instance memory overrides. Some fields are chip specific 110 // and may not apply to all chips. Since there are many fields, 111 // this is spread across several DWORD registry keys. 112 // 113 // The registry keys are defined in nvrm_registry. 114 // Specific overrrides are defined here. 115 // 116 // Type DWORD 117 // Encoding: 118 // DEFAULT RM determines 119 // COH Coherent system memory 120 // NCOH Non-coherent system memory 121 // VID Local video memory 122 // 123 #define NV_REG_STR_RM_INST_LOC_PTE 1:0 // Context PTE 124 #define NV_REG_STR_RM_INST_LOC_PTE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 125 #define NV_REG_STR_RM_INST_LOC_PTE_COH NV_REG_STR_RM_INST_LOC_COH 126 #define NV_REG_STR_RM_INST_LOC_PTE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 127 #define NV_REG_STR_RM_INST_LOC_PTE_VID NV_REG_STR_RM_INST_LOC_VID 128 #define NV_REG_STR_RM_INST_LOC_BAR_PTE 3:2 // BAR PTE 129 #define NV_REG_STR_RM_INST_LOC_BAR_PTE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 130 #define NV_REG_STR_RM_INST_LOC_BAR_PTE_COH NV_REG_STR_RM_INST_LOC_COH 131 #define NV_REG_STR_RM_INST_LOC_BAR_PTE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 132 #define NV_REG_STR_RM_INST_LOC_BAR_PTE_VID NV_REG_STR_RM_INST_LOC_VID 133 #define NV_REG_STR_RM_INST_LOC_INSTBLK 5:4 // Instance block 134 #define NV_REG_STR_RM_INST_LOC_INSTBLK_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 135 #define NV_REG_STR_RM_INST_LOC_INSTBLK_COH NV_REG_STR_RM_INST_LOC_COH 136 #define NV_REG_STR_RM_INST_LOC_INSTBLK_NCOH NV_REG_STR_RM_INST_LOC_NCOH 137 #define NV_REG_STR_RM_INST_LOC_INSTBLK_VID NV_REG_STR_RM_INST_LOC_VID 138 #define NV_REG_STR_RM_INST_LOC_RAMFC 7:6 // RAMFC save area 139 #define NV_REG_STR_RM_INST_LOC_RAMFC_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 140 #define NV_REG_STR_RM_INST_LOC_RAMFC_COH NV_REG_STR_RM_INST_LOC_COH 141 #define NV_REG_STR_RM_INST_LOC_RAMFC_NCOH NV_REG_STR_RM_INST_LOC_NCOH 142 #define NV_REG_STR_RM_INST_LOC_RAMFC_VID NV_REG_STR_RM_INST_LOC_VID 143 #define NV_REG_STR_RM_INST_LOC_CACHE1 9:8 // CACHE1 save area 144 #define NV_REG_STR_RM_INST_LOC_CACHE1_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 145 #define NV_REG_STR_RM_INST_LOC_CACHE1_COH NV_REG_STR_RM_INST_LOC_COH 146 #define NV_REG_STR_RM_INST_LOC_CACHE1_NCOH NV_REG_STR_RM_INST_LOC_NCOH 147 #define NV_REG_STR_RM_INST_LOC_CACHE1_VID NV_REG_STR_RM_INST_LOC_VID 148 #define NV_REG_STR_RM_INST_LOC_GRCTX 11:10 // Graphics contxt 149 #define NV_REG_STR_RM_INST_LOC_GRCTX_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 150 #define NV_REG_STR_RM_INST_LOC_GRCTX_COH NV_REG_STR_RM_INST_LOC_COH 151 #define NV_REG_STR_RM_INST_LOC_GRCTX_NCOH NV_REG_STR_RM_INST_LOC_NCOH 152 #define NV_REG_STR_RM_INST_LOC_GRCTX_VID NV_REG_STR_RM_INST_LOC_VID 153 #define NV_REG_STR_RM_INST_LOC_RUNLIST 13:12 // Runlist 154 #define NV_REG_STR_RM_INST_LOC_RUNLIST_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 155 #define NV_REG_STR_RM_INST_LOC_RUNLIST_COH NV_REG_STR_RM_INST_LOC_COH 156 #define NV_REG_STR_RM_INST_LOC_RUNLIST_NCOH NV_REG_STR_RM_INST_LOC_NCOH 157 #define NV_REG_STR_RM_INST_LOC_RUNLIST_VID NV_REG_STR_RM_INST_LOC_VID 158 #define NV_REG_STR_RM_INST_LOC_DISPLAY 15:14 // Display 159 #define NV_REG_STR_RM_INST_LOC_DISPLAY_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 160 #define NV_REG_STR_RM_INST_LOC_DISPLAY_COH NV_REG_STR_RM_INST_LOC_COH 161 #define NV_REG_STR_RM_INST_LOC_DISPLAY_NCOH NV_REG_STR_RM_INST_LOC_NCOH 162 #define NV_REG_STR_RM_INST_LOC_DISPLAY_VID NV_REG_STR_RM_INST_LOC_VID 163 #define NV_REG_STR_RM_INST_LOC_USERD 17:16 // USERD 164 #define NV_REG_STR_RM_INST_LOC_USERD_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 165 #define NV_REG_STR_RM_INST_LOC_USERD_COH NV_REG_STR_RM_INST_LOC_COH 166 #define NV_REG_STR_RM_INST_LOC_USERD_NCOH NV_REG_STR_RM_INST_LOC_NCOH 167 #define NV_REG_STR_RM_INST_LOC_USERD_VID NV_REG_STR_RM_INST_LOC_VID 168 #define NV_REG_STR_RM_INST_LOC_EVENTBUFFER 19:18 // EVENTBUFFER 169 #define NV_REG_STR_RM_INST_LOC_EVENTBUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 170 #define NV_REG_STR_RM_INST_LOC_EVENTBUFFER_COH NV_REG_STR_RM_INST_LOC_COH 171 #define NV_REG_STR_RM_INST_LOC_EVENTBUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 172 #define NV_REG_STR_RM_INST_LOC_EVENTBUFFER_VID NV_REG_STR_RM_INST_LOC_VID 173 #define NV_REG_STR_RM_INST_LOC_UNUSED 21:20 // UNUSED 174 #define NV_REG_STR_RM_INST_LOC_UNUSED_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 175 #define NV_REG_STR_RM_INST_LOC_CIPHER_XCHG 23:22 // Cipher exchange memory resources 176 #define NV_REG_STR_RM_INST_LOC_CIPHER_XCHG_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 177 #define NV_REG_STR_RM_INST_LOC_CIPHER_XCHG_COH NV_REG_STR_RM_INST_LOC_COH 178 #define NV_REG_STR_RM_INST_LOC_CIPHER_XCHG_NCOH NV_REG_STR_RM_INST_LOC_NCOH 179 #define NV_REG_STR_RM_INST_LOC_CIPHER_XCHG_VID NV_REG_STR_RM_INST_LOC_VID 180 #define NV_REG_STR_RM_INST_LOC_PDE 25:24 // Context PDE 181 #define NV_REG_STR_RM_INST_LOC_PDE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 182 #define NV_REG_STR_RM_INST_LOC_PDE_COH NV_REG_STR_RM_INST_LOC_COH 183 #define NV_REG_STR_RM_INST_LOC_PDE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 184 #define NV_REG_STR_RM_INST_LOC_PDE_VID NV_REG_STR_RM_INST_LOC_VID 185 #define NV_REG_STR_RM_INST_LOC_BAR_PDE 27:26 // BAR PDE 186 #define NV_REG_STR_RM_INST_LOC_BAR_PDE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 187 #define NV_REG_STR_RM_INST_LOC_BAR_PDE_COH NV_REG_STR_RM_INST_LOC_COH 188 #define NV_REG_STR_RM_INST_LOC_BAR_PDE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 189 #define NV_REG_STR_RM_INST_LOC_BAR_PDE_VID NV_REG_STR_RM_INST_LOC_VID 190 #define NV_REG_STR_RM_INST_LOC_PMUINST 29:28 // PMUINST 191 #define NV_REG_STR_RM_INST_LOC_PMUINST_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 192 #define NV_REG_STR_RM_INST_LOC_PMUINST_COH NV_REG_STR_RM_INST_LOC_COH 193 #define NV_REG_STR_RM_INST_LOC_PMUINST_NCOH NV_REG_STR_RM_INST_LOC_NCOH 194 #define NV_REG_STR_RM_INST_LOC_PMUINST_VID NV_REG_STR_RM_INST_LOC_VID 195 #define NV_REG_STR_RM_INST_LOC_PMUUCODE 31:30 // PMU UCODE 196 #define NV_REG_STR_RM_INST_LOC_PMUUCODE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 197 #define NV_REG_STR_RM_INST_LOC_PMUUCODE_COH NV_REG_STR_RM_INST_LOC_COH 198 #define NV_REG_STR_RM_INST_LOC_PMUUCODE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 199 #define NV_REG_STR_RM_INST_LOC_PMUUCODE_VID NV_REG_STR_RM_INST_LOC_VID 200 201 #define NV_REG_STR_RM_INST_LOC_2_COMPTAG_STORE 1:0 // Compbit backing store 202 #define NV_REG_STR_RM_INST_LOC_2_COMPTAG_STORE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 203 #define NV_REG_STR_RM_INST_LOC_2_COMPTAG_STORE_COH NV_REG_STR_RM_INST_LOC_COH 204 #define NV_REG_STR_RM_INST_LOC_2_COMPTAG_STORE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 205 #define NV_REG_STR_RM_INST_LOC_2_COMPTAG_STORE_VID NV_REG_STR_RM_INST_LOC_VID 206 #define NV_REG_STR_RM_INST_LOC_2_ATTR_CB 3:2 // Attribute Circular Buffer 207 #define NV_REG_STR_RM_INST_LOC_2_ATTR_CB_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 208 #define NV_REG_STR_RM_INST_LOC_2_ATTR_CB_COH NV_REG_STR_RM_INST_LOC_COH 209 #define NV_REG_STR_RM_INST_LOC_2_ATTR_CB_NCOH NV_REG_STR_RM_INST_LOC_NCOH 210 #define NV_REG_STR_RM_INST_LOC_2_ATTR_CB_VID NV_REG_STR_RM_INST_LOC_VID 211 #define NV_REG_STR_RM_INST_LOC_2_BUNDLE_CB 5:4 // Bundle Circular Buffer 212 #define NV_REG_STR_RM_INST_LOC_2_BUNDLE_CB_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 213 #define NV_REG_STR_RM_INST_LOC_2_BUNDLE_CB_COH NV_REG_STR_RM_INST_LOC_COH 214 #define NV_REG_STR_RM_INST_LOC_2_BUNDLE_CB_NCOH NV_REG_STR_RM_INST_LOC_NCOH 215 #define NV_REG_STR_RM_INST_LOC_2_BUNDLE_CB_VID NV_REG_STR_RM_INST_LOC_VID 216 #define NV_REG_STR_RM_INST_LOC_2_PAGEPOOL 7:6 // Pagepool Buffer 217 #define NV_REG_STR_RM_INST_LOC_2_PAGEPOOL_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 218 #define NV_REG_STR_RM_INST_LOC_2_PAGEPOOL_COH NV_REG_STR_RM_INST_LOC_COH 219 #define NV_REG_STR_RM_INST_LOC_2_PAGEPOOL_NCOH NV_REG_STR_RM_INST_LOC_NCOH 220 #define NV_REG_STR_RM_INST_LOC_2_PAGEPOOL_VID NV_REG_STR_RM_INST_LOC_VID 221 #define NV_REG_STR_RM_INST_LOC_2_GOLD_CTX 9:8 // Golden Context Image 222 #define NV_REG_STR_RM_INST_LOC_2_GOLD_CTX_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 223 #define NV_REG_STR_RM_INST_LOC_2_GOLD_CTX_COH NV_REG_STR_RM_INST_LOC_COH 224 #define NV_REG_STR_RM_INST_LOC_2_GOLD_CTX_NCOH NV_REG_STR_RM_INST_LOC_NCOH 225 #define NV_REG_STR_RM_INST_LOC_2_GOLD_CTX_VID NV_REG_STR_RM_INST_LOC_VID 226 #define NV_REG_STR_RM_INST_LOC_2_BAR_CTX 11:10 // Bar context aperture 227 #define NV_REG_STR_RM_INST_LOC_2_BAR_CTX_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 228 #define NV_REG_STR_RM_INST_LOC_2_BAR_CTX_COH NV_REG_STR_RM_INST_LOC_COH 229 #define NV_REG_STR_RM_INST_LOC_2_BAR_CTX_NCOH NV_REG_STR_RM_INST_LOC_NCOH 230 #define NV_REG_STR_RM_INST_LOC_2_BAR_CTX_VID NV_REG_STR_RM_INST_LOC_VID 231 #define NV_REG_STR_RM_INST_LOC_2_PMU_PWR_RAIL_VIDEO_PRED_BUFFER_SURFACE 13:12 // Power Rail Video Prediction 232 #define NV_REG_STR_RM_INST_LOC_2_PMU_PWR_RAIL_VIDEO_PRED_BUFFER_SURFACE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 233 #define NV_REG_STR_RM_INST_LOC_2_PMU_PWR_RAIL_VIDEO_PRED_BUFFER_SURFACE_COH NV_REG_STR_RM_INST_LOC_COH 234 #define NV_REG_STR_RM_INST_LOC_2_PMU_PWR_RAIL_VIDEO_PRED_BUFFER_SURFACE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 235 #define NV_REG_STR_RM_INST_LOC_2_PMU_PWR_RAIL_VIDEO_PRED_BUFFER_SURFACE_VID NV_REG_STR_RM_INST_LOC_VID 236 #define NV_REG_STR_RM_INST_LOC_2_CTX_PATCH 15:14 // context patch 237 #define NV_REG_STR_RM_INST_LOC_2_CTX_PATCH_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 238 #define NV_REG_STR_RM_INST_LOC_2_CTX_PATCH_COH NV_REG_STR_RM_INST_LOC_COH 239 #define NV_REG_STR_RM_INST_LOC_2_CTX_PATCH_NCOH NV_REG_STR_RM_INST_LOC_NCOH 240 #define NV_REG_STR_RM_INST_LOC_2_CTX_PATCH_VID NV_REG_STR_RM_INST_LOC_VID 241 #define NV_REG_STR_RM_INST_LOC_2_MMU_READ 17:16 // MMU Read 242 #define NV_REG_STR_RM_INST_LOC_2_MMU_READ_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 243 #define NV_REG_STR_RM_INST_LOC_2_MMU_READ_COH NV_REG_STR_RM_INST_LOC_COH 244 #define NV_REG_STR_RM_INST_LOC_2_MMU_READ_NCOH NV_REG_STR_RM_INST_LOC_NCOH 245 #define NV_REG_STR_RM_INST_LOC_2_MMU_READ_VID NV_REG_STR_RM_INST_LOC_VID 246 #define NV_REG_STR_RM_INST_LOC_2_MMU_WRITE 19:18 // MMU Write 247 #define NV_REG_STR_RM_INST_LOC_2_MMU_WRITE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 248 #define NV_REG_STR_RM_INST_LOC_2_MMU_WRITE_COH NV_REG_STR_RM_INST_LOC_COH 249 #define NV_REG_STR_RM_INST_LOC_2_MMU_WRITE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 250 #define NV_REG_STR_RM_INST_LOC_2_MMU_WRITE_VID NV_REG_STR_RM_INST_LOC_VID 251 #define NV_REG_STR_RM_INST_LOC_2_UNUSED 21:20 // Unused 252 #define NV_REG_STR_RM_INST_LOC_2_ZCULLCTX 23:22 // zcull context buffer 253 #define NV_REG_STR_RM_INST_LOC_2_ZCULLCTX_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 254 #define NV_REG_STR_RM_INST_LOC_2_ZCULLCTX_COH NV_REG_STR_RM_INST_LOC_COH 255 #define NV_REG_STR_RM_INST_LOC_2_ZCULLCTX_NCOH NV_REG_STR_RM_INST_LOC_NCOH 256 #define NV_REG_STR_RM_INST_LOC_2_ZCULLCTX_VID NV_REG_STR_RM_INST_LOC_VID 257 #define NV_REG_STR_RM_INST_LOC_2_PMCTX 25:24 // PM context buffer 258 #define NV_REG_STR_RM_INST_LOC_2_PMCTX_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 259 #define NV_REG_STR_RM_INST_LOC_2_PMCTX_COH NV_REG_STR_RM_INST_LOC_COH 260 #define NV_REG_STR_RM_INST_LOC_2_PMCTX_NCOH NV_REG_STR_RM_INST_LOC_NCOH 261 #define NV_REG_STR_RM_INST_LOC_2_PMCTX_VID NV_REG_STR_RM_INST_LOC_VID 262 #define NV_REG_STR_RM_INST_LOC_2_DPUDBG 27:26 // DPU Debug/Falctrace Buffer 263 #define NV_REG_STR_RM_INST_LOC_2_DPUDBG_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 264 #define NV_REG_STR_RM_INST_LOC_2_DPUDBG_COH NV_REG_STR_RM_INST_LOC_COH 265 #define NV_REG_STR_RM_INST_LOC_2_DPUDBG_NCOH NV_REG_STR_RM_INST_LOC_NCOH 266 #define NV_REG_STR_RM_INST_LOC_2_DPUDBG_VID NV_REG_STR_RM_INST_LOC_VID 267 #define NV_REG_STR_RM_INST_LOC_2_PMUPG 29:28 // PMU PG buffer 268 #define NV_REG_STR_RM_INST_LOC_2_PMUPG_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 269 #define NV_REG_STR_RM_INST_LOC_2_PMUPG_COH NV_REG_STR_RM_INST_LOC_COH 270 #define NV_REG_STR_RM_INST_LOC_2_PMUPG_NCOH NV_REG_STR_RM_INST_LOC_NCOH 271 #define NV_REG_STR_RM_INST_LOC_2_PMUPG_VID NV_REG_STR_RM_INST_LOC_VID 272 #define NV_REG_STR_RM_INST_LOC_2_PMU_LOGGER 31:30 273 #define NV_REG_STR_RM_INST_LOC_2_PMU_LOGGER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 274 #define NV_REG_STR_RM_INST_LOC_2_PMU_LOGGER_COH NV_REG_STR_RM_INST_LOC_COH 275 #define NV_REG_STR_RM_INST_LOC_2_PMU_LOGGER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 276 #define NV_REG_STR_RM_INST_LOC_2_PMU_LOGGER_VID NV_REG_STR_RM_INST_LOC_VID 277 278 #define NV_REG_STR_RM_INST_LOC_3_PG_LOG_SURFACE 1:0 // PG log surface 279 #define NV_REG_STR_RM_INST_LOC_3_PG_LOG_SURFACE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 280 #define NV_REG_STR_RM_INST_LOC_3_PG_LOG_SURFACE_COH NV_REG_STR_RM_INST_LOC_COH 281 #define NV_REG_STR_RM_INST_LOC_3_PG_LOG_SURFACE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 282 #define NV_REG_STR_RM_INST_LOC_3_PG_LOG_SURFACE_VID NV_REG_STR_RM_INST_LOC_VID 283 #define NV_REG_STR_RM_INST_LOC_3_PREEMPT_BUFFER 3:2 // Preemption buffer 284 #define NV_REG_STR_RM_INST_LOC_3_PREEMPT_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 285 #define NV_REG_STR_RM_INST_LOC_3_PREEMPT_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 286 #define NV_REG_STR_RM_INST_LOC_3_PREEMPT_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 287 #define NV_REG_STR_RM_INST_LOC_3_PREEMPT_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 288 #define NV_REG_STR_RM_INST_LOC_3_GFXP_BETACB_BUFFER 5:4 // GFXP BetaCB buffer 289 #define NV_REG_STR_RM_INST_LOC_3_GFXP_BETACB_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 290 #define NV_REG_STR_RM_INST_LOC_3_GFXP_BETACB_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 291 #define NV_REG_STR_RM_INST_LOC_3_GFXP_BETACB_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 292 #define NV_REG_STR_RM_INST_LOC_3_GFXP_BETACB_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 293 #define NV_REG_STR_RM_INST_LOC_3_GFXP_PAGEPOOL_BUFFER 7:6 // GFXP Pagepool buffer 294 #define NV_REG_STR_RM_INST_LOC_3_GFXP_PAGEPOOL_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 295 #define NV_REG_STR_RM_INST_LOC_3_GFXP_PAGEPOOL_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 296 #define NV_REG_STR_RM_INST_LOC_3_GFXP_PAGEPOOL_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 297 #define NV_REG_STR_RM_INST_LOC_3_GFXP_PAGEPOOL_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 298 #define NV_REG_STR_RM_INST_LOC_3_BSI_IMAGE 9:8 // BSI RAM image 299 #define NV_REG_STR_RM_INST_LOC_3_BSI_IMAGE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 300 #define NV_REG_STR_RM_INST_LOC_3_BSI_IMAGE_COH NV_REG_STR_RM_INST_LOC_COH 301 #define NV_REG_STR_RM_INST_LOC_3_BSI_IMAGE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 302 #define NV_REG_STR_RM_INST_LOC_3_BSI_IMAGE_VID NV_REG_STR_RM_INST_LOC_VID 303 #define NV_REG_STR_RM_INST_LOC_3_PRIV_ACCESS_MAP 11:10 // Priv whitelist buffer 304 #define NV_REG_STR_RM_INST_LOC_3_PRIV_ACCESS_MAP_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 305 #define NV_REG_STR_RM_INST_LOC_3_PRIV_ACCESS_MAP_COH NV_REG_STR_RM_INST_LOC_COH 306 #define NV_REG_STR_RM_INST_LOC_3_PRIV_ACCESS_MAP_NCOH NV_REG_STR_RM_INST_LOC_NCOH 307 #define NV_REG_STR_RM_INST_LOC_3_PRIV_ACCESS_MAP_VID NV_REG_STR_RM_INST_LOC_VID 308 #define NV_REG_STR_RM_INST_LOC_3_SEC2DBG 13:12 // SEC2 Debug/Falctrace Buffer 309 #define NV_REG_STR_RM_INST_LOC_3_SEC2DBG_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 310 #define NV_REG_STR_RM_INST_LOC_3_SEC2DBG_COH NV_REG_STR_RM_INST_LOC_COH 311 #define NV_REG_STR_RM_INST_LOC_3_SEC2DBG_NCOH NV_REG_STR_RM_INST_LOC_NCOH 312 #define NV_REG_STR_RM_INST_LOC_3_SEC2DBG_VID NV_REG_STR_RM_INST_LOC_VID 313 #define NV_REG_STR_RM_INST_LOC_3_FECS_UCODE 15:14 // FECS UCODE 314 #define NV_REG_STR_RM_INST_LOC_3_FECS_UCODE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 315 #define NV_REG_STR_RM_INST_LOC_3_FECS_UCODE_COH NV_REG_STR_RM_INST_LOC_COH 316 #define NV_REG_STR_RM_INST_LOC_3_FECS_UCODE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 317 #define NV_REG_STR_RM_INST_LOC_3_FECS_UCODE_VID NV_REG_STR_RM_INST_LOC_VID 318 #define NV_REG_STR_RM_INST_LOC_3_GFXP_SPILL_BUFFER 17:16 // GFXP Pagepool buffer 319 #define NV_REG_STR_RM_INST_LOC_3_GFXP_SPILL_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 320 #define NV_REG_STR_RM_INST_LOC_3_GFXP_SPILL_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 321 #define NV_REG_STR_RM_INST_LOC_3_GFXP_SPILL_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 322 #define NV_REG_STR_RM_INST_LOC_3_GFXP_SPILL_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 323 #define NV_REG_STR_RM_INST_LOC_3_UVM_FAULT_BUFFER_NONREPLAYABLE 19:18 // UVM Non-Replayable fault buffer 324 #define NV_REG_STR_RM_INST_LOC_3_UVM_FAULT_BUFFER_NONREPLAYABLE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 325 #define NV_REG_STR_RM_INST_LOC_3_UVM_FAULT_BUFFER_NONREPLAYABLE_COH NV_REG_STR_RM_INST_LOC_COH 326 #define NV_REG_STR_RM_INST_LOC_3_UVM_FAULT_BUFFER_NONREPLAYABLE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 327 #define NV_REG_STR_RM_INST_LOC_3_UVM_FAULT_BUFFER_NONREPLAYABLE_VID NV_REG_STR_RM_INST_LOC_VID 328 #define NV_REG_STR_RM_INST_LOC_3_BAR_SCRATCH_PAGE 21:20 // BAR scratch pages 329 #define NV_REG_STR_RM_INST_LOC_3_BAR_SCRATCH_PAGE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 330 #define NV_REG_STR_RM_INST_LOC_3_BAR_SCRATCH_PAGE_COH NV_REG_STR_RM_INST_LOC_COH 331 #define NV_REG_STR_RM_INST_LOC_3_BAR_SCRATCH_PAGE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 332 #define NV_REG_STR_RM_INST_LOC_3_BAR_SCRATCH_PAGE_VID NV_REG_STR_RM_INST_LOC_VID 333 #define NV_REG_STR_RM_INST_LOC_3_FLCNINST 23:22 // FLCNINST 334 #define NV_REG_STR_RM_INST_LOC_3_FLCNINST_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 335 #define NV_REG_STR_RM_INST_LOC_3_FLCNINST_COH NV_REG_STR_RM_INST_LOC_COH 336 #define NV_REG_STR_RM_INST_LOC_3_FLCNINST_NCOH NV_REG_STR_RM_INST_LOC_NCOH 337 #define NV_REG_STR_RM_INST_LOC_3_FLCNINST_VID NV_REG_STR_RM_INST_LOC_VID 338 #define NV_REG_STR_RM_INST_LOC_3_RTVCB_BUFFER 25:24 // RTVCB buffer 339 #define NV_REG_STR_RM_INST_LOC_3_RTVCB_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 340 #define NV_REG_STR_RM_INST_LOC_3_RTVCB_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 341 #define NV_REG_STR_RM_INST_LOC_3_RTVCB_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 342 #define NV_REG_STR_RM_INST_LOC_3_RTVCB_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 343 #define NV_REG_STR_RM_INST_LOC_3_GFXP_RTVCB_BUFFER 27:26 // GFXP RTVCB buffer 344 #define NV_REG_STR_RM_INST_LOC_3_GFXP_RTVCB_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 345 #define NV_REG_STR_RM_INST_LOC_3_GFXP_RTVCB_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 346 #define NV_REG_STR_RM_INST_LOC_3_GFXP_RTVCB_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 347 #define NV_REG_STR_RM_INST_LOC_3_GFXP_RTVCB_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 348 #define NV_REG_STR_RM_INST_LOC_3_FAULT_METHOD_BUFFER 29:28 // Fault method buffer 349 #define NV_REG_STR_RM_INST_LOC_3_FAULT_METHOD_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 350 #define NV_REG_STR_RM_INST_LOC_3_FAULT_METHOD_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 351 #define NV_REG_STR_RM_INST_LOC_3_FAULT_METHOD_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 352 #define NV_REG_STR_RM_INST_LOC_3_FAULT_METHOD_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 353 #define NV_REG_STR_RM_INST_LOC_3_PMU_DPU_DMA 31:30 // PMU/DPU DMA transfers 354 #define NV_REG_STR_RM_INST_LOC_3_PMU_DPU_DMA_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 355 #define NV_REG_STR_RM_INST_LOC_3_PMU_DPU_DMA_COH NV_REG_STR_RM_INST_LOC_COH 356 #define NV_REG_STR_RM_INST_LOC_3_PMU_DPU_DMA_NCOH NV_REG_STR_RM_INST_LOC_NCOH 357 #define NV_REG_STR_RM_INST_LOC_3_PMU_DPU_DMA_VID NV_REG_STR_RM_INST_LOC_VID 358 359 #define NV_REG_STR_RM_INST_LOC_4_DISP_SC 1:0 // Display state cache buffer 360 #define NV_REG_STR_RM_INST_LOC_4_DISP_SC_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 361 #define NV_REG_STR_RM_INST_LOC_4_DISP_SC_COH NV_REG_STR_RM_INST_LOC_COH 362 #define NV_REG_STR_RM_INST_LOC_4_DISP_SC_NCOH NV_REG_STR_RM_INST_LOC_NCOH 363 #define NV_REG_STR_RM_INST_LOC_4_DISP_SC_VID NV_REG_STR_RM_INST_LOC_VID 364 #define NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER 3:2 // FIFO channel push buffer 365 #define NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 366 #define NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_COH NV_REG_STR_RM_INST_LOC_COH 367 #define NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 368 #define NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_VID NV_REG_STR_RM_INST_LOC_VID 369 #define NV_REG_STR_RM_INST_LOC_4_FW_SEC_LIC_COMMAND 5:4 // Firmware security license command 370 #define NV_REG_STR_RM_INST_LOC_4_FW_SEC_LIC_COMMAND_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 371 #define NV_REG_STR_RM_INST_LOC_4_FW_SEC_LIC_COMMAND_COH NV_REG_STR_RM_INST_LOC_COH 372 #define NV_REG_STR_RM_INST_LOC_4_FW_SEC_LIC_COMMAND_NCOH NV_REG_STR_RM_INST_LOC_NCOH 373 #define NV_REG_STR_RM_INST_LOC_4_FW_SEC_LIC_COMMAND_VID NV_REG_STR_RM_INST_LOC_VID 374 #define NV_REG_STR_RM_INST_LOC_4_VRDS 7:6 // VBIOS runtime data security 375 #define NV_REG_STR_RM_INST_LOC_4_VRDS_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 376 #define NV_REG_STR_RM_INST_LOC_4_VRDS_COH NV_REG_STR_RM_INST_LOC_COH 377 #define NV_REG_STR_RM_INST_LOC_4_VRDS_NCOH NV_REG_STR_RM_INST_LOC_NCOH 378 #define NV_REG_STR_RM_INST_LOC_4_VRDS_VID NV_REG_STR_RM_INST_LOC_VID 379 #define NV_REG_STR_RM_INST_LOC_4_FLCN_UCODE_BUFFERS 9:8 // Falcon uCode buffers 380 #define NV_REG_STR_RM_INST_LOC_4_FLCN_UCODE_BUFFERS_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 381 #define NV_REG_STR_RM_INST_LOC_4_FLCN_UCODE_BUFFERS_COH NV_REG_STR_RM_INST_LOC_COH 382 #define NV_REG_STR_RM_INST_LOC_4_FLCN_UCODE_BUFFERS_NCOH NV_REG_STR_RM_INST_LOC_NCOH 383 #define NV_REG_STR_RM_INST_LOC_4_FLCN_UCODE_BUFFERS_VID NV_REG_STR_RM_INST_LOC_VID 384 #define NV_REG_STR_RM_INST_LOC_4_UVM_FAULT_BUFFER_REPLAYABLE 11:10 // UVM Replayable fault buffer 385 #define NV_REG_STR_RM_INST_LOC_4_UVM_FAULT_BUFFER_REPLAYABLE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 386 #define NV_REG_STR_RM_INST_LOC_4_UVM_FAULT_BUFFER_REPLAYABLE_COH NV_REG_STR_RM_INST_LOC_COH 387 #define NV_REG_STR_RM_INST_LOC_4_UVM_FAULT_BUFFER_REPLAYABLE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 388 #define NV_REG_STR_RM_INST_LOC_4_UVM_FAULT_BUFFER_REPLAYABLE_VID NV_REG_STR_RM_INST_LOC_VID 389 390 // 391 // Separately define instance block location of BARs. Default Setting 392 // reverts to NV_REG_STR_RM_INST_LOC_INSTBLK 393 // 394 #define NV_REG_STR_RM_INST_LOC_4_BAR 13:12 // BAR Bind location 395 #define NV_REG_STR_RM_INST_LOC_4_BAR_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 396 #define NV_REG_STR_RM_INST_LOC_4_BAR_COH NV_REG_STR_RM_INST_LOC_COH 397 #define NV_REG_STR_RM_INST_LOC_4_BAR_NCOH NV_REG_STR_RM_INST_LOC_NCOH 398 #define NV_REG_STR_RM_INST_LOC_4_BAR_VID NV_REG_STR_RM_INST_LOC_VID 399 400 // 401 // Separately define instance block location of async CEs. Default Setting 402 // reverts to NV_REG_STR_RM_INST_LOC_INSTBLK 403 // 404 #define NV_REG_STR_RM_INST_LOC_4_CE 15:14 // Async CE Bind location 405 #define NV_REG_STR_RM_INST_LOC_4_CE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 406 #define NV_REG_STR_RM_INST_LOC_4_CE_COH NV_REG_STR_RM_INST_LOC_COH 407 #define NV_REG_STR_RM_INST_LOC_4_CE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 408 #define NV_REG_STR_RM_INST_LOC_4_CE_VID NV_REG_STR_RM_INST_LOC_VID 409 410 // 411 // Separately define instance block location of GR/GRCE. Default Setting 412 // reverts to NV_REG_STR_RM_INST_LOC_INSTBLK 413 // 414 #define NV_REG_STR_RM_INST_LOC_4_GR 17:16 // GR/GRCE Bind location 415 #define NV_REG_STR_RM_INST_LOC_4_GR_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 416 #define NV_REG_STR_RM_INST_LOC_4_GR_COH NV_REG_STR_RM_INST_LOC_COH 417 #define NV_REG_STR_RM_INST_LOC_4_GR_NCOH NV_REG_STR_RM_INST_LOC_NCOH 418 #define NV_REG_STR_RM_INST_LOC_4_GR_VID NV_REG_STR_RM_INST_LOC_VID 419 420 // 421 // Separately define instance block location of VEs. Default Setting 422 // reverts to NV_REG_STR_RM_INST_LOC_INSTBLK 423 // 424 #define NV_REG_STR_RM_INST_LOC_4_FALCON 19:18 // FALCON Bind location 425 #define NV_REG_STR_RM_INST_LOC_4_FALCON_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 426 #define NV_REG_STR_RM_INST_LOC_4_FALCON_COH NV_REG_STR_RM_INST_LOC_COH 427 #define NV_REG_STR_RM_INST_LOC_4_FALCON_NCOH NV_REG_STR_RM_INST_LOC_NCOH 428 #define NV_REG_STR_RM_INST_LOC_4_FALCON_VID NV_REG_STR_RM_INST_LOC_VID 429 430 // 431 // Separately define instance block location of HWPM PMA. Default Setting 432 // reverts to NV_REG_STR_RM_INST_LOC_INSTBLK 433 // 434 #define NV_REG_STR_RM_INST_LOC_4_HWPM_PMA 21:20 // HWPM PMA Bind location 435 #define NV_REG_STR_RM_INST_LOC_4_HWPM_PMA_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 436 #define NV_REG_STR_RM_INST_LOC_4_HWPM_PMA_COH NV_REG_STR_RM_INST_LOC_COH 437 #define NV_REG_STR_RM_INST_LOC_4_HWPM_PMA_NCOH NV_REG_STR_RM_INST_LOC_NCOH 438 #define NV_REG_STR_RM_INST_LOC_4_HWPM_PMA_VID NV_REG_STR_RM_INST_LOC_VID 439 440 // 441 // Separately define instance block location of HWPM PMA. Default Setting 442 // reverts to NV_REG_STR_RM_INST_LOC_INSTBLK 443 // 444 #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF 23:22 // FECS EVENT buffer location 445 #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 446 #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF_COH NV_REG_STR_RM_INST_LOC_COH 447 #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF_NCOH NV_REG_STR_RM_INST_LOC_NCOH 448 #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF_VID NV_REG_STR_RM_INST_LOC_VID 449 450 // 451 // Overrides for the GFXP SETUP buffer 452 // 453 #define NV_REG_STR_RM_INST_LOC_4_GFXP_SETUP_BUFFER 25:24 // GFXP SETUP buffer 454 #define NV_REG_STR_RM_INST_LOC_4_GFXP_SETUP_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 455 #define NV_REG_STR_RM_INST_LOC_4_GFXP_SETUP_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 456 #define NV_REG_STR_RM_INST_LOC_4_GFXP_SETUP_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 457 #define NV_REG_STR_RM_INST_LOC_4_GFXP_SETUP_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 458 459 #define NV_REG_STR_RM_GSP_STATUS_QUEUE_SIZE "RmGspStatusQueueSize" 460 // TYPE DWORD 461 // Set the GSP status queue size in KB (for GSP to CPU RPC status and event communication) 462 463 #define NV_REG_STR_RM_MSG "RmMsg" 464 // Type String: Set parameters for RM DBG_PRINTF. Only for builds with printfs enabled. 465 // Encoding: 466 // rule = [!][filename|function][:startline][-endline] 467 // Format = rule[,rule] 468 469 470 #define NV_REG_STR_RM_THREAD_STATE_SETUP_FLAGS "RmThreadStateSetupFlags" 471 // Type DWORD 472 // Enables or disables various ThreadState features 473 // See resman/inc/kernel/core/thread_state.h for 474 // THREAD_STATE_SETUP_FLAGS values. 475 476 477 #define NV_REG_STR_RM_ENABLE_EVENT_TRACER "RMEnableEventTracer" 478 #define NV_REG_STR_RM_ENABLE_EVENT_TRACER_DISABLE 0 479 #define NV_REG_STR_RM_ENABLE_EVENT_TRACER_ENABLE 1 480 #define NV_REG_STR_RM_ENABLE_EVENT_TRACER_DEFAULT NV_REG_STR_RM_ENABLE_EVENT_TRACER_DISABLE 481 // Type DWORD 482 // Encoding boolean 483 // Enable/Disable RM event tracing 484 // 0 - Disable RM event tracing 485 // 1 - Enable RM event tracing 486 487 488 #define NV_REG_STR_RM_COMPUTE_MODE_RULES "RmComputeModeRules" 489 // Type DWORD 490 // Saves the last compute mode rule set by the client. 491 // Encoding: 492 // Bits 31:0 : Last compute mode rule set by the client 493 494 495 #define NV_REG_STR_RM_NVLOG_EXTRA_BUFFER_1 "RMNvLogExtraBuffer1" 496 // #define NV_REG_STR_RM_NVLOG_EXTRA_BUFFER_2 "RMNvLogExtraBuffer2" 497 // #define NV_REG_STR_RM_NVLOG_EXTRA_BUFFER_3 "RMNvLogExtraBuffer3" 498 // #define NV_REG_STR_RM_NVLOG_EXTRA_BUFFER_4 "RMNvLogExtraBuffer4" 499 // #define NV_REG_STR_RM_NVLOG_EXTRA_BUFFER_5 "RMNvLogExtraBuffer5" 500 // #define NV_REG_STR_RM_NVLOG_EXTRA_BUFFER_6 "RMNvLogExtraBuffer6" 501 // Type DWORD 502 // Used to specify up to 6 additional logging buffers 503 // Encoding: 504 // _BUFFER_FLAGS 505 // x: uses NVLOG_BUFFER_FLAGS fields, for main nvlog buffer 506 // _BUFFER_SIZE 507 // n: Size of main buffer, in kilobytes 508 509 510 // Type DWORD 511 // This can be used for dumping NvLog buffers (in /var/log/vmkernel.log ), when 512 // we hit critical XIDs e.g 31/79. 513 #define NV_REG_STR_RM_DUMP_NVLOG "RMDumpNvLog" 514 #define NV_REG_STR_RM_DUMP_NVLOG_DEFAULT (0x00000000) 515 #define NV_REG_STR_RM_DUMP_NVLOG_DISABLE (0x00000000) 516 #define NV_REG_STR_RM_DUMP_NVLOG_ENABLE (0x00000001) 517 518 519 // 520 // Type DWORD 521 // RM external fabric management. 522 // 523 // RM currently uses nvlink core driver APIs which internally trigger 524 // link initialization and training. However, nvlink core driver now exposes a 525 // set of APIs for managing nvlink fabric externally (from user mode). 526 // 527 // When the regkey is enabled, RM will skip use of APIs which trigger 528 // link initialization and training. In that case, link training needs to be 529 // triggered externally. 530 // 531 #define NV_REG_STR_RM_EXTERNAL_FABRIC_MGMT "RMExternalFabricMgmt" 532 #define NV_REG_STR_RM_EXTERNAL_FABRIC_MGMT_MODE 0:0 533 #define NV_REG_STR_RM_EXTERNAL_FABRIC_MGMT_MODE_ENABLE (0x00000001) 534 #define NV_REG_STR_RM_EXTERNAL_FABRIC_MGMT_MODE_DISABLE (0x00000000) 535 536 537 // 538 // Type DWORD 539 // BIT 1:0: All Data validation 540 // 0 - Default 541 // 1 - Validate the kernel data - enable all below 542 // 2 - Do not validate the kernel data - disable all below 543 // BIT 3:2: Buffer validation 544 // 0 - Default 545 // 1 - Validate the kernel buffers 546 // 2 - Do not validate the kernel buffers 547 // BIT 5:4: Handle validation 548 // 0 - Default 549 // 1 - Validate the handles 550 // 2 - Do not validate the handles 551 // BIT 7:6: Strict client validation 552 // 0 - Default 553 // 1 - Enable strict client validation 554 // 2 - Do not enable strict client validation 555 // 556 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION "RmValidateClientData" 557 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_ALL 1:0 558 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_ALL_DEFAULT 0x00000000 559 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_ALL_ENABLED 0x00000001 560 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_ALL_DISABLED 0x00000002 561 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_KERNEL_BUFFERS 3:2 562 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_KERNEL_BUFFERS_DEFAULT 0x00000000 563 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_KERNEL_BUFFERS_ENABLED 0x00000001 564 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_KERNEL_BUFFERS_DISABLED 0x00000002 565 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_HANDLE 5:4 566 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_HANDLE_DEFAULT 0x00000000 567 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_HANDLE_ENABLED 0x00000001 568 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_HANDLE_DISABLED 0x00000002 569 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_STRICT_CLIENT 7:6 570 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_STRICT_CLIENT_DEFAULT 0x00000000 571 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_STRICT_CLIENT_ENABLED 0x00000001 572 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_STRICT_CLIENT_DISABLED 0x00000002 573 574 575 // 576 // Type: Dword 577 // Encoding: 578 // 1 - Enable remote GPU 579 // 0 - Disable remote GPU 580 // 581 #define NV_REG_STR_RM_REMOTE_GPU "RMRemoteGpu" 582 #define NV_REG_STR_RM_REMOTE_GPU_ENABLE 0x00000001 583 #define NV_REG_STR_RM_REMOTE_GPU_DISABLE 0x00000000 584 #define NV_REG_STR_RM_REMOTE_GPU_DEFAULT NV_REG_STR_RM_REMOTE_GPU_DISABLE 585 586 587 // 588 // Type: DWORD 589 // 590 // This regkey configures thread priority boosting whenever 591 // the thread is holding a GPU lock. 592 // 593 #define NV_REG_STR_RM_PRIORITY_BOOST "RMPriorityBoost" 594 #define NV_REG_STR_RM_PRIORITY_BOOST_DISABLE 0x00000000 595 #define NV_REG_STR_RM_PRIORITY_BOOST_ENABLE 0x00000001 596 #define NV_REG_STR_RM_PRIORITY_BOOST_DEFAULT NV_REG_STR_RM_PRIORITY_BOOST_DISABLE 597 598 599 // 600 // Type: DWORD 601 // 602 // This regkey configures the delay (us) before a boosted thread is throttled 603 // down. 604 // 605 // Default value: 0 (Disable) 606 // 607 #define NV_REG_STR_RM_PRIORITY_THROTTLE_DELAY "RMPriorityThrottleDelay" 608 #define NV_REG_STR_RM_PRIORITY_THROTTLE_DELAY_DISABLE 0x00000000 609 610 611 // 612 // Type DWORD 613 // Enable support for CUDA Stream Memory Operations in user-mode applications. 614 // 615 // BIT 0:0 - Feature enablement 616 // 0 - disable feature (default) 617 // 1 - enable feature 618 // 619 #define NV_REG_STR_RM_STREAM_MEMOPS "RmStreamMemOps" 620 #define NV_REG_STR_RM_STREAM_MEMOPS_ENABLE 0:0 621 #define NV_REG_STR_RM_STREAM_MEMOPS_ENABLE_YES 1 622 #define NV_REG_STR_RM_STREAM_MEMOPS_ENABLE_NO 0 623 624 625 // 626 // Type DWORD: Enable read-only RMAPI locks for select interfaces 627 // 628 // Setting an interface to 0 will disable read-only API locks for that interface 629 // Setting an interface to 1 will enable read-only API locks for that interface, 630 // however, RM may still choose to take a read-write lock if it needs to. 631 // 632 #define NV_REG_STR_RM_READONLY_API_LOCK "RmRoApiLock" 633 #define NV_REG_STR_RM_READONLY_API_LOCK_ALLOC_RESOURCE 1:1 634 #define NV_REG_STR_RM_READONLY_API_LOCK_ALLOC_RESOURCE_DEFAULT (0x00000000) 635 #define NV_REG_STR_RM_READONLY_API_LOCK_ALLOC_RESOURCE_DISABLE (0x00000000) 636 #define NV_REG_STR_RM_READONLY_API_LOCK_ALLOC_RESOURCE_ENABLE (0x00000001) 637 #define NV_REG_STR_RM_READONLY_API_LOCK_FREE_RESOURCE 2:2 638 #define NV_REG_STR_RM_READONLY_API_LOCK_FREE_RESOURCE_DEFAULT (0x00000000) 639 #define NV_REG_STR_RM_READONLY_API_LOCK_FREE_RESOURCE_DISABLE (0x00000000) 640 #define NV_REG_STR_RM_READONLY_API_LOCK_FREE_RESOURCE_ENABLE (0x00000001) 641 #define NV_REG_STR_RM_READONLY_API_LOCK_MAP 3:3 642 #define NV_REG_STR_RM_READONLY_API_LOCK_MAP_DEFAULT (0x00000000) 643 #define NV_REG_STR_RM_READONLY_API_LOCK_MAP_DISABLE (0x00000000) 644 #define NV_REG_STR_RM_READONLY_API_LOCK_MAP_ENABLE (0x00000001) 645 #define NV_REG_STR_RM_READONLY_API_LOCK_UNMAP 4:4 646 #define NV_REG_STR_RM_READONLY_API_LOCK_UNMAP_DEFAULT (0x00000000) 647 #define NV_REG_STR_RM_READONLY_API_LOCK_UNMAP_DISABLE (0x00000000) 648 #define NV_REG_STR_RM_READONLY_API_LOCK_UNMAP_ENABLE (0x00000001) 649 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_MAP 5:5 650 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_MAP_DEFAULT (0x00000000) 651 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_MAP_DISABLE (0x00000000) 652 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_MAP_ENABLE (0x00000001) 653 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_UNMAP 6:6 654 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_UNMAP_DEFAULT (0x00000000) 655 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_UNMAP_DISABLE (0x00000000) 656 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_UNMAP_ENABLE (0x00000001) 657 #define NV_REG_STR_RM_READONLY_API_LOCK_COPY 7:7 658 #define NV_REG_STR_RM_READONLY_API_LOCK_COPY_DEFAULT (0x00000000) 659 #define NV_REG_STR_RM_READONLY_API_LOCK_COPY_DISABLE (0x00000000) 660 #define NV_REG_STR_RM_READONLY_API_LOCK_COPY_ENABLE (0x00000001) 661 #define NV_REG_STR_RM_READONLY_API_LOCK_SHARE 8:8 662 #define NV_REG_STR_RM_READONLY_API_LOCK_SHARE_DEFAULT (0x00000000) 663 #define NV_REG_STR_RM_READONLY_API_LOCK_SHARE_DISABLE (0x00000000) 664 #define NV_REG_STR_RM_READONLY_API_LOCK_SHARE_ENABLE (0x00000001) 665 #define NV_REG_STR_RM_READONLY_API_LOCK_CTRL 9:9 666 #define NV_REG_STR_RM_READONLY_API_LOCK_CTRL_DEFAULT (0x00000000) 667 #define NV_REG_STR_RM_READONLY_API_LOCK_CTRL_DISABLE (0x00000000) 668 #define NV_REG_STR_RM_READONLY_API_LOCK_CTRL_ENABLE (0x00000001) 669 670 671 // 672 // Type DWORD: Enable read-only RMAPI locks for select modules 673 // 674 // Setting an interface to 0 will disable read-only API locks for that module 675 // Setting an interface to 1 will enable read-only API locks for that module, 676 // however, RM may still choose to take a read-write lock if it needs to. 677 // 678 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE "RmRoApiLockModule" 679 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_GPU_OPS 0:0 680 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_GPU_OPS_DEFAULT (0x00000000) 681 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_GPU_OPS_DISABLE (0x00000000) 682 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_GPU_OPS_ENABLE (0x00000001) 683 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_WORKITEM 1:1 684 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_WORKITEM_DEFAULT (0x00000000) 685 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_WORKITEM_DISABLE (0x00000000) 686 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_WORKITEM_ENABLE (0x00000001) 687 688 689 // 690 // Type DWORD: Enable read-only GPU locks for select modules 691 // 692 // Setting an interface to 0 will disable read-only GPU locks for that module 693 // Setting an interface to 1 will enable read-only GPU locks for that module, 694 // however, RM may still choose to take a read-write lock if it needs to. 695 // 696 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE "RmRoGpuLockModule" 697 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_GPU_OPS 0:0 698 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_GPU_OPS_DEFAULT (0x00000000) 699 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_GPU_OPS_DISABLE (0x00000000) 700 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_GPU_OPS_ENABLE (0x00000001) 701 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_WORKITEM 1:1 702 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_WORKITEM_DEFAULT (0x00000000) 703 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_WORKITEM_DISABLE (0x00000000) 704 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_WORKITEM_ENABLE (0x00000001) 705 706 707 // Mode for CACHEABLE rmapi control 708 // RMCTRL cache mode defined in ctrl0000system.h 709 #define NV_REG_STR_RM_CACHEABLE_CONTROLS "RmEnableCacheableControls" 710 711 // Type DWORD 712 // This regkey forces for Maxwell+ that on FB Unload we wait for FB pull before issuing the 713 // L2 clean. WAR for bug 1032432 714 #define NV_REG_STR_RM_L2_CLEAN_FB_PULL "RmL2CleanFbPull" 715 #define NV_REG_STR_RM_L2_CLEAN_FB_PULL_ENABLED (0x00000000) 716 #define NV_REG_STR_RM_L2_CLEAN_FB_PULL_DISABLED (0x00000001) 717 #define NV_REG_STR_RM_L2_CLEAN_FB_PULL_DEFAULT (0x00000000) 718 719 // 720 // Type: DWORD 721 // This regkey overrides BL8, 16, and 24 kinds to only be of GENERIC_MEMORY or 722 // GENERIC_MEMORY_COMPRESSIBLE kinds. 723 // 0 - No override 724 // > 0 - Override memkind to GMK 725 // bit 0: override BL8 type 726 // bit 1: override BL16 type 727 // bit 2: override BL24 type 728 // ex. 0x00001000 means override all types 729 #define NV_REG_STR_RM_OVERRIDE_TO_GMK "RMOverrideToGMK" 730 #define NV_REG_STR_RM_OVERRIDE_TO_GMK_DISABLED (0x00000000) 731 #define NV_REG_STR_RM_OVERRIDE_TO_GMK_BL8 (0x00000001) 732 #define NV_REG_STR_RM_OVERRIDE_TO_GMK_BL16 (0x00000002) 733 #define NV_REG_STR_RM_OVERRIDE_TO_GMK_BL24 (0x00000004) 734 #define NV_REG_STR_RM_OVERRIDE_TO_GMK_ALL (0x00000007) 735 736 // Enable backtrace dumping at assertion failure. 737 // If physical RM or RCDB is unavailable, then this regkey controls the behaviour of backtrace 738 // printing. 739 // 0: disable 740 // 1 (default): only print unique backtraces, identified by instruction pointer of the failed assert 741 // 2: print all 742 #define NV_REG_STR_RM_PRINT_ASSERT_BACKTRACE "RmPrintAssertBacktrace" 743 #define NV_REG_STR_RM_PRINT_ASSERT_BACKTRACE_DISABLE 0 744 #define NV_REG_STR_RM_PRINT_ASSERT_BACKTRACE_UNIQUE 1 745 #define NV_REG_STR_RM_PRINT_ASSERT_BACKTRACE_ENABLE 2 746 747 748 // 749 // Type DWORD 750 // Used to enable no locking on copy 751 // 752 #define NV_REG_STR_RM_PARAM_COPY_NO_LOCK "RMParamCopyNoLock" 753 754 // 755 // Type DWORD 756 // Used to control RM API lock aging for low priority acquires. 757 // If 0, low priority acquires (e.g. from cleanup when a process dies) 758 // are disabled and treated like regular ones. 759 // Otherwise, they will yield the lock this many times to the higher priority 760 // threads before proceeding. 761 // Off by default; 3 would be a good starting value if the feature is desired. 762 // 763 #define NV_REG_STR_RM_LOCKING_LOW_PRIORITY_AGING "RMLockingLowPriorityAging" 764 765 // 766 // Type DWORD 767 // This regkey restricts profiling capabilities (creation of profiling objects 768 // and access to profiling-related registers) to admin only. 769 // 0 - (default - disabled) 770 // 1 - Enables admin check 771 // 772 #define NV_REG_STR_RM_PROFILING_ADMIN_ONLY "RmProfilingAdminOnly" 773 #define NV_REG_STR_RM_PROFILING_ADMIN_ONLY_FALSE 0x00000000 774 #define NV_REG_STR_RM_PROFILING_ADMIN_ONLY_TRUE 0x00000001 775 776 777 #define NV_REG_STR_GPU_BROKEN_FB "nvBrokenFb" 778 #define NV_REG_STR_GPU_BROKEN_FB_ALL_OKAY 0x00000000 779 #define NV_REG_STR_GPU_BROKEN_FB_ALL_BROKEN 0xffffffff 780 #define NV_REG_STR_GPU_BROKEN_FB_DEFAULT NV_REG_STR_GPU_BROKEN_FB_ALL_OKAY 781 #define NV_REG_STR_GPU_BROKEN_FB_DEFAULT_GF100_A01 NV_REG_STR_GPU_BROKEN_FB_MEMORY_BROKEN 782 #define NV_REG_STR_GPU_BROKEN_FB_MEMORY 0:0 783 #define NV_REG_STR_GPU_BROKEN_FB_MEMORY_OKAY 0x00000000 784 #define NV_REG_STR_GPU_BROKEN_FB_MEMORY_BROKEN 0x00000001 785 #define NV_REG_STR_GPU_BROKEN_FB_REG_VIA_CPU 1:1 786 #define NV_REG_STR_GPU_BROKEN_FB_REG_VIA_CPU_OKAY 0x00000000 787 #define NV_REG_STR_GPU_BROKEN_FB_REG_VIA_CPU_BROKEN 0x00000001 788 #define NV_REG_STR_GPU_BROKEN_FB_REG_VIA_PMU 2:2 789 #define NV_REG_STR_GPU_BROKEN_FB_REG_VIA_PMU_OKAY 0x00000000 790 #define NV_REG_STR_GPU_BROKEN_FB_REG_VIA_PMU_BROKEN 0x00000001 791 // Type DWORD 792 // _ALL_OKAY: FB is not broken. All is okay. 793 // _ALL_BROKEN: FB is broken and no software will try to use it. 794 // _MEMORY: Memory itself can/cannot be accessed. (PDB_PROP_GPU_BROKEN_FB property) 795 // _REG_VIA_CPU: CPU can/cannot access FBPA/FBIO registers. (PDB_PROP_GPU_BROKEN_FB_REG_VIA_CPU property) 796 // _REG_VIA_PMU: PMU can/cannot access FBPA/FBIO registers. (PDB_PROP_GPU_BROKEN_FB_REG_VIA_PMU property) 797 // FBPA/FBIO register addresses are defined by gpuIsBrokenFbReg(). 798 // Note that if the CPU and the PMU can't access registers, then memory isn't going to work either. 799 // In other words, the only even number that makes sense for this regkey is zero. 800 // Default depends on the chip and mask revision. 801 802 #define NV_REG_STR_OVERRIDE_FB_SIZE "OverrideFbSize" 803 // Type Dword 804 // Encoding Numeric Value 805 // Size in MB 806 // Used to reduce FB for testing memory management 807 // 808 #define NV_REG_STR_OVERRIDE_FB_SIZE_DEFAULT 0 809 810 // 811 // TYPE DWORD 812 // This regkey helps increase the size of RM reserved region. 813 // Exposed to clients for bug 2404337. 814 // Note: In GSP builds this key applies to the kernel (CPU) RM only. 815 // 816 #define NV_REG_STR_RM_INCREASE_RSVD_MEMORY_SIZE_MB "RMIncreaseRsvdMemorySizeMB" 817 #define NV_REG_STR_RM_INCREASE_RSVD_MEMORY_SIZE_MB_DEFAULT 0x0 818 819 // TYPE Dword 820 // Determines whether or not RM reserved space should be increased. 821 // 1 - Increases RM reserved space 822 // 0 - (default) Keeps RM reserved space as it is. 823 824 #define NV_REG_STR_RM_DISABLE_SCRUB_ON_FREE "RMDisableScrubOnFree" 825 // Type DWORD 826 // Encoding 0 (default) - Scrub on free 827 // 1 - Disable Scrub on Free 828 829 #define NV_REG_STR_RM_DISABLE_FAST_SCRUBBER "RMDisableFastScrubber" 830 // Type DWORD 831 // Encoding 0 (default) - Enable Fast Scrubber 832 // 1 - Disable Fast Scrubber 833 834 // 835 // Type DWORD 836 // Controls enable of PMA memory management instead of existing legacy 837 // RM FB heap manager. 838 // 839 #define NV_REG_STR_RM_ENABLE_PMA "RMEnablePMA" 840 #define NV_REG_STR_RM_ENABLE_PMA_YES (0x00000001) 841 #define NV_REG_STR_RM_ENABLE_PMA_NO (0x00000000) 842 843 // 844 // Type DWORD 845 // Controls management of client page tables by PMA on MODS. 846 // Default enable. MODS will use regkey to override to disable feature. 847 // 848 #define NV_REG_STR_RM_ENABLE_PMA_MANAGED_PTABLES "RMEnablePmaManagedPtables" 849 #define NV_REG_STR_RM_ENABLE_PMA_MANAGED_PTABLES_YES (0x00000001) 850 #define NV_REG_STR_RM_ENABLE_PMA_MANAGED_PTABLES_NO (0x00000000) 851 #define NV_REG_STR_RM_ENABLE_PMA_MANAGED_PTABLES_DEFAULT (0x00000001) 852 853 // 854 // Type DWORD 855 // Disable global CeUtils instance creation after fifo scheduling enablement 856 // 857 #define NV_REG_STR_DISABLE_GLOBAL_CE_UTILS "RmDisableGlobalCeUtils" 858 #define NV_REG_STR_DISABLE_GLOBAL_CE_UTILS_YES (0x00000001) 859 #define NV_REG_STR_DISABLE_GLOBAL_CE_UTILS_NO (0x00000000) 860 861 #define NV_REG_STR_RM_SCRUB_BLOCK_SHIFT "RMScrubBlockShift" 862 // Type DWORD 863 // Encoding Numeric Value 864 // A value in the range 12 to 20 represents logbase2 of maxBlockSize for heap 865 // scrubber. Any other value will be defaulted to 16 i.e. maxBlockSize = 64KB. 866 867 #define NV_REG_STR_RM_INST_VPR "RMInstVPR" 868 // Type DWORD 869 // Encoding: takes effect for allocations in VIDEO memory 870 // TRUE Make allocation in protected region 871 // FALSE Make allocation in non-protected region (default) 872 // 873 #define NV_REG_STR_RM_INST_VPR_INSTBLK 0:0 // Instance block 874 #define NV_REG_STR_RM_INST_VPR_INSTBLK_FALSE (0x00000000) 875 #define NV_REG_STR_RM_INST_VPR_INSTBLK_TRUE (0x00000001) 876 #define NV_REG_STR_RM_INST_VPR_RAMFC 1:1 // RAMFC save area 877 #define NV_REG_STR_RM_INST_VPR_RAMFC_FALSE (0x00000000) 878 #define NV_REG_STR_RM_INST_VPR_RAMFC_TRUE (0x00000001) 879 #define NV_REG_STR_RM_INST_VPR_RUNLIST 2:2 // Runlist 880 #define NV_REG_STR_RM_INST_VPR_RUNLIST_FALSE (0x00000000) 881 #define NV_REG_STR_RM_INST_VPR_RUNLIST_TRUE (0x00000001) 882 #define NV_REG_STR_RM_INST_VPR_MMU_READ 3:3 // MMU Debug Read 883 #define NV_REG_STR_RM_INST_VPR_MMU_READ_FALSE (0x00000000) 884 #define NV_REG_STR_RM_INST_VPR_MMU_READ_TRUE (0x00000001) 885 #define NV_REG_STR_RM_INST_VPR_MMU_WRITE 4:4 // MMU Debug Read 886 #define NV_REG_STR_RM_INST_VPR_MMU_WRITE_FALSE (0x00000000) 887 #define NV_REG_STR_RM_INST_VPR_MMU_WRITE_TRUE (0x00000001) 888 889 #define NV_REG_STR_RM_GPU_SURPRISE_REMOVAL "RMGpuSurpriseRemoval" 890 // Type DWORD 891 // Encoding boolean 892 // If set, this will cause RM mark GPU as lost when it detects 0xFF from register 893 // access. 894 895 #define NV_REG_STR_RM_BLACKLIST_ADDRESSES "RmBlackListAddresses" 896 // Type BINARY: 897 // struct 898 // { 899 // NvU64 addresses[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; 900 // }; 901 902 #define NV_REG_STR_RM_NUM_FIFOS "RmNumFifos" 903 // Type Dword 904 // Override number of fifos (channels) on NV4X 905 #define NV_REG_STR_RM_NUM_FIFOS_COMPAT 0x00000020 906 #define NV_REG_STR_RM_NUM_FIFOS_EXTENDED 0x00000200 907 908 #define NV_REG_STR_RM_SUPPORT_USERD_MAP_DMA "RMSupportUserdMapDma" 909 // Type DWORD 910 // Encoding: Boolean 911 // If set, allow MapMemoryDma calls to be made on channel objects 912 913 #define NV_REG_STR_SECONDARY_BUS_RESET_ENABLED "RMSecBusResetEnable" 914 // Type DWORD 915 // Encoding boolean 916 // Default FALSE 917 918 #define NV_REG_STR_FORCE_PCIE_CONFIG_SAVE "RMForcePcieConfigSave" 919 // Type DWORD 920 // Encoding boolean 921 // Default FALSE 922 923 #define NV_REG_STR_RM_PCIE_FLR_DEVINIT_TIMEOUT_SCALE "RMPcieFlrDevinitTimeout" 924 #define NV_REG_STR_RM_PCIE_FLR_DEVINIT_TIMEOUT_SCALE_MIN_ALLOWED 1 925 #define NV_REG_STR_RM_PCIE_FLR_DEVINIT_TIMEOUT_SCALE_MAX_ALLOWED 4 926 // Type DWORD 927 // Regkey to change FLR devinit timeout value. Increase in scale value increases 928 // the timeout value and vice versa. 929 // Scale value has to be greater than 0 since flr devinit timeout can't be 0 930 // Scale value for now is limited to 4 which translates to maximum of 931 // 3.6seconds(900ms*4) timeout value. 932 // 933 934 #define NV_REG_STR_RM_PCIE_FLR_POLICY "RMPcieFLRPolicy" 935 #define NV_REG_STR_RM_PCIE_FLR_POLICY_DEFAULT 0 936 #define NV_REG_STR_RM_PCIE_FLR_POLICY_FORCE_DISABLE 1 937 // Type DWORD 938 // Regkey to force disable Function Level Reset 939 // Note that we don't want to provision for force enabling FLR since as per current design - 940 // For Pre-Turing boards, FLR will be strictly disabled since it's not supported in HW 941 // Default policy could be different for different boards though 942 943 // Type DWORD 944 // Encoding Numeric Value 945 // Overrides chipset-based P2P configurations. 946 // Only be used to test on internal issues 947 // 948 // P2P reads: 949 // 0 - Do not allow P2P reads 950 // 1 - Allow P2P reads 951 // 2 - Do not override chipset-selected config (default) 952 // P2P writes: 953 // 0 - Do not allow P2P writes 954 // 1 - Allow P2P writes 955 // 2 - Do not override chipset-selected config (default) 956 // 957 #define NV_REG_STR_CL_FORCE_P2P "ForceP2P" 958 #define NV_REG_STR_CL_FORCE_P2P_READ 1:0 959 #define NV_REG_STR_CL_FORCE_P2P_READ_DISABLE 0x00000000 960 #define NV_REG_STR_CL_FORCE_P2P_READ_ENABLE 0x00000001 961 #define NV_REG_STR_CL_FORCE_P2P_READ_DEFAULT 0x00000002 962 #define NV_REG_STR_CL_FORCE_P2P_WRITE 5:4 963 #define NV_REG_STR_CL_FORCE_P2P_WRITE_DISABLE 0x00000000 964 #define NV_REG_STR_CL_FORCE_P2P_WRITE_ENABLE 0x00000001 965 #define NV_REG_STR_CL_FORCE_P2P_WRITE_DEFAULT 0x00000002 966 967 // 968 // Type DWORD 969 // Use this regkey to force RM to pick a P2P type. HW has to support the picked TYPE to take effect. 970 // e.g., TYPE_BAR1P2P will not work if HW does not support it. A call to create NV50_P2P object will 971 // will fail in such a case. 972 // 973 // TYPE_DEFAULT let RM to choose a P2P type. The priority is: 974 // C2C > NVLINK > mailbox P2P > BAR1P2P 975 // 976 // TYPE_C2C to use C2C P2P if it supports 977 // TYPE_NVLINK to use NVLINK P2P, including INDIRECT_NVLINK_P2P if it supports 978 // TYPE_BAR1P2P to use BAR1 P2P if it supports 979 // TYPE_MAILBOXP2P to use mailbox p2p if it supports 980 // 981 #define NV_REG_STR_RM_FORCE_P2P_TYPE "RMForceP2PType" 982 #define NV_REG_STR_RM_FORCE_P2P_TYPE_DEFAULT (0x00000000) 983 #define NV_REG_STR_RM_FORCE_P2P_TYPE_MAILBOXP2P (0x00000001) 984 #define NV_REG_STR_RM_FORCE_P2P_TYPE_BAR1P2P (0x00000002) 985 #define NV_REG_STR_RM_FORCE_P2P_TYPE_NVLINK (0x00000003) 986 #define NV_REG_STR_RM_FORCE_P2P_TYPE_C2C (0x00000004) 987 #define NV_REG_STR_RM_FORCE_P2P_TYPE_MAX NV_REG_STR_RM_FORCE_P2P_TYPE_C2C 988 989 // 990 // Type: DWORD 991 // Enables/Disables the WAR for bug 1630288 where we disable 3rd-party peer mappings 992 // Disabled by default 993 // 994 #define NV_REG_STR_PEERMAPPING_OVERRIDE "PeerMappingOverride" 995 #define NV_REG_STR_PEERMAPPING_OVERRIDE_DEFAULT 0 996 997 #define NV_REG_STR_P2P_MAILBOX_CLIENT_ALLOCATED "P2PMailboxClientAllocated" 998 #define NV_REG_STR_P2P_MAILBOX_CLIENT_ALLOCATED_FALSE 0 999 #define NV_REG_STR_P2P_MAILBOX_CLIENT_ALLOCATED_TRUE 1 1000 // Type Dword 1001 // Overrides the P2P Mailbox allocation policy 1002 // For testing only 1003 // 0 - P2P Mailbox area is allocated by RM 1004 // 1 - P2P Mailbox area is not allocated by RM, but by the client. 1005 1006 #define NV_REG_STR_RM_MAP_P2P_PEER_ID "RMP2PPeerId" 1007 // Type DWORD 1008 // Encoding: 1009 // Peer ID to use when mapping p2p to peer subdevice in p2p loopback mode 1010 // Default: RM takes care of assigning peer ID. 1011 1012 #define NV_REG_STR_OVERRIDE_GPU_NUMA_NODE_ID "RMOverrideGpuNumaNodeId" 1013 // Type DWORD: 1014 // Encoding -- NvS32 1015 // Override GPU NUMA Node ID assigned by OS 1016 1017 #define NV_REG_STR_RESTORE_BAR1_SIZE_BUG_3249028_WAR "RMBar1RestoreSize" 1018 #define NV_REG_STR_RESTORE_BAR1_SIZE_BUG_3249028_TRUE (0x00000001) 1019 #define NV_REG_STR_RESTORE_BAR1_SIZE_BUG_3249028_FALSE (0x00000000) 1020 // Type DWORD: 1021 // Encoding -- Boolean 1022 // Check if BAR1 size has been restored correctly by SBIOS across power transitions 1023 // Default: enabled for Ampere and up 1024 // 1025 1026 // 1027 // Type DWORD 1028 // Numa allocations allow for skipping reclaim less than a specified memory occupancy threshold. 1029 // This override allows for its tuning, value supplied here shall indicate a percent of free memory 1030 // less than which GFP_RECLAIM flag will be dropped. 1031 // 1032 #define NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE "RmNumaAllocSkipReclaimPercent" 1033 #define NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE_DEFAULT 4 1034 #define NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE_DISABLED 0 1035 #define NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE_MIN 0 1036 #define NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE_MAX 100 1037 1038 // 1039 // Disable 64KB BAR1 mappings 1040 // 0 - Disable 64KB BAR1 mappings 1041 // 1 - Force/Enable 64KB BAR1 mappings 1042 // 1043 #define NV_REG_STR_RM_64KB_BAR1_MAPPINGS "RM64KBBAR1Mappings" 1044 #define NV_REG_STR_RM_64KB_BAR1_MAPPINGS_ENABLED 0x00000001 1045 #define NV_REG_STR_RM_64KB_BAR1_MAPPINGS_DISABLED 0x00000000 1046 1047 #define NV_REG_STR_RM_BAR1_APERTURE_SIZE_MB "RMBar1ApertureSizeMB" 1048 // Type DWORD 1049 // Encoding Numeric Value 1050 // Overrides the size of the BAR1 aperture. Used to shrink BAR1. It cannot be 1051 // greater than the physical size of BAR1. 1052 1053 #define NV_REG_STR_RM_BAR2_APERTURE_SIZE_MB "RMBar2ApertureSizeMB" 1054 // Type DWORD 1055 // Encoding Numeric Value 1056 // Overrides the size of the BAR2 aperture. Cannot be greater than the 1057 // physical size of BAR2 available to RM (which may be less than the total size 1058 // of BAR2). When this regkey is present we cap the total aperture size to the 1059 // RM aperture size. This can result in undefined beahvior in environments that 1060 // rely on a virtual bar2 aperture shared between RM and VBIOS for VESA support. 1061 1062 #if defined(DEVELOP) || defined(DEBUG) || (defined(RMCFG_FEATURE_MODS_FEATURES) && RMCFG_FEATURE_MODS_FEATURES) 1063 // 1064 // TYPE DWORD 1065 // This setting will override the BAR1 Big page size 1066 // This is used for interop testing for MODS 1067 // 1068 #define NV_REG_STR_RM_SET_BAR1_ADDRESS_SPACE_BIG_PAGE_SIZE "RMSetBAR1AddressSpaceBigPageSize" 1069 #define NV_REG_STR_RM_SET_BAR1_ADDRESS_SPACE_BIG_PAGE_SIZE_64k (64 * 1024) 1070 #define NV_REG_STR_RM_SET_BAR1_ADDRESS_SPACE_BIG_PAGE_SIZE_128k (128 * 1024) 1071 #endif //DEVELOP || DEBUG || MODS_FEATURES 1072 1073 // This regkey is to disable coherent path CPU->Nvlink/C2C->FB and force BAR path. 1074 #define NV_REG_STR_RM_FORCE_BAR_PATH "RMForceBarPath" 1075 // Type DWORD 1076 // Encoding 0 (default) - Enable Coherent C2C/NvLink Path 1077 // 1 - Force BAR Path 1078 1079 // 1080 // Type: Dword 1081 // Encoding: 1082 // 0 - client RM allocated context buffer feature is disabled 1083 // 1 - client RM allocated context buffer feature is enabled 1084 // 1085 #define NV_REG_STR_RM_CLIENT_RM_ALLOCATED_CTX_BUFFER "RMSetClientRMAllocatedCtxBuffer" 1086 #define NV_REG_STR_RM_CLIENT_RM_ALLOCATED_CTX_BUFFER_DISABLED 0x00000000 1087 #define NV_REG_STR_RM_CLIENT_RM_ALLOCATED_CTX_BUFFER_ENABLED 0x00000001 1088 1089 // 1090 // Type: Dword 1091 // Encoding: 1092 // 0 - Split VA space management between server/client RM is disabled 1093 // 1 - Split VA space management between server/client RM is enabled 1094 // 1095 #define NV_REG_STR_RM_SPLIT_VAS_MGMT_SERVER_CLIENT_RM "RMSplitVasMgmtServerClientRm" 1096 #define NV_REG_STR_RM_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_DISABLED 0x00000000 1097 #define NV_REG_STR_RM_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_ENABLED 0x00000001 1098 1099 // 1100 // Restrict the VA range to be <= @ref VASPACE_SIZE_FERMI. 1101 // Used in cases where some engines support 49 bit VA and some don't. 1102 // Ignored if NVOS32_ALLOC_FLAGS_USE_BEGIN_END (DDMA_ALLOC_VASPACE_USE_RANGE) or 1103 // NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE (DMA_ALLOC_VASPACE_VA_FIXED) is set. 1104 // Default: OFF (0x0) 1105 // Type: DWORD 1106 // 1107 #define NV_REG_STR_RM_RESTRICT_VA_RANGE "RMRestrictVARange" 1108 #define NV_REG_STR_RM_RESTRICT_VA_RANGE_DEFAULT (0x0) 1109 #define NV_REG_STR_RM_RESTRICT_VA_RANGE_ON (0x1) 1110 1111 #define NV_REG_STR_RESERVE_PTE_SYSMEM_MB "RmReservePteSysmemMB" 1112 // Type DWORD: 1113 // Encoding -- Value = 0 -> Do not reserve sysmem for PTEs (default) 1114 // Value > 0 -> Reserve ValueMB for PTEs when we run out of video and system memory 1115 // 1116 1117 // Type DWORD 1118 // Contains the sysmem page size. 1119 #define NV_REG_STR_RM_SYSMEM_PAGE_SIZE "RMSysmemPageSize" 1120 1121 // 1122 // Allows pages that are aligned to large page boundaries to be mapped as large 1123 // pages. 1124 // 1125 #define NV_REG_STR_RM_ALLOW_SYSMEM_LARGE_PAGES "RMAllowSysmemLargePages" 1126 1127 #define NV_REG_STR_FERMI_BIG_PAGE_SIZE "RMFermiBigPageSize" 1128 #define NV_REG_STR_FERMI_BIG_PAGE_SIZE_64KB (64 * 1024) 1129 #define NV_REG_STR_FERMI_BIG_PAGE_SIZE_128KB (128 * 1024) 1130 1131 // 1132 // TYPE DWORD 1133 // This setting will disable big page size per address space 1134 // 1135 #define NV_REG_STR_RM_DISABLE_BIG_PAGE_PER_ADDRESS_SPACE "RmDisableBigPagePerAddressSpace" 1136 #define NV_REG_STR_RM_DISABLE_BIG_PAGE_PER_ADDRESS_SPACE_FALSE (0x00000000) 1137 #define NV_REG_STR_RM_DISABLE_BIG_PAGE_PER_ADDRESS_SPACE_TRUE (0x00000001) 1138 1139 #define NV_REG_STR_RM_DISABLE_NONCONTIGUOUS_ALLOCATION "RMDisableNoncontigAlloc" 1140 #define NV_REG_STR_RM_DISABLE_NONCONTIGUOUS_ALLOCATION_FALSE (0x00000000) 1141 #define NV_REG_STR_RM_DISABLE_NONCONTIGUOUS_ALLOCATION_TRUE (0x00000001) 1142 // Type DWORD: 1143 // Encoding -- Boolean 1144 // Disable noncontig vidmem allocation 1145 // 1146 1147 // Type DWORD 1148 // Encoding -- 0 -- Disable 1149 // -- 1 -- Enable 1150 // Enable MemoryMapper API (in-development). Currently disabled by default 1151 #define NV_REG_ENABLE_MEMORY_MAPPER_API "RMEnableMemoryMapperApi" 1152 #define NV_REG_ENABLE_MEMORY_MAPPER_API_FALSE 0 1153 #define NV_REG_ENABLE_MEMORY_MAPPER_API_TRUE 1 1154 1155 #define NV_REG_STR_RM_FBSR_PAGED_DMA "RmFbsrPagedDMA" 1156 #define NV_REG_STR_RM_FBSR_PAGED_DMA_ENABLE 1 1157 #define NV_REG_STR_RM_FBSR_PAGED_DMA_DISABLE 0 1158 #define NV_REG_STR_RM_FBSR_PAGED_DMA_DEFAULT NV_REG_STR_RM_FBSR_PAGED_DMA_DISABLE 1159 // Type Dword 1160 // Encoding Numeric Value 1161 // Enable the Paged DMA mode for FBSR 1162 // 0 - Disable (default) 1163 // 1 - Enable 1164 1165 #define NV_REG_STR_RM_FBSR_FILE_MODE "RmFbsrFileMode" 1166 #define NV_REG_STR_RM_FBSR_FILE_MODE_ENABLE 1 1167 #define NV_REG_STR_RM_FBSR_FILE_MODE_DISABLE 0 1168 #define NV_REG_STR_RM_FBSR_FILE_MODE_DEFAULT NV_REG_STR_RM_FBSR_FILE_MODE_DISABLE 1169 // Type Dword 1170 // Encoding Numeric Value 1171 // Enable the File based power saving mode for Linux 1172 // 0 - Disable (default) 1173 // 1 - Enable 1174 1175 #define NV_REG_STR_RM_FBSR_WDDM_MODE "RmFbsrWDDMMode" 1176 #define NV_REG_STR_RM_FBSR_WDDM_MODE_ENABLE 1 1177 #define NV_REG_STR_RM_FBSR_WDDM_MODE_DISABLE 0 1178 #define NV_REG_STR_RM_FBSR_WDDM_MODE_DEFAULT NV_REG_STR_RM_FBSR_WDDM_MODE_DISABLE 1179 // Type Dword 1180 // Encoding Numeric Value 1181 // Enable the WDDM power saving mode for FBSR 1182 // 0 - Disable (default) 1183 // 1 - Enable 1184 1185 // Type DWORD: Disables HW fault buffers on Pascal+ chips 1186 // Encoding : 1 -- TRUE 1187 // : 0 -- False 1188 // : Default -- False 1189 #define NV_REG_STR_RM_DISABLE_HW_FAULT_BUFFER "RmDisableHwFaultBuffer" 1190 #define NV_REG_STR_RM_DISABLE_HW_FAULT_BUFFER_TRUE 0x00000001 1191 #define NV_REG_STR_RM_DISABLE_HW_FAULT_BUFFER_FALSE 0x00000000 1192 #define NV_REG_STR_RM_DISABLE_HW_FAULT_BUFFER_DEFAULT 0x00000000 1193 1194 // 1195 // Type: DWORD 1196 // Encoding: 1197 // 3 - Enable interrupt-based FECS context switch logging with bottom-half/APC fall-back 1198 // 2 - Enable interrupt-based FECS context switch logging without bottom-half/APC fall-back 1199 // 1 - Enable periodic FECS context switch logging 1200 // 0 - Disable FECS context switch logging 1201 // 1202 // Note: Interrupt-based logging and periodic logging are mutually exclusive 1203 // 1204 #define NV_REG_STR_RM_CTXSW_LOG "RMCtxswLog" 1205 #define NV_REG_STR_RM_CTXSW_LOG_DISABLE 0x00000000 1206 #define NV_REG_STR_RM_CTXSW_LOG_ENABLE 0x00000001 1207 #define NV_REG_STR_RM_CTXSW_LOG_ENABLE_INTR 0x00000002 1208 #define NV_REG_STR_RM_CTXSW_LOG_ENABLE_INTR_APC 0x00000003 1209 #define NV_REG_STR_RM_CTXSW_LOG_DEFAULT NV_REG_STR_RM_CTXSW_LOG_DISABLE 1210 1211 // Type DWORD: Indicates if enabling video event tracing 1212 // 1213 // 0 - Disables Video event trace usage (default) 1214 // > 0 - Enable video event trace and define sizes for different buffers 1215 // bit 16 - 30: sizes of the event buffer in 4K pages 1216 // bit 31 - 31: Enable always logging: 1217 // By default, video engines only log video events when there is 1218 // at least one eventbuffer bound and enabled. If this flag is set, 1219 // video engines will always log events even without a consumer. This 1220 // is helpful for debugging purposes. 1221 // Example: 0x01000000 means 1MB event buffer. 1222 #define NV_REG_STR_RM_VIDEO_EVENT_TRACE "RmVideoEventTrace" 1223 #define NV_REG_STR_RM_VIDEO_EVENT_TRACE_DISABLED (0x00000000) 1224 #define NV_REG_STR_RM_VIDEO_EVENT_TRACE_EVENT_BUFFER_SIZE_IN_4k 30:16 1225 #define NV_REG_STR_RM_VIDEO_EVENT_TRACE_ALWAYS_LOG 31:31 1226 #define NV_REG_STR_RM_VIDEO_EVENT_TRACE_ALWAYS_LOG_DISABLED 0x00000000 1227 #define NV_REG_STR_RM_VIDEO_EVENT_TRACE_ALWAYS_LOG_ENABLED 0x00000001 1228 1229 // 1230 // Type: DWORD 1231 // 1232 // This regkey configures the maximum number of records that can be 1233 // processed per DPC when using interrupt-based ctxsw logging 1234 #define NV_REG_STR_RM_CTXSW_LOG_RECORDS_PER_INTR "RMCtxswLogMaxRecordsPerIntr" 1235 #define NV_REG_STR_RM_CTXSW_LOG_RECORDS_PER_INTR_DEFAULT 0x30 1236 1237 // 1238 // Type: DWORD 1239 // Encoding: 1240 // 0 - Disable more detailed debug INTR logs 1241 // 1 - Enable more detailed debug INTR logs 1242 // 1243 #define NV_REG_STR_RM_INTR_DETAILED_LOGS "RMIntrDetailedLogs" 1244 #define NV_REG_STR_RM_INTR_DETAILED_LOGS_DISABLE 0x00000000 1245 #define NV_REG_STR_RM_INTR_DETAILED_LOGS_ENABLE 0x00000001 1246 1247 #define NV_REG_STR_RM_LOCKING_MODE "RMLockingMode" 1248 // Type DWORD 1249 // Encoding enum 1250 // Overrides what Locking Mode is in use. 1251 // Default 0 1252 #define NV_REG_STR_RM_LOCKING_MODE_DEFAULT (0x00000000) 1253 #define NV_REG_STR_RM_LOCKING_MODE_INTR_MASK (0x00000001) 1254 #define NV_REG_STR_RM_LOCKING_MODE_LAZY_INTR_DISABLE (0x00000002) 1255 1256 #define NV_REG_STR_RM_PER_INTR_DPC_QUEUING "RMDisablePerIntrDPCQueueing" 1257 // Type DWORD 1258 // This regkey is used to disable per interrupt DPC queuing. 1259 // 0: Enable Per interrupt DPC Queuing 1260 // 1: Disable Per interrupt DPC Queuing 1261 1262 #define NV_REG_STR_INTR_STUCK_THRESHOLD "RM654663" 1263 // Type DWORD 1264 // Encoding NvU32 1265 // Number of iterations to see an interrupt in succession before considering it 1266 // "stuck." 1267 // Default - See INTR_STUCK_THRESHOLD 1268 1269 1270 #define NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR "RMProcessNonStallIntrInLocklessIsr" 1271 1272 // Type: DWORD 1273 // Enables/Disables processing of non-stall interrupts in lockless ISR for 1274 // Linux only. 1275 // Non-stall interrupts are processed by the function 1276 // intrServiceNonStall_HAL(pIntr,pGpu, TRUE /* bProcess*/); where bProcess is TRUE which 1277 // means that event list will be traversed to notify clients registered for it. 1278 // Disabled by default 1279 // 1280 1281 #define NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_DISABLE 0x00000000 1282 #define NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_ENABLE 0x00000001 1283 1284 #define NV_REG_STR_RM_ROBUST_CHANNELS "RmRobustChannels" 1285 #define NV_REG_STR_RM_ROBUST_CHANNELS_ENABLE 0x00000001 1286 #define NV_REG_STR_RM_ROBUST_CHANNELS_DISABLE 0x00000000 1287 #define NV_REG_STR_RM_ROBUST_CHANNELS_DEFAULT NV_REG_STR_RM_ROBUST_CHANNELS_DISABLE 1288 1289 #define NV_REG_STR_RM_RC_WATCHDOG "RmRcWatchdog" 1290 #define NV_REG_STR_RM_RC_WATCHDOG_ENABLE 0x00000001 1291 #define NV_REG_STR_RM_RC_WATCHDOG_DISABLE 0x00000000 1292 #define NV_REG_STR_RM_RC_WATCHDOG_DEFAULT NV_REG_STR_RM_RC_WATCHDOG_ENABLE 1293 1294 #define NV_REG_STR_RM_WATCHDOG_TIMEOUT "RmWatchDogTimeOut" 1295 #define NV_REG_STR_RM_WATCHDOG_TIMEOUT_LOW 0x00000007 1296 #define NV_REG_STR_RM_WATCHDOG_TIMEOUT_HI 0x0000000C 1297 #define NV_REG_STR_RM_WATCHDOG_TIMEOUT_DEFAULT NV_REG_STR_RM_WATCHDOG_TIMEOUT_LOW 1298 1299 #define NV_REG_STR_RM_WATCHDOG_INTERVAL "RmWatchDogInterval" 1300 #define NV_REG_STR_RM_WATCHDOG_INTERVAL_LOW 0x00000007 1301 #define NV_REG_STR_RM_WATCHDOG_INTERVAL_HI 0x0000000C 1302 #define NV_REG_STR_RM_WATCHDOG_INTERVAL_DEFAULT NV_REG_STR_RM_WATCHDOG_INTERVAL_LOW 1303 1304 // Enable/Disable watchcat in GSP-Plugin for Guest RPC 1305 // Default is Enabled 1306 #define NV_REG_STR_RM_GSP_VGPU_WATCHCAT "RmEnableGspPluginWatchcat" 1307 #define NV_REG_STR_RM_GSP_VGPU_WATCHCAT_ENABLE 0x00000001 1308 #define NV_REG_STR_RM_GSP_VGPU_WATCHCAT_DISABLE 0x00000000 1309 #define NV_REG_STR_RM_GSP_VGPU_WATCHCAT_DEFAULT NV_REG_STR_RM_GSP_VGPU_WATCHCAT_ENABLE 1310 1311 // Set watchcat timeout value in GSP-Plugin for Guest RPC 1312 // Default is 10 seconds 1313 #define NV_REG_STR_RM_GSP_VGPU_WATCHCAT_TIMEOUT "RmGspPluginWatchcatTimeOut" 1314 #define NV_REG_STR_RM_GSP_VGPU_WATCHCAT_TIMEOUT_MIN 0x0000000A 1315 #define NV_REG_STR_RM_GSP_VGPU_WATCHCAT_TIMEOUT_DEFAULT NV_REG_STR_RM_GSP_VGPU_WATCHCAT_TIMEOUT_MIN 1316 1317 #define NV_REG_STR_RM_DO_LOG_RC_EVENTS "RmLogonRC" 1318 // Type Dword 1319 // Encoding : 0 --> Skip Logging 1320 // 1 --> Do log 1321 // Enable/Disable Event Logging on RC errors 1322 // Default is Disabled 1323 #define NV_REG_STR_RM_DO_LOG_RC_ENABLE 0x00000001 1324 #define NV_REG_STR_RM_DO_LOG_RC_DISABLE 0x00000000 1325 #define NV_REG_STR_RM_DO_LOG_RC_DEFAULT NV_REG_STR_RM_DO_LOG_RC_DISABLE 1326 1327 // Type Dword 1328 // Encoding : 0 --> Skip Breakpoint 1329 // nonzero --> Do Breakpoint 1330 // Enable/Disable breakpoint on DEBUG resource manager on RC errors 1331 1332 #define NV_REG_STR_RM_BREAK_ON_RC "RmBreakonRC" 1333 #define NV_REG_STR_RM_BREAK_ON_RC_DISABLE 0x00000000 1334 #define NV_REG_STR_RM_BREAK_ON_RC_ENABLE 0x00000001 1335 1336 // Explicitly disable RmBreakOnRC for Retail <enable via registry> and 1337 // RMCFG_FEATURE_PLATFORM_GSP builds 1338 #if ((defined(DEBUG) || defined(QA_BUILD)) && \ 1339 (!defined(RMCFG_FEATURE_PLATFORM_GSP) || \ 1340 (defined(RMCFG_FEATURE_PLATFORM_GSP) && !RMCFG_FEATURE_PLATFORM_GSP))) 1341 #define NV_REG_STR_RM_BREAK_ON_RC_DEFAULT NV_REG_STR_RM_BREAK_ON_RC_ENABLE 1342 #else 1343 #define NV_REG_STR_RM_BREAK_ON_RC_DEFAULT NV_REG_STR_RM_BREAK_ON_RC_DISABLE 1344 #endif 1345 1346 // Volatile registry entries for previous driver version. 1347 // Used to record driver unload/reload for debugging purposes. 1348 #define NV_REG_STR_RM_RC_PREV_DRIVER_VERSION "RmRCPrevDriverVersion" 1349 #define NV_REG_STR_RM_RC_PREV_DRIVER_BRANCH "RmRCPrevDriverBranch" 1350 #define NV_REG_STR_RM_RC_PREV_DRIVER_CHANGELIST "RmRCPrevDriverChangelist" 1351 #define NV_REG_STR_RM_RC_PREV_DRIVER_LOAD_COUNT "RmRCPrevDriverLoadCount" 1352 1353 #define NV_REG_STR_USE_UNCACHED_PCI_MAPPINGS "UseUncachedPCIMappings" 1354 // Type DWORD 1355 // Encode -- Numeric Value 1356 // Check to see if we are converting PCI mappings 1357 1358 #define NV_REG_STR_RM_CE_USE_GEN4_MAPPING "RmCeUseGen4Mapping" 1359 #define NV_REG_STR_RM_CE_USE_GEN4_MAPPING_TRUE 0x1 1360 #define NV_REG_STR_RM_CE_USE_GEN4_MAPPING_FALSE 0x0 1361 // Type Dword (Boolean) 1362 // Encoding Numeric Value 1363 // Use gen4 mapping that uses a HSHUB CE, if available 1364 // Else, continue using FBHUB PCEs 1365 1366 // Type Dword 1367 // Enable PCE LCE auto config 1368 #define NV_REG_STR_RM_CE_ENABLE_AUTO_CONFIG "RmCeEnableAutoConfig" 1369 #define NV_REG_STR_RM_CE_ENABLE_AUTO_CONFIG_TRUE 0x1 1370 #define NV_REG_STR_RM_CE_ENABLE_AUTO_CONFIG_FALSE 0x0 1371 1372 // 1373 // Type DWORD 1374 // NVLINK control overrides. 1375 // 1376 // FORCE_DISABLE: Force disable NVLINK when the current default is ON (POR) 1377 // 1378 // TRAIN_AT_LOAD : Force train links during driver load 1379 // 1380 // FORCE_AUTOCONFIG : Force autoconfig training regardless of chiplib forced config links 1381 // 1382 // FORCE_ENABLE: Force enable NVLINK when the current default is OFF (bringup etc.) 1383 // 1384 // PARALLEL_TRAINING: Have the GPU endpoint parallelize link training 1385 #define NV_REG_STR_RM_NVLINK_CONTROL "RMNvLinkControl" 1386 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_DISABLE 0:0 1387 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_DISABLE_NO (0x00000000) 1388 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_DISABLE_YES (0x00000001) 1389 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_DISABLE_DEFAULT (NV_REG_STR_RM_NVLINK_CONTROL_FORCE_DISABLE_NO) 1390 #define NV_REG_STR_RM_NVLINK_CONTROL_TRAIN_AT_LOAD 1:1 1391 #define NV_REG_STR_RM_NVLINK_CONTROL_TRAIN_AT_LOAD_NO (0x00000000) 1392 #define NV_REG_STR_RM_NVLINK_CONTROL_TRAIN_AT_LOAD_YES (0x00000001) 1393 #define NV_REG_STR_RM_NVLINK_CONTROL_TRAIN_AT_LOAD_DEFAULT (NV_REG_STR_RM_NVLINK_CONTROL_TRAIN_AT_LOAD_NO) 1394 #define NV_REG_STR_RM_NVLINK_CONTROL_SKIP_TRAIN 2:2 1395 #define NV_REG_STR_RM_NVLINK_CONTROL_SKIP_TRAIN_NO (0x00000000) 1396 #define NV_REG_STR_RM_NVLINK_CONTROL_SKIP_TRAIN_YES (0x00000001) 1397 #define NV_REG_STR_RM_NVLINK_CONTROL_SKIP_TRAIN_DEFAULT (NV_REG_STR_RM_NVLINK_CONTROL_SKIP_TRAIN_NO) 1398 #define NV_REG_STR_RM_NVLINK_CONTROL_RESERVED_0 6:3 1399 #define NV_REG_STR_RM_NVLINK_CONTROL_LINK_TRAINING_DEBUG_SPEW 7:7 1400 #define NV_REG_STR_RM_NVLINK_CONTROL_LINK_TRAINING_DEBUG_SPEW_OFF (0x00000000) 1401 #define NV_REG_STR_RM_NVLINK_CONTROL_LINK_TRAINING_DEBUG_SPEW_ON (0x00000001) 1402 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_AUTOCONFIG 8:8 1403 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_AUTOCONFIG_NO (0x00000000) 1404 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_AUTOCONFIG_YES (0x00000001) 1405 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_AUTOCONFIG_DEFAULT (NV_REG_STR_RM_NVLINK_CONTROL_FORCE_AUTOCONFIG_NO) 1406 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_ENABLE 31:31 1407 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_ENABLE_NO (0x00000000) 1408 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_ENABLE_YES (0x00000001) 1409 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_ENABLE_DEFAULT (NV_REG_STR_RM_NVLINK_CONTROL_FORCE_ENABLE_NO) 1410 1411 // 1412 // Type DWORD 1413 // Knob to control NVLink MINION 1414 // 1415 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL "RMNvLinkMinionControl" 1416 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ENABLE 3:0 1417 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ENABLE_DEFAULT (0x00000000) 1418 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ENABLE_FORCE_ON (0x00000001) 1419 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ENABLE_FORCE_OFF (0x00000002) 1420 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_PHY_CONFIG 7:4 1421 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_PHY_CONFIG_DEFAULT (0x00000000) 1422 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_PHY_CONFIG_ENABLE (0x00000001) 1423 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_PHY_CONFIG_DISABLE (0x00000002) 1424 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_DL_STATUS 11:8 1425 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_DL_STATUS_DEFAULT (0x00000000) 1426 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_DL_STATUS_ENABLE (0x00000001) 1427 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_DL_STATUS_DISABLE (0x00000002) 1428 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITNEGOTIATE 15:12 1429 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITNEGOTIATE_DEFAULT (0x00000000) 1430 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITNEGOTIATE_ENABLE (0x00000001) 1431 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITNEGOTIATE_DISABLE (0x00000002) 1432 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITOPTIMIZE 19:16 1433 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITOPTIMIZE_DEFAULT (0x00000000) 1434 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITOPTIMIZE_ENABLE (0x00000001) 1435 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITOPTIMIZE_DISABLE (0x00000002) 1436 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_CACHE_SEEDS 23:20 1437 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_CACHE_SEEDS_DEFAULT (0x00000000) 1438 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_CACHE_SEEDS_ENABLE (0x00000001) 1439 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_CACHE_SEEDS_DISABLE (0x00000002) 1440 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE 27:24 1441 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE_DEFAULT (0x00000000) 1442 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE_RISCV (0x00000001) 1443 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE_FALCON (0x00000002) 1444 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE_RISCV_MANIFEST (0x00000003) 1445 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE_NO_MANIFEST (0x00000004) 1446 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ALI_TRAINING 30:28 1447 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ALI_TRAINING_DEFAULT (0x00000000) 1448 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ALI_TRAINING_ENABLE (0x00000001) 1449 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ALI_TRAINING_DISABLE (0x00000002) 1450 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_GFW_BOOT_DISABLE 31:31 1451 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_GFW_BOOT_DISABLE_DEFAULT (0x00000000) 1452 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_GFW_BOOT_DISABLE_DISABLE (0x00000001) 1453 1454 // 1455 // Type DWORD 1456 // Knob to change NVLink link speed 1457 // __LAST is same as highest supported speed 1458 // NOTE: 1459 // NVLINK_SPEED_CONTROL_SPEED_25G is exactly 25.00000Gbps on Pascal 1460 // NVLINK_SPEED_CONTROL_SPEED_25G is exactly 25.78125Gbps on Volta and later 1461 // NVLINK_SPEED_CONTROL_SPEED_2500000G is exactly 25.00000Gbps on all chips 1462 // 1463 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL "RMNvLinkSpeedControl" 1464 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED 4:0 1465 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_DEFAULT (0x00000000) 1466 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_16G (0x00000001) 1467 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_19_2G (0x00000002) 1468 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_20G (0x00000003) 1469 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_21G (0x00000004) 1470 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_22G (0x00000005) 1471 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_23G (0x00000006) 1472 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_24G (0x00000007) 1473 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_25G (0x00000008) 1474 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_25_78125G (0x00000008) 1475 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_25_00000G (0x00000009) 1476 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_16_14583G (0x0000000A) 1477 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_26_56250G (0x0000000B) 1478 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_27_34375G (0x0000000C) 1479 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_28_12500G (0x0000000D) 1480 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_32G (0x0000000E) 1481 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_40G (0x0000000F) 1482 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_50_00000G (0x00000010) 1483 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_53_12500G (0x00000011) 1484 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_100_00000G (0x00000012) 1485 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_106_25000G (0x00000013) 1486 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_FAULT (0x00000014) 1487 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED__LAST (0x00000014) 1488 1489 // 1490 // Type DWORD 1491 // P2P Loopback over NVLINK will be enabled by default if RM 1492 // detects loopback links. For P2P over PCIE, force disable 1493 // P2P loopback over NVLINK using the following regkey 1494 // 1495 #define NV_REG_STR_RM_NVLINK_DISABLE_P2P_LOOPBACK "RMNvLinkDisableP2PLoopback" 1496 #define NV_REG_STR_RM_NVLINK_DISABLE_P2P_LOOPBACK_DEFAULT (0x00000000) 1497 #define NV_REG_STR_RM_NVLINK_DISABLE_P2P_LOOPBACK_TRUE (0x00000001) 1498 #define NV_REG_STR_RM_NVLINK_DISABLE_P2P_LOOPBACK_FALSE (0x00000000) 1499 1500 // 1501 // Type DWORD 1502 // Knob to control NVLink Link Power States 1503 // 1504 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL "RMNvLinkControlLinkPM" 1505 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_SINGLE_LANE_MODE 1:0 1506 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_SINGLE_LANE_MODE_DEFAULT (0x00000000) 1507 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_SINGLE_LANE_MODE_ENABLE (0x00000001) 1508 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_SINGLE_LANE_MODE_DISABLE (0x00000002) 1509 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_PROD_WRITES 3:2 1510 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_PROD_WRITES_DEFAULT (0x00000000) 1511 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_PROD_WRITES_ENABLE (0x00000001) 1512 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_PROD_WRITES_DISABLE (0x00000002) 1513 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L1_MODE 5:4 1514 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L1_MODE_DEFAULT (0x00000000) 1515 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L1_MODE_ENABLE (0x00000001) 1516 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L1_MODE_DISABLE (0x00000002) 1517 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L2_MODE 7:6 1518 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L2_MODE_DEFAULT (0x00000000) 1519 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L2_MODE_ENABLE (0x00000001) 1520 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L2_MODE_DISABLE (0x00000002) 1521 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_RESERVED 31:8 1522 1523 // 1524 // Type DWORD 1525 // Knob to force lane disable and shutdown during driver unload 1526 // The regkey will also cause a toggle of link reset on driver load 1527 // The regkey should not be used in S/R paths 1528 // 1529 #define NV_REG_STR_RM_NVLINK_FORCE_LANESHUTDOWN "RMNvLinkForceLaneshutdown" 1530 #define NV_REG_STR_RM_NVLINK_FORCE_LANESHUTDOWN_TRUE (0x00000001) 1531 #define NV_REG_STR_RM_NVLINK_FORCE_LANESHUTDOWN_FALSE (0x00000000) 1532 #define NV_REG_STR_RM_NVLINK_FORCE_LANESHUTDOWN_DEFAULT (NV_REG_STR_RM_NVLINK_FORCE_LANESHUTDOWN_FALSE) 1533 1534 // 1535 // Type DWORD 1536 // For links that are SYSMEM, use this device type for force configs 1537 // Choose the value from NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_* 1538 // 1539 #define NV_REG_STR_RM_NVLINK_SYSMEM_DEVICE_TYPE "RMNvLinkForcedSysmemDeviceType" 1540 1541 // 1542 // Type DWORD 1543 // NVLink Disable Link Overrides 1544 // The supplied value is ANDed with the set of discovered 1545 // (not necessarily connected) links to remove unwanted links. 1546 // A value of DISABLE_ALL removes/disables all links on this device. 1547 // A value of DISABLE_NONE removes no links. 1548 // If not present, this regkey has no effect. 1549 // 1550 #define NV_REG_STR_RM_NVLINK_DISABLE_LINKS "RMNvLinkDisableLinks" 1551 #define NV_REG_STR_RM_NVLINK_DISABLE_LINKS_DISABLE_ALL (0xFFFFFFFF) 1552 #define NV_REG_STR_RM_NVLINK_DISABLE_LINKS_DISABLE_NONE (0x00000000) 1553 1554 // 1555 // Type DWORD 1556 // NVLINK Enable Links Overrides 1557 // Note that this control does not force enable links, rather, it should be 1558 // used to disable or mask off SW discovered links supported by the HW. 1559 // 1560 // NOTE: THIS REGKEY HAS BEEN DEPRECATED IN RM, since it does NOT work 1561 // with NVLink auto-configuration. Instead, please move to using 1562 // the new regkey NV_REG_STR_RM_NVLINK_DISABLE_LINKS 1563 // 1564 #define NV_REG_STR_RM_NVLINK_ENABLE "RMNvLinkEnable" 1565 #define NV_REG_STR_RM_NVLINK_ENABLE_IDX(i) (i):(i) 1566 #define NV_REG_STR_RM_NVLINK_ENABLE_IDX__SIZE 32 1567 #define NV_REG_STR_RM_NVLINK_ENABLE_IDX_TRUE (0x00000001) 1568 #define NV_REG_STR_RM_NVLINK_ENABLE_IDX_FALSE (0x00000000) 1569 1570 // 1571 // Type DWORD 1572 // Knob to control NVLink Verbose Prints 1573 // 1574 #define NV_REG_STR_RM_NVLINK_VERBOSE_MASK_CONTROL "RMNvLinkverboseControlMask" 1575 #define NV_REG_STR_RM_NVLINK_VERBOSE_MASK_CONTROL_REGINIT 0:0 1576 #define NV_REG_STR_RM_NVLINK_VERBOSE_MASK_CONTROL_REGINIT_DEFAULT (0x00000000) 1577 #define NV_REG_STR_RM_NVLINK_VERBOSE_MASK_CONTROL_REGINIT_ON (0x00000001) 1578 #define NV_REG_STR_RM_NVLINK_VERBOSE_MASK_CONTROL_REGINIT_OFF (0x00000000) 1579 1580 // Type DWORD: 1581 #define NV_REG_STR_RM_PCIE_LINK_SPEED "RMPcieLinkSpeed" 1582 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN2 1:0 1583 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN2_DEFAULT (0x00000000) 1584 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN2_ENABLE (0x00000001) 1585 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN2_DISABLE (0x00000002) 1586 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN3 3:2 1587 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN3_DEFAULT (0x00000000) 1588 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN3_ENABLE (0x00000001) 1589 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN3_DISABLE (0x00000002) 1590 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN4 5:4 1591 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN4_DEFAULT (0x00000000) 1592 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN4_ENABLE (0x00000001) 1593 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN4_DISABLE (0x00000002) 1594 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN5 7:6 1595 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN5_DEFAULT (0x00000000) 1596 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN5_ENABLE (0x00000001) 1597 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN5_DISABLE (0x00000002) 1598 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN6 9:8 1599 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN6_DEFAULT (0x00000000) 1600 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN6_ENABLE (0x00000001) 1601 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN6_DISABLE (0x00000002) 1602 #define NV_REG_STR_RM_PCIE_LINK_SPEED_LOCK_AT_LOAD 31:31 1603 #define NV_REG_STR_RM_PCIE_LINK_SPEED_LOCK_AT_LOAD_DISABLE (0x00000000) 1604 #define NV_REG_STR_RM_PCIE_LINK_SPEED_LOCK_AT_LOAD_ENABLE (0x00000001) 1605 1606 // 1607 // Type DWORD 1608 // 1609 // 1610 // This can be used as a per-device regkey or not, in which case the setting 1611 // will apply to all devices. If this key is supplied as both a per-device and 1612 // non-per-device regkey, the non-per-device option will apply first to all 1613 // devices, and then the per-device key settings will apply, overriding the 1614 // settings for the relevant devices. 1615 // 1616 // Encoding : 0 - Disable PCIe Relaxed Ordering TLP header bit setting. This is 1617 // the default option. 1618 // 1 - Try to enable PCIe Relaxed Ordering TLP header bit setting. 1619 // Traverses the PCIe topology and only enables the header bit if 1620 // it is safe to do so, with regard to all devices that could be 1621 // affected. 1622 // 2 - Forcibly enable PCIe Relaxed Ordering TLP header bit setting. 1623 // Explicitly ignores the compatibility of the PCIe topology 1624 // around the device or devices in question. 1625 // 1626 #define NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING "RmSetPCIERelaxedOrdering" 1627 #define NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING_DEFAULT 0x00000000 1628 #define NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING_DISABLE 0x00000000 1629 #define NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING_ENABLE 0x00000001 1630 #define NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING_FORCE_ENABLE 0x00000002 1631 1632 // Type DWORD 1633 // This regkey overrides the default use case to optimize the GPU for. 1634 // This regkey should not be used with the RMFermiBigPageSize regkey. 1635 // This regkey should only be set by the RM. 1636 #define NV_REG_STR_RM_OPTIMIZE_COMPUTE_OR_SPARSE_TEX "RMOptimizeComputeOrSparseTex" 1637 #define NV_REG_STR_RM_OPTIMIZE_COMPUTE_OR_SPARSE_TEX_DEFAULT (0x00000000) 1638 #define NV_REG_STR_RM_OPTIMIZE_COMPUTE_OR_SPARSE_TEX_COMPUTE (0x00000001) 1639 #define NV_REG_STR_RM_OPTIMIZE_COMPUTE_OR_SPARSE_TEX_SPARSE_TEX (0x00000002) 1640 1641 #define NV_REG_STR_CL_ASLM_CFG "AslmCfg" 1642 #define NV_REG_STR_CL_ASLM_CFG_NV_LINK_UPGRADE 1:0 1643 #define NV_REG_STR_CL_ASLM_CFG_NV_LINK_UPGRADE_NO 0x00000000 1644 #define NV_REG_STR_CL_ASLM_CFG_NV_LINK_UPGRADE_YES 0x00000001 1645 #define NV_REG_STR_CL_ASLM_CFG_NV_LINK_UPGRADE_DEFAULT 0x00000002 1646 #define NV_REG_STR_CL_ASLM_CFG_HOT_RESET 5:4 1647 #define NV_REG_STR_CL_ASLM_CFG_HOT_RESET_NO 0x00000000 1648 #define NV_REG_STR_CL_ASLM_CFG_HOT_RESET_YES 0x00000001 1649 #define NV_REG_STR_CL_ASLM_CFG_HOT_RESET_DEFAULT 0x00000002 1650 #define NV_REG_STR_CL_ASLM_CFG_FAST_UPGRADE 9:8 1651 #define NV_REG_STR_CL_ASLM_CFG_FAST_UPGRADE_NO 0x00000000 1652 #define NV_REG_STR_CL_ASLM_CFG_FAST_UPGRADE_YES 0x00000001 1653 #define NV_REG_STR_CL_ASLM_CFG_FAST_UPGRADE_DEFAULT 0x00000002 1654 #define NV_REG_STR_CL_ASLM_CFG_GEN2_LINK_UPGRADE 11:10 1655 #define NV_REG_STR_CL_ASLM_CFG_GEN2_LINK_UPGRADE_NO 0x00000000 1656 #define NV_REG_STR_CL_ASLM_CFG_GEN2_LINK_UPGRADE_YES 0x00000001 1657 #define NV_REG_STR_CL_ASLM_CFG_GEN2_LINK_UPGRADE_DEFAULT 0x00000002 1658 // Type Dword 1659 // Encoding Numeric Value 1660 // Overrides chipset-based ASLM configurations. 1661 // 1662 // NV link upgrade: 1663 // 0 - Do not use NV link upgrade for ASLM 1664 // 1 - Use NV link upgrade for ASLM 1665 // 2 - Do not override chipset-selected config (default) 1666 // Hot reset: 1667 // 0 - Do not use hot reset for ASLM 1668 // 1 - Use hot reset for ASLM 1669 // 2 - Do not override chipset-selected config (default) 1670 // Fast link upgrade: 1671 // 0 - Do not use fast link upgrade for ASLM 1672 // 1 - Use fast link upgrade for ASLM 1673 // 2 - Do not override chipset-selected config (default) 1674 // Gen2 link width upgrade: 1675 // 0 - Do not use Gen2 link upgrade for ASLM 1676 // 1 - Use Gen2 link upgrade for ASLM 1677 // 2 - Do not override chipset-selected config (default) 1678 1679 #define NV_REG_STR_RM_DISABLE_BR03_FLOW_CONTROL "MB_DisableBr03FlowControl" 1680 // Type DWORD 1681 // Encoding 1 -> Do not program BR03 flow control registers 1682 // 0 -> Setup BR03 flow control registers 1683 // Determine whether we need to program BR03 flow control registers, in objcl.c 1684 1685 #define NV_REG_STR_RM_FORCE_ENABLE_GEN2 "RmForceEnableGen2" 1686 #define NV_REG_STR_RM_FORCE_ENABLE_GEN2_NO 0 1687 #define NV_REG_STR_RM_FORCE_ENABLE_GEN2_YES 1 1688 #define NV_REG_STR_RM_FORCE_ENABLE_GEN2_DEFAULT NV_REG_STR_RM_FORCE_ENABLE_GEN2_NO 1689 // Type DWORD: On some platform, Gen2 is disabled to work around system problems. 1690 // This key is to force enabling Gen2 for testing or other purpose. It is 1691 // ineffective on platforms not Gen2 capable. 1692 // Encoding boolean: 1693 // 0 - Do Nothing 1694 // 1 - Force Enable Gen2 (to invalidate PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED) 1695 // 1696 1697 #define NV_REG_STR_RM_D3_FEATURE "RMD3Feature" 1698 // Type DWORD 1699 // This regkey controls D3 related features 1700 #define NV_REG_STR_RM_D3_FEATURE_DRIVER_CFG_SPACE_RESTORE 1:0 1701 #define NV_REG_STR_RM_D3_FEATURE_DRIVER_CFG_SPACE_RESTORE_DEFAULT (0x00000000) 1702 #define NV_REG_STR_RM_D3_FEATURE_DRIVER_CFG_SPACE_RESTORE_ENABLED (0x00000001) 1703 #define NV_REG_STR_RM_D3_FEATURE_DRIVER_CFG_SPACE_RESTORE_DISABLED (0x00000002) 1704 #define NV_REG_STR_RM_D3_FEATURE_DRIVER_CFG_SPACE_RESTORE_UNUSED (0x00000003) 1705 1706 #define NV_REG_STR_EMULATED_NBSI_TABLE "RMemNBSItable" 1707 // The emulated NBSI table 1708 1709 #define NV_REG_STR_RM_DISABLE_FSP "RmDisableFsp" 1710 #define NV_REG_STR_RM_DISABLE_FSP_NO (0x00000000) 1711 #define NV_REG_STR_RM_DISABLE_FSP_YES (0x00000001) 1712 // Type DWORD (Boolean) 1713 // Override any other settings and disable FSP 1714 1715 #define NV_REG_STR_RM_DISABLE_COT_CMD "RmDisableCotCmd" 1716 #define NV_REG_STR_RM_DISABLE_COT_CMD_FRTS_SYSMEM 1:0 1717 #define NV_REG_STR_RM_DISABLE_COT_CMD_FRTS_VIDMEM 3:2 1718 #define NV_REG_STR_RM_DISABLE_COT_CMD_GSPFMC 5:4 1719 #define NV_REG_STR_RM_DISABLE_COT_CMD_DEFAULT (0x00000000) 1720 #define NV_REG_STR_RM_DISABLE_COT_CMD_YES (0x00000001) 1721 // Type DWORD (Boolean) 1722 // Disable the specified commands as part of Chain-Of-Trust feature 1723 1724 #define NV_REG_STR_PCI_LATENCY_TIMER_CONTROL "PciLatencyTimerControl" 1725 // Type Dword 1726 // Encoding Numeric Value 1727 // Override to control setting/not setting of pci timer latency value. 1728 // Not present suggests default value. A value 0xFFFFFFFF will leave the value unmodified (ie bios value). 1729 // All other values must be multiples of 8 1730 1731 #define NV_REG_STR_RM_ENABLE_ROUTE_TO_PHYSICAL_LOCK_BYPASS "RmRouteToPhyiscalLockBypass" 1732 // Type Bool 1733 // Enable optimisation to only take API READ (not WRITE) lock when forwarding ROUTE_TO_PHYSICAL 1734 // control calls to GSP-enabled GPUs. 1735 // This will heavily improve multi-gpu-multi-process control call latency and throughput. 1736 // This optimisation will only work when *all* GPUs in the system are in offload mode (GSP mode). 1737 1738 #define NV_REG_STR_RM_GPU_FABRIC_PROBE "RmGpuFabricProbe" 1739 #define NV_REG_STR_RM_GPU_FABRIC_PROBE_DELAY 7:0 1740 #define NV_REG_STR_RM_GPU_FABRIC_PROBE_SLOWDOWN_THRESHOLD 15:8 1741 #define NV_REG_STR_RM_GPU_FABRIC_PROBE_OVERRIDE 31:31 1742 // Type DWORD 1743 // Enable GPU fabric probe 1744 // 1745 // When this option is enabled, the GPU will probe its fabric state over the 1746 // NVLink inband channel. The fabric state includes the attributes to allow 1747 // the GPU to participate in P2P over the NVLink fabric. 1748 // 1749 // This option is only honored on NVSwitch based systems. 1750 // 1751 // Encoding: 1752 // _DELAY : Delay between consecutive probe retries (in sec) 1753 // before the slowdown starts. (Default: 5 sec) 1754 // _SLOWDOWN_THRESHOLD : Number of probes retries before the slowdown starts 1755 // (Default: 10). The slowdown doubles the delay 1756 // between every consecutive probe retries until success. 1757 // 1758 1759 // Enable plugin logs in ftrace buffer. 1760 // 0 - Default 1761 // 0 - Disabled 1762 // 1 - Enabled 1763 #define NV_REG_STR_RM_ENABLE_PLUGIN_IN_FTRACE_BUFFER "RmEnablePluginFtrace" 1764 #define NV_REG_STR_RM_ENABLE_PLUGIN_IN_FTRACE_BUFFER_ENABLED 0x00000001 1765 #define NV_REG_STR_RM_ENABLE_PLUGIN_IN_FTRACE_BUFFER_DISABLED 0x00000000 1766 #define NV_REG_STR_RM_ENABLE_PLUGIN_IN_FTRACE_BUFFER_DEFAULT 0x00000000 1767 1768 // TYPE Dword 1769 // Enable vGPU migration on KVM hyperivsor. 1770 // 1 - (Default) Enable vGPU migration on KVM 1771 // 0 - Disable vGPU migration on KVM hypervisor 1772 // 1773 #define NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION "RmEnableKvmVgpuMigration" 1774 #define NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION_TRUE 0x00000001 1775 #define NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION_FALSE 0x00000000 1776 #define NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION_DEFAULT 0x00000001 1777 1778 #define NV_REG_STR_RM_QSYNC_FW_REV_CHECK "QuadroSyncFirmwareRevisionCheckDisable" 1779 #define NV_REG_STR_RM_QSYNC_FW_REV_CHECK_DEFAULT 0x00000000 1780 #define NV_REG_STR_RM_QSYNC_FW_REV_CHECK_ENABLE 0x00000000 1781 #define NV_REG_STR_RM_QSYNC_FW_REV_CHECK_DISABLE 0x00000001 1782 1783 // Type DWORD 1784 // Disable Quadro Sync Firmware Revision Checking, for testing new versions. 1785 // 1786 1787 // 1788 // Type: Dword 1789 // Encoding: 1790 // 1 - SRIOV Enabled on supported GPU 1791 // 0 - SRIOV Disabled on specific GPU 1792 // 1793 #define NV_REG_STR_RM_SET_SRIOV_MODE "RMSetSriovMode" 1794 #define NV_REG_STR_RM_SET_SRIOV_MODE_DISABLED 0x00000000 1795 #define NV_REG_STR_RM_SET_SRIOV_MODE_ENABLED 0x00000001 1796 1797 #define NV_REG_STR_RM_SET_VGPU_VERSION_MIN "RMSetVGPUVersionMin" 1798 // 1799 // TYPE DWORD 1800 // Set the minimum vGPU version enforced to support 1801 1802 #define NV_REG_STR_RM_SET_VGPU_VERSION_MAX "RMSetVGPUVersionMax" 1803 // 1804 // TYPE DWORD 1805 // Set the maximum vGPU version enforced to support 1806 1807 #define NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_LSR_MIN_TIME "TSwapRdyHiLsrMinTime" 1808 #define NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_LSR_MIN_TIME_DEFAULT 250 // 250 micro seconds 1809 // Type: DWORD 1810 // Encoding: 1811 // To modify LSR_MIN_TIME parameter according to the time 1812 // period for which swap lock window will remain HIGH for QSYNC III 1813 // i.e. P2060 during swap barrier. 1814 1815 #define NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_SWAP_LOCKOUT_START "TSwapRdyHiSwapLockoutStart" 1816 #define NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_SWAP_LOCKOUT_START_DEFAULT 250 // 250 micro seconds 1817 // Type: DWORD 1818 // Encoding: 1819 // To modify SWAP_LOCKOUT_START parameter according to the time 1820 // period for which swap lock window will remain HIGH for QSYNC III. 1821 // 1822 1823 #define NV_REG_STR_RM_NVLINK_BW "RmNvlinkBandwidth" 1824 // Type String 1825 // The option is in the string format. 1826 // 1827 // Possible string values: 1828 // OFF: 0% bandwidth 1829 // MIN: 15%-25% bandwidth depending on the system's NVLink topology 1830 // HALF: 50% bandwidth 1831 // 3QUARTER: 75% bandwidth 1832 // FULL: 100% bandwidth (default) 1833 // 1834 // This option is only for Hopper+ GPU with NVLINK version 4.0. 1835 1836 #define NV_REG_STR_RM_CLIENT_HANDLE_LOOKUP "RmClientHandleLookup" 1837 // Type DWORD (Boolean) 1838 // 1 - Store active RM clients in a multimap to speed up lookups (currently only in thirdpartyp2p) 1839 // 0 - (Default) Linear list search for clients 1840 1841 // 1842 // Type DWORD (Boolean) 1843 // 1 - Measure API and GPU lock hold/wait times which can be retrieved with the 1844 // NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES control call 1845 // 0 - (Default) Don't measure lock hold/wait times 1846 // 1847 #define NV_REG_STR_RM_LOCK_TIME_COLLECT "RmLockTimeCollect" 1848 1849 // 1850 // Type: DWORD (Boolean) 1851 // 1852 // 1 - Only invalidate and free CPU mappings immediatelly, then collect GPU resources 1853 // from individual clients under separate lock acquire/release sequences. 1854 // 0 - (Default) Immediately free all clients resources when freeing a client list 1855 #define NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE "RMClientListDeferredFree" 1856 1857 // 1858 // Type: DWORD 1859 // 1860 // Number of clients to free in a single chunk before yielding and scheduling 1861 // a work item to handle the rest. 1862 // 1863 // Only valid if NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE is set. 1864 // 1865 // Value of 0 (default) means there is no limit and all clients will be freed 1866 // at once before the process terminates. 1867 // 1868 #define NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE_LIMIT "RMClientListDeferredFreeLimit" 1869 1870 // 1871 // TYPE Dword 1872 // Determines whether or not to emulate VF MMU TLB Invalidation register range 1873 // Encoding : 1 - Emulate register range (Default) 1874 // : 0 - Do not emulate register range. 1875 // 1876 #define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE "RMBug3007008EmulateVfMmuTlbInvalidate" 1877 #define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_ENABLE 0x00000001 1878 #define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_DISABLE 0x00000000 1879 #define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_DEFAULT NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_ENABLE 1880 1881 #define NV_REG_STR_RM_POWER_FEATURES "RMPowerFeature" 1882 1883 // Type DWORD 1884 // This Regkey controls inforom black box data recording. This can be used to 1885 // restrict access to BBX. 1886 // 0 - Enable BBX. (Default) 1887 // COMPLETELY - Enable/Disable BBX access (read/write). 1888 // WRITE_BY_RM - Enable/Disable writes by RM itself. 1889 // WRITE_BY_CLIENT - Enable/Disable writes by clients to RM. 1890 // PERIODIC FLUSH - Enable/Disable periodic flush to inforom (Also enables/disables Power data collection) 1891 // 1892 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX "RmDisableInforomBBX" 1893 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_NO (0x00000000) 1894 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_YES (0x00000001) 1895 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_COMPLETELY 0:0 1896 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_COMPLETELY_NO (0x00000000) 1897 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_COMPLETELY_YES (0x00000001) 1898 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_RM 1:1 1899 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_RM_NO (0x00000000) 1900 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_RM_YES (0x00000001) 1901 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_CLIENT 2:2 1902 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_CLIENT_NO (0x00000000) 1903 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_CLIENT_YES (0x00000001) 1904 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_PERIODIC_FLUSH 3:3 1905 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_PERIODIC_FLUSH_YES (0x00000000) 1906 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_PERIODIC_FLUSH_NO (0x00000001) 1907 1908 // 1909 // Type DWORD (Boolean) 1910 // RmNvlinkEnablePrivErrorRc 1911 // 1912 // 0 - (default) does not do RC recovery when PRIV_ERROR 1913 // 1 - enable FLA PRIV_ERROR RC recovery 1914 // 1915 #define NV_REG_STR_RM_NVLINK_ENABLE_PRIV_ERROR_RC "RmNvlinkEnablePrivErrorRc" 1916 #define NV_REG_STR_RM_NVLINK_ENABLE_PRIV_ERROR_RC_NO 0 1917 #define NV_REG_STR_RM_NVLINK_ENABLE_PRIV_ERROR_RC_YES 1 1918 1919 // 1920 // Add the conditions to exclude these macros from Orin build, as CONFIDENTIAL_COMPUTE 1921 // is a guardword. The #if could be removed when nvRmReg.h file is trimmed from Orin build. 1922 // 1923 // Enable Disable Confidential Compute and control its various modes of operation 1924 // 0 - Feature Disable 1925 // 1 - Feature Enable 1926 // 1927 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE "RmConfidentialCompute" 1928 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_ENABLED 0:0 1929 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_ENABLED_NO 0x00000000 1930 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_ENABLED_YES 0x00000001 1931 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_DEV_MODE_ENABLED 1:1 1932 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_DEV_MODE_ENABLED_NO 0x00000000 1933 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_DEV_MODE_ENABLED_YES 0x00000001 1934 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_GPUS_READY_CHECK 2:2 1935 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_GPUS_READY_CHECK_DISABLED 0x00000000 1936 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_GPUS_READY_CHECK_ENABLED 0x00000001 1937 1938 #define NV_REG_STR_RM_CONF_COMPUTE_EARLY_INIT "RmConfComputeEarlyInit" 1939 #define NV_REG_STR_RM_CONF_COMPUTE_EARLY_INIT_DISABLED 0x00000000 1940 #define NV_REG_STR_RM_CONF_COMPUTE_EARLY_INIT_ENABLED 0x00000001 1941 1942 // 1943 // Enable/disable SPDM feature in Confidential Compute. SPDM-capable profiles 1944 // may not be loaded by default. This regkey allows us to override the default 1945 // behavior and force SPDM to enabled/disabled. 1946 // 1947 // 0 - Feature disable 1948 // 1 - Feature enable 1949 // 1950 #define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY "RmConfComputeSpdmPolicy" 1951 #define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY_ENABLED 0:0 1952 #define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY_ENABLED_NO 0x00000000 1953 #define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY_ENABLED_YES 0x00000001 1954 1955 // 1956 // Enable/disable key rotation in Confidential Compute. 1957 // 1958 // 0 - Feature disabled 1959 // 1 - Feature enabled 1960 // 1961 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION "RmConfComputeKeyRotation" 1962 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_ENABLED 0:0 1963 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_ENABLED_NO 0x00000000 1964 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_ENABLED_YES 0x00000001 1965 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_SEC2_KEYS 1:1 1966 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_SEC2_KEYS_NO 0x00000000 1967 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_SEC2_KEYS_YES 0x00000001 1968 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE2_KEYS 2:2 1969 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE2_KEYS_NO 0x00000000 1970 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE2_KEYS_YES 0x00000001 1971 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE3_KEYS 3:3 1972 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE3_KEYS_NO 0x00000000 1973 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE3_KEYS_YES 0x00000001 1974 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE4_KEYS 4:4 1975 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE4_KEYS_NO 0x00000000 1976 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE4_KEYS_YES 0x00000001 1977 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE5_KEYS 5:5 1978 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE5_KEYS_NO 0x00000000 1979 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE5_KEYS_YES 0x00000001 1980 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE6_KEYS 6:6 1981 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE6_KEYS_NO 0x00000000 1982 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE6_KEYS_YES 0x00000001 1983 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE7_KEYS 7:7 1984 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE7_KEYS_NO 0x00000000 1985 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE7_KEYS_YES 0x00000001 1986 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE8_KEYS 8:8 1987 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE8_KEYS_NO 0x00000000 1988 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE8_KEYS_YES 0x00000001 1989 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE9_KEYS 9:9 1990 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE9_KEYS_NO 0x00000000 1991 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE9_KEYS_YES 0x00000001 1992 1993 // if all kernel keys should be considered for key rotation 1994 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_KERNEL_KEYS 10:10 1995 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_KERNEL_KEYS_NO 0x00000000 1996 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_KERNEL_KEYS_YES 0x00000001 1997 1998 // if all user keys should be considered for key rotation 1999 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_USER_KEYS 11:11 2000 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_USER_KEYS_NO 0x00000000 2001 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_USER_KEYS_YES 0x00000001 2002 2003 // if internal RM keys should be considered for key rotation 2004 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_INTERNAL_KEYS 12:12 2005 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_INTERNAL_KEYS_NO 0x00000000 2006 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_INTERNAL_KEYS_YES 0x00000001 2007 2008 // 2009 // Set period for "keep-alive" heartbeat message sent between SPDM Requester and Responder. 2010 // This will sent a keep-alive message every period to GPU. GPU will set timeout to 2 * period. 2011 // If GPU doesn't receive message within 2 * period, it is fatal error and GPU will require reset. 2012 // Minimum period is 4 seconds, maximum period is 255 seconds. Setting period to 0 will disable heartbeat. 2013 // 2014 // 0 - Disable feature (no heartbeat sending) 2015 // x - Period value in seconds 2016 // 2017 #define NV_REG_STR_RM_CONF_COMPUTE_HEARTBEAT "RmConfComputeHeartbeatPeriod" 2018 #define NV_REG_STR_RM_CONF_COMPUTE_HEARTBEAT_PERIOD_SECONDS 31:0 2019 #define NV_REG_STR_RM_CONF_COMPUTE_HEARTBEAT_PERIOD_SECONDS_DISABLE 0x00000000 2020 #define NV_REG_STR_RM_CONF_COMPUTE_HEARTBEAT_PERIOD_SECONDS_MIN 0x00000004 2021 #define NV_REG_STR_RM_CONF_COMPUTE_HEARTBEAT_PERIOD_SECONDS_MAX 0x000000FF 2022 2023 // 2024 // Set the key rotation timeout value for user-mode clients. 2025 // This is the amount of time in seconds, after the threshold has been crossed, that user-mode clients 2026 // have to idle their channels before RM RCs the channels for key rotation. 2027 // This value must be greater than or equal to 2. 2028 // 2029 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_TIMEOUT_IN_SEC "RmKeyRotationTimeout" 2030 2031 // 2032 // Set the difference between the lower and upper thresholds. 2033 // Value is in units of (amount of data encrypted in units of 16 bytes + number of encryption invocations) 2034 // If this is set then NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LOWER_THRESHOLD and 2035 // NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_UPPER_THRESHOLD are ignored. 2036 // This value must be greater than 0. 2037 // 2038 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_THRESHOLD_DELTA "RmKeyRotationThresholdDelta" 2039 2040 // 2041 // Set lower threshold for key rotation. 2042 // Value is in units of (amount of data encrypted in units of 16 bytes + number of encryption invocations) 2043 // If this is set then RmKeyRotationUpperThreshold must also be set. 2044 // This value must be less than RmKeyRotationUpperThreshold. 2045 // Note that setting the attacker advantage via SMI/NVML will overwrite this value. 2046 // 2047 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LOWER_THRESHOLD "RmKeyRotationLowerThreshold" 2048 2049 // 2050 // Set upper threshold for key rotation. 2051 // Value is in units of (amount of data encrypted in units of 16 bytes + number of encryption invocations) 2052 // If this is set then RmKeyRotationLowerThreshold must also be set. 2053 // This value must be greater than RmKeyRotationLowerThreshold. 2054 // Note that setting the attacker advantage via SMI/NVML will overwrite this value. 2055 // 2056 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_UPPER_THRESHOLD "RmKeyRotationUpperThreshold" 2057 2058 // 2059 // Set threshold for rotation of internal (RM only) keys. 2060 // Value is in units of (amount of data encrypted in units of 16 bytes + number of encryption invocations) 2061 // Value must be greater than minimum of (0x7FFFFFF). 2062 // This value cannot be changed at runtime, only via this registry key at boot time. 2063 // 2064 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_INTERNAL_THRESHOLD "RmKeyRotationInternalThreshold" 2065 2066 // 2067 // TYPE Dword 2068 // Encoding boolean 2069 // Regkey based solution to serialize VBlank Aggressive Handling in Top Half using spinlock 2070 // 2 - Enable serialization of aggressive vblank callbacks when HMD is active 2071 // 2072 // 2073 // 1 - Enable serialization of aggressive vblank callbacks in all scenarios 2074 // (even when a HMD is not active) 2075 // 2076 // 0 - (default) Disable WAR 2077 // This regkey settings are enabled when Aggressive Vblanks are enabled, 2078 // if RmDisableAggressiveVblank is set to disable then these regkeys do not have any affect 2079 #define NV_REG_STR_RM_BUG_2089053_WAR "RmBug2089053War" 2080 #define NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ON_HMD_ACTIVE_ONLY 0x00000002 2081 #define NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ALWAYS 0x00000001 2082 #define NV_REG_STR_RM_BUG_2089053_WAR_DISABLE 0x00000000 2083 #define NV_REG_STR_RM_BUG_2089053_WAR_DEFAULT (NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ALWAYS) 2084 2085 // 2086 // Controls whether GSP-RM profiling is enabled. 2087 // 0 (default): disabled 2088 // 1: enabled 2089 // 2090 #define NV_REG_STR_RM_GSPRM_PROFILING "RmGspRmProfiling" 2091 #define NV_REG_STR_RM_GSPRM_PROFILING_DISABLE 0 2092 #define NV_REG_STR_RM_GSPRM_PROFILING_ENABLE 1 2093 2094 // 2095 // Controls, GSP-RM start with boost clocks. 2096 // 0 : disabled 2097 // 1 : enabled (default) 2098 // 2099 #define NV_REG_STR_RM_BOOT_GSPRM_WITH_BOOST_CLOCKS "RmBootGspRmWithBoostClocks" 2100 #define NV_REG_STR_RM_BOOT_GSPRM_WITH_BOOST_CLOCKS_DISABLED 0 2101 #define NV_REG_STR_RM_BOOT_GSPRM_WITH_BOOST_CLOCKS_ENABLED 1 2102 2103 // 2104 // Enable Local EGM HW verification using RM/SW stack. 2105 // Must be specified with a peerID corresponding to local EGM 2106 // 2107 #define NV_REG_STR_RM_ENABLE_LOCAL_EGM_PEER_ID "RMEnableLocalEgmPeerId" 2108 2109 // 2110 // Overrides the size of the GSP-RM firmware heap in GPU memory. 2111 // The GSP-RM firmware heap is reserved for system use and is not available to 2112 // applications. This regkey can be used to optimize the amount of memory 2113 // reserved for system use for targeted use cases. The default value for this 2114 // regkey is determined to support certain worst case resource allocation 2115 // patterns, but many use cases do not exhibit such resource allocation patterns 2116 // and could benefit from the lesser reserved GPU memory. Other use cases may 2117 // exhibit an even more pathological/stressful resource allocation pattern, 2118 // which can be enabled (up to a limit) with this regkey. 2119 // 2120 // However, NVIDIA does not support setting this registry key, and will require 2121 // that any bugs observed with it set be reproducible with the default setting 2122 // as well. 2123 // 2124 // The value of this regkey is specified in megabytes. A value of 0 indicates to 2125 // use the default value. Values less than the minimum or greater than the 2126 // maximum will be clamped to the nearest optimum. The default values are 2127 // are dynamically computed for each GPU prior to booting GSP-RM. 2128 // 2129 #define NV_REG_STR_GSP_FIRMWARE_HEAP_SIZE_MB "RmGspFirmwareHeapSizeMB" 2130 #define NV_REG_STR_GSP_FIRMWARE_HEAP_SIZE_MB_DEFAULT 0 2131 2132 // 2133 // Type DWORD 2134 // This regkey can be used to enable GSP owned fault buffers 2135 // 2136 #define NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE "RmGspOwnedFaultBuffersEnable" 2137 #define NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE_NO 0x00000000 2138 #define NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE_YES 0x00000001 2139 2140 // 2141 // WAR for BlueField3: Bug 4040336 2142 // BF3's PCI MMIO bus address 0x800000000000 is too high for Ampere to address. 2143 // Due to this, BF3's bus address is now moved to < 4GB. So, the CPU PA is no longer 2144 // the same as the bus address and this regkey adjusts the CPU PA passed in to the 2145 // correct bus address. 2146 // 2147 #define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3 "RmDmaAdjustPeerMmioBF3" 2148 #define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_DISABLE 0 2149 #define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_ENABLE 1 2150 2151 #define NV_REG_STR_RM_NVLINK_FORCED_LOOPBACK_ON_SWITCH "RMNvLinkForcedLoopbackOnSwitch" 2152 #define NV_REG_STR_RM_NVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE 0:0 2153 #define NV_REG_STR_RM_NVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE_DEFAULT (0x00000000) 2154 #define NV_REG_STR_RM_NVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE_ENABLED (0x00000001) 2155 2156 // 2157 // Type: Dword 2158 // Encoding: 2159 // 0 - Iterative MMU Walker is not enabled. Normal recursive implementation is used. (default) 2160 // 1 - Iterative MMU Walker is used 2161 // 2162 #define NV_REG_STR_RM_ITERATIVE_MMU_WALKER "RMUseIterativeMMUWalker" 2163 #define NV_REG_STR_RM_ITERATIVE_MMU_WALKER_DISABLED 0x00000000 2164 #define NV_REG_STR_RM_ITERATIVE_MMU_WALKER_ENABLED 0x00000001 2165 #define NV_REG_STR_RM_ITERATIVE_MMU_WALKER_DEFAULT NV_REG_STR_RM_ITERATIVE_MMU_WALKER_DISABLED 2166 2167 // 2168 // Type DWORD 2169 // This set of MIG regkeys specifies a set of allocation requests to be issued to the GPU on boot. 2170 // MIG configuration contained within GPUMGR always supersedes these regkeys, if present and valid. 2171 // The entire configuration specified by these regkeys is validated before being applied. An error 2172 // reflected in whole or in part on these regkeys will cause them to be discarded entirely. 2173 // 2174 // RmMIGBootConfigurationGI is used to encode a series of GPU instance allocations. These are applied in order. 2175 // RmMIGBootConfigurationCI is used to encode a series of CI instance allocations. 2176 // The GI associated with each CI allocation entry is specified by RmMIGBootConfigurationCIAssignment. 2177 // It is an error to specify a CI via RmMIGBootConfigurationCI without specifying the associated GPU 2178 // instance entry via RmMIGBootConfigurationCIAssignment. The values for any CI assignment for a CI 2179 // entry left unspecified must be 0. 2180 // 2181 // RmMIGBootConfigurationGI_N 2182 // _FLAGS - determines granularity of GPU partitioning. See NV2080_CTRL_CMD_GPU_SET_PARTITIONS 2183 // _PLACEMENT_LO - Optional placement span to allocate the partition into. Unused if HI<LO 2184 // _PLACEMENT_HI - Optional placement span to allocate the partition into. Unused if HI<LO 2185 // _REQ_DEC_JPG_OFA - For single slice instances, request at least 1 video decode, jpeg, and optical flow engine 2186 // 2187 // RmMIGBootConfigurationCI_N 2188 // _FLAGS - determines granularity of GPU partitioning. Subset of the GI flags - only the compute size flags are used here. See NV2080_CTRL_CMD_GPU_SET_PARTITIONS 2189 // _PLACEMENT_LO - Starting slice in GPU instance 2190 // _CES - # Copy engines to share with other CIs in this GI. 0 denotes all available. 2191 // _DECS - # video decoder engines to share with other CIs in this GI. 0 denotes all available. 2192 // _ENCS - # video decoder engines to share with other CIs in this GI. 0 denotes all available. 2193 // _JPGS - # jpeg engines to share with other CIs in this GI. 0 denotes all available. 2194 // _OFAS - # optical flow engines to share with other CIs in this GI. 0 denotes all available. 2195 // 2196 // RmMIGBootConfigurationCIAssignment 2197 // _GI(n) - Assign Compute instance n to GPU instance entry according to this value 2198 // 2199 // RmMIGBootConfigurationFeatureFlags 2200 // _AUTO_UPDATE - Windows only. RM updates the regkeys at runtime as MIG configuration changes. 2201 // 2202 2203 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI(n) "RmMIGBootConfigurationGI_" #n 2204 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI__SIZE 8 2205 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI_FLAGS 7:0 2206 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI_PLACEMENT_LO 15:8 2207 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI_PLACEMENT_HI 23:16 2208 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI_REQ_DEC_JPG_OFA 31:31 2209 2210 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI(n) "RmMIGBootConfigurationCI_" #n 2211 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI__SIZE 8 2212 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_FLAGS 7:0 2213 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_PLACEMENT_LO 11:8 2214 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_CES 15:12 2215 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_DECS 19:16 2216 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_ENCS 23:20 2217 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_JPGS 27:24 2218 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_OFAS 31:28 2219 2220 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_ASSIGNMENT "RmMIGBootConfigurationCIAssignment" 2221 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_ASSIGNMENT_GI(n) ((4 * ((n) + 1)) - 1):(4 * (n)) 2222 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_ASSIGNMENT_GI__SIZE 8 2223 2224 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS "RmMIGBootConfigurationFeatureFlags" 2225 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_SUPPORTED 0:0 2226 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_SUPPORTED_DEFAULT 0x0 2227 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_SUPPORTED_FALSE 0x0 2228 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_SUPPORTED_TRUE 0x1 2229 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_AUTO_UPDATE 1:1 2230 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_AUTO_UPDATE_DEFAULT 0x0 2231 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_AUTO_UPDATE_DISABLED 0x0 2232 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_AUTO_UPDATE_ENABLED 0x1 2233 2234 // 2235 // Type: DWORD 2236 // 2237 // If the midpath spinning feature of the GPU lock is enabled. 2238 // 2239 // 0 (default) - Midpath Spinning disabled 2240 // 1 - Midpath spinning enabled 2241 // 2242 #define NV_REG_STR_RM_GPU_LOCK_MIDPATH "RMGpuLockMidpath" 2243 #define NV_REG_STR_RM_GPU_LOCK_MIDPATH_DISABLED 0x00000000 2244 #define NV_REG_STR_RM_GPU_LOCK_MIDPATH_ENABLED 0x00000001 2245 2246 // 2247 // This regkey controls the GPU load failure test. 2248 // Supported only on DEBUG, DEVELOP, or RELEASE drivers built with the parameter INSTRUMENT_RM=true 2249 // This is an input/output registry key. 2250 // NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_START: input - start the text at the specified stage and engine index. 2251 // Typically when the test starts, it is with NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_PREINIT + ENGINEINDEX = 0 2252 // NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_RUNNING: output - the test is running. 2253 // The next stage and engine index are specified 2254 // The test executable just needs to change NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_NEXT to _START for the next step 2255 // NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_FINISHED: output - there is no morre stages and engines to test 2256 // 2257 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST "RmGpuLoadFailureTest" 2258 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS 1:0 2259 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_NONE 0x00000000 2260 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_START 0x00000001 2261 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_RUNNING 0x00000002 2262 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_FINISHED 0x00000003 2263 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE 4:2 2264 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_PREINIT 0x00000000 2265 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_INIT 0x00000001 2266 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_PRELOAD 0x00000002 2267 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_LOAD 0x00000003 2268 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_POSTLOAD 0x00000004 2269 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_ENGINEINDEX 31:5 2270 2271 // 2272 // Type: DWORD 2273 // Encoding: 2274 // 0 - Disable MIG auto online mode on driver load 2275 // 1 - Enable MIG auto online mode on driver load 2276 // 2277 #define NV_REG_STR_RM_SET_MIG_AUTO_ONLINE_MODE "RMSetMIGAutoOnlineMode" 2278 #define NV_REG_STR_RM_SET_MIG_AUTO_ONLINE_MODE_DISABLED 0 2279 #define NV_REG_STR_RM_SET_MIG_AUTO_ONLINE_MODE_ENABLED 1 2280 2281 // 2282 // Type: DWORD 2283 // Encoding: 2284 // 0 - Disable multi gpu mode 2285 // 1 - Enable protected pcie 2286 // 2287 #define NV_REG_STR_RM_CC_MULTI_GPU_MODE "RmCCMultiGpuMode" 2288 #define NV_REG_STR_RM_CC_MULTI_GPU_MODE_NONE 0x00000000 2289 #define NV_REG_STR_RM_CC_MULTI_GPU_MODE_PROTECTED_PCIE 0x00000001 2290 2291 // This regkey allows RM to access CPR vidmem over BARs when HCC devtools mode is ON 2292 #define NV_REG_STR_RM_FORCE_BAR_ACCESS_ON_HCC "RmForceBarAccessOnHcc" 2293 #define NV_REG_STR_RM_FORCE_BAR_ACCESS_ON_HCC_NO 0x00000000 2294 #define NV_REG_STR_RM_FORCE_BAR_ACCESS_ON_HCC_YES 0x00000001 2295 2296 // 2297 // TYPE DWORD 2298 // This regkey allows to change the state of NVENC sessions stats reporting. 2299 // Note : Currently only used and works for Grid. 2300 // 0 - Disable NVENC session stats reporting. 2301 // 1 - Enable NVENC session stats reporting. 2302 // 2303 #define NV_REG_STR_RM_NVENC_SESSION_STATS_REPORTING_STATE "EncSessionStatsReportingState" 2304 #define NV_REG_STR_RM_NVENC_SESSION_STATS_REPORTING_STATE_DISABLED 0x00000000 2305 #define NV_REG_STR_RM_NVENC_SESSION_STATS_REPORTING_STATE_ENABLED 0x00000001 2306 2307 // TYPE DWORD 2308 // Set to provide ECC state in guest 2309 // Used for vGPU 2310 // The value default is set if ECC is enabled in USM profile. 2311 // 2312 #define NV_REG_STR_RM_GUEST_ECC_STATE "RMGuestECCState" 2313 #define NV_REG_STR_RM_GUEST_ECC_STATE_DISABLED 0x00000000 2314 #define NV_REG_STR_RM_GUEST_ECC_STATE_ENABLED 0x00000001 2315 #define NV_REG_STR_RM_GUEST_ECC_STATE_DEFAULT 0x00000001 2316 2317 // 2318 // Type DWORD 2319 // This regkey force-disables write-combine iomap allocations, used for chipsets where 2320 // write-combine is broken. 2321 // 2322 #define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC "RmForceDisableIomapWC" 2323 #define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_YES 0x00000001 2324 #define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_NO 0x00000000 2325 #define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_DEFAULT NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_NO 2326 2327 // 2328 // Regkey to configure Per VM RunList. 2329 // Type Dword 2330 // BIT 0:0 - Overall PVMRL enable/disable. 2331 // 0 - Disable / Default - 1 HW runlist per engine. 2332 // 1 - Enable - 1 SW runlist per VM for some engines. 2333 // BIT 1:1 - Adaptive Round Robin Scheduler 2334 // 0 - Enable / Default - Use Adaptive Round Robin Scheduler 2335 // 1 - Disable - Use Legacy PVMRL 2336 // BIT 7:4 - PVMRL scheduler to run. 2337 // 0 - equal share / Default - equal share amongst running vGPUs. 2338 // 1 - fixed share - fixed share of the physical GPU. 2339 // BIT 21:12 - PVMRL Scheduling frequency. 2340 // 0 - Default timeslice. 2341 // F - Timeslice = 1000 / F. 2342 // BIT 23:16 - PVMRL timeslice in ms (Milli-seconds). 2343 // 0 - Default timeslice. 2344 // T - Timeslice of T ms. 2345 // BIT 31:24 - ARR Average Factor 2346 // 0 - Default Average Factor 2347 // F - Average Factor = F 2348 // 2349 #define NV_REG_STR_RM_PVMRL "RmPVMRL" 2350 #define NV_REG_STR_RM_PVMRL_ENABLE 0:0 2351 #define NV_REG_STR_RM_PVMRL_ENABLE_DEFAULT 0x00000000 2352 #define NV_REG_STR_RM_PVMRL_ENABLE_NO 0x00000000 2353 #define NV_REG_STR_RM_PVMRL_ENABLE_YES 0x00000001 2354 #define NV_REG_STR_RM_PVMRL_ARR_DISABLE 1:1 2355 #define NV_REG_STR_RM_PVMRL_ARR_DISABLE_DEFAULT 0x00000000 2356 #define NV_REG_STR_RM_PVMRL_ARR_DISABLE_NO 0x00000000 2357 #define NV_REG_STR_RM_PVMRL_ARR_DISABLE_YES 0x00000001 2358 #define NV_REG_STR_RM_PVMRL_SCHED_POLICY 7:4 2359 #define NV_REG_STR_RM_PVMRL_SCHED_POLICY_DEFAULT 0x00000000 2360 #define NV_REG_STR_RM_PVMRL_SCHED_POLICY_VGPU_EQUAL_SHARE 0x00000000 2361 #define NV_REG_STR_RM_PVMRL_SCHED_POLICY_VGPU_FIXED_SHARE 0x00000001 2362 #define NV_REG_STR_RM_PVMRL_FREQUENCY 21:12 2363 #define NV_REG_STR_RM_PVMRL_TIMESLICE 23:16 2364 #define NV_REG_STR_RM_PVMRL_AVERAGE_FACTOR 31:24 2365 2366 // 2367 // TYPE DWORD 2368 // This regkey will increase the margin after the end of WPR2 when booting GSP-RM. 2369 // 2370 // This margin can be used to help GSP firmware boot in the presence of ECC 2371 // errors which might affect the default GSP firmware image location in the GPU 2372 // framebuffer. If GPU firmware is able to successfully boot with this registry 2373 // key enabled, it should scan the margin area to attempt to handle ECC errors in 2374 // the region, so that the region can be safely used in a subsequent boot. 2375 // 2376 // NV_REG_RM_GSP_WPR_END_MARGIN_MB 2377 // Possible values: 2378 // 0 - (Default) use the default calculated GSP WPR size 2379 // 1+ - size of the end margin in megabytes 2380 // 2381 // NV_REG_RM_GSP_WPR_END_MARGIN_APPLY 2382 // Possible values: 2383 // _ON_RETRY (0) - (Default) only increase the margin to the requested size 2384 // when retrying GSP firmware boot after a failed boot attempt 2385 // _ALWAYS (1) - increase the margin to the requested size for all GSP 2386 // firmware boot attempts, including the first 2387 // 2388 #define NV_REG_STR_RM_GSP_WPR_END_MARGIN "RmGspWprEndMargin" 2389 #define NV_REG_RM_GSP_WPR_END_MARGIN_MB 30:0 2390 #define NV_REG_RM_GSP_WPR_END_MARGIN_APPLY 31:31 2391 #define NV_REG_RM_GSP_WPR_END_MARGIN_APPLY_ON_RETRY 0x00000000 2392 #define NV_REG_RM_GSP_WPR_END_MARGIN_APPLY_ALWAYS 0x00000001 2393 // 2394 // Type: Dword 2395 // This regkey toggles whether to release API lock during initialization to 2396 // allow multiple GPUS to initialize in parallel 2397 // 0 - API lock will not be released 2398 // 1 - API lock will be released 2399 // 2 - API lock release determined by platform (default) 2400 // 2401 #define NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING "RmRelaxedGspInitLocking" 2402 #define NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_DISABLE 0x00000000 2403 #define NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_ENABLE 0x00000001 2404 #define NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_DEFAULT 0x00000002 2405 2406 // 2407 // Type: Dword 2408 // This regkey overrides the state of the GR scrubber channel and determines 2409 // whether it should be created or not. 2410 // 2411 #define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL "RmForceGrScrubberChannel" 2412 #define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL_DISABLE 0x00000000 2413 #define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL_ENABLE 0x00000001 2414 #endif // NVRM_REGISTRY_H 2415