1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 1997-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 // 25 // This file holds NVIDIA Resource Manager registry key definitions that are 26 // shared between Windows and Unix 27 // 28 29 #ifndef NVRM_REGISTRY_H 30 #define NVRM_REGISTRY_H 31 32 #include "nvtypes.h" 33 34 // 35 // Some shared defines with nvReg.h 36 // 37 #if defined(NV_UNIX) 38 #define NV4_REG_GLOBAL_BASE_KEY "" 39 #define NV4_REG_GLOBAL_BASE_PATH "_NV_" 40 #else 41 #define NV4_REG_GLOBAL_BASE_KEY HKEY_LOCAL_MACHINE 42 #define NV4_REG_GLOBAL_BASE_PATH "SOFTWARE\\NVIDIA Corporation\\Global" 43 #endif 44 #define NV4_REG_SUBKEY "NVidia" 45 #define NV4_REG_DISPLAY_DRIVER_SUBKEY "Display" 46 #define NV4_REG_RESOURCE_MANAGER_SUBKEY "System" 47 48 // 49 // Globally overrides the memory type used to store surfaces. 50 // Used by all parts of the driver and stored in the hardware-specific key. 51 // Mirrored from nvReg.h 52 // 53 #define NV_REG_STR_GLOBAL_SURFACE_OVERRIDE "GlobalSurfaceOverrides" 54 #define NV_REG_STR_GLOBAL_SURFACE_OVERRIDE_DISABLE (0x00000000) // Do not use global surface overrides 55 #define NV_REG_STR_GLOBAL_SURFACE_OVERRIDE_ENABLE (0x00000001) 56 #define NV_REG_STR_GLOBAL_SURFACE_OVERRIDE_RM_VALUE 1:0 57 #define NV_REG_STR_GLOBAL_SURFACE_OVERRIDE_RM_ENABLE 3:3 58 59 60 #define NV_REG_STR_RM_OVERRIDE_DEFAULT_TIMEOUT "RmDefaultTimeout" 61 // Type Dword 62 // Override default RM timeout. Measured in milliseconds. 63 // Not scaled for emulation 64 65 #define NV_REG_STR_RM_OVERRIDE_DEFAULT_TIMEOUT_FLAGS "RmDefaultTimeoutFlags" 66 #define NV_REG_STR_RM_OVERRIDE_DEFAULT_TIMEOUT_FLAGS_OSTIMER 4 67 #define NV_REG_STR_RM_OVERRIDE_DEFAULT_TIMEOUT_FLAGS_OSDELAY 8 68 // Type Dword 69 // Override default RM timeout flags to either OSDELAY or OSTIMER. 70 71 72 #define NV_REG_STR_SUPPRESS_CLASS_LIST "SuppressClassList" 73 // Type String 74 // A list of comma separated classes to suppress 75 // examples: 76 // 5097 77 // 4097, 5097 78 // etc 79 80 81 // 82 // Allow instance memory overrides. Some fields are chip specific 83 // and may not apply to all chips. Since there are many fields, 84 // this is spread across several DWORD registry keys. 85 // 86 // Type DWORD 87 // Encoding: 88 // DEFAULT RM determines 89 // COH Coherent system memory 90 // NCOH Non-coherent system memory 91 // VID Local video memory 92 // 93 #define NV_REG_STR_RM_INST_LOC "RMInstLoc" 94 #define NV_REG_STR_RM_INST_LOC_2 "RMInstLoc2" 95 #define NV_REG_STR_RM_INST_LOC_3 "RMInstLoc3" 96 #define NV_REG_STR_RM_INST_LOC_4 "RMInstLoc4" 97 98 #define NV_REG_STR_RM_INST_LOC_DEFAULT (0x00000000) 99 #define NV_REG_STR_RM_INST_LOC_COH (0x00000001) 100 #define NV_REG_STR_RM_INST_LOC_NCOH (0x00000002) 101 #define NV_REG_STR_RM_INST_LOC_VID (0x00000003) 102 103 #define NV_REG_STR_RM_INST_LOC_ALL_DEFAULT (0x00000000) 104 #define NV_REG_STR_RM_INST_LOC_ALL_COH (0x55555555) 105 #define NV_REG_STR_RM_INST_LOC_ALL_NCOH (0xAAAAAAAA) 106 #define NV_REG_STR_RM_INST_LOC_ALL_VID (0xFFFFFFFF) 107 108 // 109 // Allow instance memory overrides. Some fields are chip specific 110 // and may not apply to all chips. Since there are many fields, 111 // this is spread across several DWORD registry keys. 112 // 113 // The registry keys are defined in nvrm_registry. 114 // Specific overrrides are defined here. 115 // 116 // Type DWORD 117 // Encoding: 118 // DEFAULT RM determines 119 // COH Coherent system memory 120 // NCOH Non-coherent system memory 121 // VID Local video memory 122 // 123 #define NV_REG_STR_RM_INST_LOC_PTE 1:0 // Context PTE 124 #define NV_REG_STR_RM_INST_LOC_PTE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 125 #define NV_REG_STR_RM_INST_LOC_PTE_COH NV_REG_STR_RM_INST_LOC_COH 126 #define NV_REG_STR_RM_INST_LOC_PTE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 127 #define NV_REG_STR_RM_INST_LOC_PTE_VID NV_REG_STR_RM_INST_LOC_VID 128 #define NV_REG_STR_RM_INST_LOC_BAR_PTE 3:2 // BAR PTE 129 #define NV_REG_STR_RM_INST_LOC_BAR_PTE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 130 #define NV_REG_STR_RM_INST_LOC_BAR_PTE_COH NV_REG_STR_RM_INST_LOC_COH 131 #define NV_REG_STR_RM_INST_LOC_BAR_PTE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 132 #define NV_REG_STR_RM_INST_LOC_BAR_PTE_VID NV_REG_STR_RM_INST_LOC_VID 133 #define NV_REG_STR_RM_INST_LOC_INSTBLK 5:4 // Instance block 134 #define NV_REG_STR_RM_INST_LOC_INSTBLK_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 135 #define NV_REG_STR_RM_INST_LOC_INSTBLK_COH NV_REG_STR_RM_INST_LOC_COH 136 #define NV_REG_STR_RM_INST_LOC_INSTBLK_NCOH NV_REG_STR_RM_INST_LOC_NCOH 137 #define NV_REG_STR_RM_INST_LOC_INSTBLK_VID NV_REG_STR_RM_INST_LOC_VID 138 #define NV_REG_STR_RM_INST_LOC_RAMFC 7:6 // RAMFC save area 139 #define NV_REG_STR_RM_INST_LOC_RAMFC_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 140 #define NV_REG_STR_RM_INST_LOC_RAMFC_COH NV_REG_STR_RM_INST_LOC_COH 141 #define NV_REG_STR_RM_INST_LOC_RAMFC_NCOH NV_REG_STR_RM_INST_LOC_NCOH 142 #define NV_REG_STR_RM_INST_LOC_RAMFC_VID NV_REG_STR_RM_INST_LOC_VID 143 #define NV_REG_STR_RM_INST_LOC_CACHE1 9:8 // CACHE1 save area 144 #define NV_REG_STR_RM_INST_LOC_CACHE1_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 145 #define NV_REG_STR_RM_INST_LOC_CACHE1_COH NV_REG_STR_RM_INST_LOC_COH 146 #define NV_REG_STR_RM_INST_LOC_CACHE1_NCOH NV_REG_STR_RM_INST_LOC_NCOH 147 #define NV_REG_STR_RM_INST_LOC_CACHE1_VID NV_REG_STR_RM_INST_LOC_VID 148 #define NV_REG_STR_RM_INST_LOC_GRCTX 11:10 // Graphics contxt 149 #define NV_REG_STR_RM_INST_LOC_GRCTX_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 150 #define NV_REG_STR_RM_INST_LOC_GRCTX_COH NV_REG_STR_RM_INST_LOC_COH 151 #define NV_REG_STR_RM_INST_LOC_GRCTX_NCOH NV_REG_STR_RM_INST_LOC_NCOH 152 #define NV_REG_STR_RM_INST_LOC_GRCTX_VID NV_REG_STR_RM_INST_LOC_VID 153 #define NV_REG_STR_RM_INST_LOC_RUNLIST 13:12 // Runlist 154 #define NV_REG_STR_RM_INST_LOC_RUNLIST_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 155 #define NV_REG_STR_RM_INST_LOC_RUNLIST_COH NV_REG_STR_RM_INST_LOC_COH 156 #define NV_REG_STR_RM_INST_LOC_RUNLIST_NCOH NV_REG_STR_RM_INST_LOC_NCOH 157 #define NV_REG_STR_RM_INST_LOC_RUNLIST_VID NV_REG_STR_RM_INST_LOC_VID 158 #define NV_REG_STR_RM_INST_LOC_DISPLAY 15:14 // Display 159 #define NV_REG_STR_RM_INST_LOC_DISPLAY_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 160 #define NV_REG_STR_RM_INST_LOC_DISPLAY_COH NV_REG_STR_RM_INST_LOC_COH 161 #define NV_REG_STR_RM_INST_LOC_DISPLAY_NCOH NV_REG_STR_RM_INST_LOC_NCOH 162 #define NV_REG_STR_RM_INST_LOC_DISPLAY_VID NV_REG_STR_RM_INST_LOC_VID 163 #define NV_REG_STR_RM_INST_LOC_USERD 17:16 // USERD 164 #define NV_REG_STR_RM_INST_LOC_USERD_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 165 #define NV_REG_STR_RM_INST_LOC_USERD_COH NV_REG_STR_RM_INST_LOC_COH 166 #define NV_REG_STR_RM_INST_LOC_USERD_NCOH NV_REG_STR_RM_INST_LOC_NCOH 167 #define NV_REG_STR_RM_INST_LOC_USERD_VID NV_REG_STR_RM_INST_LOC_VID 168 #define NV_REG_STR_RM_INST_LOC_EVENTBUFFER 19:18 // EVENTBUFFER 169 #define NV_REG_STR_RM_INST_LOC_EVENTBUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 170 #define NV_REG_STR_RM_INST_LOC_EVENTBUFFER_COH NV_REG_STR_RM_INST_LOC_COH 171 #define NV_REG_STR_RM_INST_LOC_EVENTBUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 172 #define NV_REG_STR_RM_INST_LOC_EVENTBUFFER_VID NV_REG_STR_RM_INST_LOC_VID 173 #define NV_REG_STR_RM_INST_LOC_UNUSED 21:20 // UNUSED 174 #define NV_REG_STR_RM_INST_LOC_UNUSED_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 175 #define NV_REG_STR_RM_INST_LOC_CIPHER_XCHG 23:22 // Cipher exchange memory resources 176 #define NV_REG_STR_RM_INST_LOC_CIPHER_XCHG_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 177 #define NV_REG_STR_RM_INST_LOC_CIPHER_XCHG_COH NV_REG_STR_RM_INST_LOC_COH 178 #define NV_REG_STR_RM_INST_LOC_CIPHER_XCHG_NCOH NV_REG_STR_RM_INST_LOC_NCOH 179 #define NV_REG_STR_RM_INST_LOC_CIPHER_XCHG_VID NV_REG_STR_RM_INST_LOC_VID 180 #define NV_REG_STR_RM_INST_LOC_PDE 25:24 // Context PDE 181 #define NV_REG_STR_RM_INST_LOC_PDE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 182 #define NV_REG_STR_RM_INST_LOC_PDE_COH NV_REG_STR_RM_INST_LOC_COH 183 #define NV_REG_STR_RM_INST_LOC_PDE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 184 #define NV_REG_STR_RM_INST_LOC_PDE_VID NV_REG_STR_RM_INST_LOC_VID 185 #define NV_REG_STR_RM_INST_LOC_BAR_PDE 27:26 // BAR PDE 186 #define NV_REG_STR_RM_INST_LOC_BAR_PDE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 187 #define NV_REG_STR_RM_INST_LOC_BAR_PDE_COH NV_REG_STR_RM_INST_LOC_COH 188 #define NV_REG_STR_RM_INST_LOC_BAR_PDE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 189 #define NV_REG_STR_RM_INST_LOC_BAR_PDE_VID NV_REG_STR_RM_INST_LOC_VID 190 #define NV_REG_STR_RM_INST_LOC_PMUINST 29:28 // PMUINST 191 #define NV_REG_STR_RM_INST_LOC_PMUINST_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 192 #define NV_REG_STR_RM_INST_LOC_PMUINST_COH NV_REG_STR_RM_INST_LOC_COH 193 #define NV_REG_STR_RM_INST_LOC_PMUINST_NCOH NV_REG_STR_RM_INST_LOC_NCOH 194 #define NV_REG_STR_RM_INST_LOC_PMUINST_VID NV_REG_STR_RM_INST_LOC_VID 195 #define NV_REG_STR_RM_INST_LOC_PMUUCODE 31:30 // PMU UCODE 196 #define NV_REG_STR_RM_INST_LOC_PMUUCODE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 197 #define NV_REG_STR_RM_INST_LOC_PMUUCODE_COH NV_REG_STR_RM_INST_LOC_COH 198 #define NV_REG_STR_RM_INST_LOC_PMUUCODE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 199 #define NV_REG_STR_RM_INST_LOC_PMUUCODE_VID NV_REG_STR_RM_INST_LOC_VID 200 201 #define NV_REG_STR_RM_INST_LOC_2_COMPTAG_STORE 1:0 // Compbit backing store 202 #define NV_REG_STR_RM_INST_LOC_2_COMPTAG_STORE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 203 #define NV_REG_STR_RM_INST_LOC_2_COMPTAG_STORE_COH NV_REG_STR_RM_INST_LOC_COH 204 #define NV_REG_STR_RM_INST_LOC_2_COMPTAG_STORE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 205 #define NV_REG_STR_RM_INST_LOC_2_COMPTAG_STORE_VID NV_REG_STR_RM_INST_LOC_VID 206 #define NV_REG_STR_RM_INST_LOC_2_ATTR_CB 3:2 // Attribute Circular Buffer 207 #define NV_REG_STR_RM_INST_LOC_2_ATTR_CB_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 208 #define NV_REG_STR_RM_INST_LOC_2_ATTR_CB_COH NV_REG_STR_RM_INST_LOC_COH 209 #define NV_REG_STR_RM_INST_LOC_2_ATTR_CB_NCOH NV_REG_STR_RM_INST_LOC_NCOH 210 #define NV_REG_STR_RM_INST_LOC_2_ATTR_CB_VID NV_REG_STR_RM_INST_LOC_VID 211 #define NV_REG_STR_RM_INST_LOC_2_BUNDLE_CB 5:4 // Bundle Circular Buffer 212 #define NV_REG_STR_RM_INST_LOC_2_BUNDLE_CB_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 213 #define NV_REG_STR_RM_INST_LOC_2_BUNDLE_CB_COH NV_REG_STR_RM_INST_LOC_COH 214 #define NV_REG_STR_RM_INST_LOC_2_BUNDLE_CB_NCOH NV_REG_STR_RM_INST_LOC_NCOH 215 #define NV_REG_STR_RM_INST_LOC_2_BUNDLE_CB_VID NV_REG_STR_RM_INST_LOC_VID 216 #define NV_REG_STR_RM_INST_LOC_2_PAGEPOOL 7:6 // Pagepool Buffer 217 #define NV_REG_STR_RM_INST_LOC_2_PAGEPOOL_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 218 #define NV_REG_STR_RM_INST_LOC_2_PAGEPOOL_COH NV_REG_STR_RM_INST_LOC_COH 219 #define NV_REG_STR_RM_INST_LOC_2_PAGEPOOL_NCOH NV_REG_STR_RM_INST_LOC_NCOH 220 #define NV_REG_STR_RM_INST_LOC_2_PAGEPOOL_VID NV_REG_STR_RM_INST_LOC_VID 221 #define NV_REG_STR_RM_INST_LOC_2_GOLD_CTX 9:8 // Golden Context Image 222 #define NV_REG_STR_RM_INST_LOC_2_GOLD_CTX_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 223 #define NV_REG_STR_RM_INST_LOC_2_GOLD_CTX_COH NV_REG_STR_RM_INST_LOC_COH 224 #define NV_REG_STR_RM_INST_LOC_2_GOLD_CTX_NCOH NV_REG_STR_RM_INST_LOC_NCOH 225 #define NV_REG_STR_RM_INST_LOC_2_GOLD_CTX_VID NV_REG_STR_RM_INST_LOC_VID 226 #define NV_REG_STR_RM_INST_LOC_2_BAR_CTX 11:10 // Bar context aperture 227 #define NV_REG_STR_RM_INST_LOC_2_BAR_CTX_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 228 #define NV_REG_STR_RM_INST_LOC_2_BAR_CTX_COH NV_REG_STR_RM_INST_LOC_COH 229 #define NV_REG_STR_RM_INST_LOC_2_BAR_CTX_NCOH NV_REG_STR_RM_INST_LOC_NCOH 230 #define NV_REG_STR_RM_INST_LOC_2_BAR_CTX_VID NV_REG_STR_RM_INST_LOC_VID 231 #define NV_REG_STR_RM_INST_LOC_2_PMU_PWR_RAIL_VIDEO_PRED_BUFFER_SURFACE 13:12 // Power Rail Video Prediction 232 #define NV_REG_STR_RM_INST_LOC_2_PMU_PWR_RAIL_VIDEO_PRED_BUFFER_SURFACE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 233 #define NV_REG_STR_RM_INST_LOC_2_PMU_PWR_RAIL_VIDEO_PRED_BUFFER_SURFACE_COH NV_REG_STR_RM_INST_LOC_COH 234 #define NV_REG_STR_RM_INST_LOC_2_PMU_PWR_RAIL_VIDEO_PRED_BUFFER_SURFACE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 235 #define NV_REG_STR_RM_INST_LOC_2_PMU_PWR_RAIL_VIDEO_PRED_BUFFER_SURFACE_VID NV_REG_STR_RM_INST_LOC_VID 236 #define NV_REG_STR_RM_INST_LOC_2_CTX_PATCH 15:14 // context patch 237 #define NV_REG_STR_RM_INST_LOC_2_CTX_PATCH_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 238 #define NV_REG_STR_RM_INST_LOC_2_CTX_PATCH_COH NV_REG_STR_RM_INST_LOC_COH 239 #define NV_REG_STR_RM_INST_LOC_2_CTX_PATCH_NCOH NV_REG_STR_RM_INST_LOC_NCOH 240 #define NV_REG_STR_RM_INST_LOC_2_CTX_PATCH_VID NV_REG_STR_RM_INST_LOC_VID 241 #define NV_REG_STR_RM_INST_LOC_2_MMU_READ 17:16 // MMU Read 242 #define NV_REG_STR_RM_INST_LOC_2_MMU_READ_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 243 #define NV_REG_STR_RM_INST_LOC_2_MMU_READ_COH NV_REG_STR_RM_INST_LOC_COH 244 #define NV_REG_STR_RM_INST_LOC_2_MMU_READ_NCOH NV_REG_STR_RM_INST_LOC_NCOH 245 #define NV_REG_STR_RM_INST_LOC_2_MMU_READ_VID NV_REG_STR_RM_INST_LOC_VID 246 #define NV_REG_STR_RM_INST_LOC_2_MMU_WRITE 19:18 // MMU Write 247 #define NV_REG_STR_RM_INST_LOC_2_MMU_WRITE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 248 #define NV_REG_STR_RM_INST_LOC_2_MMU_WRITE_COH NV_REG_STR_RM_INST_LOC_COH 249 #define NV_REG_STR_RM_INST_LOC_2_MMU_WRITE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 250 #define NV_REG_STR_RM_INST_LOC_2_MMU_WRITE_VID NV_REG_STR_RM_INST_LOC_VID 251 #define NV_REG_STR_RM_INST_LOC_2_UNUSED 21:20 // Unused 252 #define NV_REG_STR_RM_INST_LOC_2_ZCULLCTX 23:22 // zcull context buffer 253 #define NV_REG_STR_RM_INST_LOC_2_ZCULLCTX_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 254 #define NV_REG_STR_RM_INST_LOC_2_ZCULLCTX_COH NV_REG_STR_RM_INST_LOC_COH 255 #define NV_REG_STR_RM_INST_LOC_2_ZCULLCTX_NCOH NV_REG_STR_RM_INST_LOC_NCOH 256 #define NV_REG_STR_RM_INST_LOC_2_ZCULLCTX_VID NV_REG_STR_RM_INST_LOC_VID 257 #define NV_REG_STR_RM_INST_LOC_2_PMCTX 25:24 // PM context buffer 258 #define NV_REG_STR_RM_INST_LOC_2_PMCTX_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 259 #define NV_REG_STR_RM_INST_LOC_2_PMCTX_COH NV_REG_STR_RM_INST_LOC_COH 260 #define NV_REG_STR_RM_INST_LOC_2_PMCTX_NCOH NV_REG_STR_RM_INST_LOC_NCOH 261 #define NV_REG_STR_RM_INST_LOC_2_PMCTX_VID NV_REG_STR_RM_INST_LOC_VID 262 #define NV_REG_STR_RM_INST_LOC_2_DPUDBG 27:26 // DPU Debug/Falctrace Buffer 263 #define NV_REG_STR_RM_INST_LOC_2_DPUDBG_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 264 #define NV_REG_STR_RM_INST_LOC_2_DPUDBG_COH NV_REG_STR_RM_INST_LOC_COH 265 #define NV_REG_STR_RM_INST_LOC_2_DPUDBG_NCOH NV_REG_STR_RM_INST_LOC_NCOH 266 #define NV_REG_STR_RM_INST_LOC_2_DPUDBG_VID NV_REG_STR_RM_INST_LOC_VID 267 #define NV_REG_STR_RM_INST_LOC_2_PMUPG 29:28 // PMU PG buffer 268 #define NV_REG_STR_RM_INST_LOC_2_PMUPG_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 269 #define NV_REG_STR_RM_INST_LOC_2_PMUPG_COH NV_REG_STR_RM_INST_LOC_COH 270 #define NV_REG_STR_RM_INST_LOC_2_PMUPG_NCOH NV_REG_STR_RM_INST_LOC_NCOH 271 #define NV_REG_STR_RM_INST_LOC_2_PMUPG_VID NV_REG_STR_RM_INST_LOC_VID 272 // 273 // Note: on Blackwell-and-later, the location of the PMU_LOGGER cannot be 274 // independently controlled. If the regkey is set and the PMU_LOGGER is not 275 // already being placed in the specified surface, the driver will fail to load. 276 // 277 #define NV_REG_STR_RM_INST_LOC_2_PMU_LOGGER 31:30 278 #define NV_REG_STR_RM_INST_LOC_2_PMU_LOGGER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 279 #define NV_REG_STR_RM_INST_LOC_2_PMU_LOGGER_COH NV_REG_STR_RM_INST_LOC_COH 280 #define NV_REG_STR_RM_INST_LOC_2_PMU_LOGGER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 281 #define NV_REG_STR_RM_INST_LOC_2_PMU_LOGGER_VID NV_REG_STR_RM_INST_LOC_VID 282 283 #define NV_REG_STR_RM_INST_LOC_3_PG_LOG_SURFACE 1:0 // PG log surface 284 #define NV_REG_STR_RM_INST_LOC_3_PG_LOG_SURFACE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 285 #define NV_REG_STR_RM_INST_LOC_3_PG_LOG_SURFACE_COH NV_REG_STR_RM_INST_LOC_COH 286 #define NV_REG_STR_RM_INST_LOC_3_PG_LOG_SURFACE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 287 #define NV_REG_STR_RM_INST_LOC_3_PG_LOG_SURFACE_VID NV_REG_STR_RM_INST_LOC_VID 288 #define NV_REG_STR_RM_INST_LOC_3_PREEMPT_BUFFER 3:2 // Preemption buffer 289 #define NV_REG_STR_RM_INST_LOC_3_PREEMPT_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 290 #define NV_REG_STR_RM_INST_LOC_3_PREEMPT_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 291 #define NV_REG_STR_RM_INST_LOC_3_PREEMPT_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 292 #define NV_REG_STR_RM_INST_LOC_3_PREEMPT_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 293 #define NV_REG_STR_RM_INST_LOC_3_GFXP_BETACB_BUFFER 5:4 // GFXP BetaCB buffer 294 #define NV_REG_STR_RM_INST_LOC_3_GFXP_BETACB_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 295 #define NV_REG_STR_RM_INST_LOC_3_GFXP_BETACB_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 296 #define NV_REG_STR_RM_INST_LOC_3_GFXP_BETACB_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 297 #define NV_REG_STR_RM_INST_LOC_3_GFXP_BETACB_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 298 #define NV_REG_STR_RM_INST_LOC_3_GFXP_PAGEPOOL_BUFFER 7:6 // GFXP Pagepool buffer 299 #define NV_REG_STR_RM_INST_LOC_3_GFXP_PAGEPOOL_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 300 #define NV_REG_STR_RM_INST_LOC_3_GFXP_PAGEPOOL_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 301 #define NV_REG_STR_RM_INST_LOC_3_GFXP_PAGEPOOL_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 302 #define NV_REG_STR_RM_INST_LOC_3_GFXP_PAGEPOOL_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 303 #define NV_REG_STR_RM_INST_LOC_3_BSI_IMAGE 9:8 // BSI RAM image 304 #define NV_REG_STR_RM_INST_LOC_3_BSI_IMAGE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 305 #define NV_REG_STR_RM_INST_LOC_3_BSI_IMAGE_COH NV_REG_STR_RM_INST_LOC_COH 306 #define NV_REG_STR_RM_INST_LOC_3_BSI_IMAGE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 307 #define NV_REG_STR_RM_INST_LOC_3_BSI_IMAGE_VID NV_REG_STR_RM_INST_LOC_VID 308 #define NV_REG_STR_RM_INST_LOC_3_PRIV_ACCESS_MAP 11:10 // Priv whitelist buffer 309 #define NV_REG_STR_RM_INST_LOC_3_PRIV_ACCESS_MAP_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 310 #define NV_REG_STR_RM_INST_LOC_3_PRIV_ACCESS_MAP_COH NV_REG_STR_RM_INST_LOC_COH 311 #define NV_REG_STR_RM_INST_LOC_3_PRIV_ACCESS_MAP_NCOH NV_REG_STR_RM_INST_LOC_NCOH 312 #define NV_REG_STR_RM_INST_LOC_3_PRIV_ACCESS_MAP_VID NV_REG_STR_RM_INST_LOC_VID 313 #define NV_REG_STR_RM_INST_LOC_3_SEC2DBG 13:12 // SEC2 Debug/Falctrace Buffer 314 #define NV_REG_STR_RM_INST_LOC_3_SEC2DBG_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 315 #define NV_REG_STR_RM_INST_LOC_3_SEC2DBG_COH NV_REG_STR_RM_INST_LOC_COH 316 #define NV_REG_STR_RM_INST_LOC_3_SEC2DBG_NCOH NV_REG_STR_RM_INST_LOC_NCOH 317 #define NV_REG_STR_RM_INST_LOC_3_SEC2DBG_VID NV_REG_STR_RM_INST_LOC_VID 318 #define NV_REG_STR_RM_INST_LOC_3_FECS_UCODE 15:14 // FECS UCODE 319 #define NV_REG_STR_RM_INST_LOC_3_FECS_UCODE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 320 #define NV_REG_STR_RM_INST_LOC_3_FECS_UCODE_COH NV_REG_STR_RM_INST_LOC_COH 321 #define NV_REG_STR_RM_INST_LOC_3_FECS_UCODE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 322 #define NV_REG_STR_RM_INST_LOC_3_FECS_UCODE_VID NV_REG_STR_RM_INST_LOC_VID 323 #define NV_REG_STR_RM_INST_LOC_3_GFXP_SPILL_BUFFER 17:16 // GFXP Pagepool buffer 324 #define NV_REG_STR_RM_INST_LOC_3_GFXP_SPILL_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 325 #define NV_REG_STR_RM_INST_LOC_3_GFXP_SPILL_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 326 #define NV_REG_STR_RM_INST_LOC_3_GFXP_SPILL_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 327 #define NV_REG_STR_RM_INST_LOC_3_GFXP_SPILL_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 328 #define NV_REG_STR_RM_INST_LOC_3_UVM_FAULT_BUFFER_NONREPLAYABLE 19:18 // UVM Non-Replayable fault buffer 329 #define NV_REG_STR_RM_INST_LOC_3_UVM_FAULT_BUFFER_NONREPLAYABLE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 330 #define NV_REG_STR_RM_INST_LOC_3_UVM_FAULT_BUFFER_NONREPLAYABLE_COH NV_REG_STR_RM_INST_LOC_COH 331 #define NV_REG_STR_RM_INST_LOC_3_UVM_FAULT_BUFFER_NONREPLAYABLE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 332 #define NV_REG_STR_RM_INST_LOC_3_UVM_FAULT_BUFFER_NONREPLAYABLE_VID NV_REG_STR_RM_INST_LOC_VID 333 #define NV_REG_STR_RM_INST_LOC_3_BAR_SCRATCH_PAGE 21:20 // BAR scratch pages 334 #define NV_REG_STR_RM_INST_LOC_3_BAR_SCRATCH_PAGE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 335 #define NV_REG_STR_RM_INST_LOC_3_BAR_SCRATCH_PAGE_COH NV_REG_STR_RM_INST_LOC_COH 336 #define NV_REG_STR_RM_INST_LOC_3_BAR_SCRATCH_PAGE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 337 #define NV_REG_STR_RM_INST_LOC_3_BAR_SCRATCH_PAGE_VID NV_REG_STR_RM_INST_LOC_VID 338 #define NV_REG_STR_RM_INST_LOC_3_FLCNINST 23:22 // FLCNINST 339 #define NV_REG_STR_RM_INST_LOC_3_FLCNINST_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 340 #define NV_REG_STR_RM_INST_LOC_3_FLCNINST_COH NV_REG_STR_RM_INST_LOC_COH 341 #define NV_REG_STR_RM_INST_LOC_3_FLCNINST_NCOH NV_REG_STR_RM_INST_LOC_NCOH 342 #define NV_REG_STR_RM_INST_LOC_3_FLCNINST_VID NV_REG_STR_RM_INST_LOC_VID 343 #define NV_REG_STR_RM_INST_LOC_3_RTVCB_BUFFER 25:24 // RTVCB buffer 344 #define NV_REG_STR_RM_INST_LOC_3_RTVCB_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 345 #define NV_REG_STR_RM_INST_LOC_3_RTVCB_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 346 #define NV_REG_STR_RM_INST_LOC_3_RTVCB_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 347 #define NV_REG_STR_RM_INST_LOC_3_RTVCB_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 348 #define NV_REG_STR_RM_INST_LOC_3_GFXP_RTVCB_BUFFER 27:26 // GFXP RTVCB buffer 349 #define NV_REG_STR_RM_INST_LOC_3_GFXP_RTVCB_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 350 #define NV_REG_STR_RM_INST_LOC_3_GFXP_RTVCB_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 351 #define NV_REG_STR_RM_INST_LOC_3_GFXP_RTVCB_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 352 #define NV_REG_STR_RM_INST_LOC_3_GFXP_RTVCB_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 353 #define NV_REG_STR_RM_INST_LOC_3_FAULT_METHOD_BUFFER 29:28 // Fault method buffer 354 #define NV_REG_STR_RM_INST_LOC_3_FAULT_METHOD_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 355 #define NV_REG_STR_RM_INST_LOC_3_FAULT_METHOD_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 356 #define NV_REG_STR_RM_INST_LOC_3_FAULT_METHOD_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 357 #define NV_REG_STR_RM_INST_LOC_3_FAULT_METHOD_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 358 #define NV_REG_STR_RM_INST_LOC_3_PMU_DPU_DMA 31:30 // PMU/DPU DMA transfers 359 #define NV_REG_STR_RM_INST_LOC_3_PMU_DPU_DMA_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 360 #define NV_REG_STR_RM_INST_LOC_3_PMU_DPU_DMA_COH NV_REG_STR_RM_INST_LOC_COH 361 #define NV_REG_STR_RM_INST_LOC_3_PMU_DPU_DMA_NCOH NV_REG_STR_RM_INST_LOC_NCOH 362 #define NV_REG_STR_RM_INST_LOC_3_PMU_DPU_DMA_VID NV_REG_STR_RM_INST_LOC_VID 363 364 #define NV_REG_STR_RM_INST_LOC_4_DISP_SC 1:0 // Display state cache buffer 365 #define NV_REG_STR_RM_INST_LOC_4_DISP_SC_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 366 #define NV_REG_STR_RM_INST_LOC_4_DISP_SC_COH NV_REG_STR_RM_INST_LOC_COH 367 #define NV_REG_STR_RM_INST_LOC_4_DISP_SC_NCOH NV_REG_STR_RM_INST_LOC_NCOH 368 #define NV_REG_STR_RM_INST_LOC_4_DISP_SC_VID NV_REG_STR_RM_INST_LOC_VID 369 #define NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER 3:2 // FIFO channel push buffer 370 #define NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 371 #define NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_COH NV_REG_STR_RM_INST_LOC_COH 372 #define NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 373 #define NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_VID NV_REG_STR_RM_INST_LOC_VID 374 #define NV_REG_STR_RM_INST_LOC_4_FW_SEC_LIC_COMMAND 5:4 // Firmware security license command 375 #define NV_REG_STR_RM_INST_LOC_4_FW_SEC_LIC_COMMAND_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 376 #define NV_REG_STR_RM_INST_LOC_4_FW_SEC_LIC_COMMAND_COH NV_REG_STR_RM_INST_LOC_COH 377 #define NV_REG_STR_RM_INST_LOC_4_FW_SEC_LIC_COMMAND_NCOH NV_REG_STR_RM_INST_LOC_NCOH 378 #define NV_REG_STR_RM_INST_LOC_4_FW_SEC_LIC_COMMAND_VID NV_REG_STR_RM_INST_LOC_VID 379 #define NV_REG_STR_RM_INST_LOC_4_VRDS 7:6 // VBIOS runtime data security 380 #define NV_REG_STR_RM_INST_LOC_4_VRDS_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 381 #define NV_REG_STR_RM_INST_LOC_4_VRDS_COH NV_REG_STR_RM_INST_LOC_COH 382 #define NV_REG_STR_RM_INST_LOC_4_VRDS_NCOH NV_REG_STR_RM_INST_LOC_NCOH 383 #define NV_REG_STR_RM_INST_LOC_4_VRDS_VID NV_REG_STR_RM_INST_LOC_VID 384 #define NV_REG_STR_RM_INST_LOC_4_FLCN_UCODE_BUFFERS 9:8 // Falcon uCode buffers 385 #define NV_REG_STR_RM_INST_LOC_4_FLCN_UCODE_BUFFERS_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 386 #define NV_REG_STR_RM_INST_LOC_4_FLCN_UCODE_BUFFERS_COH NV_REG_STR_RM_INST_LOC_COH 387 #define NV_REG_STR_RM_INST_LOC_4_FLCN_UCODE_BUFFERS_NCOH NV_REG_STR_RM_INST_LOC_NCOH 388 #define NV_REG_STR_RM_INST_LOC_4_FLCN_UCODE_BUFFERS_VID NV_REG_STR_RM_INST_LOC_VID 389 #define NV_REG_STR_RM_INST_LOC_4_UVM_FAULT_BUFFER_REPLAYABLE 11:10 // UVM Replayable fault buffer 390 #define NV_REG_STR_RM_INST_LOC_4_UVM_FAULT_BUFFER_REPLAYABLE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 391 #define NV_REG_STR_RM_INST_LOC_4_UVM_FAULT_BUFFER_REPLAYABLE_COH NV_REG_STR_RM_INST_LOC_COH 392 #define NV_REG_STR_RM_INST_LOC_4_UVM_FAULT_BUFFER_REPLAYABLE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 393 #define NV_REG_STR_RM_INST_LOC_4_UVM_FAULT_BUFFER_REPLAYABLE_VID NV_REG_STR_RM_INST_LOC_VID 394 395 // 396 // Separately define instance block location of BARs. Default Setting 397 // reverts to NV_REG_STR_RM_INST_LOC_INSTBLK 398 // 399 #define NV_REG_STR_RM_INST_LOC_4_BAR 13:12 // BAR Bind location 400 #define NV_REG_STR_RM_INST_LOC_4_BAR_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 401 #define NV_REG_STR_RM_INST_LOC_4_BAR_COH NV_REG_STR_RM_INST_LOC_COH 402 #define NV_REG_STR_RM_INST_LOC_4_BAR_NCOH NV_REG_STR_RM_INST_LOC_NCOH 403 #define NV_REG_STR_RM_INST_LOC_4_BAR_VID NV_REG_STR_RM_INST_LOC_VID 404 405 // 406 // Separately define instance block location of async CEs. Default Setting 407 // reverts to NV_REG_STR_RM_INST_LOC_INSTBLK 408 // 409 #define NV_REG_STR_RM_INST_LOC_4_CE 15:14 // Async CE Bind location 410 #define NV_REG_STR_RM_INST_LOC_4_CE_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 411 #define NV_REG_STR_RM_INST_LOC_4_CE_COH NV_REG_STR_RM_INST_LOC_COH 412 #define NV_REG_STR_RM_INST_LOC_4_CE_NCOH NV_REG_STR_RM_INST_LOC_NCOH 413 #define NV_REG_STR_RM_INST_LOC_4_CE_VID NV_REG_STR_RM_INST_LOC_VID 414 415 // 416 // Separately define instance block location of GR/GRCE. Default Setting 417 // reverts to NV_REG_STR_RM_INST_LOC_INSTBLK 418 // 419 #define NV_REG_STR_RM_INST_LOC_4_GR 17:16 // GR/GRCE Bind location 420 #define NV_REG_STR_RM_INST_LOC_4_GR_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 421 #define NV_REG_STR_RM_INST_LOC_4_GR_COH NV_REG_STR_RM_INST_LOC_COH 422 #define NV_REG_STR_RM_INST_LOC_4_GR_NCOH NV_REG_STR_RM_INST_LOC_NCOH 423 #define NV_REG_STR_RM_INST_LOC_4_GR_VID NV_REG_STR_RM_INST_LOC_VID 424 425 // 426 // Separately define instance block location of VEs. Default Setting 427 // reverts to NV_REG_STR_RM_INST_LOC_INSTBLK 428 // 429 #define NV_REG_STR_RM_INST_LOC_4_FALCON 19:18 // FALCON Bind location 430 #define NV_REG_STR_RM_INST_LOC_4_FALCON_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 431 #define NV_REG_STR_RM_INST_LOC_4_FALCON_COH NV_REG_STR_RM_INST_LOC_COH 432 #define NV_REG_STR_RM_INST_LOC_4_FALCON_NCOH NV_REG_STR_RM_INST_LOC_NCOH 433 #define NV_REG_STR_RM_INST_LOC_4_FALCON_VID NV_REG_STR_RM_INST_LOC_VID 434 435 // 436 // Separately define instance block location of HWPM PMA. Default Setting 437 // reverts to NV_REG_STR_RM_INST_LOC_INSTBLK 438 // 439 #define NV_REG_STR_RM_INST_LOC_4_HWPM_PMA 21:20 // HWPM PMA Bind location 440 #define NV_REG_STR_RM_INST_LOC_4_HWPM_PMA_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 441 #define NV_REG_STR_RM_INST_LOC_4_HWPM_PMA_COH NV_REG_STR_RM_INST_LOC_COH 442 #define NV_REG_STR_RM_INST_LOC_4_HWPM_PMA_NCOH NV_REG_STR_RM_INST_LOC_NCOH 443 #define NV_REG_STR_RM_INST_LOC_4_HWPM_PMA_VID NV_REG_STR_RM_INST_LOC_VID 444 445 // 446 // Separately define instance block location of HWPM PMA. Default Setting 447 // reverts to NV_REG_STR_RM_INST_LOC_INSTBLK 448 // 449 #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF 23:22 // FECS EVENT buffer location 450 #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 451 #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF_COH NV_REG_STR_RM_INST_LOC_COH 452 #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF_NCOH NV_REG_STR_RM_INST_LOC_NCOH 453 #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF_VID NV_REG_STR_RM_INST_LOC_VID 454 455 // 456 // Overrides for the GFXP SETUP buffer 457 // 458 #define NV_REG_STR_RM_INST_LOC_4_GFXP_SETUP_BUFFER 25:24 // GFXP SETUP buffer 459 #define NV_REG_STR_RM_INST_LOC_4_GFXP_SETUP_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 460 #define NV_REG_STR_RM_INST_LOC_4_GFXP_SETUP_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH 461 #define NV_REG_STR_RM_INST_LOC_4_GFXP_SETUP_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH 462 #define NV_REG_STR_RM_INST_LOC_4_GFXP_SETUP_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID 463 464 // 465 // Overrides for the VIDEO ENGINE BOOTARGS buffer 466 // 467 #define NV_REG_STR_RM_INST_LOC_4_VIDEO_ENGINE_BOOTARGS 27:26 // VIDEO_ENGINE BOOTARGS buffer 468 #define NV_REG_STR_RM_INST_LOC_4_VIDEO_ENGINE_BOOTARGS_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT 469 #define NV_REG_STR_RM_INST_LOC_4_VIDEO_ENGINE_BOOTARGS_COH NV_REG_STR_RM_INST_LOC_COH 470 #define NV_REG_STR_RM_INST_LOC_4_VIDEO_ENGINE_BOOTARGS_NCOH NV_REG_STR_RM_INST_LOC_NCOH 471 #define NV_REG_STR_RM_INST_LOC_4_VIDEO_ENGINE_BOOTARGS_VID NV_REG_STR_RM_INST_LOC_VID 472 473 #define NV_REG_STR_RM_GSP_STATUS_QUEUE_SIZE "RmGspStatusQueueSize" 474 // TYPE DWORD 475 // Set the GSP status queue size in KB (for GSP to CPU RPC status and event communication) 476 477 #define NV_REG_STR_RM_MSG "RmMsg" 478 // Type String: Set parameters for RM DBG_PRINTF. Only for builds with printfs enabled. 479 // Encoding: 480 // rule = [!][filename|function][:startline][-endline] 481 // Format = rule[,rule] 482 483 484 #define NV_REG_STR_RM_THREAD_STATE_SETUP_FLAGS "RmThreadStateSetupFlags" 485 // Type DWORD 486 // Enables or disables various ThreadState features 487 // See resman/inc/kernel/core/thread_state.h for 488 // THREAD_STATE_SETUP_FLAGS values. 489 490 491 #define NV_REG_STR_RM_ENABLE_EVENT_TRACER "RMEnableEventTracer" 492 #define NV_REG_STR_RM_ENABLE_EVENT_TRACER_DISABLE 0 493 #define NV_REG_STR_RM_ENABLE_EVENT_TRACER_ENABLE 1 494 #define NV_REG_STR_RM_ENABLE_EVENT_TRACER_DEFAULT NV_REG_STR_RM_ENABLE_EVENT_TRACER_DISABLE 495 // Type DWORD 496 // Encoding boolean 497 // Enable/Disable RM event tracing 498 // 0 - Disable RM event tracing 499 // 1 - Enable RM event tracing 500 501 502 #define NV_REG_STR_RM_COMPUTE_MODE_RULES "RmComputeModeRules" 503 // Type DWORD 504 // Saves the last compute mode rule set by the client. 505 // Encoding: 506 // Bits 31:0 : Last compute mode rule set by the client 507 508 #define NV_REG_STR_ILLUM_ATTRIB_LOGO_BRIGHTNESS "RmIllumLogoBrightness" 509 // Type DWORD: 510 // contains Logo Illumination Brightness in percent to be used on driver load. 511 512 #define NV_REG_STR_ILLUM_ATTRIB_SLI_BRIGHTNESS "RmIllumSLIBrightness" 513 // Type DWORD: 514 // contains SLI Illumination Brightness in percent to be used on driver load. 515 516 517 #define NV_REG_STR_RM_NVLOG_EXTRA_BUFFER_1 "RMNvLogExtraBuffer1" 518 // #define NV_REG_STR_RM_NVLOG_EXTRA_BUFFER_2 "RMNvLogExtraBuffer2" 519 // #define NV_REG_STR_RM_NVLOG_EXTRA_BUFFER_3 "RMNvLogExtraBuffer3" 520 // #define NV_REG_STR_RM_NVLOG_EXTRA_BUFFER_4 "RMNvLogExtraBuffer4" 521 // #define NV_REG_STR_RM_NVLOG_EXTRA_BUFFER_5 "RMNvLogExtraBuffer5" 522 // #define NV_REG_STR_RM_NVLOG_EXTRA_BUFFER_6 "RMNvLogExtraBuffer6" 523 // Type DWORD 524 // Used to specify up to 6 additional logging buffers 525 // Encoding: 526 // _BUFFER_FLAGS 527 // x: uses NVLOG_BUFFER_FLAGS fields, for main nvlog buffer 528 // _BUFFER_SIZE 529 // n: Size of main buffer, in kilobytes 530 531 532 // Type DWORD 533 // This can be used for dumping NvLog buffers (in /var/log/vmkernel.log ), when 534 // we hit critical XIDs e.g 31/79. 535 #define NV_REG_STR_RM_DUMP_NVLOG "RMDumpNvLog" 536 #define NV_REG_STR_RM_DUMP_NVLOG_DEFAULT (0x00000000) 537 #define NV_REG_STR_RM_DUMP_NVLOG_DISABLE (0x00000000) 538 #define NV_REG_STR_RM_DUMP_NVLOG_ENABLE (0x00000001) 539 540 541 // 542 // Type DWORD 543 // RM external fabric management. 544 // 545 // RM currently uses nvlink core driver APIs which internally trigger 546 // link initialization and training. However, nvlink core driver now exposes a 547 // set of APIs for managing nvlink fabric externally (from user mode). 548 // 549 // When the regkey is enabled, RM will skip use of APIs which trigger 550 // link initialization and training. In that case, link training needs to be 551 // triggered externally. 552 // 553 #define NV_REG_STR_RM_EXTERNAL_FABRIC_MGMT "RMExternalFabricMgmt" 554 #define NV_REG_STR_RM_EXTERNAL_FABRIC_MGMT_MODE 0:0 555 #define NV_REG_STR_RM_EXTERNAL_FABRIC_MGMT_MODE_ENABLE (0x00000001) 556 #define NV_REG_STR_RM_EXTERNAL_FABRIC_MGMT_MODE_DISABLE (0x00000000) 557 558 559 // 560 // Type DWORD 561 // BIT 1:0: All Data validation 562 // 0 - Default 563 // 1 - Validate the kernel data - enable all below 564 // 2 - Do not validate the kernel data - disable all below 565 // BIT 3:2: Buffer validation 566 // 0 - Default 567 // 1 - Validate the kernel buffers 568 // 2 - Do not validate the kernel buffers 569 // BIT 5:4: Handle validation 570 // 0 - Default 571 // 1 - Validate the handles 572 // 2 - Do not validate the handles 573 // BIT 7:6: Strict client validation 574 // 0 - Default 575 // 1 - Enable strict client validation 576 // 2 - Do not enable strict client validation 577 // 578 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION "RmValidateClientData" 579 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_ALL 1:0 580 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_ALL_DEFAULT 0x00000000 581 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_ALL_ENABLED 0x00000001 582 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_ALL_DISABLED 0x00000002 583 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_KERNEL_BUFFERS 3:2 584 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_KERNEL_BUFFERS_DEFAULT 0x00000000 585 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_KERNEL_BUFFERS_ENABLED 0x00000001 586 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_KERNEL_BUFFERS_DISABLED 0x00000002 587 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_HANDLE 5:4 588 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_HANDLE_DEFAULT 0x00000000 589 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_HANDLE_ENABLED 0x00000001 590 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_HANDLE_DISABLED 0x00000002 591 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_STRICT_CLIENT 7:6 592 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_STRICT_CLIENT_DEFAULT 0x00000000 593 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_STRICT_CLIENT_ENABLED 0x00000001 594 #define NV_REG_STR_RM_CLIENT_DATA_VALIDATION_STRICT_CLIENT_DISABLED 0x00000002 595 596 597 // 598 // Type: Dword 599 // Encoding: 600 // 1 - Enable remote GPU 601 // 0 - Disable remote GPU 602 // 603 #define NV_REG_STR_RM_REMOTE_GPU "RMRemoteGpu" 604 #define NV_REG_STR_RM_REMOTE_GPU_ENABLE 0x00000001 605 #define NV_REG_STR_RM_REMOTE_GPU_DISABLE 0x00000000 606 #define NV_REG_STR_RM_REMOTE_GPU_DEFAULT NV_REG_STR_RM_REMOTE_GPU_DISABLE 607 608 609 // 610 // Type: DWORD 611 // 612 // This regkey configures thread priority boosting whenever 613 // the thread is holding a GPU lock. 614 // 615 #define NV_REG_STR_RM_PRIORITY_BOOST "RMPriorityBoost" 616 #define NV_REG_STR_RM_PRIORITY_BOOST_DISABLE 0x00000000 617 #define NV_REG_STR_RM_PRIORITY_BOOST_ENABLE 0x00000001 618 #define NV_REG_STR_RM_PRIORITY_BOOST_DEFAULT NV_REG_STR_RM_PRIORITY_BOOST_DISABLE 619 620 621 // 622 // Type: DWORD 623 // 624 // This regkey configures the delay (us) before a boosted thread is throttled 625 // down. 626 // 627 // Default value: 0 (Disable) 628 // 629 #define NV_REG_STR_RM_PRIORITY_THROTTLE_DELAY "RMPriorityThrottleDelay" 630 #define NV_REG_STR_RM_PRIORITY_THROTTLE_DELAY_DISABLE 0x00000000 631 632 633 // 634 // Type DWORD 635 // Enable support for CUDA Stream Memory Operations in user-mode applications. 636 // 637 // BIT 0:0 - Feature enablement 638 // 0 - disable feature (default) 639 // 1 - enable feature 640 // 641 #define NV_REG_STR_RM_STREAM_MEMOPS "RmStreamMemOps" 642 #define NV_REG_STR_RM_STREAM_MEMOPS_ENABLE 0:0 643 #define NV_REG_STR_RM_STREAM_MEMOPS_ENABLE_YES 1 644 #define NV_REG_STR_RM_STREAM_MEMOPS_ENABLE_NO 0 645 646 647 // 648 // Type DWORD: Enable read-only RMAPI locks for select interfaces 649 // 650 // Setting an interface to 0 will disable read-only API locks for that interface 651 // Setting an interface to 1 will enable read-only API locks for that interface, 652 // however, RM may still choose to take a read-write lock if it needs to. 653 // 654 #define NV_REG_STR_RM_READONLY_API_LOCK "RmRoApiLock" 655 #define NV_REG_STR_RM_READONLY_API_LOCK_ALLOC_RESOURCE 1:1 656 #define NV_REG_STR_RM_READONLY_API_LOCK_ALLOC_RESOURCE_DEFAULT (0x00000000) 657 #define NV_REG_STR_RM_READONLY_API_LOCK_ALLOC_RESOURCE_DISABLE (0x00000000) 658 #define NV_REG_STR_RM_READONLY_API_LOCK_ALLOC_RESOURCE_ENABLE (0x00000001) 659 #define NV_REG_STR_RM_READONLY_API_LOCK_FREE_RESOURCE 2:2 660 #define NV_REG_STR_RM_READONLY_API_LOCK_FREE_RESOURCE_DEFAULT (0x00000000) 661 #define NV_REG_STR_RM_READONLY_API_LOCK_FREE_RESOURCE_DISABLE (0x00000000) 662 #define NV_REG_STR_RM_READONLY_API_LOCK_FREE_RESOURCE_ENABLE (0x00000001) 663 #define NV_REG_STR_RM_READONLY_API_LOCK_MAP 3:3 664 #define NV_REG_STR_RM_READONLY_API_LOCK_MAP_DEFAULT (0x00000000) 665 #define NV_REG_STR_RM_READONLY_API_LOCK_MAP_DISABLE (0x00000000) 666 #define NV_REG_STR_RM_READONLY_API_LOCK_MAP_ENABLE (0x00000001) 667 #define NV_REG_STR_RM_READONLY_API_LOCK_UNMAP 4:4 668 #define NV_REG_STR_RM_READONLY_API_LOCK_UNMAP_DEFAULT (0x00000000) 669 #define NV_REG_STR_RM_READONLY_API_LOCK_UNMAP_DISABLE (0x00000000) 670 #define NV_REG_STR_RM_READONLY_API_LOCK_UNMAP_ENABLE (0x00000001) 671 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_MAP 5:5 672 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_MAP_DEFAULT (0x00000000) 673 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_MAP_DISABLE (0x00000000) 674 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_MAP_ENABLE (0x00000001) 675 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_UNMAP 6:6 676 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_UNMAP_DEFAULT (0x00000000) 677 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_UNMAP_DISABLE (0x00000000) 678 #define NV_REG_STR_RM_READONLY_API_LOCK_INTER_UNMAP_ENABLE (0x00000001) 679 #define NV_REG_STR_RM_READONLY_API_LOCK_COPY 7:7 680 #define NV_REG_STR_RM_READONLY_API_LOCK_COPY_DEFAULT (0x00000000) 681 #define NV_REG_STR_RM_READONLY_API_LOCK_COPY_DISABLE (0x00000000) 682 #define NV_REG_STR_RM_READONLY_API_LOCK_COPY_ENABLE (0x00000001) 683 #define NV_REG_STR_RM_READONLY_API_LOCK_SHARE 8:8 684 #define NV_REG_STR_RM_READONLY_API_LOCK_SHARE_DEFAULT (0x00000000) 685 #define NV_REG_STR_RM_READONLY_API_LOCK_SHARE_DISABLE (0x00000000) 686 #define NV_REG_STR_RM_READONLY_API_LOCK_SHARE_ENABLE (0x00000001) 687 #define NV_REG_STR_RM_READONLY_API_LOCK_CTRL 9:9 688 #define NV_REG_STR_RM_READONLY_API_LOCK_CTRL_DEFAULT (0x00000000) 689 #define NV_REG_STR_RM_READONLY_API_LOCK_CTRL_DISABLE (0x00000000) 690 #define NV_REG_STR_RM_READONLY_API_LOCK_CTRL_ENABLE (0x00000001) 691 692 693 // 694 // Type DWORD: Enable read-only RMAPI locks for select modules 695 // 696 // Setting an interface to 0 will disable read-only API locks for that module 697 // Setting an interface to 1 will enable read-only API locks for that module, 698 // however, RM may still choose to take a read-write lock if it needs to. 699 // 700 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE "RmRoApiLockModule" 701 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_GPU_OPS 0:0 702 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_GPU_OPS_DEFAULT (0x00000000) 703 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_GPU_OPS_DISABLE (0x00000000) 704 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_GPU_OPS_ENABLE (0x00000001) 705 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_WORKITEM 1:1 706 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_WORKITEM_DEFAULT (0x00000000) 707 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_WORKITEM_DISABLE (0x00000000) 708 #define NV_REG_STR_RM_READONLY_API_LOCK_MODULE_WORKITEM_ENABLE (0x00000001) 709 710 711 // 712 // Type DWORD: Enable read-only GPU locks for select modules 713 // 714 // Setting an interface to 0 will disable read-only GPU locks for that module 715 // Setting an interface to 1 will enable read-only GPU locks for that module, 716 // however, RM may still choose to take a read-write lock if it needs to. 717 // 718 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE "RmRoGpuLockModule" 719 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_GPU_OPS 0:0 720 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_GPU_OPS_DEFAULT (0x00000000) 721 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_GPU_OPS_DISABLE (0x00000000) 722 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_GPU_OPS_ENABLE (0x00000001) 723 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_WORKITEM 1:1 724 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_WORKITEM_DEFAULT (0x00000000) 725 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_WORKITEM_DISABLE (0x00000000) 726 #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_WORKITEM_ENABLE (0x00000001) 727 728 729 // Mode for CACHEABLE rmapi control 730 // RMCTRL cache mode defined in ctrl0000system.h 731 #define NV_REG_STR_RM_CACHEABLE_CONTROLS "RmEnableCacheableControls" 732 733 // Type DWORD 734 // This regkey forces for Maxwell+ that on FB Unload we wait for FB pull before issuing the 735 // L2 clean. WAR for bug 1032432 736 #define NV_REG_STR_RM_L2_CLEAN_FB_PULL "RmL2CleanFbPull" 737 #define NV_REG_STR_RM_L2_CLEAN_FB_PULL_ENABLED (0x00000000) 738 #define NV_REG_STR_RM_L2_CLEAN_FB_PULL_DISABLED (0x00000001) 739 #define NV_REG_STR_RM_L2_CLEAN_FB_PULL_DEFAULT (0x00000000) 740 741 // 742 // Type: DWORD 743 // This regkey overrides BL8, 16, and 24 kinds to only be of GENERIC_MEMORY or 744 // GENERIC_MEMORY_COMPRESSIBLE kinds. 745 // 0 - No override 746 // > 0 - Override memkind to GMK 747 // bit 0: override BL8 type 748 // bit 1: override BL16 type 749 // bit 2: override BL24 type 750 // ex. 0x00001000 means override all types 751 #define NV_REG_STR_RM_OVERRIDE_TO_GMK "RMOverrideToGMK" 752 #define NV_REG_STR_RM_OVERRIDE_TO_GMK_DISABLED (0x00000000) 753 #define NV_REG_STR_RM_OVERRIDE_TO_GMK_BL8 (0x00000001) 754 #define NV_REG_STR_RM_OVERRIDE_TO_GMK_BL16 (0x00000002) 755 #define NV_REG_STR_RM_OVERRIDE_TO_GMK_BL24 (0x00000004) 756 #define NV_REG_STR_RM_OVERRIDE_TO_GMK_ALL (0x00000007) 757 758 // Enable backtrace dumping at assertion failure. 759 // If physical RM or RCDB is unavailable, then this regkey controls the behaviour of backtrace 760 // printing. 761 // 0: disable 762 // 1 (default): only print unique backtraces, identified by instruction pointer of the failed assert 763 // 2: print all 764 #define NV_REG_STR_RM_PRINT_ASSERT_BACKTRACE "RmPrintAssertBacktrace" 765 #define NV_REG_STR_RM_PRINT_ASSERT_BACKTRACE_DISABLE 0 766 #define NV_REG_STR_RM_PRINT_ASSERT_BACKTRACE_UNIQUE 1 767 #define NV_REG_STR_RM_PRINT_ASSERT_BACKTRACE_ENABLE 2 768 769 770 // 771 // Type DWORD 772 // Used to enable no locking on copy 773 // 774 #define NV_REG_STR_RM_PARAM_COPY_NO_LOCK "RMParamCopyNoLock" 775 776 // 777 // Type DWORD 778 // Used to control RM API lock aging for low priority acquires. 779 // If 0, low priority acquires (e.g. from cleanup when a process dies) 780 // are disabled and treated like regular ones. 781 // Otherwise, they will yield the lock this many times to the higher priority 782 // threads before proceeding. 783 // Off by default; 3 would be a good starting value if the feature is desired. 784 // 785 #define NV_REG_STR_RM_LOCKING_LOW_PRIORITY_AGING "RMLockingLowPriorityAging" 786 787 // 788 // Type DWORD 789 // This regkey restricts profiling capabilities (creation of profiling objects 790 // and access to profiling-related registers) to admin only. 791 // 0 - (default - disabled) 792 // 1 - Enables admin check 793 // 794 #define NV_REG_STR_RM_PROFILING_ADMIN_ONLY "RmProfilingAdminOnly" 795 #define NV_REG_STR_RM_PROFILING_ADMIN_ONLY_FALSE 0x00000000 796 #define NV_REG_STR_RM_PROFILING_ADMIN_ONLY_TRUE 0x00000001 797 798 799 #define NV_REG_STR_GPU_BROKEN_FB "nvBrokenFb" 800 #define NV_REG_STR_GPU_BROKEN_FB_ALL_OKAY 0x00000000 801 #define NV_REG_STR_GPU_BROKEN_FB_ALL_BROKEN 0xffffffff 802 #define NV_REG_STR_GPU_BROKEN_FB_DEFAULT NV_REG_STR_GPU_BROKEN_FB_ALL_OKAY 803 #define NV_REG_STR_GPU_BROKEN_FB_DEFAULT_GF100_A01 NV_REG_STR_GPU_BROKEN_FB_MEMORY_BROKEN 804 #define NV_REG_STR_GPU_BROKEN_FB_MEMORY 0:0 805 #define NV_REG_STR_GPU_BROKEN_FB_MEMORY_OKAY 0x00000000 806 #define NV_REG_STR_GPU_BROKEN_FB_MEMORY_BROKEN 0x00000001 807 #define NV_REG_STR_GPU_BROKEN_FB_REG_VIA_CPU 1:1 808 #define NV_REG_STR_GPU_BROKEN_FB_REG_VIA_CPU_OKAY 0x00000000 809 #define NV_REG_STR_GPU_BROKEN_FB_REG_VIA_CPU_BROKEN 0x00000001 810 #define NV_REG_STR_GPU_BROKEN_FB_REG_VIA_PMU 2:2 811 #define NV_REG_STR_GPU_BROKEN_FB_REG_VIA_PMU_OKAY 0x00000000 812 #define NV_REG_STR_GPU_BROKEN_FB_REG_VIA_PMU_BROKEN 0x00000001 813 // Type DWORD 814 // _ALL_OKAY: FB is not broken. All is okay. 815 // _ALL_BROKEN: FB is broken and no software will try to use it. 816 // _MEMORY: Memory itself can/cannot be accessed. (PDB_PROP_GPU_BROKEN_FB property) 817 // _REG_VIA_CPU: CPU can/cannot access FBPA/FBIO registers. (PDB_PROP_GPU_BROKEN_FB_REG_VIA_CPU property) 818 // _REG_VIA_PMU: PMU can/cannot access FBPA/FBIO registers. (PDB_PROP_GPU_BROKEN_FB_REG_VIA_PMU property) 819 // FBPA/FBIO register addresses are defined by gpuIsBrokenFbReg(). 820 // Note that if the CPU and the PMU can't access registers, then memory isn't going to work either. 821 // In other words, the only even number that makes sense for this regkey is zero. 822 // Default depends on the chip and mask revision. 823 824 #define NV_REG_STR_OVERRIDE_FB_SIZE "OverrideFbSize" 825 // Type Dword 826 // Encoding Numeric Value 827 // Size in MB 828 // Used to reduce FB for testing memory management 829 // 830 #define NV_REG_STR_OVERRIDE_FB_SIZE_DEFAULT 0 831 832 // 833 // TYPE DWORD 834 // This regkey helps increase the size of RM reserved region. 835 // Exposed to clients for bug 2404337. 836 // Note: In GSP builds this key applies to the kernel (CPU) RM only. 837 // 838 #define NV_REG_STR_RM_INCREASE_RSVD_MEMORY_SIZE_MB "RMIncreaseRsvdMemorySizeMB" 839 #define NV_REG_STR_RM_INCREASE_RSVD_MEMORY_SIZE_MB_DEFAULT 0x0 840 841 // TYPE Dword 842 // Determines whether or not RM reserved space should be increased. 843 // 1 - Increases RM reserved space 844 // 0 - (default) Keeps RM reserved space as it is. 845 846 #define NV_REG_STR_RM_DISABLE_SCRUB_ON_FREE "RMDisableScrubOnFree" 847 // Type DWORD 848 // Encoding 0 (default) - Scrub on free 849 // 1 - Disable Scrub on Free 850 851 #define NV_REG_STR_RM_DISABLE_FAST_SCRUBBER "RMDisableFastScrubber" 852 // Type DWORD 853 // Encoding 0 (default) - Enable Fast Scrubber 854 // 1 - Disable Fast Scrubber 855 856 // 857 // Type DWORD 858 // Controls enable of PMA memory management instead of existing legacy 859 // RM FB heap manager. 860 // 861 #define NV_REG_STR_RM_ENABLE_PMA "RMEnablePMA" 862 #define NV_REG_STR_RM_ENABLE_PMA_YES (0x00000001) 863 #define NV_REG_STR_RM_ENABLE_PMA_NO (0x00000000) 864 865 // 866 // Type DWORD 867 // Controls management of client page tables by PMA on MODS. 868 // Default enable. MODS will use regkey to override to disable feature. 869 // 870 #define NV_REG_STR_RM_ENABLE_PMA_MANAGED_PTABLES "RMEnablePmaManagedPtables" 871 #define NV_REG_STR_RM_ENABLE_PMA_MANAGED_PTABLES_YES (0x00000001) 872 #define NV_REG_STR_RM_ENABLE_PMA_MANAGED_PTABLES_NO (0x00000000) 873 #define NV_REG_STR_RM_ENABLE_PMA_MANAGED_PTABLES_DEFAULT (0x00000001) 874 875 // 876 // Type DWORD 877 // Disable global CeUtils instance creation after fifo scheduling enablement 878 // 879 #define NV_REG_STR_DISABLE_GLOBAL_CE_UTILS "RmDisableGlobalCeUtils" 880 #define NV_REG_STR_DISABLE_GLOBAL_CE_UTILS_YES (0x00000001) 881 #define NV_REG_STR_DISABLE_GLOBAL_CE_UTILS_NO (0x00000000) 882 883 #define NV_REG_STR_RM_SCRUB_BLOCK_SHIFT "RMScrubBlockShift" 884 // Type DWORD 885 // Encoding Numeric Value 886 // A value in the range 12 to 20 represents logbase2 of maxBlockSize for heap 887 // scrubber. Any other value will be defaulted to 16 i.e. maxBlockSize = 64KB. 888 889 #define NV_REG_STR_RM_INST_VPR "RMInstVPR" 890 // Type DWORD 891 // Encoding: takes effect for allocations in VIDEO memory 892 // TRUE Make allocation in protected region 893 // FALSE Make allocation in non-protected region (default) 894 // 895 #define NV_REG_STR_RM_INST_VPR_INSTBLK 0:0 // Instance block 896 #define NV_REG_STR_RM_INST_VPR_INSTBLK_FALSE (0x00000000) 897 #define NV_REG_STR_RM_INST_VPR_INSTBLK_TRUE (0x00000001) 898 #define NV_REG_STR_RM_INST_VPR_RAMFC 1:1 // RAMFC save area 899 #define NV_REG_STR_RM_INST_VPR_RAMFC_FALSE (0x00000000) 900 #define NV_REG_STR_RM_INST_VPR_RAMFC_TRUE (0x00000001) 901 #define NV_REG_STR_RM_INST_VPR_RUNLIST 2:2 // Runlist 902 #define NV_REG_STR_RM_INST_VPR_RUNLIST_FALSE (0x00000000) 903 #define NV_REG_STR_RM_INST_VPR_RUNLIST_TRUE (0x00000001) 904 #define NV_REG_STR_RM_INST_VPR_MMU_READ 3:3 // MMU Debug Read 905 #define NV_REG_STR_RM_INST_VPR_MMU_READ_FALSE (0x00000000) 906 #define NV_REG_STR_RM_INST_VPR_MMU_READ_TRUE (0x00000001) 907 #define NV_REG_STR_RM_INST_VPR_MMU_WRITE 4:4 // MMU Debug Read 908 #define NV_REG_STR_RM_INST_VPR_MMU_WRITE_FALSE (0x00000000) 909 #define NV_REG_STR_RM_INST_VPR_MMU_WRITE_TRUE (0x00000001) 910 911 #define NV_REG_STR_RM_GPU_SURPRISE_REMOVAL "RMGpuSurpriseRemoval" 912 // Type DWORD 913 // Encoding boolean 914 // If set, this will cause RM mark GPU as lost when it detects 0xFF from register 915 // access. 916 917 #define NV_REG_STR_RM_BLACKLIST_ADDRESSES "RmBlackListAddresses" 918 // Type BINARY: 919 // struct 920 // { 921 // NvU64 addresses[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; 922 // }; 923 924 #define NV_REG_STR_RM_NUM_FIFOS "RmNumFifos" 925 // Type Dword 926 // Override number of fifos (channels) on NV4X 927 #define NV_REG_STR_RM_NUM_FIFOS_COMPAT 0x00000020 928 #define NV_REG_STR_RM_NUM_FIFOS_EXTENDED 0x00000200 929 930 #define NV_REG_STR_RM_SUPPORT_USERD_MAP_DMA "RMSupportUserdMapDma" 931 // Type DWORD 932 // Encoding: Boolean 933 // If set, allow MapMemoryDma calls to be made on channel objects 934 935 #define NV_REG_STR_SECONDARY_BUS_RESET_ENABLED "RMSecBusResetEnable" 936 // Type DWORD 937 // Encoding boolean 938 // Default FALSE 939 940 #define NV_REG_STR_FORCE_PCIE_CONFIG_SAVE "RMForcePcieConfigSave" 941 // Type DWORD 942 // Encoding boolean 943 // Default FALSE 944 945 #define NV_REG_STR_RM_PCIE_FLR_DEVINIT_TIMEOUT_SCALE "RMPcieFlrDevinitTimeout" 946 #define NV_REG_STR_RM_PCIE_FLR_DEVINIT_TIMEOUT_SCALE_MIN_ALLOWED 1 947 #define NV_REG_STR_RM_PCIE_FLR_DEVINIT_TIMEOUT_SCALE_MAX_ALLOWED 4 948 // Type DWORD 949 // Regkey to change FLR devinit timeout value. Increase in scale value increases 950 // the timeout value and vice versa. 951 // Scale value has to be greater than 0 since flr devinit timeout can't be 0 952 // Scale value for now is limited to 4 which translates to maximum of 953 // 3.6seconds(900ms*4) timeout value. 954 // 955 956 #define NV_REG_STR_RM_PCIE_FLR_POLICY "RMPcieFLRPolicy" 957 #define NV_REG_STR_RM_PCIE_FLR_POLICY_DEFAULT 0 958 #define NV_REG_STR_RM_PCIE_FLR_POLICY_FORCE_DISABLE 1 959 // Type DWORD 960 // Regkey to force disable Function Level Reset 961 // Note that we don't want to provision for force enabling FLR since as per current design - 962 // For Pre-Turing boards, FLR will be strictly disabled since it's not supported in HW 963 // Default policy could be different for different boards though 964 965 // Type DWORD 966 // Encoding Numeric Value 967 // Overrides chipset-based P2P configurations. 968 // Only be used to test on internal issues 969 // 970 // P2P reads: 971 // 0 - Do not allow P2P reads 972 // 1 - Allow P2P reads 973 // 2 - Do not override chipset-selected config (default) 974 // P2P writes: 975 // 0 - Do not allow P2P writes 976 // 1 - Allow P2P writes 977 // 2 - Do not override chipset-selected config (default) 978 // 979 #define NV_REG_STR_CL_FORCE_P2P "ForceP2P" 980 #define NV_REG_STR_CL_FORCE_P2P_READ 1:0 981 #define NV_REG_STR_CL_FORCE_P2P_READ_DISABLE 0x00000000 982 #define NV_REG_STR_CL_FORCE_P2P_READ_ENABLE 0x00000001 983 #define NV_REG_STR_CL_FORCE_P2P_READ_DEFAULT 0x00000002 984 #define NV_REG_STR_CL_FORCE_P2P_WRITE 5:4 985 #define NV_REG_STR_CL_FORCE_P2P_WRITE_DISABLE 0x00000000 986 #define NV_REG_STR_CL_FORCE_P2P_WRITE_ENABLE 0x00000001 987 #define NV_REG_STR_CL_FORCE_P2P_WRITE_DEFAULT 0x00000002 988 989 // 990 // Type DWORD 991 // Use this regkey to force RM to pick a P2P type. HW has to support the picked TYPE to take effect. 992 // e.g., TYPE_BAR1P2P will not work if HW does not support it. A call to create NV50_P2P object will 993 // will fail in such a case. 994 // 995 // TYPE_DEFAULT let RM to choose a P2P type. The priority is: 996 // C2C > NVLINK > mailbox P2P > BAR1P2P 997 // 998 // TYPE_C2C to use C2C P2P if it supports 999 // TYPE_NVLINK to use NVLINK P2P, including INDIRECT_NVLINK_P2P if it supports 1000 // TYPE_BAR1P2P to use BAR1 P2P if it supports 1001 // TYPE_MAILBOXP2P to use mailbox p2p if it supports 1002 // 1003 #define NV_REG_STR_RM_FORCE_P2P_TYPE "RMForceP2PType" 1004 #define NV_REG_STR_RM_FORCE_P2P_TYPE_DEFAULT (0x00000000) 1005 #define NV_REG_STR_RM_FORCE_P2P_TYPE_MAILBOXP2P (0x00000001) 1006 #define NV_REG_STR_RM_FORCE_P2P_TYPE_BAR1P2P (0x00000002) 1007 #define NV_REG_STR_RM_FORCE_P2P_TYPE_NVLINK (0x00000003) 1008 #define NV_REG_STR_RM_FORCE_P2P_TYPE_C2C (0x00000004) 1009 #define NV_REG_STR_RM_FORCE_P2P_TYPE_MAX NV_REG_STR_RM_FORCE_P2P_TYPE_C2C 1010 1011 // 1012 // Type: DWORD 1013 // Enables/Disables the WAR for bug 1630288 where we disable 3rd-party peer mappings 1014 // Disabled by default 1015 // 1016 #define NV_REG_STR_PEERMAPPING_OVERRIDE "PeerMappingOverride" 1017 #define NV_REG_STR_PEERMAPPING_OVERRIDE_DEFAULT 0 1018 1019 #define NV_REG_STR_P2P_MAILBOX_CLIENT_ALLOCATED "P2PMailboxClientAllocated" 1020 #define NV_REG_STR_P2P_MAILBOX_CLIENT_ALLOCATED_FALSE 0 1021 #define NV_REG_STR_P2P_MAILBOX_CLIENT_ALLOCATED_TRUE 1 1022 // Type Dword 1023 // Overrides the P2P Mailbox allocation policy 1024 // For testing only 1025 // 0 - P2P Mailbox area is allocated by RM 1026 // 1 - P2P Mailbox area is not allocated by RM, but by the client. 1027 1028 #define NV_REG_STR_RM_MAP_P2P_PEER_ID "RMP2PPeerId" 1029 // Type DWORD 1030 // Encoding: 1031 // Peer ID to use when mapping p2p to peer subdevice in p2p loopback mode 1032 // Default: RM takes care of assigning peer ID. 1033 1034 #define NV_REG_STR_OVERRIDE_GPU_NUMA_NODE_ID "RMOverrideGpuNumaNodeId" 1035 // Type DWORD: 1036 // Encoding -- NvS32 1037 // Override GPU NUMA Node ID assigned by OS 1038 1039 #define NV_REG_STR_RESTORE_BAR1_SIZE_BUG_3249028_WAR "RMBar1RestoreSize" 1040 #define NV_REG_STR_RESTORE_BAR1_SIZE_BUG_3249028_TRUE (0x00000001) 1041 #define NV_REG_STR_RESTORE_BAR1_SIZE_BUG_3249028_FALSE (0x00000000) 1042 // Type DWORD: 1043 // Encoding -- Boolean 1044 // Check if BAR1 size has been restored correctly by SBIOS across power transitions 1045 // Default: enabled for Ampere and up 1046 // 1047 1048 // 1049 // Type DWORD 1050 // Numa allocations allow for skipping reclaim less than a specified memory occupancy threshold. 1051 // This override allows for its tuning, value supplied here shall indicate a percent of free memory 1052 // less than which GFP_RECLAIM flag will be dropped. 1053 // 1054 #define NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE "RmNumaAllocSkipReclaimPercent" 1055 #define NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE_DEFAULT 4 1056 #define NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE_DISABLED 0 1057 #define NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE_MIN 0 1058 #define NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE_MAX 100 1059 1060 // 1061 // Disable 64KB BAR1 mappings 1062 // 0 - Disable 64KB BAR1 mappings 1063 // 1 - Force/Enable 64KB BAR1 mappings 1064 // 1065 #define NV_REG_STR_RM_64KB_BAR1_MAPPINGS "RM64KBBAR1Mappings" 1066 #define NV_REG_STR_RM_64KB_BAR1_MAPPINGS_ENABLED 0x00000001 1067 #define NV_REG_STR_RM_64KB_BAR1_MAPPINGS_DISABLED 0x00000000 1068 1069 #define NV_REG_STR_RM_BAR1_APERTURE_SIZE_MB "RMBar1ApertureSizeMB" 1070 // Type DWORD 1071 // Encoding Numeric Value 1072 // Overrides the size of the BAR1 aperture. Used to shrink BAR1. It cannot be 1073 // greater than the physical size of BAR1. 1074 1075 #define NV_REG_STR_RM_BAR2_APERTURE_SIZE_MB "RMBar2ApertureSizeMB" 1076 // Type DWORD 1077 // Encoding Numeric Value 1078 // Overrides the size of the BAR2 aperture. Cannot be greater than the 1079 // physical size of BAR2 available to RM (which may be less than the total size 1080 // of BAR2). When this regkey is present we cap the total aperture size to the 1081 // RM aperture size. This can result in undefined beahvior in environments that 1082 // rely on a virtual bar2 aperture shared between RM and VBIOS for VESA support. 1083 1084 #if defined(DEVELOP) || defined(DEBUG) || (defined(RMCFG_FEATURE_MODS_FEATURES) && RMCFG_FEATURE_MODS_FEATURES) 1085 // 1086 // TYPE DWORD 1087 // This setting will override the BAR1 Big page size 1088 // This is used for interop testing for MODS 1089 // 1090 #define NV_REG_STR_RM_SET_BAR1_ADDRESS_SPACE_BIG_PAGE_SIZE "RMSetBAR1AddressSpaceBigPageSize" 1091 #define NV_REG_STR_RM_SET_BAR1_ADDRESS_SPACE_BIG_PAGE_SIZE_64k (64 * 1024) 1092 #define NV_REG_STR_RM_SET_BAR1_ADDRESS_SPACE_BIG_PAGE_SIZE_128k (128 * 1024) 1093 #endif //DEVELOP || DEBUG || MODS_FEATURES 1094 1095 // This regkey is to disable coherent path CPU->Nvlink/C2C->FB and force BAR path. 1096 #define NV_REG_STR_RM_FORCE_BAR_PATH "RMForceBarPath" 1097 // Type DWORD 1098 // Encoding 0 (default) - Enable Coherent C2C/NvLink Path 1099 // 1 - Force BAR Path 1100 1101 // 1102 // Type: Dword 1103 // Encoding: 1104 // 0 - client RM allocated context buffer feature is disabled 1105 // 1 - client RM allocated context buffer feature is enabled 1106 // 1107 #define NV_REG_STR_RM_CLIENT_RM_ALLOCATED_CTX_BUFFER "RMSetClientRMAllocatedCtxBuffer" 1108 #define NV_REG_STR_RM_CLIENT_RM_ALLOCATED_CTX_BUFFER_DISABLED 0x00000000 1109 #define NV_REG_STR_RM_CLIENT_RM_ALLOCATED_CTX_BUFFER_ENABLED 0x00000001 1110 1111 // 1112 // Type: Dword 1113 // Encoding: 1114 // 0 - Split VA space management between server/client RM is disabled 1115 // 1 - Split VA space management between server/client RM is enabled 1116 // 1117 #define NV_REG_STR_RM_SPLIT_VAS_MGMT_SERVER_CLIENT_RM "RMSplitVasMgmtServerClientRm" 1118 #define NV_REG_STR_RM_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_DISABLED 0x00000000 1119 #define NV_REG_STR_RM_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_ENABLED 0x00000001 1120 1121 // 1122 // Restrict the VA range to be <= @ref VASPACE_SIZE_FERMI. 1123 // Used in cases where some engines support 49 bit VA and some don't. 1124 // Ignored if NVOS32_ALLOC_FLAGS_USE_BEGIN_END (DDMA_ALLOC_VASPACE_USE_RANGE) or 1125 // NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE (DMA_ALLOC_VASPACE_VA_FIXED) is set. 1126 // Default: OFF (0x0) 1127 // Type: DWORD 1128 // 1129 #define NV_REG_STR_RM_RESTRICT_VA_RANGE "RMRestrictVARange" 1130 #define NV_REG_STR_RM_RESTRICT_VA_RANGE_DEFAULT (0x0) 1131 #define NV_REG_STR_RM_RESTRICT_VA_RANGE_ON (0x1) 1132 1133 #define NV_REG_STR_RESERVE_PTE_SYSMEM_MB "RmReservePteSysmemMB" 1134 // Type DWORD: 1135 // Encoding -- Value = 0 -> Do not reserve sysmem for PTEs (default) 1136 // Value > 0 -> Reserve ValueMB for PTEs when we run out of video and system memory 1137 // 1138 1139 // Type DWORD 1140 // Contains the sysmem page size. 1141 #define NV_REG_STR_RM_SYSMEM_PAGE_SIZE "RMSysmemPageSize" 1142 1143 // 1144 // Allows pages that are aligned to large page boundaries to be mapped as large 1145 // pages. 1146 // 1147 #define NV_REG_STR_RM_ALLOW_SYSMEM_LARGE_PAGES "RMAllowSysmemLargePages" 1148 1149 #define NV_REG_STR_FERMI_BIG_PAGE_SIZE "RMFermiBigPageSize" 1150 #define NV_REG_STR_FERMI_BIG_PAGE_SIZE_64KB (64 * 1024) 1151 #define NV_REG_STR_FERMI_BIG_PAGE_SIZE_128KB (128 * 1024) 1152 1153 // 1154 // TYPE DWORD 1155 // This setting will disable big page size per address space 1156 // 1157 #define NV_REG_STR_RM_DISABLE_BIG_PAGE_PER_ADDRESS_SPACE "RmDisableBigPagePerAddressSpace" 1158 #define NV_REG_STR_RM_DISABLE_BIG_PAGE_PER_ADDRESS_SPACE_FALSE (0x00000000) 1159 #define NV_REG_STR_RM_DISABLE_BIG_PAGE_PER_ADDRESS_SPACE_TRUE (0x00000001) 1160 1161 #define NV_REG_STR_RM_DISABLE_NONCONTIGUOUS_ALLOCATION "RMDisableNoncontigAlloc" 1162 #define NV_REG_STR_RM_DISABLE_NONCONTIGUOUS_ALLOCATION_FALSE (0x00000000) 1163 #define NV_REG_STR_RM_DISABLE_NONCONTIGUOUS_ALLOCATION_TRUE (0x00000001) 1164 // Type DWORD: 1165 // Encoding -- Boolean 1166 // Disable noncontig vidmem allocation 1167 // 1168 1169 #define NV_REG_STR_RM_FBSR_PAGED_DMA "RmFbsrPagedDMA" 1170 #define NV_REG_STR_RM_FBSR_PAGED_DMA_ENABLE 1 1171 #define NV_REG_STR_RM_FBSR_PAGED_DMA_DISABLE 0 1172 #define NV_REG_STR_RM_FBSR_PAGED_DMA_DEFAULT NV_REG_STR_RM_FBSR_PAGED_DMA_DISABLE 1173 // Type Dword 1174 // Encoding Numeric Value 1175 // Enable the Paged DMA mode for FBSR 1176 // 0 - Disable (default) 1177 // 1 - Enable 1178 1179 #define NV_REG_STR_RM_FBSR_FILE_MODE "RmFbsrFileMode" 1180 #define NV_REG_STR_RM_FBSR_FILE_MODE_ENABLE 1 1181 #define NV_REG_STR_RM_FBSR_FILE_MODE_DISABLE 0 1182 #define NV_REG_STR_RM_FBSR_FILE_MODE_DEFAULT NV_REG_STR_RM_FBSR_FILE_MODE_DISABLE 1183 // Type Dword 1184 // Encoding Numeric Value 1185 // Enable the File based power saving mode for Linux 1186 // 0 - Disable (default) 1187 // 1 - Enable 1188 1189 #define NV_REG_STR_RM_FBSR_WDDM_MODE "RmFbsrWDDMMode" 1190 #define NV_REG_STR_RM_FBSR_WDDM_MODE_ENABLE 1 1191 #define NV_REG_STR_RM_FBSR_WDDM_MODE_DISABLE 0 1192 #define NV_REG_STR_RM_FBSR_WDDM_MODE_DEFAULT NV_REG_STR_RM_FBSR_WDDM_MODE_DISABLE 1193 // Type Dword 1194 // Encoding Numeric Value 1195 // Enable the WDDM power saving mode for FBSR 1196 // 0 - Disable (default) 1197 // 1 - Enable 1198 1199 // Type DWORD: Disables HW fault buffers on Pascal+ chips 1200 // Encoding : 1 -- TRUE 1201 // : 0 -- False 1202 // : Default -- False 1203 #define NV_REG_STR_RM_DISABLE_HW_FAULT_BUFFER "RmDisableHwFaultBuffer" 1204 #define NV_REG_STR_RM_DISABLE_HW_FAULT_BUFFER_TRUE 0x00000001 1205 #define NV_REG_STR_RM_DISABLE_HW_FAULT_BUFFER_FALSE 0x00000000 1206 #define NV_REG_STR_RM_DISABLE_HW_FAULT_BUFFER_DEFAULT 0x00000000 1207 1208 // 1209 // Type: DWORD 1210 // Encoding: 1211 // 3 - Enable interrupt-based FECS context switch logging with bottom-half/APC fall-back 1212 // 2 - Enable interrupt-based FECS context switch logging without bottom-half/APC fall-back 1213 // 1 - Enable periodic FECS context switch logging 1214 // 0 - Disable FECS context switch logging 1215 // 1216 // Note: Interrupt-based logging and periodic logging are mutually exclusive 1217 // 1218 #define NV_REG_STR_RM_CTXSW_LOG "RMCtxswLog" 1219 #define NV_REG_STR_RM_CTXSW_LOG_DISABLE 0x00000000 1220 #define NV_REG_STR_RM_CTXSW_LOG_ENABLE 0x00000001 1221 #define NV_REG_STR_RM_CTXSW_LOG_ENABLE_INTR 0x00000002 1222 #define NV_REG_STR_RM_CTXSW_LOG_ENABLE_INTR_APC 0x00000003 1223 #define NV_REG_STR_RM_CTXSW_LOG_DEFAULT NV_REG_STR_RM_CTXSW_LOG_DISABLE 1224 1225 // Type DWORD: Indicates if enabling video event tracing 1226 // 1227 // 0 - Disables Video event trace usage (default) 1228 // > 0 - Enable video event trace and define sizes for different buffers 1229 // bit 16 - 30: sizes of the event buffer in 4K pages 1230 // bit 31 - 31: Enable always logging: 1231 // By default, video engines only log video events when there is 1232 // at least one eventbuffer bound and enabled. If this flag is set, 1233 // video engines will always log events even without a consumer. This 1234 // is helpful for debugging purposes. 1235 // Example: 0x01000000 means 1MB event buffer. 1236 #define NV_REG_STR_RM_VIDEO_EVENT_TRACE "RmVideoEventTrace" 1237 #define NV_REG_STR_RM_VIDEO_EVENT_TRACE_DISABLED (0x00000000) 1238 #define NV_REG_STR_RM_VIDEO_EVENT_TRACE_EVENT_BUFFER_SIZE_IN_4k 30:16 1239 #define NV_REG_STR_RM_VIDEO_EVENT_TRACE_ALWAYS_LOG 31:31 1240 #define NV_REG_STR_RM_VIDEO_EVENT_TRACE_ALWAYS_LOG_DISABLED 0x00000000 1241 #define NV_REG_STR_RM_VIDEO_EVENT_TRACE_ALWAYS_LOG_ENABLED 0x00000001 1242 1243 // 1244 // Type: DWORD 1245 // 1246 // This regkey configures the maximum number of records that can be 1247 // processed per DPC when using interrupt-based ctxsw logging 1248 #define NV_REG_STR_RM_CTXSW_LOG_RECORDS_PER_INTR "RMCtxswLogMaxRecordsPerIntr" 1249 #define NV_REG_STR_RM_CTXSW_LOG_RECORDS_PER_INTR_DEFAULT 0x30 1250 1251 // 1252 // Type: DWORD 1253 // Encoding: 1254 // 0 - Disable more detailed debug INTR logs 1255 // 1 - Enable more detailed debug INTR logs 1256 // 1257 #define NV_REG_STR_RM_INTR_DETAILED_LOGS "RMIntrDetailedLogs" 1258 #define NV_REG_STR_RM_INTR_DETAILED_LOGS_DISABLE 0x00000000 1259 #define NV_REG_STR_RM_INTR_DETAILED_LOGS_ENABLE 0x00000001 1260 1261 #define NV_REG_STR_RM_LOCKING_MODE "RMLockingMode" 1262 // Type DWORD 1263 // Encoding enum 1264 // Overrides what Locking Mode is in use. 1265 // Default 0 1266 #define NV_REG_STR_RM_LOCKING_MODE_DEFAULT (0x00000000) 1267 #define NV_REG_STR_RM_LOCKING_MODE_INTR_MASK (0x00000001) 1268 1269 #define NV_REG_STR_RM_PER_INTR_DPC_QUEUING "RMDisablePerIntrDPCQueueing" 1270 // Type DWORD 1271 // This regkey is used to disable per interrupt DPC queuing. 1272 // 0: Enable Per interrupt DPC Queuing 1273 // 1: Disable Per interrupt DPC Queuing 1274 1275 #define NV_REG_STR_INTR_STUCK_THRESHOLD "RM654663" 1276 // Type DWORD 1277 // Encoding NvU32 1278 // Number of iterations to see an interrupt in succession before considering it 1279 // "stuck." 1280 // Default - See INTR_STUCK_THRESHOLD 1281 1282 1283 #define NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR "RMProcessNonStallIntrInLocklessIsr" 1284 1285 // Type: DWORD 1286 // Enables/Disables processing of non-stall interrupts in lockless ISR for 1287 // Linux only. 1288 // Non-stall interrupts are processed by the function 1289 // intrServiceNonStall_HAL(pIntr,pGpu, TRUE /* bProcess*/); where bProcess is TRUE which 1290 // means that event list will be traversed to notify clients registered for it. 1291 // Disabled by default 1292 // 1293 1294 #define NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_DISABLE 0x00000000 1295 #define NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_ENABLE 0x00000001 1296 1297 #define NV_REG_STR_RM_ROBUST_CHANNELS "RmRobustChannels" 1298 #define NV_REG_STR_RM_ROBUST_CHANNELS_ENABLE 0x00000001 1299 #define NV_REG_STR_RM_ROBUST_CHANNELS_DISABLE 0x00000000 1300 #define NV_REG_STR_RM_ROBUST_CHANNELS_DEFAULT NV_REG_STR_RM_ROBUST_CHANNELS_DISABLE 1301 1302 #define NV_REG_STR_RM_RC_WATCHDOG "RmRcWatchdog" 1303 #define NV_REG_STR_RM_RC_WATCHDOG_ENABLE 0x00000001 1304 #define NV_REG_STR_RM_RC_WATCHDOG_DISABLE 0x00000000 1305 #define NV_REG_STR_RM_RC_WATCHDOG_DEFAULT NV_REG_STR_RM_RC_WATCHDOG_ENABLE 1306 1307 #define NV_REG_STR_RM_WATCHDOG_TIMEOUT "RmWatchDogTimeOut" 1308 #define NV_REG_STR_RM_WATCHDOG_TIMEOUT_LOW 0x00000007 1309 #define NV_REG_STR_RM_WATCHDOG_TIMEOUT_HI 0x0000000C 1310 #define NV_REG_STR_RM_WATCHDOG_TIMEOUT_DEFAULT NV_REG_STR_RM_WATCHDOG_TIMEOUT_LOW 1311 1312 #define NV_REG_STR_RM_WATCHDOG_INTERVAL "RmWatchDogInterval" 1313 #define NV_REG_STR_RM_WATCHDOG_INTERVAL_LOW 0x00000007 1314 #define NV_REG_STR_RM_WATCHDOG_INTERVAL_HI 0x0000000C 1315 #define NV_REG_STR_RM_WATCHDOG_INTERVAL_DEFAULT NV_REG_STR_RM_WATCHDOG_INTERVAL_LOW 1316 1317 // Enable/Disable watchcat in GSP-Plugin for Guest RPC 1318 // Default is Enabled 1319 #define NV_REG_STR_RM_GSP_VGPU_WATCHCAT "RmEnableGspPluginWatchcat" 1320 #define NV_REG_STR_RM_GSP_VGPU_WATCHCAT_ENABLE 0x00000001 1321 #define NV_REG_STR_RM_GSP_VGPU_WATCHCAT_DISABLE 0x00000000 1322 #define NV_REG_STR_RM_GSP_VGPU_WATCHCAT_DEFAULT NV_REG_STR_RM_GSP_VGPU_WATCHCAT_ENABLE 1323 1324 // Set watchcat timeout value in GSP-Plugin for Guest RPC 1325 // Default is 10 seconds 1326 #define NV_REG_STR_RM_GSP_VGPU_WATCHCAT_TIMEOUT "RmGspPluginWatchcatTimeOut" 1327 #define NV_REG_STR_RM_GSP_VGPU_WATCHCAT_TIMEOUT_MIN 0x0000000A 1328 #define NV_REG_STR_RM_GSP_VGPU_WATCHCAT_TIMEOUT_DEFAULT NV_REG_STR_RM_GSP_VGPU_WATCHCAT_TIMEOUT_MIN 1329 1330 #define NV_REG_STR_RM_DO_LOG_RC_EVENTS "RmLogonRC" 1331 // Type Dword 1332 // Encoding : 0 --> Skip Logging 1333 // 1 --> Do log 1334 // Enable/Disable Event Logging on RC errors 1335 // Default is Disabled 1336 #define NV_REG_STR_RM_DO_LOG_RC_ENABLE 0x00000001 1337 #define NV_REG_STR_RM_DO_LOG_RC_DISABLE 0x00000000 1338 #define NV_REG_STR_RM_DO_LOG_RC_DEFAULT NV_REG_STR_RM_DO_LOG_RC_DISABLE 1339 1340 // Type Dword 1341 // Encoding : 0 --> Skip Breakpoint 1342 // nonzero --> Do Breakpoint 1343 // Enable/Disable breakpoint on DEBUG resource manager on RC errors 1344 1345 #define NV_REG_STR_RM_BREAK_ON_RC "RmBreakonRC" 1346 #define NV_REG_STR_RM_BREAK_ON_RC_DISABLE 0x00000000 1347 #define NV_REG_STR_RM_BREAK_ON_RC_ENABLE 0x00000001 1348 1349 // Explicitly disable RmBreakOnRC for Retail <enable via registry> and 1350 // RMCFG_FEATURE_PLATFORM_GSP builds 1351 #if ((defined(DEBUG) || defined(QA_BUILD)) && \ 1352 (!defined(RMCFG_FEATURE_PLATFORM_GSP) || \ 1353 (defined(RMCFG_FEATURE_PLATFORM_GSP) && !RMCFG_FEATURE_PLATFORM_GSP))) 1354 #define NV_REG_STR_RM_BREAK_ON_RC_DEFAULT NV_REG_STR_RM_BREAK_ON_RC_ENABLE 1355 #else 1356 #define NV_REG_STR_RM_BREAK_ON_RC_DEFAULT NV_REG_STR_RM_BREAK_ON_RC_DISABLE 1357 #endif 1358 1359 // Volatile registry entries for previous driver version. 1360 // Used to record driver unload/reload for debugging purposes. 1361 #define NV_REG_STR_RM_RC_PREV_DRIVER_VERSION "RmRCPrevDriverVersion" 1362 #define NV_REG_STR_RM_RC_PREV_DRIVER_BRANCH "RmRCPrevDriverBranch" 1363 #define NV_REG_STR_RM_RC_PREV_DRIVER_CHANGELIST "RmRCPrevDriverChangelist" 1364 #define NV_REG_STR_RM_RC_PREV_DRIVER_LOAD_COUNT "RmRCPrevDriverLoadCount" 1365 1366 #define NV_REG_STR_USE_UNCACHED_PCI_MAPPINGS "UseUncachedPCIMappings" 1367 // Type DWORD 1368 // Encode -- Numeric Value 1369 // Check to see if we are converting PCI mappings 1370 1371 #define NV_REG_STR_RM_CE_USE_GEN4_MAPPING "RmCeUseGen4Mapping" 1372 #define NV_REG_STR_RM_CE_USE_GEN4_MAPPING_TRUE 0x1 1373 #define NV_REG_STR_RM_CE_USE_GEN4_MAPPING_FALSE 0x0 1374 // Type Dword (Boolean) 1375 // Encoding Numeric Value 1376 // Use gen4 mapping that uses a HSHUB CE, if available 1377 // Else, continue using FBHUB PCEs 1378 1379 // Type Dword 1380 // Enable PCE LCE auto config 1381 #define NV_REG_STR_RM_CE_ENABLE_AUTO_CONFIG "RmCeEnableAutoConfig" 1382 #define NV_REG_STR_RM_CE_ENABLE_AUTO_CONFIG_TRUE 0x1 1383 #define NV_REG_STR_RM_CE_ENABLE_AUTO_CONFIG_FALSE 0x0 1384 1385 // 1386 // Type DWORD 1387 // NVLINK control overrides. 1388 // 1389 // FORCE_DISABLE: Force disable NVLINK when the current default is ON (POR) 1390 // 1391 // TRAIN_AT_LOAD : Force train links during driver load 1392 // 1393 // FORCE_AUTOCONFIG : Force autoconfig training regardless of chiplib forced config links 1394 // 1395 // FORCE_ENABLE: Force enable NVLINK when the current default is OFF (bringup etc.) 1396 // 1397 // PARALLEL_TRAINING: Have the GPU endpoint parallelize link training 1398 #define NV_REG_STR_RM_NVLINK_CONTROL "RMNvLinkControl" 1399 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_DISABLE 0:0 1400 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_DISABLE_NO (0x00000000) 1401 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_DISABLE_YES (0x00000001) 1402 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_DISABLE_DEFAULT (NV_REG_STR_RM_NVLINK_CONTROL_FORCE_DISABLE_NO) 1403 #define NV_REG_STR_RM_NVLINK_CONTROL_TRAIN_AT_LOAD 1:1 1404 #define NV_REG_STR_RM_NVLINK_CONTROL_TRAIN_AT_LOAD_NO (0x00000000) 1405 #define NV_REG_STR_RM_NVLINK_CONTROL_TRAIN_AT_LOAD_YES (0x00000001) 1406 #define NV_REG_STR_RM_NVLINK_CONTROL_TRAIN_AT_LOAD_DEFAULT (NV_REG_STR_RM_NVLINK_CONTROL_TRAIN_AT_LOAD_NO) 1407 #define NV_REG_STR_RM_NVLINK_CONTROL_SKIP_TRAIN 2:2 1408 #define NV_REG_STR_RM_NVLINK_CONTROL_SKIP_TRAIN_NO (0x00000000) 1409 #define NV_REG_STR_RM_NVLINK_CONTROL_SKIP_TRAIN_YES (0x00000001) 1410 #define NV_REG_STR_RM_NVLINK_CONTROL_SKIP_TRAIN_DEFAULT (NV_REG_STR_RM_NVLINK_CONTROL_SKIP_TRAIN_NO) 1411 #define NV_REG_STR_RM_NVLINK_CONTROL_RESERVED_0 6:3 1412 #define NV_REG_STR_RM_NVLINK_CONTROL_LINK_TRAINING_DEBUG_SPEW 7:7 1413 #define NV_REG_STR_RM_NVLINK_CONTROL_LINK_TRAINING_DEBUG_SPEW_OFF (0x00000000) 1414 #define NV_REG_STR_RM_NVLINK_CONTROL_LINK_TRAINING_DEBUG_SPEW_ON (0x00000001) 1415 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_AUTOCONFIG 8:8 1416 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_AUTOCONFIG_NO (0x00000000) 1417 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_AUTOCONFIG_YES (0x00000001) 1418 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_AUTOCONFIG_DEFAULT (NV_REG_STR_RM_NVLINK_CONTROL_FORCE_AUTOCONFIG_NO) 1419 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_ENABLE 31:31 1420 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_ENABLE_NO (0x00000000) 1421 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_ENABLE_YES (0x00000001) 1422 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_ENABLE_DEFAULT (NV_REG_STR_RM_NVLINK_CONTROL_FORCE_ENABLE_NO) 1423 1424 // 1425 // Type DWORD 1426 // Knob to control NVLink MINION 1427 // 1428 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL "RMNvLinkMinionControl" 1429 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ENABLE 3:0 1430 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ENABLE_DEFAULT (0x00000000) 1431 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ENABLE_FORCE_ON (0x00000001) 1432 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ENABLE_FORCE_OFF (0x00000002) 1433 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_PHY_CONFIG 7:4 1434 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_PHY_CONFIG_DEFAULT (0x00000000) 1435 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_PHY_CONFIG_ENABLE (0x00000001) 1436 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_PHY_CONFIG_DISABLE (0x00000002) 1437 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_DL_STATUS 11:8 1438 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_DL_STATUS_DEFAULT (0x00000000) 1439 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_DL_STATUS_ENABLE (0x00000001) 1440 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_DL_STATUS_DISABLE (0x00000002) 1441 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITNEGOTIATE 15:12 1442 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITNEGOTIATE_DEFAULT (0x00000000) 1443 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITNEGOTIATE_ENABLE (0x00000001) 1444 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITNEGOTIATE_DISABLE (0x00000002) 1445 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITOPTIMIZE 19:16 1446 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITOPTIMIZE_DEFAULT (0x00000000) 1447 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITOPTIMIZE_ENABLE (0x00000001) 1448 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITOPTIMIZE_DISABLE (0x00000002) 1449 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_CACHE_SEEDS 23:20 1450 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_CACHE_SEEDS_DEFAULT (0x00000000) 1451 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_CACHE_SEEDS_ENABLE (0x00000001) 1452 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_CACHE_SEEDS_DISABLE (0x00000002) 1453 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE 27:24 1454 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE_DEFAULT (0x00000000) 1455 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE_RISCV (0x00000001) 1456 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE_FALCON (0x00000002) 1457 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE_RISCV_MANIFEST (0x00000003) 1458 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE_NO_MANIFEST (0x00000004) 1459 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ALI_TRAINING 30:28 1460 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ALI_TRAINING_DEFAULT (0x00000000) 1461 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ALI_TRAINING_ENABLE (0x00000001) 1462 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ALI_TRAINING_DISABLE (0x00000002) 1463 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_GFW_BOOT_DISABLE 31:31 1464 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_GFW_BOOT_DISABLE_DEFAULT (0x00000000) 1465 #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_GFW_BOOT_DISABLE_DISABLE (0x00000001) 1466 1467 // 1468 // Type DWORD 1469 // Knob to change NVLink link speed 1470 // __LAST is same as highest supported speed 1471 // NOTE: 1472 // NVLINK_SPEED_CONTROL_SPEED_25G is exactly 25.00000Gbps on Pascal 1473 // NVLINK_SPEED_CONTROL_SPEED_25G is exactly 25.78125Gbps on Volta and later 1474 // NVLINK_SPEED_CONTROL_SPEED_2500000G is exactly 25.00000Gbps on all chips 1475 // 1476 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL "RMNvLinkSpeedControl" 1477 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED 4:0 1478 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_DEFAULT (0x00000000) 1479 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_16G (0x00000001) 1480 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_19_2G (0x00000002) 1481 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_20G (0x00000003) 1482 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_21G (0x00000004) 1483 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_22G (0x00000005) 1484 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_23G (0x00000006) 1485 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_24G (0x00000007) 1486 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_25G (0x00000008) 1487 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_25_78125G (0x00000008) 1488 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_25_00000G (0x00000009) 1489 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_16_14583G (0x0000000A) 1490 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_26_56250G (0x0000000B) 1491 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_27_34375G (0x0000000C) 1492 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_28_12500G (0x0000000D) 1493 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_32G (0x0000000E) 1494 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_40G (0x0000000F) 1495 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_50_00000G (0x00000010) 1496 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_53_12500G (0x00000011) 1497 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_100_00000G (0x00000012) 1498 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_106_25000G (0x00000013) 1499 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_FAULT (0x00000014) 1500 #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED__LAST (0x00000014) 1501 1502 // 1503 // Type DWORD 1504 // P2P Loopback over NVLINK will be enabled by default if RM 1505 // detects loopback links. For P2P over PCIE, force disable 1506 // P2P loopback over NVLINK using the following regkey 1507 // 1508 #define NV_REG_STR_RM_NVLINK_DISABLE_P2P_LOOPBACK "RMNvLinkDisableP2PLoopback" 1509 #define NV_REG_STR_RM_NVLINK_DISABLE_P2P_LOOPBACK_DEFAULT (0x00000000) 1510 #define NV_REG_STR_RM_NVLINK_DISABLE_P2P_LOOPBACK_TRUE (0x00000001) 1511 #define NV_REG_STR_RM_NVLINK_DISABLE_P2P_LOOPBACK_FALSE (0x00000000) 1512 1513 // 1514 // Type DWORD 1515 // Knob to control NVLink Link Power States 1516 // 1517 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL "RMNvLinkControlLinkPM" 1518 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_SINGLE_LANE_MODE 1:0 1519 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_SINGLE_LANE_MODE_DEFAULT (0x00000000) 1520 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_SINGLE_LANE_MODE_ENABLE (0x00000001) 1521 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_SINGLE_LANE_MODE_DISABLE (0x00000002) 1522 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_PROD_WRITES 3:2 1523 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_PROD_WRITES_DEFAULT (0x00000000) 1524 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_PROD_WRITES_ENABLE (0x00000001) 1525 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_PROD_WRITES_DISABLE (0x00000002) 1526 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L1_MODE 5:4 1527 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L1_MODE_DEFAULT (0x00000000) 1528 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L1_MODE_ENABLE (0x00000001) 1529 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L1_MODE_DISABLE (0x00000002) 1530 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L2_MODE 7:6 1531 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L2_MODE_DEFAULT (0x00000000) 1532 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L2_MODE_ENABLE (0x00000001) 1533 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L2_MODE_DISABLE (0x00000002) 1534 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_RESERVED 31:8 1535 1536 // 1537 // Type DWORD 1538 // Knob to force lane disable and shutdown during driver unload 1539 // The regkey will also cause a toggle of link reset on driver load 1540 // The regkey should not be used in S/R paths 1541 // 1542 #define NV_REG_STR_RM_NVLINK_FORCE_LANESHUTDOWN "RMNvLinkForceLaneshutdown" 1543 #define NV_REG_STR_RM_NVLINK_FORCE_LANESHUTDOWN_TRUE (0x00000001) 1544 #define NV_REG_STR_RM_NVLINK_FORCE_LANESHUTDOWN_FALSE (0x00000000) 1545 #define NV_REG_STR_RM_NVLINK_FORCE_LANESHUTDOWN_DEFAULT (NV_REG_STR_RM_NVLINK_FORCE_LANESHUTDOWN_FALSE) 1546 1547 // 1548 // Type DWORD 1549 // For links that are SYSMEM, use this device type for force configs 1550 // Choose the value from NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_* 1551 // 1552 #define NV_REG_STR_RM_NVLINK_SYSMEM_DEVICE_TYPE "RMNvLinkForcedSysmemDeviceType" 1553 1554 // 1555 // Type DWORD 1556 // NVLink Disable Link Overrides 1557 // The supplied value is ANDed with the set of discovered 1558 // (not necessarily connected) links to remove unwanted links. 1559 // A value of DISABLE_ALL removes/disables all links on this device. 1560 // A value of DISABLE_NONE removes no links. 1561 // If not present, this regkey has no effect. 1562 // 1563 #define NV_REG_STR_RM_NVLINK_DISABLE_LINKS "RMNvLinkDisableLinks" 1564 #define NV_REG_STR_RM_NVLINK_DISABLE_LINKS_DISABLE_ALL (0xFFFFFFFF) 1565 #define NV_REG_STR_RM_NVLINK_DISABLE_LINKS_DISABLE_NONE (0x00000000) 1566 1567 // 1568 // Type DWORD 1569 // NVLINK Enable Links Overrides 1570 // Note that this control does not force enable links, rather, it should be 1571 // used to disable or mask off SW discovered links supported by the HW. 1572 // 1573 // NOTE: THIS REGKEY HAS BEEN DEPRECATED IN RM, since it does NOT work 1574 // with NVLink auto-configuration. Instead, please move to using 1575 // the new regkey NV_REG_STR_RM_NVLINK_DISABLE_LINKS 1576 // 1577 #define NV_REG_STR_RM_NVLINK_ENABLE "RMNvLinkEnable" 1578 #define NV_REG_STR_RM_NVLINK_ENABLE_IDX(i) (i):(i) 1579 #define NV_REG_STR_RM_NVLINK_ENABLE_IDX__SIZE 32 1580 #define NV_REG_STR_RM_NVLINK_ENABLE_IDX_TRUE (0x00000001) 1581 #define NV_REG_STR_RM_NVLINK_ENABLE_IDX_FALSE (0x00000000) 1582 1583 // 1584 // Type DWORD 1585 // Knob to control NVLink Verbose Prints 1586 // 1587 #define NV_REG_STR_RM_NVLINK_VERBOSE_MASK_CONTROL "RMNvLinkverboseControlMask" 1588 #define NV_REG_STR_RM_NVLINK_VERBOSE_MASK_CONTROL_REGINIT 0:0 1589 #define NV_REG_STR_RM_NVLINK_VERBOSE_MASK_CONTROL_REGINIT_DEFAULT (0x00000000) 1590 #define NV_REG_STR_RM_NVLINK_VERBOSE_MASK_CONTROL_REGINIT_ON (0x00000001) 1591 #define NV_REG_STR_RM_NVLINK_VERBOSE_MASK_CONTROL_REGINIT_OFF (0x00000000) 1592 1593 // Type DWORD: 1594 #define NV_REG_STR_RM_PCIE_LINK_SPEED "RMPcieLinkSpeed" 1595 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN2 1:0 1596 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN2_DEFAULT (0x00000000) 1597 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN2_ENABLE (0x00000001) 1598 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN2_DISABLE (0x00000002) 1599 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN3 3:2 1600 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN3_DEFAULT (0x00000000) 1601 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN3_ENABLE (0x00000001) 1602 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN3_DISABLE (0x00000002) 1603 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN4 5:4 1604 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN4_DEFAULT (0x00000000) 1605 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN4_ENABLE (0x00000001) 1606 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN4_DISABLE (0x00000002) 1607 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN5 7:6 1608 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN5_DEFAULT (0x00000000) 1609 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN5_ENABLE (0x00000001) 1610 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN5_DISABLE (0x00000002) 1611 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN6 9:8 1612 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN6_DEFAULT (0x00000000) 1613 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN6_ENABLE (0x00000001) 1614 #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN6_DISABLE (0x00000002) 1615 #define NV_REG_STR_RM_PCIE_LINK_SPEED_LOCK_AT_LOAD 31:31 1616 #define NV_REG_STR_RM_PCIE_LINK_SPEED_LOCK_AT_LOAD_DISABLE (0x00000000) 1617 #define NV_REG_STR_RM_PCIE_LINK_SPEED_LOCK_AT_LOAD_ENABLE (0x00000001) 1618 1619 // 1620 // Type DWORD 1621 // 1622 // 1623 // This can be used as a per-device regkey or not, in which case the setting 1624 // will apply to all devices. If this key is supplied as both a per-device and 1625 // non-per-device regkey, the non-per-device option will apply first to all 1626 // devices, and then the per-device key settings will apply, overriding the 1627 // settings for the relevant devices. 1628 // 1629 // Encoding : 0 - Disable PCIe Relaxed Ordering TLP header bit setting. This is 1630 // the default option. 1631 // 1 - Try to enable PCIe Relaxed Ordering TLP header bit setting. 1632 // Traverses the PCIe topology and only enables the header bit if 1633 // it is safe to do so, with regard to all devices that could be 1634 // affected. 1635 // 2 - Forcibly enable PCIe Relaxed Ordering TLP header bit setting. 1636 // Explicitly ignores the compatibility of the PCIe topology 1637 // around the device or devices in question. 1638 // 1639 #define NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING "RmSetPCIERelaxedOrdering" 1640 #define NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING_DEFAULT 0x00000000 1641 #define NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING_DISABLE 0x00000000 1642 #define NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING_ENABLE 0x00000001 1643 #define NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING_FORCE_ENABLE 0x00000002 1644 1645 // Type DWORD 1646 // This regkey overrides the default use case to optimize the GPU for. 1647 // This regkey should not be used with the RMFermiBigPageSize regkey. 1648 // This regkey should only be set by the RM. 1649 #define NV_REG_STR_RM_OPTIMIZE_COMPUTE_OR_SPARSE_TEX "RMOptimizeComputeOrSparseTex" 1650 #define NV_REG_STR_RM_OPTIMIZE_COMPUTE_OR_SPARSE_TEX_DEFAULT (0x00000000) 1651 #define NV_REG_STR_RM_OPTIMIZE_COMPUTE_OR_SPARSE_TEX_COMPUTE (0x00000001) 1652 #define NV_REG_STR_RM_OPTIMIZE_COMPUTE_OR_SPARSE_TEX_SPARSE_TEX (0x00000002) 1653 1654 #define NV_REG_STR_CL_ASLM_CFG "AslmCfg" 1655 #define NV_REG_STR_CL_ASLM_CFG_NV_LINK_UPGRADE 1:0 1656 #define NV_REG_STR_CL_ASLM_CFG_NV_LINK_UPGRADE_NO 0x00000000 1657 #define NV_REG_STR_CL_ASLM_CFG_NV_LINK_UPGRADE_YES 0x00000001 1658 #define NV_REG_STR_CL_ASLM_CFG_NV_LINK_UPGRADE_DEFAULT 0x00000002 1659 #define NV_REG_STR_CL_ASLM_CFG_HOT_RESET 5:4 1660 #define NV_REG_STR_CL_ASLM_CFG_HOT_RESET_NO 0x00000000 1661 #define NV_REG_STR_CL_ASLM_CFG_HOT_RESET_YES 0x00000001 1662 #define NV_REG_STR_CL_ASLM_CFG_HOT_RESET_DEFAULT 0x00000002 1663 #define NV_REG_STR_CL_ASLM_CFG_FAST_UPGRADE 9:8 1664 #define NV_REG_STR_CL_ASLM_CFG_FAST_UPGRADE_NO 0x00000000 1665 #define NV_REG_STR_CL_ASLM_CFG_FAST_UPGRADE_YES 0x00000001 1666 #define NV_REG_STR_CL_ASLM_CFG_FAST_UPGRADE_DEFAULT 0x00000002 1667 #define NV_REG_STR_CL_ASLM_CFG_GEN2_LINK_UPGRADE 11:10 1668 #define NV_REG_STR_CL_ASLM_CFG_GEN2_LINK_UPGRADE_NO 0x00000000 1669 #define NV_REG_STR_CL_ASLM_CFG_GEN2_LINK_UPGRADE_YES 0x00000001 1670 #define NV_REG_STR_CL_ASLM_CFG_GEN2_LINK_UPGRADE_DEFAULT 0x00000002 1671 // Type Dword 1672 // Encoding Numeric Value 1673 // Overrides chipset-based ASLM configurations. 1674 // 1675 // NV link upgrade: 1676 // 0 - Do not use NV link upgrade for ASLM 1677 // 1 - Use NV link upgrade for ASLM 1678 // 2 - Do not override chipset-selected config (default) 1679 // Hot reset: 1680 // 0 - Do not use hot reset for ASLM 1681 // 1 - Use hot reset for ASLM 1682 // 2 - Do not override chipset-selected config (default) 1683 // Fast link upgrade: 1684 // 0 - Do not use fast link upgrade for ASLM 1685 // 1 - Use fast link upgrade for ASLM 1686 // 2 - Do not override chipset-selected config (default) 1687 // Gen2 link width upgrade: 1688 // 0 - Do not use Gen2 link upgrade for ASLM 1689 // 1 - Use Gen2 link upgrade for ASLM 1690 // 2 - Do not override chipset-selected config (default) 1691 1692 #define NV_REG_STR_RM_DISABLE_BR03_FLOW_CONTROL "MB_DisableBr03FlowControl" 1693 // Type DWORD 1694 // Encoding 1 -> Do not program BR03 flow control registers 1695 // 0 -> Setup BR03 flow control registers 1696 // Determine whether we need to program BR03 flow control registers, in objcl.c 1697 1698 #define NV_REG_STR_RM_FORCE_ENABLE_GEN2 "RmForceEnableGen2" 1699 #define NV_REG_STR_RM_FORCE_ENABLE_GEN2_NO 0 1700 #define NV_REG_STR_RM_FORCE_ENABLE_GEN2_YES 1 1701 #define NV_REG_STR_RM_FORCE_ENABLE_GEN2_DEFAULT NV_REG_STR_RM_FORCE_ENABLE_GEN2_NO 1702 // Type DWORD: On some platform, Gen2 is disabled to work around system problems. 1703 // This key is to force enabling Gen2 for testing or other purpose. It is 1704 // ineffective on platforms not Gen2 capable. 1705 // Encoding boolean: 1706 // 0 - Do Nothing 1707 // 1 - Force Enable Gen2 (to invalidate PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED) 1708 // 1709 1710 #define NV_REG_STR_RM_D3_FEATURE "RMD3Feature" 1711 // Type DWORD 1712 // This regkey controls D3 related features 1713 #define NV_REG_STR_RM_D3_FEATURE_DRIVER_CFG_SPACE_RESTORE 1:0 1714 #define NV_REG_STR_RM_D3_FEATURE_DRIVER_CFG_SPACE_RESTORE_DEFAULT (0x00000000) 1715 #define NV_REG_STR_RM_D3_FEATURE_DRIVER_CFG_SPACE_RESTORE_ENABLED (0x00000001) 1716 #define NV_REG_STR_RM_D3_FEATURE_DRIVER_CFG_SPACE_RESTORE_DISABLED (0x00000002) 1717 #define NV_REG_STR_RM_D3_FEATURE_DRIVER_CFG_SPACE_RESTORE_UNUSED (0x00000003) 1718 1719 #define NV_REG_STR_EMULATED_NBSI_TABLE "RMemNBSItable" 1720 // The emulated NBSI table 1721 1722 #define NV_REG_STR_RM_DISABLE_FSP "RmDisableFsp" 1723 #define NV_REG_STR_RM_DISABLE_FSP_NO (0x00000000) 1724 #define NV_REG_STR_RM_DISABLE_FSP_YES (0x00000001) 1725 // Type DWORD (Boolean) 1726 // Override any other settings and disable FSP 1727 1728 #define NV_REG_STR_RM_DISABLE_COT_CMD "RmDisableCotCmd" 1729 #define NV_REG_STR_RM_DISABLE_COT_CMD_FRTS_SYSMEM 1:0 1730 #define NV_REG_STR_RM_DISABLE_COT_CMD_FRTS_VIDMEM 3:2 1731 #define NV_REG_STR_RM_DISABLE_COT_CMD_GSPFMC 5:4 1732 #define NV_REG_STR_RM_DISABLE_COT_CMD_DEFAULT (0x00000000) 1733 #define NV_REG_STR_RM_DISABLE_COT_CMD_YES (0x00000001) 1734 // Type DWORD (Boolean) 1735 // Disable the specified commands as part of Chain-Of-Trust feature 1736 1737 #define NV_REG_STR_PCI_LATENCY_TIMER_CONTROL "PciLatencyTimerControl" 1738 // Type Dword 1739 // Encoding Numeric Value 1740 // Override to control setting/not setting of pci timer latency value. 1741 // Not present suggests default value. A value 0xFFFFFFFF will leave the value unmodified (ie bios value). 1742 // All other values must be multiples of 8 1743 1744 #define NV_REG_STR_RM_ENABLE_ROUTE_TO_PHYSICAL_LOCK_BYPASS "RmRouteToPhyiscalLockBypass" 1745 // Type Bool 1746 // Enable optimisation to only take API READ (not WRITE) lock when forwarding ROUTE_TO_PHYSICAL 1747 // control calls to GSP-enabled GPUs. 1748 // This will heavily improve multi-gpu-multi-process control call latency and throughput. 1749 // This optimisation will only work when *all* GPUs in the system are in offload mode (GSP mode). 1750 1751 #define NV_REG_STR_RM_GPU_FABRIC_PROBE "RmGpuFabricProbe" 1752 #define NV_REG_STR_RM_GPU_FABRIC_PROBE_DELAY 7:0 1753 #define NV_REG_STR_RM_GPU_FABRIC_PROBE_SLOWDOWN_THRESHOLD 15:8 1754 #define NV_REG_STR_RM_GPU_FABRIC_PROBE_OVERRIDE 31:31 1755 // Type DWORD 1756 // Enable GPU fabric probe 1757 // 1758 // When this option is enabled, the GPU will probe its fabric state over the 1759 // NVLink inband channel. The fabric state includes the attributes to allow 1760 // the GPU to participate in P2P over the NVLink fabric. 1761 // 1762 // This option is only honored on NVSwitch based systems. 1763 // 1764 // Encoding: 1765 // _DELAY : Delay between consecutive probe retries (in sec) 1766 // before the slowdown starts. (Default: 5 sec) 1767 // _SLOWDOWN_THRESHOLD : Number of probes retries before the slowdown starts 1768 // (Default: 10). The slowdown doubles the delay 1769 // between every consecutive probe retries until success. 1770 // 1771 1772 // Enable plugin logs in ftrace buffer. 1773 // 0 - Default 1774 // 0 - Disabled 1775 // 1 - Enabled 1776 #define NV_REG_STR_RM_ENABLE_PLUGIN_IN_FTRACE_BUFFER "RmEnablePluginFtrace" 1777 #define NV_REG_STR_RM_ENABLE_PLUGIN_IN_FTRACE_BUFFER_ENABLED 0x00000001 1778 #define NV_REG_STR_RM_ENABLE_PLUGIN_IN_FTRACE_BUFFER_DISABLED 0x00000000 1779 #define NV_REG_STR_RM_ENABLE_PLUGIN_IN_FTRACE_BUFFER_DEFAULT 0x00000000 1780 1781 // TYPE Dword 1782 // Enable vGPU migration on KVM hyperivsor. 1783 // 1 - (Default) Enable vGPU migration on KVM 1784 // 0 - Disable vGPU migration on KVM hypervisor 1785 // 1786 #define NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION "RmEnableKvmVgpuMigration" 1787 #define NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION_TRUE 0x00000001 1788 #define NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION_FALSE 0x00000000 1789 #define NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION_DEFAULT 0x00000001 1790 1791 #define NV_REG_STR_RM_QSYNC_FW_REV_CHECK "QuadroSyncFirmwareRevisionCheckDisable" 1792 #define NV_REG_STR_RM_QSYNC_FW_REV_CHECK_DEFAULT 0x00000000 1793 #define NV_REG_STR_RM_QSYNC_FW_REV_CHECK_ENABLE 0x00000000 1794 #define NV_REG_STR_RM_QSYNC_FW_REV_CHECK_DISABLE 0x00000001 1795 1796 // Type DWORD 1797 // Disable Quadro Sync Firmware Revision Checking, for testing new versions. 1798 // 1799 1800 // 1801 // Type: Dword 1802 // Encoding: 1803 // 1 - SRIOV Enabled on supported GPU 1804 // 0 - SRIOV Disabled on specific GPU 1805 // 1806 #define NV_REG_STR_RM_SET_SRIOV_MODE "RMSetSriovMode" 1807 #define NV_REG_STR_RM_SET_SRIOV_MODE_DISABLED 0x00000000 1808 #define NV_REG_STR_RM_SET_SRIOV_MODE_ENABLED 0x00000001 1809 1810 #define NV_REG_STR_RM_SET_VGPU_VERSION_MIN "RMSetVGPUVersionMin" 1811 // 1812 // TYPE DWORD 1813 // Set the minimum vGPU version enforced to support 1814 1815 #define NV_REG_STR_RM_SET_VGPU_VERSION_MAX "RMSetVGPUVersionMax" 1816 // 1817 // TYPE DWORD 1818 // Set the maximum vGPU version enforced to support 1819 1820 #define NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_LSR_MIN_TIME "TSwapRdyHiLsrMinTime" 1821 #define NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_LSR_MIN_TIME_DEFAULT 250 // 250 micro seconds 1822 // Type: DWORD 1823 // Encoding: 1824 // To modify LSR_MIN_TIME parameter according to the time 1825 // period for which swap lock window will remain HIGH for QSYNC III 1826 // i.e. P2060 during swap barrier. 1827 1828 #define NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_SWAP_LOCKOUT_START "TSwapRdyHiSwapLockoutStart" 1829 #define NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_SWAP_LOCKOUT_START_DEFAULT 250 // 250 micro seconds 1830 // Type: DWORD 1831 // Encoding: 1832 // To modify SWAP_LOCKOUT_START parameter according to the time 1833 // period for which swap lock window will remain HIGH for QSYNC III. 1834 // 1835 1836 #define NV_REG_STR_RM_NVLINK_BW "RmNvlinkBandwidth" 1837 // Type String 1838 // The option is in the string format. 1839 // 1840 // Possible string values: 1841 // OFF: 0% bandwidth 1842 // MIN: 15%-25% bandwidth depending on the system's NVLink topology 1843 // HALF: 50% bandwidth 1844 // 3QUARTER: 75% bandwidth 1845 // FULL: 100% bandwidth (default) 1846 // 1847 // This option is only for Hopper+ GPU with NVLINK version 4.0. 1848 1849 // 1850 // Type DWORD (Boolean) 1851 // 1 - Measure API and GPU lock hold/wait times which can be retrieved with the 1852 // NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES control call 1853 // 0 - (Default) Don't measure lock hold/wait times 1854 // 1855 #define NV_REG_STR_RM_LOCK_TIME_COLLECT "RmLockTimeCollect" 1856 1857 // 1858 // Type: DWORD (Boolean) 1859 // 1860 // 1 - Only invalidate and free CPU mappings immediatelly, then collect GPU resources 1861 // from individual clients under separate lock acquire/release sequences. 1862 // 0 - (Default) Immediately free all clients resources when freeing a client list 1863 #define NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE "RMClientListDeferredFree" 1864 1865 // 1866 // Type: DWORD 1867 // 1868 // Number of clients to free in a single chunk before yielding and scheduling 1869 // a work item to handle the rest. 1870 // 1871 // Only valid if NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE is set. 1872 // 1873 // Value of 0 (default) means there is no limit and all clients will be freed 1874 // at once before the process terminates. 1875 // 1876 #define NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE_LIMIT "RMClientListDeferredFreeLimit" 1877 1878 // 1879 // TYPE Dword 1880 // Determines whether or not to emulate VF MMU TLB Invalidation register range 1881 // Encoding : 1 - Emulate register range (Default) 1882 // : 0 - Do not emulate register range. 1883 // 1884 #define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE "RMBug3007008EmulateVfMmuTlbInvalidate" 1885 #define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_ENABLE 0x00000001 1886 #define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_DISABLE 0x00000000 1887 #define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_DEFAULT NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_ENABLE 1888 1889 #define NV_REG_STR_RM_POWER_FEATURES "RMPowerFeature" 1890 1891 // Type DWORD 1892 // This Regkey controls inforom black box data recording. This can be used to 1893 // restrict access to BBX. 1894 // 0 - Enable BBX. (Default) 1895 // COMPLETELY - Enable/Disable BBX access (read/write). 1896 // WRITE_BY_RM - Enable/Disable writes by RM itself. 1897 // WRITE_BY_CLIENT - Enable/Disable writes by clients to RM. 1898 // PERIODIC FLUSH - Enable/Disable periodic flush to inforom (Also enables/disables Power data collection) 1899 // 1900 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX "RmDisableInforomBBX" 1901 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_NO (0x00000000) 1902 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_YES (0x00000001) 1903 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_COMPLETELY 0:0 1904 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_COMPLETELY_NO (0x00000000) 1905 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_COMPLETELY_YES (0x00000001) 1906 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_RM 1:1 1907 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_RM_NO (0x00000000) 1908 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_RM_YES (0x00000001) 1909 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_CLIENT 2:2 1910 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_CLIENT_NO (0x00000000) 1911 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_CLIENT_YES (0x00000001) 1912 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_PERIODIC_FLUSH 3:3 1913 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_PERIODIC_FLUSH_YES (0x00000000) 1914 #define NV_REG_STR_RM_INFOROM_DISABLE_BBX_PERIODIC_FLUSH_NO (0x00000001) 1915 1916 // 1917 // Type DWORD (Boolean) 1918 // RmNvlinkEnablePrivErrorRc 1919 // 1920 // 0 - (default) does not do RC recovery when PRIV_ERROR 1921 // 1 - enable FLA PRIV_ERROR RC recovery 1922 // 1923 #define NV_REG_STR_RM_NVLINK_ENABLE_PRIV_ERROR_RC "RmNvlinkEnablePrivErrorRc" 1924 #define NV_REG_STR_RM_NVLINK_ENABLE_PRIV_ERROR_RC_NO 0 1925 #define NV_REG_STR_RM_NVLINK_ENABLE_PRIV_ERROR_RC_YES 1 1926 1927 // 1928 // Add the conditions to exclude these macros from Orin build, as CONFIDENTIAL_COMPUTE 1929 // is a guardword. The #if could be removed when nvRmReg.h file is trimmed from Orin build. 1930 // 1931 // Enable Disable Confidential Compute and control its various modes of operation 1932 // 0 - Feature Disable 1933 // 1 - Feature Enable 1934 // 1935 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE "RmConfidentialCompute" 1936 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_ENABLED 0:0 1937 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_ENABLED_NO 0x00000000 1938 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_ENABLED_YES 0x00000001 1939 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_DEV_MODE_ENABLED 1:1 1940 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_DEV_MODE_ENABLED_NO 0x00000000 1941 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_DEV_MODE_ENABLED_YES 0x00000001 1942 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_GPUS_READY_CHECK 2:2 1943 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_GPUS_READY_CHECK_DISABLED 0x00000000 1944 #define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_GPUS_READY_CHECK_ENABLED 0x00000001 1945 1946 // 1947 // Enable/disable SPDM feature in Confidential Compute. SPDM-capable profiles 1948 // may not be loaded by default. This regkey allows us to override the default 1949 // behavior and force SPDM to enabled/disabled. 1950 // 1951 // 0 - Feature disable 1952 // 1 - Feature enable 1953 // 1954 #define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY "RmConfComputeSpdmPolicy" 1955 #define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY_ENABLED 0:0 1956 #define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY_ENABLED_NO 0x00000000 1957 #define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY_ENABLED_YES 0x00000001 1958 1959 // 1960 // Enable/disable key rotation in Confidential Compute. 1961 // If this is defined then NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION is ignored. 1962 // 1963 // 0 - Feature disabled 1964 // 1 - Feature enabled 1965 // 1966 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION "RmConfComputeKeyRotation" 1967 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_ENABLED 0:0 1968 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_ENABLED_NO 0x00000000 1969 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_ENABLED_YES 0x00000001 1970 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_SEC2_KEYS 1:1 1971 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_SEC2_KEYS_NO 0x00000000 1972 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_SEC2_KEYS_YES 0x00000001 1973 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE2_KEYS 2:2 1974 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE2_KEYS_NO 0x00000000 1975 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE2_KEYS_YES 0x00000001 1976 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE3_KEYS 3:3 1977 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE3_KEYS_NO 0x00000000 1978 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE3_KEYS_YES 0x00000001 1979 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE4_KEYS 4:4 1980 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE4_KEYS_NO 0x00000000 1981 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE4_KEYS_YES 0x00000001 1982 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE5_KEYS 5:5 1983 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE5_KEYS_NO 0x00000000 1984 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE5_KEYS_YES 0x00000001 1985 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE6_KEYS 6:6 1986 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE6_KEYS_NO 0x00000000 1987 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE6_KEYS_YES 0x00000001 1988 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE7_KEYS 7:7 1989 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE7_KEYS_NO 0x00000000 1990 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE7_KEYS_YES 0x00000001 1991 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE8_KEYS 8:8 1992 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE8_KEYS_NO 0x00000000 1993 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE8_KEYS_YES 0x00000001 1994 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE9_KEYS 9:9 1995 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE9_KEYS_NO 0x00000000 1996 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LCE9_KEYS_YES 0x00000001 1997 1998 // if all kernel keys should be considered for key rotation 1999 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_KERNEL_KEYS 10:10 2000 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_KERNEL_KEYS_NO 0x00000000 2001 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_KERNEL_KEYS_YES 0x00000001 2002 2003 // if all user keys should be considered for key rotation 2004 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_USER_KEYS 11:11 2005 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_USER_KEYS_NO 0x00000000 2006 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_USER_KEYS_YES 0x00000001 2007 2008 // if internal RM keys should be considered for key rotation 2009 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_INTERNAL_KEYS 12:12 2010 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_INTERNAL_KEYS_NO 0x00000000 2011 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_INTERNAL_KEYS_YES 0x00000001 2012 2013 // 2014 // Enable/disable dummy key rotation in Confidential Compute. 2015 // This is a temp reg key that will be removed once all RM clients 2016 // support key rotation by default. 2017 // 2018 // 0 - Feature disabled 2019 // 1 - Feature enabled 2020 // 2021 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION "RmConfComputeDummyKeyRotation" 2022 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_ENABLED 0:0 2023 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_ENABLED_NO 0x00000000 2024 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_ENABLED_YES 0x00000001 2025 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_SEC2_KEYS 1:1 2026 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_SEC2_KEYS_NO 0x00000000 2027 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_SEC2_KEYS_YES 0x00000001 2028 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE2_KEYS 2:2 2029 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE2_KEYS_NO 0x00000000 2030 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE2_KEYS_YES 0x00000001 2031 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE3_KEYS 3:3 2032 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE3_KEYS_NO 0x00000000 2033 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE3_KEYS_YES 0x00000001 2034 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE4_KEYS 4:4 2035 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE4_KEYS_NO 0x00000000 2036 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE4_KEYS_YES 0x00000001 2037 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE5_KEYS 5:5 2038 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE5_KEYS_NO 0x00000000 2039 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE5_KEYS_YES 0x00000001 2040 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE6_KEYS 6:6 2041 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE6_KEYS_NO 0x00000000 2042 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE6_KEYS_YES 0x00000001 2043 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE7_KEYS 7:7 2044 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE7_KEYS_NO 0x00000000 2045 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE7_KEYS_YES 0x00000001 2046 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE8_KEYS 8:8 2047 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE8_KEYS_NO 0x00000000 2048 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE8_KEYS_YES 0x00000001 2049 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE9_KEYS 9:9 2050 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE9_KEYS_NO 0x00000000 2051 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LCE9_KEYS_YES 0x00000001 2052 2053 // if all kernel keys should be considered for key rotation 2054 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_KERNEL_KEYS 10:10 2055 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_KERNEL_KEYS_NO 0x00000000 2056 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_KERNEL_KEYS_YES 0x00000001 2057 2058 // if all user keys should be considered for key rotation 2059 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_USER_KEYS 11:11 2060 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_USER_KEYS_NO 0x00000000 2061 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_USER_KEYS_YES 0x00000001 2062 2063 // 2064 // Set period for "keep-alive" heartbeat message sent between SPDM Requester and Responder. 2065 // This will sent a keep-alive message every period to GPU. GPU will set timeout to 2 * period. 2066 // If GPU doesn't receive message within 2 * period, it is fatal error and GPU will require reset. 2067 // Minimum period is 4 seconds, maximum period is 255 seconds. Setting period to 0 will disable heartbeat. 2068 // 2069 // 0 - Disable feature (no heartbeat sending) 2070 // x - Period value in seconds 2071 // 2072 #define NV_REG_STR_RM_CONF_COMPUTE_HEARTBEAT "RmConfComputeHeartbeatPeriod" 2073 #define NV_REG_STR_RM_CONF_COMPUTE_HEARTBEAT_PERIOD_SECONDS 31:0 2074 #define NV_REG_STR_RM_CONF_COMPUTE_HEARTBEAT_PERIOD_SECONDS_DISABLE 0x00000000 2075 #define NV_REG_STR_RM_CONF_COMPUTE_HEARTBEAT_PERIOD_SECONDS_MIN 0x00000004 2076 #define NV_REG_STR_RM_CONF_COMPUTE_HEARTBEAT_PERIOD_SECONDS_MAX 0x000000FF 2077 2078 // 2079 // Set the key rotation timeout value for user-mode clients. 2080 // This is the amount of time in seconds, after the threshold has been crossed, that user-mode clients 2081 // have to idle their channels before RM RCs the channels for key rotation. 2082 // This value must be greater than or equal to 2. 2083 // 2084 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_TIMEOUT_IN_SEC "RmKeyRotationTimeout" 2085 2086 // 2087 // Set the difference between the lower and upper thresholds. 2088 // Value is in units of (amount of data encrypted in units of 16 bytes + number of encryption invocations) 2089 // If this is set then NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LOWER_THRESHOLD and 2090 // NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_UPPER_THRESHOLD are ignored. 2091 // This value must be greater than 0. 2092 // 2093 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_THRESHOLD_DELTA "RmKeyRotationThresholdDelta" 2094 2095 // 2096 // Set lower threshold for key rotation. 2097 // Value is in units of (amount of data encrypted in units of 16 bytes + number of encryption invocations) 2098 // If this is set then RmKeyRotationUpperThreshold must also be set. 2099 // This value must be less than RmKeyRotationUpperThreshold. 2100 // Note that setting the attacker advantage via SMI/NVML will overwrite this value. 2101 // 2102 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_LOWER_THRESHOLD "RmKeyRotationLowerThreshold" 2103 2104 // 2105 // Set upper threshold for key rotation. 2106 // Value is in units of (amount of data encrypted in units of 16 bytes + number of encryption invocations) 2107 // If this is set then RmKeyRotationLowerThreshold must also be set. 2108 // This value must be greater than RmKeyRotationLowerThreshold. 2109 // Note that setting the attacker advantage via SMI/NVML will overwrite this value. 2110 // 2111 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_UPPER_THRESHOLD "RmKeyRotationUpperThreshold" 2112 2113 // 2114 // Set threshold for rotation of internal (RM only) keys. 2115 // Value is in units of (amount of data encrypted in units of 16 bytes + number of encryption invocations) 2116 // Value must be greater than minimum of (0x7FFFFFF). 2117 // This value cannot be changed at runtime, only via this registry key at boot time. 2118 // 2119 #define NV_REG_STR_RM_CONF_COMPUTE_KEY_ROTATION_INTERNAL_THRESHOLD "RmKeyRotationInternalThreshold" 2120 2121 // 2122 // Set lower threshold for dummy key rotation. 2123 // This is a temp reg key that will be removed once all RM clients 2124 // support prod key rotation. 2125 // Value is in seconds. 2126 // 2127 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_LOWER_THRESHOLD "RmDummyKeyRotationLowerThreshold" 2128 2129 // 2130 // Set upper threshold for dummy key rotation. 2131 // This is a temp reg key that will be removed once all RM clients 2132 // support prod key rotation. 2133 // Value is in seconds. 2134 // 2135 #define NV_REG_STR_RM_CONF_COMPUTE_DUMMY_KEY_ROTATION_UPPER_THRESHOLD "RmDummyKeyRotationUpperThreshold" 2136 2137 // TYPE Dword 2138 // Encoding boolean 2139 // Regkey based solution to serialize VBlank Aggressive Handling in Top Half using spinlock 2140 // 2 - Enable serialization of aggressive vblank callbacks when HMD is active 2141 // 2142 // 2143 // 1 - Enable serialization of aggressive vblank callbacks in all scenarios 2144 // (even when a HMD is not active) 2145 // 2146 // 0 - (default) Disable WAR 2147 // This regkey settings are enabled when Aggressive Vblanks are enabled, 2148 // if RmDisableAggressiveVblank is set to disable then these regkeys do not have any affect 2149 #define NV_REG_STR_RM_BUG_2089053_WAR "RmBug2089053War" 2150 #define NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ON_HMD_ACTIVE_ONLY 0x00000002 2151 #define NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ALWAYS 0x00000001 2152 #define NV_REG_STR_RM_BUG_2089053_WAR_DISABLE 0x00000000 2153 #define NV_REG_STR_RM_BUG_2089053_WAR_DEFAULT (NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ALWAYS) 2154 2155 // 2156 // Controls whether GSP-RM profiling is enabled. 2157 // 0 (default): disabled 2158 // 1: enabled 2159 // 2160 #define NV_REG_STR_RM_GSPRM_PROFILING "RmGspRmProfiling" 2161 #define NV_REG_STR_RM_GSPRM_PROFILING_DISABLE 0 2162 #define NV_REG_STR_RM_GSPRM_PROFILING_ENABLE 1 2163 2164 // 2165 // Controls, GSP-RM start with boost clocks. 2166 // 0 : disabled 2167 // 1 : enabled (default) 2168 // 2169 #define NV_REG_STR_RM_BOOT_GSPRM_WITH_BOOST_CLOCKS "RmBootGspRmWithBoostClocks" 2170 #define NV_REG_STR_RM_BOOT_GSPRM_WITH_BOOST_CLOCKS_DISABLED 0 2171 #define NV_REG_STR_RM_BOOT_GSPRM_WITH_BOOST_CLOCKS_ENABLED 1 2172 2173 // 2174 // Enable Local EGM HW verification using RM/SW stack. 2175 // Must be specified with a peerID corresponding to local EGM 2176 // 2177 #define NV_REG_STR_RM_ENABLE_LOCAL_EGM_PEER_ID "RMEnableLocalEgmPeerId" 2178 2179 // 2180 // Overrides the size of the GSP-RM firmware heap in GPU memory. 2181 // The GSP-RM firmware heap is reserved for system use and is not available to 2182 // applications. This regkey can be used to optimize the amount of memory 2183 // reserved for system use for targeted use cases. The default value for this 2184 // regkey is determined to support certain worst case resource allocation 2185 // patterns, but many use cases do not exhibit such resource allocation patterns 2186 // and could benefit from the lesser reserved GPU memory. Other use cases may 2187 // exhibit an even more pathological/stressful resource allocation pattern, 2188 // which can be enabled (up to a limit) with this regkey. 2189 // 2190 // However, NVIDIA does not support setting this registry key, and will require 2191 // that any bugs observed with it set be reproducible with the default setting 2192 // as well. 2193 // 2194 // The value of this regkey is specified in megabytes. A value of 0 indicates to 2195 // use the default value. Values less than the minimum or greater than the 2196 // maximum will be clamped to the nearest optimum. The default values are 2197 // are dynamically computed for each GPU prior to booting GSP-RM. 2198 // 2199 #define NV_REG_STR_GSP_FIRMWARE_HEAP_SIZE_MB "RmGspFirmwareHeapSizeMB" 2200 #define NV_REG_STR_GSP_FIRMWARE_HEAP_SIZE_MB_DEFAULT 0 2201 2202 // 2203 // Type DWORD 2204 // This regkey can be used to enable GSP owned fault buffers 2205 // 2206 #define NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE "RmGspOwnedFaultBuffersEnable" 2207 #define NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE_NO 0x00000000 2208 #define NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE_YES 0x00000001 2209 2210 // 2211 // WAR for BlueField3: Bug 4040336 2212 // BF3's PCI MMIO bus address 0x800000000000 is too high for Ampere to address. 2213 // Due to this, BF3's bus address is now moved to < 4GB. So, the CPU PA is no longer 2214 // the same as the bus address and this regkey adjusts the CPU PA passed in to the 2215 // correct bus address. 2216 // 2217 #define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3 "RmDmaAdjustPeerMmioBF3" 2218 #define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_DISABLE 0 2219 #define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_ENABLE 1 2220 2221 #define NV_REG_STR_RM_NVLINK_FORCED_LOOPBACK_ON_SWITCH "RMNvLinkForcedLoopbackOnSwitch" 2222 #define NV_REG_STR_RM_NVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE 0:0 2223 #define NV_REG_STR_RM_NVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE_DEFAULT (0x00000000) 2224 #define NV_REG_STR_RM_NVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE_ENABLED (0x00000001) 2225 2226 // 2227 // Type: Dword 2228 // Encoding: 2229 // 0 - Iterative MMU Walker is not enabled. Normal recursive implementation is used. (default) 2230 // 1 - Iterative MMU Walker is used 2231 // 2232 #define NV_REG_STR_RM_ITERATIVE_MMU_WALKER "RMUseIterativeMMUWalker" 2233 #define NV_REG_STR_RM_ITERATIVE_MMU_WALKER_DISABLED 0x00000000 2234 #define NV_REG_STR_RM_ITERATIVE_MMU_WALKER_ENABLED 0x00000001 2235 #define NV_REG_STR_RM_ITERATIVE_MMU_WALKER_DEFAULT NV_REG_STR_RM_ITERATIVE_MMU_WALKER_DISABLED 2236 2237 // 2238 // Type DWORD 2239 // This set of MIG regkeys specifies a set of allocation requests to be issued to the GPU on boot. 2240 // MIG configuration contained within GPUMGR always supersedes these regkeys, if present and valid. 2241 // The entire configuration specified by these regkeys is validated before being applied. An error 2242 // reflected in whole or in part on these regkeys will cause them to be discarded entirely. 2243 // 2244 // RmMIGBootConfigurationGI is used to encode a series of GPU instance allocations. These are applied in order. 2245 // RmMIGBootConfigurationCI is used to encode a series of CI instance allocations. 2246 // The GI associated with each CI allocation entry is specified by RmMIGBootConfigurationCIAssignment. 2247 // It is an error to specify a CI via RmMIGBootConfigurationCI without specifying the associated GPU 2248 // instance entry via RmMIGBootConfigurationCIAssignment. The values for any CI assignment for a CI 2249 // entry left unspecified must be 0. 2250 // 2251 // RmMIGBootConfigurationGI_N 2252 // _FLAGS - determines granularity of GPU partitioning. See NV2080_CTRL_CMD_GPU_SET_PARTITIONS 2253 // _PLACEMENT_LO - Optional placement span to allocate the partition into. Unused if HI<LO 2254 // _PLACEMENT_HI - Optional placement span to allocate the partition into. Unused if HI<LO 2255 // _REQ_DEC_JPG_OFA - For single slice instances, request at least 1 video decode, jpeg, and optical flow engine 2256 // 2257 // RmMIGBootConfigurationCI_N 2258 // _FLAGS - determines granularity of GPU partitioning. Subset of the GI flags - only the compute size flags are used here. See NV2080_CTRL_CMD_GPU_SET_PARTITIONS 2259 // _PLACEMENT_LO - Starting slice in GPU instance 2260 // _CES - # Copy engines to share with other CIs in this GI. 0 denotes all available. 2261 // _DECS - # video decoder engines to share with other CIs in this GI. 0 denotes all available. 2262 // _ENCS - # video decoder engines to share with other CIs in this GI. 0 denotes all available. 2263 // _JPGS - # jpeg engines to share with other CIs in this GI. 0 denotes all available. 2264 // _OFAS - # optical flow engines to share with other CIs in this GI. 0 denotes all available. 2265 // 2266 // RmMIGBootConfigurationCIAssignment 2267 // _GI(n) - Assign Compute instance n to GPU instance entry according to this value 2268 // 2269 // RmMIGBootConfigurationFeatureFlags 2270 // _AUTO_UPDATE - Windows only. RM updates the regkeys at runtime as MIG configuration changes. 2271 // 2272 2273 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI(n) "RmMIGBootConfigurationGI_" #n 2274 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI__SIZE 8 2275 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI_FLAGS 7:0 2276 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI_PLACEMENT_LO 15:8 2277 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI_PLACEMENT_HI 23:16 2278 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI_REQ_DEC_JPG_OFA 31:31 2279 2280 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI(n) "RmMIGBootConfigurationCI_" #n 2281 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI__SIZE 8 2282 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_FLAGS 7:0 2283 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_PLACEMENT_LO 11:8 2284 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_CES 15:12 2285 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_DECS 19:16 2286 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_ENCS 23:20 2287 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_JPGS 27:24 2288 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_OFAS 31:28 2289 2290 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_ASSIGNMENT "RmMIGBootConfigurationCIAssignment" 2291 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_ASSIGNMENT_GI(n) ((4 * ((n) + 1)) - 1):(4 * (n)) 2292 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_ASSIGNMENT_GI__SIZE 8 2293 2294 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS "RmMIGBootConfigurationFeatureFlags" 2295 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_SUPPORTED 0:0 2296 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_SUPPORTED_DEFAULT 0x0 2297 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_SUPPORTED_FALSE 0x0 2298 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_SUPPORTED_TRUE 0x1 2299 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_AUTO_UPDATE 1:1 2300 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_AUTO_UPDATE_DEFAULT 0x0 2301 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_AUTO_UPDATE_DISABLED 0x0 2302 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_AUTO_UPDATE_ENABLED 0x1 2303 2304 // 2305 // Type: DWORD 2306 // 2307 // If the midpath spinning feature of the GPU lock is enabled. 2308 // 2309 // 0 (default) - Midpath Spinning disabled 2310 // 1 - Midpath spinning enabled 2311 // 2312 #define NV_REG_STR_RM_GPU_LOCK_MIDPATH "RMGpuLockMidpath" 2313 #define NV_REG_STR_RM_GPU_LOCK_MIDPATH_DISABLED 0x00000000 2314 #define NV_REG_STR_RM_GPU_LOCK_MIDPATH_ENABLED 0x00000001 2315 2316 // 2317 // This regkey controls the GPU load failure test. 2318 // Supported only on DEBUG, DEVELOP, or RELEASE drivers built with the parameter INSTRUMENT_RM=true 2319 // This is an input/output registry key. 2320 // NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_START: input - start the text at the specified stage and engine index. 2321 // Typically when the test starts, it is with NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_PREINIT + ENGINEINDEX = 0 2322 // NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_RUNNING: output - the test is running. 2323 // The next stage and engine index are specified 2324 // The test executable just needs to change NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_NEXT to _START for the next step 2325 // NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_FINISHED: output - there is no morre stages and engines to test 2326 // 2327 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST "RmGpuLoadFailureTest" 2328 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS 1:0 2329 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_NONE 0x00000000 2330 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_START 0x00000001 2331 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_RUNNING 0x00000002 2332 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STATUS_FINISHED 0x00000003 2333 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE 4:2 2334 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_PREINIT 0x00000000 2335 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_INIT 0x00000001 2336 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_PRELOAD 0x00000002 2337 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_LOAD 0x00000003 2338 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_POSTLOAD 0x00000004 2339 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_ENGINEINDEX 31:5 2340 2341 // 2342 // Type: DWORD 2343 // Encoding: 2344 // 0 - Disable MIG auto online mode on driver load 2345 // 1 - Enable MIG auto online mode on driver load 2346 // 2347 #define NV_REG_STR_RM_SET_MIG_AUTO_ONLINE_MODE "RMSetMIGAutoOnlineMode" 2348 #define NV_REG_STR_RM_SET_MIG_AUTO_ONLINE_MODE_DISABLED 0 2349 #define NV_REG_STR_RM_SET_MIG_AUTO_ONLINE_MODE_ENABLED 1 2350 2351 // 2352 // Type: DWORD 2353 // Encoding: 2354 // 0 - Disable multi gpu mode 2355 // 1 - Enable protected pcie 2356 // 2357 #define NV_REG_STR_RM_CC_MULTI_GPU_MODE "RmCCMultiGpuMode" 2358 #define NV_REG_STR_RM_CC_MULTI_GPU_MODE_NONE 0x00000000 2359 #define NV_REG_STR_RM_CC_MULTI_GPU_MODE_PROTECTED_PCIE 0x00000001 2360 2361 // This regkey allows RM to access CPR vidmem over BARs when HCC devtools mode is ON 2362 #define NV_REG_STR_RM_FORCE_BAR_ACCESS_ON_HCC "RmForceBarAccessOnHcc" 2363 #define NV_REG_STR_RM_FORCE_BAR_ACCESS_ON_HCC_NO 0x00000000 2364 #define NV_REG_STR_RM_FORCE_BAR_ACCESS_ON_HCC_YES 0x00000001 2365 2366 // 2367 // TYPE DWORD 2368 // This regkey allows to change the state of NVENC sessions stats reporting. 2369 // Note : Currently only used and works for Grid. 2370 // 0 - Disable NVENC session stats reporting. 2371 // 1 - Enable NVENC session stats reporting. 2372 // 2373 #define NV_REG_STR_RM_NVENC_SESSION_STATS_REPORTING_STATE "EncSessionStatsReportingState" 2374 #define NV_REG_STR_RM_NVENC_SESSION_STATS_REPORTING_STATE_DISABLED 0x00000000 2375 #define NV_REG_STR_RM_NVENC_SESSION_STATS_REPORTING_STATE_ENABLED 0x00000001 2376 2377 // TYPE DWORD 2378 // Set to provide ECC state in guest 2379 // Used for vGPU 2380 // The value default is set if ECC is enabled in USM profile. 2381 // 2382 #define NV_REG_STR_RM_GUEST_ECC_STATE "RMGuestECCState" 2383 #define NV_REG_STR_RM_GUEST_ECC_STATE_DISABLED 0x00000000 2384 #define NV_REG_STR_RM_GUEST_ECC_STATE_ENABLED 0x00000001 2385 #define NV_REG_STR_RM_GUEST_ECC_STATE_DEFAULT 0x00000001 2386 2387 // 2388 // TYPE DWORD 2389 // This regkey allows to enable RM test only code paths 2390 // 0 - Disable RM test only code 2391 // 1 - Enable RM test only code 2392 // 2393 #define NV_REG_STR_RM_ENABLE_RM_TEST_ONLY_CODE "EnableRmTestOnlyCode" 2394 #define NV_REG_STR_RM_ENABLE_RM_TEST_ONLY_CODE_DISABLED 0x00000000 2395 #define NV_REG_STR_RM_ENABLE_RM_TEST_ONLY_CODE_ENABLED 0x00000001 2396 2397 // 2398 // Type DWORD 2399 // This regkey force-disables write-combine iomap allocations, used for chipsets where 2400 // write-combine is broken. 2401 // 2402 #define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC "RmForceDisableIomapWC" 2403 #define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_YES 0x00000001 2404 #define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_NO 0x00000000 2405 #define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_DEFAULT NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_NO 2406 2407 // 2408 // TYPE DWORD 2409 // This regkey will increase the margin after the end of WPR2 when booting GSP-RM. 2410 // 2411 // This margin can be used to help GSP firmware boot in the presence of ECC 2412 // errors which might affect the default GSP firmware image location in the GPU 2413 // framebuffer. If GPU firmware is able to successfully boot with this registry 2414 // key enabled, it should scan the margin area to attempt to handle ECC errors in 2415 // the region, so that the region can be safely used in a subsequent boot. 2416 // 2417 // NV_REG_RM_GSP_WPR_END_MARGIN_MB 2418 // Possible values: 2419 // 0 - (Default) use the default calculated GSP WPR size 2420 // 1+ - size of the end margin in megabytes 2421 // 2422 // NV_REG_RM_GSP_WPR_END_MARGIN_APPLY 2423 // Possible values: 2424 // _ON_RETRY (0) - (Default) only increase the margin to the requested size 2425 // when retrying GSP firmware boot after a failed boot attempt 2426 // _ALWAYS (1) - increase the margin to the requested size for all GSP 2427 // firmware boot attempts, including the first 2428 // 2429 #define NV_REG_STR_RM_GSP_WPR_END_MARGIN "RmGspWprEndMargin" 2430 #define NV_REG_RM_GSP_WPR_END_MARGIN_MB 30:0 2431 #define NV_REG_RM_GSP_WPR_END_MARGIN_APPLY 31:31 2432 #define NV_REG_RM_GSP_WPR_END_MARGIN_APPLY_ON_RETRY 0x00000000 2433 #define NV_REG_RM_GSP_WPR_END_MARGIN_APPLY_ALWAYS 0x00000001 2434 // 2435 // Type: Dword 2436 // This regkey toggles whether to release API lock during initialization to 2437 // allow multiple GPUS to initialize in parallel 2438 // 0 - API lock will not be released 2439 // 1 - API lock will be released 2440 // 2 - API lock release determined by platform (default) 2441 // 2442 #define NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING "RmRelaxedGspInitLocking" 2443 #define NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_DISABLE 0x00000000 2444 #define NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_ENABLE 0x00000001 2445 #define NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_DEFAULT 0x00000002 2446 2447 // 2448 // Regkey to configure Per VM RunList. 2449 // Type Dword 2450 // BIT 0:0 - Overall PVMRL enable/disable. 2451 // 0 - Disable / Default - 1 HW runlist per engine. 2452 // 1 - Enable - 1 SW runlist per VM for some engines. 2453 // BIT 1:1 - Adaptive Round Robin Scheduler 2454 // 0 - Enable / Default - Use Adaptive Round Robin Scheduler 2455 // 1 - Disable - Use Legacy PVMRL 2456 // BIT 7:4 - PVMRL scheduler to run. 2457 // 0 - equal share / Default - equal share amongst running vGPUs. 2458 // 1 - fixed share - fixed share of the physical GPU. 2459 // BIT 21:12 - PVMRL Scheduling frequency. 2460 // 0 - Default timeslice. 2461 // F - Timeslice = 1000 / F. 2462 // BIT 23:16 - PVMRL timeslice in ms (Milli-seconds). 2463 // 0 - Default timeslice. 2464 // T - Timeslice of T ms. 2465 // BIT 31:24 - ARR Average Factor 2466 // 0 - Default Average Factor 2467 // F - Average Factor = F 2468 // 2469 #define NV_REG_STR_RM_PVMRL "RmPVMRL" 2470 #define NV_REG_STR_RM_PVMRL_ENABLE 0:0 2471 #define NV_REG_STR_RM_PVMRL_ENABLE_DEFAULT 0x00000000 2472 #define NV_REG_STR_RM_PVMRL_ENABLE_NO 0x00000000 2473 #define NV_REG_STR_RM_PVMRL_ENABLE_YES 0x00000001 2474 #define NV_REG_STR_RM_PVMRL_ARR_DISABLE 1:1 2475 #define NV_REG_STR_RM_PVMRL_ARR_DISABLE_DEFAULT 0x00000000 2476 #define NV_REG_STR_RM_PVMRL_ARR_DISABLE_NO 0x00000000 2477 #define NV_REG_STR_RM_PVMRL_ARR_DISABLE_YES 0x00000001 2478 #define NV_REG_STR_RM_PVMRL_SCHED_POLICY 7:4 2479 #define NV_REG_STR_RM_PVMRL_SCHED_POLICY_DEFAULT 0x00000000 2480 #define NV_REG_STR_RM_PVMRL_SCHED_POLICY_VGPU_EQUAL_SHARE 0x00000000 2481 #define NV_REG_STR_RM_PVMRL_SCHED_POLICY_VGPU_FIXED_SHARE 0x00000001 2482 #define NV_REG_STR_RM_PVMRL_FREQUENCY 21:12 2483 #define NV_REG_STR_RM_PVMRL_TIMESLICE 23:16 2484 #define NV_REG_STR_RM_PVMRL_AVERAGE_FACTOR 31:24 2485 2486 // 2487 // Type: Dword 2488 // This regkey is used to enable Nvlink Encryption. By default it is disabled 2489 // 2490 #define NV_REG_STR_RM_NVLINK_ENCRYPTION "RmNvlinkEncryption" 2491 #define NV_REG_STR_RM_NVLINK_ENCRYPTION_MODE 0:0 2492 #define NV_REG_STR_RM_NVLINK_ENCRYPTION_MODE_DEFAULT 0x00000000 2493 #define NV_REG_STR_RM_NVLINK_ENCRYPTION_MODE_ENABLE 0x00000001 2494 2495 // 2496 // Type: Dword 2497 // This regkey overrides the state of the GR scrubber channel and determines 2498 // whether it should be created or not. 2499 // 2500 #define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL "RmForceGrScrubberChannel" 2501 #define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL_DISABLE 0x00000000 2502 #define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL_ENABLE 0x00000001 2503 2504 #define NV_REG_STR_RM_DISABLE_FSP_FUSE_ERROR_CHECK "RmDisableFspFuseErrorCheck" 2505 #define NV_REG_STR_RM_DISABLE_FSP_FUSE_ERROR_CHECK_YES (0x00000001) 2506 #define NV_REG_STR_RM_DISABLE_FSP_FUSE_ERROR_CHECK_NO (0x00000000) 2507 #define NV_REG_STR_RM_DISABLE_FSP_FUSE_ERROR_CHECK_DEFAULT (0x00000000) 2508 // Type DWORD (Boolean) 2509 // Disable the check for FSP's fuse error detection status during boot. 2510 // By default, the check would be enabled and we would bail out during boot on error. 2511 2512 #endif // NVRM_REGISTRY_H 2513