1 /* 2 * PROJECT: ReactOS nVidia nForce Ethernet Controller Driver 3 * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later) 4 * PURPOSE: Hardware specific definitions 5 * COPYRIGHT: Copyright 2021-2022 Dmitry Borisov <di.sean@protonmail.com> 6 */ 7 8 /* 9 * Definitions were taken from the Linux forcedeth driver 10 * Copyright (C) 2003,4,5 Manfred Spraul 11 * Copyright (C) 2004 Andrew de Quincey 12 * Copyright (C) 2004 Carl-Daniel Hailfinger 13 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation 14 */ 15 16 #pragma once 17 18 #define DEV_NEED_TIMERIRQ 0x00000001 /* Set the timer IRQ flag in the IRQ mask */ 19 #define DEV_NEED_LINKTIMER 0x00000002 /* Poll link settings. Relies on the timer IRQ */ 20 #define DEV_HAS_LARGEDESC 0x00000004 /* Device supports Jumbo Frames 21 * and needs packet format 2 */ 22 #define DEV_HAS_HIGH_DMA 0x00000008 /* Device supports 64-bit DMA */ 23 #define DEV_HAS_CHECKSUM 0x00000010 /* Device supports TX and RX checksum offloads */ 24 #define DEV_HAS_VLAN 0x00000020 /* Device supports VLAN tagging and striping */ 25 #define DEV_HAS_MSI 0x00000040 /* Device supports MSI */ 26 #define DEV_HAS_MSI_X 0x00000080 /* Device supports MSI-X */ 27 #define DEV_HAS_POWER_CNTRL 0x00000100 /* Device supports power savings */ 28 #define DEV_HAS_STATISTICS_V1 0x00000200 /* Device supports HW statistics version 1 */ 29 #define DEV_HAS_STATISTICS_V2 0x00000400 /* Device supports HW statistics version 2 */ 30 #define DEV_HAS_STATISTICS_V3 0x00000800 /* Device supports HW statistics version 3 */ 31 #define DEV_HAS_TEST_EXTENDED 0x00001000 /* Device supports extended diagnostic test */ 32 #define DEV_HAS_MGMT_UNIT 0x00002000 /* Device supports management unit */ 33 #define DEV_HAS_CORRECT_MACADDR 0x00004000 /* Device supports correct MAC address order */ 34 #define DEV_HAS_COLLISION_FIX 0x00008000 /* Device supports TX collision fix */ 35 #define DEV_HAS_PAUSEFRAME_TX_V1 0x00010000 /* Device supports TX pause frames version 1 */ 36 #define DEV_HAS_PAUSEFRAME_TX_V2 0x00020000 /* Device supports TX pause frames version 2 */ 37 #define DEV_HAS_PAUSEFRAME_TX_V3 0x00040000 /* Device supports TX pause frames version 3 */ 38 #define DEV_NEED_TX_LIMIT 0x00080000 /* Device needs to limit TX */ 39 #define DEV_NEED_TX_LIMIT2 0x00100000 /* Device needs to limit TX, expect for some revs */ 40 #define DEV_HAS_GEAR_MODE 0x00200000 /* Device supports gear mode */ 41 #define DEV_NEED_PHY_INIT_FIX 0x00400000 /* Device needs specific PHY workaround */ 42 #define DEV_NEED_LOW_POWER_FIX 0x00800000 /* Device needs special power up workaround */ 43 #define DEV_NEED_MSI_FIX 0x01000000 /* Device needs MSI workaround */ 44 45 #define DEV_HAS_STATISTICS_COUNTERS (DEV_HAS_STATISTICS_V1 | DEV_HAS_STATISTICS_V2 | \ 46 DEV_HAS_STATISTICS_V3) 47 #define DEV_HAS_TX_PAUSEFRAME (DEV_HAS_PAUSEFRAME_TX_V1 | DEV_HAS_PAUSEFRAME_TX_V2 | \ 48 DEV_HAS_PAUSEFRAME_TX_V3) 49 50 typedef enum _NVNET_REGISTER 51 { 52 NvRegIrqStatus = 0x000, 53 #define NVREG_IRQSTAT_MIIEVENT 0x040 54 #define NVREG_IRQSTAT_MASK 0x83ff 55 56 NvRegIrqMask = 0x004, 57 #define NVREG_IRQ_RX_ERROR 0x0001 58 #define NVREG_IRQ_RX 0x0002 59 #define NVREG_IRQ_RX_NOBUF 0x0004 60 #define NVREG_IRQ_TX_ERR 0x0008 61 #define NVREG_IRQ_TX_OK 0x0010 62 #define NVREG_IRQ_TIMER 0x0020 63 #define NVREG_IRQ_LINK 0x0040 64 #define NVREG_IRQ_RX_FORCED 0x0080 65 #define NVREG_IRQ_TX_FORCED 0x0100 66 #define NVREG_IRQ_RECOVER_ERROR 0x8200 67 #define NVREG_IRQMASK_THROUGHPUT 0x00df 68 #define NVREG_IRQMASK_CPU 0x0060 69 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) 70 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF| \ 71 NVREG_IRQ_RX_FORCED) 72 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR) 73 74 NvRegUnknownSetupReg6 = 0x008, 75 #define NVREG_UNKSETUP6_VAL 3 76 77 NvRegPollingInterval = 0x00c, 78 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 79 #define NVREG_POLL_DEFAULT_CPU 13 80 81 NvRegMSIMap0 = 0x020, 82 NvRegMSIMap1 = 0x024, 83 84 NvRegMSIIrqMask = 0x030, 85 #define NVREG_MSI_VECTOR_0_ENABLED 0x01 86 87 NvRegMacReset = 0x34, 88 #define NVREG_MAC_RESET_ASSERT 0x0F3 89 90 NvRegMisc1 = 0x080, 91 #define NVREG_MISC1_PAUSE_TX 0x01 92 #define NVREG_MISC1_HD 0x02 93 #define NVREG_MISC1_FORCE 0x3b0f3c 94 95 NvRegTransmitterControl = 0x084, 96 #define NVREG_XMITCTL_START 0x01 97 #define NVREG_XMITCTL_MGMT_ST 0x40000000 98 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000 99 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0 100 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000 101 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00 102 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0 103 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000 104 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000 105 #define NVREG_XMITCTL_HOST_LOADED 0x00004000 106 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000 107 #define NVREG_XMITCTL_DATA_START 0x00100000 108 #define NVREG_XMITCTL_DATA_READY 0x00010000 109 #define NVREG_XMITCTL_DATA_ERROR 0x00020000 110 111 NvRegTransmitterStatus = 0x088, 112 #define NVREG_XMITSTAT_BUSY 0x01 113 114 NvRegPacketFilterFlags = 0x8c, 115 #define NVREG_PFF_PAUSE_RX 0x08 116 #define NVREG_PFF_ALWAYS 0x7F0000 117 #define NVREG_PFF_PROMISC 0x80 118 #define NVREG_PFF_MYADDR 0x20 119 #define NVREG_PFF_LOOPBACK 0x10 120 121 NvRegOffloadConfig = 0x90, 122 #define NVREG_OFFLOAD_HOMEPHY 0x601 123 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE 124 125 NvRegReceiverControl = 0x094, 126 #define NVREG_RCVCTL_START 0x01 127 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000 128 129 NvRegReceiverStatus = 0x98, 130 #define NVREG_RCVSTAT_BUSY 0x01 131 132 NvRegSlotTime = 0x9c, 133 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000 134 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00 135 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00 136 #define NVREG_SLOTTIME_HALF 0x0000ff00 137 #define NVREG_SLOTTIME_DEFAULT 0x00007f00 138 #define NVREG_SLOTTIME_MASK 0x000000ff 139 140 NvRegTxDeferral = 0xA0, 141 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f 142 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f 143 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f 144 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f 145 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f 146 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000 147 148 NvRegRxDeferral = 0xA4, 149 #define NVREG_RX_DEFERRAL_DEFAULT 0x16 150 151 NvRegMacAddrA = 0xA8, 152 NvRegMacAddrB = 0xAC, 153 154 NvRegMulticastAddrA = 0xB0, 155 NvRegMulticastAddrB = 0xB4, 156 #define NVREG_MCASTADDRA_FORCE 0x01 157 158 NvRegMulticastMaskA = 0xB8, 159 #define NVREG_MCASTMASKA_NONE 0xffffffff 160 161 NvRegMulticastMaskB = 0xBC, 162 #define NVREG_MCASTMASKB_NONE 0xffff 163 164 NvRegPhyInterface = 0xC0, 165 #define PHY_100 0x1 166 #define PHY_1000 0x2 167 #define PHY_HALF 0x100 168 #define PHY_RGMII 0x10000000 169 170 NvRegBackOffControl = 0xC4, 171 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000 172 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff 173 #define NVREG_BKOFFCTRL_SELECT 24 174 #define NVREG_BKOFFCTRL_GEAR 12 175 176 NvRegTxRingPhysAddr = 0x100, 177 NvRegRxRingPhysAddr = 0x104, 178 179 NvRegRingSizes = 0x108, 180 #define NVREG_RINGSZ_TXSHIFT 0 181 #define NVREG_RINGSZ_RXSHIFT 16 182 183 NvRegTransmitPoll = 0x10c, 184 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000 185 186 NvRegLinkSpeed = 0x110, 187 #define NVREG_LINKSPEED_FORCE 0x10000 188 #define NVREG_LINKSPEED_10 1000 189 #define NVREG_LINKSPEED_100 100 190 #define NVREG_LINKSPEED_1000 50 191 #define NVREG_LINKSPEED_MASK (0xFFF) 192 193 NvRegUnknownSetupReg5 = 0x130, 194 #define NVREG_UNKSETUP5_BIT31 (1<<31) 195 196 NvRegTxWatermark = 0x13c, 197 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010 198 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000 199 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000 200 201 NvRegTxRxControl = 0x144, 202 #define NVREG_TXRXCTL_KICK 0x0001 203 #define NVREG_TXRXCTL_BIT1 0x0002 204 #define NVREG_TXRXCTL_BIT2 0x0004 205 #define NVREG_TXRXCTL_IDLE 0x0008 206 #define NVREG_TXRXCTL_RESET 0x0010 207 #define NVREG_TXRXCTL_RXCHECK 0x0400 208 #define NVREG_TXRXCTL_DESC_1 0 209 #define NVREG_TXRXCTL_DESC_2 0x002100 210 #define NVREG_TXRXCTL_DESC_3 0xc02200 211 #define NVREG_TXRXCTL_VLANSTRIP 0x00040 212 #define NVREG_TXRXCTL_VLANINS 0x00080 213 214 NvRegTxRingPhysAddrHigh = 0x148, 215 NvRegRxRingPhysAddrHigh = 0x14C, 216 217 NvRegTxPauseFrame = 0x170, 218 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080 219 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010 220 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0 221 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880 222 223 NvRegTxPauseFrameLimit = 0x174, 224 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000 225 226 NvRegMIIStatus = 0x180, 227 #define NVREG_MIISTAT_ERROR 0x0001 228 #define NVREG_MIISTAT_LINKCHANGE 0x0008 229 #define NVREG_MIISTAT_MASK_RW 0x0007 230 #define NVREG_MIISTAT_MASK_ALL 0x000f 231 232 NvRegMIIMask = 0x184, 233 #define NVREG_MII_LINKCHANGE 0x0008 234 235 NvRegAdapterControl = 0x188, 236 #define NVREG_ADAPTCTL_START 0x02 237 #define NVREG_ADAPTCTL_LINKUP 0x04 238 #define NVREG_ADAPTCTL_PHYVALID 0x40000 239 #define NVREG_ADAPTCTL_RUNNING 0x100000 240 #define NVREG_ADAPTCTL_PHYSHIFT 24 241 242 NvRegMIISpeed = 0x18c, 243 #define NVREG_MIISPEED_BIT8 (1<<8) 244 #define NVREG_MIIDELAY 5 245 246 NvRegMIIControl = 0x190, 247 #define NVREG_MIICTL_INUSE 0x08000 248 #define NVREG_MIICTL_WRITE 0x00400 249 #define NVREG_MIICTL_ADDRSHIFT 5 250 251 NvRegMIIData = 0x194, 252 NvRegTxUnicast = 0x1a0, 253 NvRegTxMulticast = 0x1a4, 254 NvRegTxBroadcast = 0x1a8, 255 256 NvRegWakeUpFlags = 0x200, 257 #define NVREG_WAKEUPFLAGS_VAL 0x7770 258 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 259 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 260 #define NVREG_WAKEUPFLAGS_D3SHIFT 12 261 #define NVREG_WAKEUPFLAGS_D2SHIFT 8 262 #define NVREG_WAKEUPFLAGS_D1SHIFT 4 263 #define NVREG_WAKEUPFLAGS_D0SHIFT 0 264 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 265 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 266 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 267 #define NVREG_WAKEUPFLAGS_ENABLE_MAGPAT 0x1111 268 #define NVREG_WAKEUPFLAGS_ENABLE_WAKEUPPAT 0x2222 269 #define NVREG_WAKEUPFLAGS_ENABLE_LINKCHANGE 0x4444 270 271 NvRegPatternCrc = 0x204, 272 NvRegPatternMask0 = 0x208, 273 NvRegPatternMask1 = 0x20C, 274 NvRegPatternMask2 = 0x210, 275 NvRegPatternMask3 = 0x214, 276 277 NvRegMgmtUnitGetVersion = 0x204, 278 #define NVREG_MGMTUNITGETVERSION 0x01 279 280 NvRegMgmtUnitVersion = 0x208, 281 #define NVREG_MGMTUNITVERSION 0x08 282 283 NvRegPowerCap = 0x268, 284 #define NVREG_POWERCAP_D3SUPP (1<<30) 285 #define NVREG_POWERCAP_D2SUPP (1<<26) 286 #define NVREG_POWERCAP_D1SUPP (1<<25) 287 288 NvRegPowerState = 0x26c, 289 #define NVREG_POWERSTATE_POWEREDUP 0x8000 290 #define NVREG_POWERSTATE_VALID 0x0100 291 #define NVREG_POWERSTATE_MASK 0x0003 292 #define NVREG_POWERSTATE_D0 0x0000 293 #define NVREG_POWERSTATE_D1 0x0001 294 #define NVREG_POWERSTATE_D2 0x0002 295 #define NVREG_POWERSTATE_D3 0x0003 296 297 NvRegMgmtUnitControl = 0x278, 298 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000 299 300 NvRegTxCnt = 0x280, 301 NvRegTxZeroReXmt = 0x284, 302 NvRegTxOneReXmt = 0x288, 303 NvRegTxManyReXmt = 0x28c, 304 NvRegTxLateCol = 0x290, 305 NvRegTxUnderflow = 0x294, 306 NvRegTxLossCarrier = 0x298, 307 NvRegTxExcessDef = 0x29c, 308 NvRegTxRetryErr = 0x2a0, 309 NvRegRxFrameErr = 0x2a4, 310 NvRegRxExtraByte = 0x2a8, 311 NvRegRxLateCol = 0x2ac, 312 NvRegRxRunt = 0x2b0, 313 NvRegRxFrameTooLong = 0x2b4, 314 NvRegRxOverflow = 0x2b8, 315 NvRegRxFCSErr = 0x2bc, 316 NvRegRxFrameAlignErr = 0x2c0, 317 NvRegRxLenErr = 0x2c4, 318 NvRegRxUnicast = 0x2c8, 319 NvRegRxMulticast = 0x2cc, 320 NvRegRxBroadcast = 0x2d0, 321 NvRegTxDef = 0x2d4, 322 NvRegTxFrame = 0x2d8, 323 NvRegRxCnt = 0x2dc, 324 NvRegTxPause = 0x2e0, 325 NvRegRxPause = 0x2e4, 326 NvRegRxDropFrame = 0x2e8, 327 328 NvRegVlanControl = 0x300, 329 #define NVREG_VLANCONTROL_ENABLE 0x2000 330 331 NvRegMSIXMap0 = 0x3e0, 332 NvRegMSIXMap1 = 0x3e4, 333 NvRegMSIXIrqStatus = 0x3f0, 334 335 NvRegPowerState2 = 0x600, 336 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15 337 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 338 #define NVREG_POWERSTATE2_PHY_RESET 0x0004 339 #define NVREG_POWERSTATE2_GATE_CLOCK_1 0x0100 340 #define NVREG_POWERSTATE2_GATE_CLOCK_2 0x0200 341 #define NVREG_POWERSTATE2_GATE_CLOCK_3 0x0400 342 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00 343 #define NVREG_POWERSTATE2_WAKEUPPAT_5 (1<<16) 344 #define NVREG_POWERSTATE2_WAKEUPPAT_6 (1<<17) 345 #define NVREG_POWERSTATE2_WAKEUPPAT_7 (1<<18) 346 347 NvRegPatternCrcEx = 0x604, 348 NvRegPatternMask0Ex = 0x608, 349 NvRegPatternMask1Ex = 0x60C, 350 NvRegPatternMask2Ex = 0x610, 351 NvRegPatternMask3Ex = 0x614 352 } NVNET_REGISTER; 353 354 #include <pshpack1.h> 355 typedef struct _NVNET_DESCRIPTOR_32 356 { 357 ULONG Address; 358 ULONG FlagsLength; 359 } NVNET_DESCRIPTOR_32, *PNVNET_DESCRIPTOR_32; 360 361 typedef struct _NVNET_DESCRIPTOR_64 362 { 363 ULONG AddressHigh; 364 ULONG AddressLow; 365 ULONG VlanTag; 366 ULONG FlagsLength; 367 } NVNET_DESCRIPTOR_64, *PNVNET_DESCRIPTOR_64; 368 #include <poppack.h> 369 370 #define FLAG_MASK_V1 0xffff0000 371 #define FLAG_MASK_V2 0xffffc000 372 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) 373 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) 374 375 #define NV_TX_LASTPACKET (1<<16) 376 #define NV_TX_RETRYERROR (1<<19) 377 #define NV_TX_RETRYCOUNT_MASK (0xF<<20) 378 #define NV_TX_ONE_RETRY (1<<20) 379 #define NV_TX_FORCED_INTERRUPT (1<<24) 380 #define NV_TX_DEFERRED (1<<26) 381 #define NV_TX_CARRIERLOST (1<<27) 382 #define NV_TX_LATECOLLISION (1<<28) 383 #define NV_TX_UNDERFLOW (1<<29) 384 #define NV_TX_ERROR (1<<30) 385 #define NV_TX_VALID (1<<31) 386 387 #define NV_TX2_LASTPACKET (1<<29) 388 #define NV_TX2_RETRYERROR (1<<18) 389 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19) 390 #define NV_TX2_FORCED_INTERRUPT (1<<30) 391 #define NV_TX2_DEFERRED (1<<25) 392 #define NV_TX2_CARRIERLOST (1<<26) 393 #define NV_TX2_LATECOLLISION (1<<27) 394 #define NV_TX2_UNDERFLOW (1<<28) 395 /* Error and valid are the same for both */ 396 #define NV_TX2_ERROR (1<<30) 397 #define NV_TX2_VALID (1<<31) 398 #define NV_TX2_TSO (1<<28) 399 #define NV_TX2_TSO_SHIFT 14 400 #define NV_TX2_TSO_MAX_SHIFT 14 401 #define NV_TX2_CHECKSUM_L3 (1<<27) 402 #define NV_TX2_CHECKSUM_L4 (1<<26) 403 404 #define NV_MAXIMUM_SG_SIZE (1<<NV_TX2_TSO_MAX_SHIFT) 405 406 #define NV_TX3_VLAN_TAG_PRESENT (1<<18) 407 408 #define NV_RX_DESCRIPTORVALID (1<<16) 409 #define NV_RX_MISSEDFRAME (1<<17) 410 #define NV_RX_SUBTRACT1 (1<<18) 411 #define NV_RX_ERROR1 (1<<23) 412 #define NV_RX_ERROR2 (1<<24) 413 #define NV_RX_ERROR3 (1<<25) 414 #define NV_RX_ERROR4 (1<<26) 415 #define NV_RX_CRCERR (1<<27) 416 #define NV_RX_OVERFLOW (1<<28) 417 #define NV_RX_FRAMINGERR (1<<29) 418 #define NV_RX_ERROR (1<<30) 419 #define NV_RX_AVAIL (1<<31) 420 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR| \ 421 NV_RX_OVERFLOW|NV_RX_FRAMINGERR) 422 423 #define NV_RX2_CHECKSUMMASK (0x1C000000) 424 #define NV_RX2_CHECKSUM_IP (0x10000000) 425 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000) 426 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000) 427 #define NV_RX2_DESCRIPTORVALID (1<<29) 428 #define NV_RX2_SUBTRACT1 (1<<25) 429 #define NV_RX2_ERROR1 (1<<18) 430 #define NV_RX2_ERROR2 (1<<19) 431 #define NV_RX2_ERROR3 (1<<20) 432 #define NV_RX2_ERROR4 (1<<21) 433 #define NV_RX2_CRCERR (1<<22) 434 #define NV_RX2_OVERFLOW (1<<23) 435 #define NV_RX2_FRAMINGERR (1<<24) 436 /* Error and avail are the same for both */ 437 #define NV_RX2_ERROR (1<<30) 438 #define NV_RX2_AVAIL (1<<31) 439 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4| \ 440 NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR) 441 442 #define NV_RX3_VLAN_TAG_PRESENT (1<<16) 443 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) 444 445 #define NV_TXRX_RESET_DELAY 4 446 #define NV_TXSTOP_DELAY1 10 447 #define NV_TXSTOP_DELAY1MAX 500000 448 #define NV_TXSTOP_DELAY2 100 449 #define NV_TXIDLE_DELAY 10 450 #define NV_TXIDLE_ATTEMPTS 100000 451 #define NV_RXSTOP_DELAY1 10 452 #define NV_RXSTOP_DELAY1MAX 500000 453 #define NV_RXSTOP_DELAY2 100 454 #define NV_SETUP5_DELAY 5 455 #define NV_SETUP5_DELAYMAX 50000 456 #define NV_POWERUP_DELAY 5 457 #define NV_POWERUP_DELAYMAX 5000 458 #define NV_POWER_DELAY 50 459 #define NV_POWER_STALL 3000 460 #define NV_POWER_ATTEMPTS 20 461 #define NV_MIIBUSY_DELAY 50 462 #define NV_MIIPHY_DELAY 10 463 #define NV_MIIPHY_DELAYMAX 10000 464 #define NV_MAC_RESET_DELAY 64 465 466 #define NV_WAKEUPPATTERNS 5 467 #define NV_WAKEUPPATTERNS_V2 8 468 #define NV_WAKEUPMASKENTRIES 4 469 #define NV_PATTERN_V2_OFFSET 0x39C 470 471 /* RX/TX MAC address + type + VLAN + align + slack */ 472 #define NV_RX_HEADERS (64) 473 /* even more slack. */ 474 #define NV_RX_ALLOC_PAD (64) 475 476 #define PHY_OUI_MARVELL 0x5043 477 #define PHY_OUI_CICADA 0x03f1 478 #define PHY_OUI_VITESSE 0x01c1 479 #define PHY_OUI_REALTEK 0x0732 480 #define PHY_OUI_REALTEK2 0x0020 481 #define PHY_MODEL_REALTEK_8211 0x0110 482 #define PHY_MODEL_REALTEK_8201 0x0200 483 #define PHY_MODEL_MARVELL_E3016 0x0220 484 485 #define PHYID1_OUI_MASK 0x03ff 486 #define PHYID1_OUI_SHFT 6 487 #define PHYID2_MODEL_MASK 0x03f0 488 #define PHYID2_OUI_MASK 0xfc00 489 #define PHYID2_OUI_SHFT 10 490 491 #define PHY_GIGABIT 0x0100 492 493 #define PHY_CICADA_INIT_REG1 0x16 494 #define PHY_CICADA_INIT6 0x02000 495 #define PHY_CICADA_INIT_REG2 0x17 496 #define PHY_CICADA_INIT1 0x0f000 497 #define PHY_CICADA_INIT2 0x0e00 498 #define PHY_CICADA_INIT3 0x01000 499 #define PHY_CICADA_INIT4 0x0200 500 #define PHY_CICADA_INIT_REG3 0x1c 501 #define PHY_CICADA_INIT5 0x0004 502 #define PHY_MARVELL_INIT_REG1 0x1c 503 #define PHY_MARVELL_E3016_INITMASK 0x0300 504 #define PHY_VITESSE_INIT_REG2 0x10 505 #define PHY_VITESSE_INIT2 0xaf8a 506 #define PHY_VITESSE_INIT4 0x8f8a 507 #define PHY_VITESSE_INIT5 0xaf86 508 #define PHY_VITESSE_INIT6 0x8f86 509 #define PHY_VITESSE_INIT7 0xaf82 510 #define PHY_VITESSE_INIT9 0x8f82 511 #define PHY_VITESSE_INIT_REG3 0x11 512 #define PHY_VITESSE_INIT_REG4 0x12 513 #define PHY_VITESSE_INIT_MSK1 0xc 514 #define PHY_VITESSE_INIT3 0x8 515 #define PHY_VITESSE_INIT_MSK2 0x0180 516 #define PHY_VITESSE_INIT8 0x0100 517 #define PHY_VITESSE_INIT_REG1 0x1f 518 #define PHY_VITESSE_INIT1 0x52b5 519 #define PHY_VITESSE_INIT10 0x0 520 #define PHY_REALTEK_INIT_REG7 0x01 521 #define PHY_REALTEK_INIT11 0x0200 522 #define PHY_REALTEK_INIT_REG6 0x11 523 #define PHY_REALTEK_INIT7 0x1000 524 #define PHY_REALTEK_INIT9 0x0008 525 #define PHY_REALTEK_INIT_REG3 0x13 526 #define PHY_REALTEK_INIT4 0xad17 527 #define PHY_REALTEK_INIT_REG4 0x14 528 #define PHY_REALTEK_INIT5 0xfb54 529 #define PHY_REALTEK_REVISION 0x17 530 #define PHY_REV_MASK 0x0001 531 #define PHY_REV_REALTEK_8211B 0x0000 532 #define PHY_REV_REALTEK_8211C 0x0001 533 #define PHY_REALTEK_INIT_REG5 0x18 534 #define PHY_REALTEK_INIT6 0xf5c7 535 #define PHY_REALTEK_INIT_REG2 0x19 536 #define PHY_REALTEK_INIT2 0x8e00 537 #define PHY_REALTEK_INIT8 0x0003 538 #define PHY_REALTEK_INIT_MSK1 0x0003 539 #define PHY_REALTEK_INIT_REG1 0x1f 540 #define PHY_REALTEK_INIT1 0x0000 541 #define PHY_REALTEK_INIT3 0x0001 542 #define PHY_REALTEK_INIT10 0x0005 543 544 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001 545 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002 546 #define NV_PAUSEFRAME_RX_ENABLE 0x0004 547 #define NV_PAUSEFRAME_TX_ENABLE 0x0008 548 #define NV_PAUSEFRAME_RX_REQ 0x0010 549 #define NV_PAUSEFRAME_TX_REQ 0x0020 550 #define NV_PAUSEFRAME_AUTONEG 0x0040 551 552 #define NV_MSI_X_MAX_VECTORS 8 553 #define NV_MSI_X_VECTORS_MASK 0x000f 554 #define NV_MSI_CAPABLE 0x0010 555 #define NV_MSI_X_CAPABLE 0x0020 556 #define NV_MSI_ENABLED 0x0040 557 #define NV_MSI_X_ENABLED 0x0080 558 559 #define NV_MSI_X_VECTOR_ALL 0x0 560 #define NV_MSI_X_VECTOR_RX 0x0 561 #define NV_MSI_X_VECTOR_TX 0x1 562 #define NV_MSI_X_VECTOR_OTHER 0x2 563 564 #define NV_MSI_PRIV_OFFSET 0x68 565 #define NV_MSI_PRIV_VALUE 0xffffffff 566 567 #define NV_TX_LIMIT_COUNT 16 568