1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef __tu102_dev_nv_xve_h__ 25 #define __tu102_dev_nv_xve_h__ 26 #define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */ 27 #define NV_XVE_ID 0x00000000 /* R--4R */ 28 #define NV_XVE_ID_VENDOR 15:0 /* C--VF */ 29 #define NV_XVE_ID_VENDOR_NVIDIA 0x000010DE /* C---V */ 30 #define NV_XVE_SW_RESET 0x00000718 /* RW-4R */ 31 #define NV_XVE_DEVICE_CAPABILITY 0x0000007C /* R--4R */ 32 #define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET 28:28 /* R-XVF */ 33 #define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_NOT_SUPPORTED 0x00000000 /* R---V */ 34 #define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_SUPPORTED 0x00000001 /* R---V */ 35 #define NV_XVE_DEVICE_CONTROL_STATUS 0x00000080 /* RW-4R */ 36 #define NV_XVE_DEVICE_CONTROL_STATUS_INITIATE_FN_LVL_RST 15:15 /* RWIVF */ 37 #define NV_XVE_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING 21:21 /* R-IVF */ 38 #define NV_XVE_MSIX_CAP_HDR 0x000000C8 /* RW-4R */ 39 #define NV_XVE_MSIX_CAP_HDR_ENABLE 31:31 /* RWIVF */ 40 #define NV_XVE_MSIX_CAP_HDR_ENABLE_ENABLED 0x00000001 /* RW--V */ 41 #define NV_XVE_MSIX_CAP_HDR_ENABLE_DISABLED 0x00000000 /* RWI-V */ 42 #define NV_XVE_PRIV_MISC_1 0x0000041C /* RW-4R */ 43 #define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP 29:29 /* RWCVF */ 44 #define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_TRUE 0x00000001 /* RW--V */ 45 #define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_FALSE 0x00000000 /* RWC-V */ 46 #define NV_XVE_SRIOV_CAP_HDR3 0x00000BD8 /* R--4R */ 47 #define NV_XVE_SRIOV_CAP_HDR3_TOTAL_VFS 31:16 /* R-EVF */ 48 #define NV_XVE_SRIOV_CAP_HDR5 0x00000BE0 /* R--4R */ 49 #define NV_XVE_SRIOV_CAP_HDR5_FIRST_VF_OFFSET 15:0 /* R-IVF */ 50 #define NV_XVE_SRIOV_CAP_HDR9 0x00000BF0 /* RW-4R */ 51 #define NV_XVE_SRIOV_CAP_HDR10 0x00000BF4 /* RW-4R */ 52 #define NV_XVE_SRIOV_CAP_HDR11_VF_BAR1_HI 0x00000BF8 /* RW-4R */ 53 #define NV_XVE_SRIOV_CAP_HDR12 0x00000BFC /* RW-4R */ 54 #define NV_XVE_SRIOV_CAP_HDR13_VF_BAR2_HI 0x00000C00 /* RW-4R */ 55 #endif // __tu102_dev_nv_xve_h__ 56