1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This tablegen backend emits an assembly printer for the current target.
10 // Note that this is currently fairly skeletal, but will grow over time.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "AsmWriterInst.h"
15 #include "CodeGenInstAlias.h"
16 #include "CodeGenInstruction.h"
17 #include "CodeGenRegisters.h"
18 #include "CodeGenTarget.h"
19 #include "SequenceToOffsetTable.h"
20 #include "Types.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/SmallString.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringRef.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/Support/Casting.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/Format.h"
32 #include "llvm/Support/FormatVariadic.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/TableGen/Error.h"
36 #include "llvm/TableGen/Record.h"
37 #include "llvm/TableGen/TableGenBackend.h"
38 #include <algorithm>
39 #include <cassert>
40 #include <cstddef>
41 #include <cstdint>
42 #include <deque>
43 #include <iterator>
44 #include <map>
45 #include <set>
46 #include <string>
47 #include <tuple>
48 #include <utility>
49 #include <vector>
50
51 using namespace llvm;
52
53 #define DEBUG_TYPE "asm-writer-emitter"
54
55 namespace {
56
57 class AsmWriterEmitter {
58 RecordKeeper &Records;
59 CodeGenTarget Target;
60 ArrayRef<const CodeGenInstruction *> NumberedInstructions;
61 std::vector<AsmWriterInst> Instructions;
62
63 public:
64 AsmWriterEmitter(RecordKeeper &R);
65
66 void run(raw_ostream &o);
67 private:
68 void EmitGetMnemonic(
69 raw_ostream &o,
70 std::vector<std::vector<std::string>> &TableDrivenOperandPrinters,
71 unsigned &BitsLeft, unsigned &AsmStrBits);
72 void EmitPrintInstruction(
73 raw_ostream &o,
74 std::vector<std::vector<std::string>> &TableDrivenOperandPrinters,
75 unsigned &BitsLeft, unsigned &AsmStrBits);
76 void EmitGetRegisterName(raw_ostream &o);
77 void EmitPrintAliasInstruction(raw_ostream &O);
78
79 void FindUniqueOperandCommands(std::vector<std::string> &UOC,
80 std::vector<std::vector<unsigned>> &InstIdxs,
81 std::vector<unsigned> &InstOpsUsed,
82 bool PassSubtarget) const;
83 };
84
85 } // end anonymous namespace
86
PrintCases(std::vector<std::pair<std::string,AsmWriterOperand>> & OpsToPrint,raw_ostream & O,bool PassSubtarget)87 static void PrintCases(std::vector<std::pair<std::string,
88 AsmWriterOperand>> &OpsToPrint, raw_ostream &O,
89 bool PassSubtarget) {
90 O << " case " << OpsToPrint.back().first << ":";
91 AsmWriterOperand TheOp = OpsToPrint.back().second;
92 OpsToPrint.pop_back();
93
94 // Check to see if any other operands are identical in this list, and if so,
95 // emit a case label for them.
96 for (unsigned i = OpsToPrint.size(); i != 0; --i)
97 if (OpsToPrint[i-1].second == TheOp) {
98 O << "\n case " << OpsToPrint[i-1].first << ":";
99 OpsToPrint.erase(OpsToPrint.begin()+i-1);
100 }
101
102 // Finally, emit the code.
103 O << "\n " << TheOp.getCode(PassSubtarget);
104 O << "\n break;\n";
105 }
106
107 /// EmitInstructions - Emit the last instruction in the vector and any other
108 /// instructions that are suitably similar to it.
EmitInstructions(std::vector<AsmWriterInst> & Insts,raw_ostream & O,bool PassSubtarget)109 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
110 raw_ostream &O, bool PassSubtarget) {
111 AsmWriterInst FirstInst = Insts.back();
112 Insts.pop_back();
113
114 std::vector<AsmWriterInst> SimilarInsts;
115 unsigned DifferingOperand = ~0;
116 for (unsigned i = Insts.size(); i != 0; --i) {
117 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
118 if (DiffOp != ~1U) {
119 if (DifferingOperand == ~0U) // First match!
120 DifferingOperand = DiffOp;
121
122 // If this differs in the same operand as the rest of the instructions in
123 // this class, move it to the SimilarInsts list.
124 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
125 SimilarInsts.push_back(Insts[i-1]);
126 Insts.erase(Insts.begin()+i-1);
127 }
128 }
129 }
130
131 O << " case " << FirstInst.CGI->Namespace << "::"
132 << FirstInst.CGI->TheDef->getName() << ":\n";
133 for (const AsmWriterInst &AWI : SimilarInsts)
134 O << " case " << AWI.CGI->Namespace << "::"
135 << AWI.CGI->TheDef->getName() << ":\n";
136 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
137 if (i != DifferingOperand) {
138 // If the operand is the same for all instructions, just print it.
139 O << " " << FirstInst.Operands[i].getCode(PassSubtarget);
140 } else {
141 // If this is the operand that varies between all of the instructions,
142 // emit a switch for just this operand now.
143 O << " switch (MI->getOpcode()) {\n";
144 O << " default: llvm_unreachable(\"Unexpected opcode.\");\n";
145 std::vector<std::pair<std::string, AsmWriterOperand>> OpsToPrint;
146 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace.str() + "::" +
147 FirstInst.CGI->TheDef->getName().str(),
148 FirstInst.Operands[i]));
149
150 for (const AsmWriterInst &AWI : SimilarInsts) {
151 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace.str()+"::" +
152 AWI.CGI->TheDef->getName().str(),
153 AWI.Operands[i]));
154 }
155 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
156 while (!OpsToPrint.empty())
157 PrintCases(OpsToPrint, O, PassSubtarget);
158 O << " }";
159 }
160 O << "\n";
161 }
162 O << " break;\n";
163 }
164
165 void AsmWriterEmitter::
FindUniqueOperandCommands(std::vector<std::string> & UniqueOperandCommands,std::vector<std::vector<unsigned>> & InstIdxs,std::vector<unsigned> & InstOpsUsed,bool PassSubtarget) const166 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
167 std::vector<std::vector<unsigned>> &InstIdxs,
168 std::vector<unsigned> &InstOpsUsed,
169 bool PassSubtarget) const {
170 // This vector parallels UniqueOperandCommands, keeping track of which
171 // instructions each case are used for. It is a comma separated string of
172 // enums.
173 std::vector<std::string> InstrsForCase;
174 InstrsForCase.resize(UniqueOperandCommands.size());
175 InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
176
177 for (size_t i = 0, e = Instructions.size(); i != e; ++i) {
178 const AsmWriterInst &Inst = Instructions[i];
179 if (Inst.Operands.empty())
180 continue; // Instruction already done.
181
182 std::string Command = " "+Inst.Operands[0].getCode(PassSubtarget)+"\n";
183
184 // Check to see if we already have 'Command' in UniqueOperandCommands.
185 // If not, add it.
186 auto I = llvm::find(UniqueOperandCommands, Command);
187 if (I != UniqueOperandCommands.end()) {
188 size_t idx = I - UniqueOperandCommands.begin();
189 InstrsForCase[idx] += ", ";
190 InstrsForCase[idx] += Inst.CGI->TheDef->getName();
191 InstIdxs[idx].push_back(i);
192 } else {
193 UniqueOperandCommands.push_back(std::move(Command));
194 InstrsForCase.push_back(std::string(Inst.CGI->TheDef->getName()));
195 InstIdxs.emplace_back();
196 InstIdxs.back().push_back(i);
197
198 // This command matches one operand so far.
199 InstOpsUsed.push_back(1);
200 }
201 }
202
203 // For each entry of UniqueOperandCommands, there is a set of instructions
204 // that uses it. If the next command of all instructions in the set are
205 // identical, fold it into the command.
206 for (size_t CommandIdx = 0, e = UniqueOperandCommands.size();
207 CommandIdx != e; ++CommandIdx) {
208
209 const auto &Idxs = InstIdxs[CommandIdx];
210
211 for (unsigned Op = 1; ; ++Op) {
212 // Find the first instruction in the set.
213 const AsmWriterInst &FirstInst = Instructions[Idxs.front()];
214 // If this instruction has no more operands, we isn't anything to merge
215 // into this command.
216 if (FirstInst.Operands.size() == Op)
217 break;
218
219 // Otherwise, scan to see if all of the other instructions in this command
220 // set share the operand.
221 if (any_of(drop_begin(Idxs), [&](unsigned Idx) {
222 const AsmWriterInst &OtherInst = Instructions[Idx];
223 return OtherInst.Operands.size() == Op ||
224 OtherInst.Operands[Op] != FirstInst.Operands[Op];
225 }))
226 break;
227
228 // Okay, everything in this command set has the same next operand. Add it
229 // to UniqueOperandCommands and remember that it was consumed.
230 std::string Command = " " +
231 FirstInst.Operands[Op].getCode(PassSubtarget) + "\n";
232
233 UniqueOperandCommands[CommandIdx] += Command;
234 InstOpsUsed[CommandIdx]++;
235 }
236 }
237
238 // Prepend some of the instructions each case is used for onto the case val.
239 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
240 std::string Instrs = InstrsForCase[i];
241 if (Instrs.size() > 70) {
242 Instrs.erase(Instrs.begin()+70, Instrs.end());
243 Instrs += "...";
244 }
245
246 if (!Instrs.empty())
247 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
248 UniqueOperandCommands[i];
249 }
250 }
251
UnescapeString(std::string & Str)252 static void UnescapeString(std::string &Str) {
253 for (unsigned i = 0; i != Str.size(); ++i) {
254 if (Str[i] == '\\' && i != Str.size()-1) {
255 switch (Str[i+1]) {
256 default: continue; // Don't execute the code after the switch.
257 case 'a': Str[i] = '\a'; break;
258 case 'b': Str[i] = '\b'; break;
259 case 'e': Str[i] = 27; break;
260 case 'f': Str[i] = '\f'; break;
261 case 'n': Str[i] = '\n'; break;
262 case 'r': Str[i] = '\r'; break;
263 case 't': Str[i] = '\t'; break;
264 case 'v': Str[i] = '\v'; break;
265 case '"': Str[i] = '\"'; break;
266 case '\'': Str[i] = '\''; break;
267 case '\\': Str[i] = '\\'; break;
268 }
269 // Nuke the second character.
270 Str.erase(Str.begin()+i+1);
271 }
272 }
273 }
274
275 /// UnescapeAliasString - Supports literal braces in InstAlias asm string which
276 /// are escaped with '\\' to avoid being interpreted as variants. Braces must
277 /// be unescaped before c++ code is generated as (e.g.):
278 ///
279 /// AsmString = "foo \{$\x01\}";
280 ///
281 /// causes non-standard escape character warnings.
UnescapeAliasString(std::string & Str)282 static void UnescapeAliasString(std::string &Str) {
283 for (unsigned i = 0; i != Str.size(); ++i) {
284 if (Str[i] == '\\' && i != Str.size()-1) {
285 switch (Str[i+1]) {
286 default: continue; // Don't execute the code after the switch.
287 case '{': Str[i] = '{'; break;
288 case '}': Str[i] = '}'; break;
289 }
290 // Nuke the second character.
291 Str.erase(Str.begin()+i+1);
292 }
293 }
294 }
295
EmitGetMnemonic(raw_ostream & O,std::vector<std::vector<std::string>> & TableDrivenOperandPrinters,unsigned & BitsLeft,unsigned & AsmStrBits)296 void AsmWriterEmitter::EmitGetMnemonic(
297 raw_ostream &O,
298 std::vector<std::vector<std::string>> &TableDrivenOperandPrinters,
299 unsigned &BitsLeft, unsigned &AsmStrBits) {
300 Record *AsmWriter = Target.getAsmWriter();
301 StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
302 bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
303
304 O << "/// getMnemonic - This method is automatically generated by "
305 "tablegen\n"
306 "/// from the instruction set description.\n"
307 "std::pair<const char *, uint64_t> "
308 << Target.getName() << ClassName << "::getMnemonic(const MCInst *MI) {\n";
309
310 // Build an aggregate string, and build a table of offsets into it.
311 SequenceToOffsetTable<std::string> StringTable;
312
313 /// OpcodeInfo - This encodes the index of the string to use for the first
314 /// chunk of the output as well as indices used for operand printing.
315 std::vector<uint64_t> OpcodeInfo(NumberedInstructions.size());
316 const unsigned OpcodeInfoBits = 64;
317
318 // Add all strings to the string table upfront so it can generate an optimized
319 // representation.
320 for (AsmWriterInst &AWI : Instructions) {
321 if (AWI.Operands[0].OperandType ==
322 AsmWriterOperand::isLiteralTextOperand &&
323 !AWI.Operands[0].Str.empty()) {
324 std::string Str = AWI.Operands[0].Str;
325 UnescapeString(Str);
326 StringTable.add(Str);
327 }
328 }
329
330 StringTable.layout();
331
332 unsigned MaxStringIdx = 0;
333 for (AsmWriterInst &AWI : Instructions) {
334 unsigned Idx;
335 if (AWI.Operands[0].OperandType != AsmWriterOperand::isLiteralTextOperand ||
336 AWI.Operands[0].Str.empty()) {
337 // Something handled by the asmwriter printer, but with no leading string.
338 Idx = StringTable.get("");
339 } else {
340 std::string Str = AWI.Operands[0].Str;
341 UnescapeString(Str);
342 Idx = StringTable.get(Str);
343 MaxStringIdx = std::max(MaxStringIdx, Idx);
344
345 // Nuke the string from the operand list. It is now handled!
346 AWI.Operands.erase(AWI.Operands.begin());
347 }
348
349 // Bias offset by one since we want 0 as a sentinel.
350 OpcodeInfo[AWI.CGIIndex] = Idx+1;
351 }
352
353 // Figure out how many bits we used for the string index.
354 AsmStrBits = Log2_32_Ceil(MaxStringIdx + 2);
355
356 // To reduce code size, we compactify common instructions into a few bits
357 // in the opcode-indexed table.
358 BitsLeft = OpcodeInfoBits - AsmStrBits;
359
360 while (true) {
361 std::vector<std::string> UniqueOperandCommands;
362 std::vector<std::vector<unsigned>> InstIdxs;
363 std::vector<unsigned> NumInstOpsHandled;
364 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
365 NumInstOpsHandled, PassSubtarget);
366
367 // If we ran out of operands to print, we're done.
368 if (UniqueOperandCommands.empty()) break;
369
370 // Compute the number of bits we need to represent these cases, this is
371 // ceil(log2(numentries)).
372 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
373
374 // If we don't have enough bits for this operand, don't include it.
375 if (NumBits > BitsLeft) {
376 LLVM_DEBUG(errs() << "Not enough bits to densely encode " << NumBits
377 << " more bits\n");
378 break;
379 }
380
381 // Otherwise, we can include this in the initial lookup table. Add it in.
382 for (size_t i = 0, e = InstIdxs.size(); i != e; ++i) {
383 unsigned NumOps = NumInstOpsHandled[i];
384 for (unsigned Idx : InstIdxs[i]) {
385 OpcodeInfo[Instructions[Idx].CGIIndex] |=
386 (uint64_t)i << (OpcodeInfoBits-BitsLeft);
387 // Remove the info about this operand from the instruction.
388 AsmWriterInst &Inst = Instructions[Idx];
389 if (!Inst.Operands.empty()) {
390 assert(NumOps <= Inst.Operands.size() &&
391 "Can't remove this many ops!");
392 Inst.Operands.erase(Inst.Operands.begin(),
393 Inst.Operands.begin()+NumOps);
394 }
395 }
396 }
397 BitsLeft -= NumBits;
398
399 // Remember the handlers for this set of operands.
400 TableDrivenOperandPrinters.push_back(std::move(UniqueOperandCommands));
401 }
402
403 // Emit the string table itself.
404 StringTable.emitStringLiteralDef(O, " static const char AsmStrs[]");
405
406 // Emit the lookup tables in pieces to minimize wasted bytes.
407 unsigned BytesNeeded = ((OpcodeInfoBits - BitsLeft) + 7) / 8;
408 unsigned Table = 0, Shift = 0;
409 SmallString<128> BitsString;
410 raw_svector_ostream BitsOS(BitsString);
411 // If the total bits is more than 32-bits we need to use a 64-bit type.
412 BitsOS << " uint" << ((BitsLeft < (OpcodeInfoBits - 32)) ? 64 : 32)
413 << "_t Bits = 0;\n";
414 while (BytesNeeded != 0) {
415 // Figure out how big this table section needs to be, but no bigger than 4.
416 unsigned TableSize = std::min(llvm::bit_floor(BytesNeeded), 4u);
417 BytesNeeded -= TableSize;
418 TableSize *= 8; // Convert to bits;
419 uint64_t Mask = (1ULL << TableSize) - 1;
420 O << " static const uint" << TableSize << "_t OpInfo" << Table
421 << "[] = {\n";
422 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
423 O << " " << ((OpcodeInfo[i] >> Shift) & Mask) << "U,\t// "
424 << NumberedInstructions[i]->TheDef->getName() << "\n";
425 }
426 O << " };\n\n";
427 // Emit string to combine the individual table lookups.
428 BitsOS << " Bits |= ";
429 // If the total bits is more than 32-bits we need to use a 64-bit type.
430 if (BitsLeft < (OpcodeInfoBits - 32))
431 BitsOS << "(uint64_t)";
432 BitsOS << "OpInfo" << Table << "[MI->getOpcode()] << " << Shift << ";\n";
433 // Prepare the shift for the next iteration and increment the table count.
434 Shift += TableSize;
435 ++Table;
436 }
437
438 O << " // Emit the opcode for the instruction.\n";
439 O << BitsString;
440
441 // Make sure we don't return an invalid pointer if bits is 0
442 O << " if (Bits == 0)\n"
443 " return {nullptr, Bits};\n";
444
445 // Return mnemonic string and bits.
446 O << " return {AsmStrs+(Bits & " << (1 << AsmStrBits) - 1
447 << ")-1, Bits};\n\n";
448
449 O << "}\n";
450 }
451
452 /// EmitPrintInstruction - Generate the code for the "printInstruction" method
453 /// implementation. Destroys all instances of AsmWriterInst information, by
454 /// clearing the Instructions vector.
EmitPrintInstruction(raw_ostream & O,std::vector<std::vector<std::string>> & TableDrivenOperandPrinters,unsigned & BitsLeft,unsigned & AsmStrBits)455 void AsmWriterEmitter::EmitPrintInstruction(
456 raw_ostream &O,
457 std::vector<std::vector<std::string>> &TableDrivenOperandPrinters,
458 unsigned &BitsLeft, unsigned &AsmStrBits) {
459 const unsigned OpcodeInfoBits = 64;
460 Record *AsmWriter = Target.getAsmWriter();
461 StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
462 bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
463
464 // This function has some huge switch statements that causing excessive
465 // compile time in LLVM profile instrumenation build. This print function
466 // usually is not frequently called in compilation. Here we disable the
467 // profile instrumenation for this function.
468 O << "/// printInstruction - This method is automatically generated by "
469 "tablegen\n"
470 "/// from the instruction set description.\n"
471 "LLVM_NO_PROFILE_INSTRUMENT_FUNCTION\n"
472 "void "
473 << Target.getName() << ClassName
474 << "::printInstruction(const MCInst *MI, uint64_t Address, "
475 << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
476 << "raw_ostream &O) {\n";
477
478 // Emit the initial tab character.
479 O << " O << \"\\t\";\n\n";
480
481 // Emit the starting string.
482 O << " auto MnemonicInfo = getMnemonic(MI);\n\n";
483 O << " O << MnemonicInfo.first;\n\n";
484
485 O << " uint" << ((BitsLeft < (OpcodeInfoBits - 32)) ? 64 : 32)
486 << "_t Bits = MnemonicInfo.second;\n"
487 << " assert(Bits != 0 && \"Cannot print this instruction.\");\n";
488
489 // Output the table driven operand information.
490 BitsLeft = OpcodeInfoBits-AsmStrBits;
491 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
492 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
493
494 // Compute the number of bits we need to represent these cases, this is
495 // ceil(log2(numentries)).
496 unsigned NumBits = Log2_32_Ceil(Commands.size());
497 assert(NumBits <= BitsLeft && "consistency error");
498
499 // Emit code to extract this field from Bits.
500 O << "\n // Fragment " << i << " encoded into " << NumBits
501 << " bits for " << Commands.size() << " unique commands.\n";
502
503 if (Commands.size() == 2) {
504 // Emit two possibilitys with if/else.
505 O << " if ((Bits >> "
506 << (OpcodeInfoBits-BitsLeft) << ") & "
507 << ((1 << NumBits)-1) << ") {\n"
508 << Commands[1]
509 << " } else {\n"
510 << Commands[0]
511 << " }\n\n";
512 } else if (Commands.size() == 1) {
513 // Emit a single possibility.
514 O << Commands[0] << "\n\n";
515 } else {
516 O << " switch ((Bits >> "
517 << (OpcodeInfoBits-BitsLeft) << ") & "
518 << ((1 << NumBits)-1) << ") {\n"
519 << " default: llvm_unreachable(\"Invalid command number.\");\n";
520
521 // Print out all the cases.
522 for (unsigned j = 0, e = Commands.size(); j != e; ++j) {
523 O << " case " << j << ":\n";
524 O << Commands[j];
525 O << " break;\n";
526 }
527 O << " }\n\n";
528 }
529 BitsLeft -= NumBits;
530 }
531
532 // Okay, delete instructions with no operand info left.
533 llvm::erase_if(Instructions,
534 [](AsmWriterInst &Inst) { return Inst.Operands.empty(); });
535
536 // Because this is a vector, we want to emit from the end. Reverse all of the
537 // elements in the vector.
538 std::reverse(Instructions.begin(), Instructions.end());
539
540
541 // Now that we've emitted all of the operand info that fit into 64 bits, emit
542 // information for those instructions that are left. This is a less dense
543 // encoding, but we expect the main 64-bit table to handle the majority of
544 // instructions.
545 if (!Instructions.empty()) {
546 // Find the opcode # of inline asm.
547 O << " switch (MI->getOpcode()) {\n";
548 O << " default: llvm_unreachable(\"Unexpected opcode.\");\n";
549 while (!Instructions.empty())
550 EmitInstructions(Instructions, O, PassSubtarget);
551
552 O << " }\n";
553 }
554
555 O << "}\n";
556 }
557
558 static void
emitRegisterNameString(raw_ostream & O,StringRef AltName,const std::deque<CodeGenRegister> & Registers)559 emitRegisterNameString(raw_ostream &O, StringRef AltName,
560 const std::deque<CodeGenRegister> &Registers) {
561 SequenceToOffsetTable<std::string> StringTable;
562 SmallVector<std::string, 4> AsmNames(Registers.size());
563 unsigned i = 0;
564 for (const auto &Reg : Registers) {
565 std::string &AsmName = AsmNames[i++];
566
567 // "NoRegAltName" is special. We don't need to do a lookup for that,
568 // as it's just a reference to the default register name.
569 if (AltName == "" || AltName == "NoRegAltName") {
570 AsmName = std::string(Reg.TheDef->getValueAsString("AsmName"));
571 if (AsmName.empty())
572 AsmName = std::string(Reg.getName());
573 } else {
574 // Make sure the register has an alternate name for this index.
575 std::vector<Record*> AltNameList =
576 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
577 unsigned Idx = 0, e;
578 for (e = AltNameList.size();
579 Idx < e && (AltNameList[Idx]->getName() != AltName);
580 ++Idx)
581 ;
582 // If the register has an alternate name for this index, use it.
583 // Otherwise, leave it empty as an error flag.
584 if (Idx < e) {
585 std::vector<StringRef> AltNames =
586 Reg.TheDef->getValueAsListOfStrings("AltNames");
587 if (AltNames.size() <= Idx)
588 PrintFatalError(Reg.TheDef->getLoc(),
589 "Register definition missing alt name for '" +
590 AltName + "'.");
591 AsmName = std::string(AltNames[Idx]);
592 }
593 }
594 StringTable.add(AsmName);
595 }
596
597 StringTable.layout();
598 StringTable.emitStringLiteralDef(O, Twine(" static const char AsmStrs") +
599 AltName + "[]");
600
601 O << " static const " << getMinimalTypeForRange(StringTable.size() - 1, 32)
602 << " RegAsmOffset" << AltName << "[] = {";
603 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
604 if ((i % 14) == 0)
605 O << "\n ";
606 O << StringTable.get(AsmNames[i]) << ", ";
607 }
608 O << "\n };\n"
609 << "\n";
610 }
611
EmitGetRegisterName(raw_ostream & O)612 void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
613 Record *AsmWriter = Target.getAsmWriter();
614 StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
615 const auto &Registers = Target.getRegBank().getRegisters();
616 const std::vector<Record*> &AltNameIndices = Target.getRegAltNameIndices();
617 bool hasAltNames = AltNameIndices.size() > 1;
618 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace");
619
620 O <<
621 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
622 "/// from the register set description. This returns the assembler name\n"
623 "/// for the specified register.\n"
624 "const char *" << Target.getName() << ClassName << "::";
625 if (hasAltNames)
626 O << "\ngetRegisterName(MCRegister Reg, unsigned AltIdx) {\n";
627 else
628 O << "getRegisterName(MCRegister Reg) {\n";
629 O << " unsigned RegNo = Reg.id();\n"
630 << " assert(RegNo && RegNo < " << (Registers.size() + 1)
631 << " && \"Invalid register number!\");\n"
632 << "\n";
633
634 if (hasAltNames) {
635 for (const Record *R : AltNameIndices)
636 emitRegisterNameString(O, R->getName(), Registers);
637 } else
638 emitRegisterNameString(O, "", Registers);
639
640 if (hasAltNames) {
641 O << " switch(AltIdx) {\n"
642 << " default: llvm_unreachable(\"Invalid register alt name index!\");\n";
643 for (const Record *R : AltNameIndices) {
644 StringRef AltName = R->getName();
645 O << " case ";
646 if (!Namespace.empty())
647 O << Namespace << "::";
648 O << AltName << ":\n";
649 if (R->isValueUnset("FallbackRegAltNameIndex"))
650 O << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" << AltName
651 << "[RegNo-1]) &&\n"
652 << " \"Invalid alt name index for register!\");\n";
653 else {
654 O << " if (!*(AsmStrs" << AltName << "+RegAsmOffset" << AltName
655 << "[RegNo-1]))\n"
656 << " return getRegisterName(RegNo, ";
657 if (!Namespace.empty())
658 O << Namespace << "::";
659 O << R->getValueAsDef("FallbackRegAltNameIndex")->getName() << ");\n";
660 }
661 O << " return AsmStrs" << AltName << "+RegAsmOffset" << AltName
662 << "[RegNo-1];\n";
663 }
664 O << " }\n";
665 } else {
666 O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
667 << " \"Invalid alt name index for register!\");\n"
668 << " return AsmStrs+RegAsmOffset[RegNo-1];\n";
669 }
670 O << "}\n";
671 }
672
673 namespace {
674
675 // IAPrinter - Holds information about an InstAlias. Two InstAliases match if
676 // they both have the same conditionals. In which case, we cannot print out the
677 // alias for that pattern.
678 class IAPrinter {
679 std::map<StringRef, std::pair<int, int>> OpMap;
680
681 std::vector<std::string> Conds;
682
683 std::string Result;
684 std::string AsmString;
685
686 unsigned NumMIOps;
687
688 public:
IAPrinter(std::string R,std::string AS,unsigned NumMIOps)689 IAPrinter(std::string R, std::string AS, unsigned NumMIOps)
690 : Result(std::move(R)), AsmString(std::move(AS)), NumMIOps(NumMIOps) {}
691
addCond(std::string C)692 void addCond(std::string C) { Conds.push_back(std::move(C)); }
getConds() const693 ArrayRef<std::string> getConds() const { return Conds; }
getCondCount() const694 size_t getCondCount() const { return Conds.size(); }
695
addOperand(StringRef Op,int OpIdx,int PrintMethodIdx=-1)696 void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) {
697 assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range");
698 assert(PrintMethodIdx >= -1 && PrintMethodIdx < 0xFF &&
699 "Idx out of range");
700 OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx);
701 }
702
getNumMIOps()703 unsigned getNumMIOps() { return NumMIOps; }
704
getResult()705 StringRef getResult() { return Result; }
706
isOpMapped(StringRef Op)707 bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); }
getOpIndex(StringRef Op)708 int getOpIndex(StringRef Op) { return OpMap[Op].first; }
getOpData(StringRef Op)709 std::pair<int, int> &getOpData(StringRef Op) { return OpMap[Op]; }
710
parseName(StringRef::iterator Start,StringRef::iterator End)711 std::pair<StringRef, StringRef::iterator> parseName(StringRef::iterator Start,
712 StringRef::iterator End) {
713 StringRef::iterator I = Start;
714 StringRef::iterator Next;
715 if (*I == '{') {
716 // ${some_name}
717 Start = ++I;
718 while (I != End && *I != '}')
719 ++I;
720 Next = I;
721 // eat the final '}'
722 if (Next != End)
723 ++Next;
724 } else {
725 // $name, just eat the usual suspects.
726 while (I != End && (isAlnum(*I) || *I == '_'))
727 ++I;
728 Next = I;
729 }
730
731 return std::make_pair(StringRef(Start, I - Start), Next);
732 }
733
formatAliasString(uint32_t & UnescapedSize)734 std::string formatAliasString(uint32_t &UnescapedSize) {
735 // Directly mangle mapped operands into the string. Each operand is
736 // identified by a '$' sign followed by a byte identifying the number of the
737 // operand. We add one to the index to avoid zero bytes.
738 StringRef ASM(AsmString);
739 std::string OutString;
740 raw_string_ostream OS(OutString);
741 for (StringRef::iterator I = ASM.begin(), E = ASM.end(); I != E;) {
742 OS << *I;
743 ++UnescapedSize;
744 if (*I == '$') {
745 StringRef Name;
746 std::tie(Name, I) = parseName(++I, E);
747 assert(isOpMapped(Name) && "Unmapped operand!");
748
749 int OpIndex, PrintIndex;
750 std::tie(OpIndex, PrintIndex) = getOpData(Name);
751 if (PrintIndex == -1) {
752 // Can use the default printOperand route.
753 OS << format("\\x%02X", (unsigned char)OpIndex + 1);
754 ++UnescapedSize;
755 } else {
756 // 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand
757 // number, and which of our pre-detected Methods to call.
758 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1);
759 UnescapedSize += 3;
760 }
761 } else {
762 ++I;
763 }
764 }
765 return OutString;
766 }
767
operator ==(const IAPrinter & RHS) const768 bool operator==(const IAPrinter &RHS) const {
769 if (NumMIOps != RHS.NumMIOps)
770 return false;
771 if (Conds.size() != RHS.Conds.size())
772 return false;
773
774 unsigned Idx = 0;
775 for (const auto &str : Conds)
776 if (str != RHS.Conds[Idx++])
777 return false;
778
779 return true;
780 }
781 };
782
783 } // end anonymous namespace
784
CountNumOperands(StringRef AsmString,unsigned Variant)785 static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) {
786 return AsmString.count(' ') + AsmString.count('\t');
787 }
788
789 namespace {
790
791 struct AliasPriorityComparator {
792 typedef std::pair<CodeGenInstAlias, int> ValueType;
operator ()__anond69e789b0511::AliasPriorityComparator793 bool operator()(const ValueType &LHS, const ValueType &RHS) const {
794 if (LHS.second == RHS.second) {
795 // We don't actually care about the order, but for consistency it
796 // shouldn't depend on pointer comparisons.
797 return LessRecordByID()(LHS.first.TheDef, RHS.first.TheDef);
798 }
799
800 // Aliases with larger priorities should be considered first.
801 return LHS.second > RHS.second;
802 }
803 };
804
805 } // end anonymous namespace
806
EmitPrintAliasInstruction(raw_ostream & O)807 void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
808 Record *AsmWriter = Target.getAsmWriter();
809
810 O << "\n#ifdef PRINT_ALIAS_INSTR\n";
811 O << "#undef PRINT_ALIAS_INSTR\n\n";
812
813 //////////////////////////////
814 // Gather information about aliases we need to print
815 //////////////////////////////
816
817 // Emit the method that prints the alias instruction.
818 StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
819 unsigned Variant = AsmWriter->getValueAsInt("Variant");
820 bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
821
822 std::vector<Record*> AllInstAliases =
823 Records.getAllDerivedDefinitions("InstAlias");
824
825 // Create a map from the qualified name to a list of potential matches.
826 typedef std::set<std::pair<CodeGenInstAlias, int>, AliasPriorityComparator>
827 AliasWithPriority;
828 std::map<std::string, AliasWithPriority> AliasMap;
829 for (Record *R : AllInstAliases) {
830 int Priority = R->getValueAsInt("EmitPriority");
831 if (Priority < 1)
832 continue; // Aliases with priority 0 are never emitted.
833
834 const DagInit *DI = R->getValueAsDag("ResultInst");
835 AliasMap[getQualifiedName(DI->getOperatorAsDef(R->getLoc()))].insert(
836 std::make_pair(CodeGenInstAlias(R, Target), Priority));
837 }
838
839 // A map of which conditions need to be met for each instruction operand
840 // before it can be matched to the mnemonic.
841 std::map<std::string, std::vector<IAPrinter>> IAPrinterMap;
842
843 std::vector<std::pair<std::string, bool>> PrintMethods;
844
845 // A list of MCOperandPredicates for all operands in use, and the reverse map
846 std::vector<const Record*> MCOpPredicates;
847 DenseMap<const Record*, unsigned> MCOpPredicateMap;
848
849 for (auto &Aliases : AliasMap) {
850 // Collection of instruction alias rules. May contain ambiguous rules.
851 std::vector<IAPrinter> IAPs;
852
853 for (auto &Alias : Aliases.second) {
854 const CodeGenInstAlias &CGA = Alias.first;
855 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
856 std::string FlatInstAsmString =
857 CodeGenInstruction::FlattenAsmStringVariants(CGA.ResultInst->AsmString,
858 Variant);
859 unsigned NumResultOps = CountNumOperands(FlatInstAsmString, Variant);
860
861 std::string FlatAliasAsmString =
862 CodeGenInstruction::FlattenAsmStringVariants(CGA.AsmString, Variant);
863 UnescapeAliasString(FlatAliasAsmString);
864
865 // Don't emit the alias if it has more operands than what it's aliasing.
866 if (NumResultOps < CountNumOperands(FlatAliasAsmString, Variant))
867 continue;
868
869 StringRef Namespace = Target.getName();
870 unsigned NumMIOps = 0;
871 for (auto &ResultInstOpnd : CGA.ResultInst->Operands)
872 NumMIOps += ResultInstOpnd.MINumOperands;
873
874 IAPrinter IAP(CGA.Result->getAsString(), FlatAliasAsmString, NumMIOps);
875
876 unsigned MIOpNum = 0;
877 for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
878 // Skip over tied operands as they're not part of an alias declaration.
879 auto &Operands = CGA.ResultInst->Operands;
880 while (true) {
881 unsigned OpNum = Operands.getSubOperandNumber(MIOpNum).first;
882 if (Operands[OpNum].MINumOperands == 1 &&
883 Operands[OpNum].getTiedRegister() != -1) {
884 // Tied operands of different RegisterClass should be explicit within
885 // an instruction's syntax and so cannot be skipped.
886 int TiedOpNum = Operands[OpNum].getTiedRegister();
887 if (Operands[OpNum].Rec->getName() ==
888 Operands[TiedOpNum].Rec->getName()) {
889 ++MIOpNum;
890 continue;
891 }
892 }
893 break;
894 }
895
896 // Ignore unchecked result operands.
897 while (IAP.getCondCount() < MIOpNum)
898 IAP.addCond("AliasPatternCond::K_Ignore, 0");
899
900 const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i];
901
902 switch (RO.Kind) {
903 case CodeGenInstAlias::ResultOperand::K_Record: {
904 const Record *Rec = RO.getRecord();
905 StringRef ROName = RO.getName();
906 int PrintMethodIdx = -1;
907
908 // These two may have a PrintMethod, which we want to record (if it's
909 // the first time we've seen it) and provide an index for the aliasing
910 // code to use.
911 if (Rec->isSubClassOf("RegisterOperand") ||
912 Rec->isSubClassOf("Operand")) {
913 StringRef PrintMethod = Rec->getValueAsString("PrintMethod");
914 bool IsPCRel =
915 Rec->getValueAsString("OperandType") == "OPERAND_PCREL";
916 if (PrintMethod != "" && PrintMethod != "printOperand") {
917 PrintMethodIdx = llvm::find_if(PrintMethods,
918 [&](auto &X) {
919 return X.first == PrintMethod;
920 }) -
921 PrintMethods.begin();
922 if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size())
923 PrintMethods.emplace_back(std::string(PrintMethod), IsPCRel);
924 }
925 }
926
927 if (Rec->isSubClassOf("RegisterOperand"))
928 Rec = Rec->getValueAsDef("RegClass");
929 if (Rec->isSubClassOf("RegisterClass")) {
930 if (!IAP.isOpMapped(ROName)) {
931 IAP.addOperand(ROName, MIOpNum, PrintMethodIdx);
932 Record *R = CGA.ResultOperands[i].getRecord();
933 if (R->isSubClassOf("RegisterOperand"))
934 R = R->getValueAsDef("RegClass");
935 IAP.addCond(std::string(
936 formatv("AliasPatternCond::K_RegClass, {0}::{1}RegClassID",
937 Namespace, R->getName())));
938 } else {
939 IAP.addCond(std::string(formatv(
940 "AliasPatternCond::K_TiedReg, {0}", IAP.getOpIndex(ROName))));
941 }
942 } else {
943 // Assume all printable operands are desired for now. This can be
944 // overridden in the InstAlias instantiation if necessary.
945 IAP.addOperand(ROName, MIOpNum, PrintMethodIdx);
946
947 // There might be an additional predicate on the MCOperand
948 unsigned Entry = MCOpPredicateMap[Rec];
949 if (!Entry) {
950 if (!Rec->isValueUnset("MCOperandPredicate")) {
951 MCOpPredicates.push_back(Rec);
952 Entry = MCOpPredicates.size();
953 MCOpPredicateMap[Rec] = Entry;
954 } else
955 break; // No conditions on this operand at all
956 }
957 IAP.addCond(
958 std::string(formatv("AliasPatternCond::K_Custom, {0}", Entry)));
959 }
960 break;
961 }
962 case CodeGenInstAlias::ResultOperand::K_Imm: {
963 // Just because the alias has an immediate result, doesn't mean the
964 // MCInst will. An MCExpr could be present, for example.
965 auto Imm = CGA.ResultOperands[i].getImm();
966 int32_t Imm32 = int32_t(Imm);
967 if (Imm != Imm32)
968 PrintFatalError("Matching an alias with an immediate out of the "
969 "range of int32_t is not supported");
970 IAP.addCond(std::string(
971 formatv("AliasPatternCond::K_Imm, uint32_t({0})", Imm32)));
972 break;
973 }
974 case CodeGenInstAlias::ResultOperand::K_Reg:
975 if (!CGA.ResultOperands[i].getRegister()) {
976 IAP.addCond(std::string(formatv(
977 "AliasPatternCond::K_Reg, {0}::NoRegister", Namespace)));
978 break;
979 }
980
981 StringRef Reg = CGA.ResultOperands[i].getRegister()->getName();
982 IAP.addCond(std::string(
983 formatv("AliasPatternCond::K_Reg, {0}::{1}", Namespace, Reg)));
984 break;
985 }
986
987 MIOpNum += RO.getMINumOperands();
988 }
989
990 std::vector<Record *> ReqFeatures;
991 if (PassSubtarget) {
992 // We only consider ReqFeatures predicates if PassSubtarget
993 std::vector<Record *> RF =
994 CGA.TheDef->getValueAsListOfDefs("Predicates");
995 copy_if(RF, std::back_inserter(ReqFeatures), [](Record *R) {
996 return R->getValueAsBit("AssemblerMatcherPredicate");
997 });
998 }
999
1000 for (Record *const R : ReqFeatures) {
1001 const DagInit *D = R->getValueAsDag("AssemblerCondDag");
1002 auto *Op = dyn_cast<DefInit>(D->getOperator());
1003 if (!Op)
1004 PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
1005 StringRef CombineType = Op->getDef()->getName();
1006 if (CombineType != "any_of" && CombineType != "all_of")
1007 PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
1008 if (D->getNumArgs() == 0)
1009 PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
1010 bool IsOr = CombineType == "any_of";
1011 // Change (any_of FeatureAll, (any_of ...)) to (any_of FeatureAll, ...).
1012 if (IsOr && D->getNumArgs() == 2 && isa<DagInit>(D->getArg(1))) {
1013 DagInit *RHS = cast<DagInit>(D->getArg(1));
1014 SmallVector<Init *> Args{D->getArg(0)};
1015 SmallVector<StringInit *> ArgNames{D->getArgName(0)};
1016 for (unsigned i = 0, e = RHS->getNumArgs(); i != e; ++i) {
1017 Args.push_back(RHS->getArg(i));
1018 ArgNames.push_back(RHS->getArgName(i));
1019 }
1020 D = DagInit::get(D->getOperator(), nullptr, Args, ArgNames);
1021 }
1022
1023 for (auto *Arg : D->getArgs()) {
1024 bool IsNeg = false;
1025 if (auto *NotArg = dyn_cast<DagInit>(Arg)) {
1026 if (NotArg->getOperator()->getAsString() != "not" ||
1027 NotArg->getNumArgs() != 1)
1028 PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
1029 Arg = NotArg->getArg(0);
1030 IsNeg = true;
1031 }
1032 if (!isa<DefInit>(Arg) ||
1033 !cast<DefInit>(Arg)->getDef()->isSubClassOf("SubtargetFeature"))
1034 PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
1035
1036 IAP.addCond(std::string(formatv(
1037 "AliasPatternCond::K_{0}{1}Feature, {2}::{3}", IsOr ? "Or" : "",
1038 IsNeg ? "Neg" : "", Namespace, Arg->getAsString())));
1039 }
1040 // If an AssemblerPredicate with ors is used, note end of list should
1041 // these be combined.
1042 if (IsOr)
1043 IAP.addCond("AliasPatternCond::K_EndOrFeatures, 0");
1044 }
1045
1046 IAPrinterMap[Aliases.first].push_back(std::move(IAP));
1047 }
1048 }
1049
1050 //////////////////////////////
1051 // Write out the printAliasInstr function
1052 //////////////////////////////
1053
1054 std::string Header;
1055 raw_string_ostream HeaderO(Header);
1056
1057 HeaderO << "bool " << Target.getName() << ClassName
1058 << "::printAliasInstr(const MCInst"
1059 << " *MI, uint64_t Address, "
1060 << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
1061 << "raw_ostream &OS) {\n";
1062
1063 std::string PatternsForOpcode;
1064 raw_string_ostream OpcodeO(PatternsForOpcode);
1065
1066 unsigned PatternCount = 0;
1067 std::string Patterns;
1068 raw_string_ostream PatternO(Patterns);
1069
1070 unsigned CondCount = 0;
1071 std::string Conds;
1072 raw_string_ostream CondO(Conds);
1073
1074 // All flattened alias strings.
1075 std::map<std::string, uint32_t> AsmStringOffsets;
1076 std::vector<std::pair<uint32_t, std::string>> AsmStrings;
1077 size_t AsmStringsSize = 0;
1078
1079 // Iterate over the opcodes in enum order so they are sorted by opcode for
1080 // binary search.
1081 for (const CodeGenInstruction *Inst : NumberedInstructions) {
1082 auto It = IAPrinterMap.find(getQualifiedName(Inst->TheDef));
1083 if (It == IAPrinterMap.end())
1084 continue;
1085 std::vector<IAPrinter> &IAPs = It->second;
1086 std::vector<IAPrinter*> UniqueIAPs;
1087
1088 // Remove any ambiguous alias rules.
1089 for (auto &LHS : IAPs) {
1090 bool IsDup = false;
1091 for (const auto &RHS : IAPs) {
1092 if (&LHS != &RHS && LHS == RHS) {
1093 IsDup = true;
1094 break;
1095 }
1096 }
1097
1098 if (!IsDup)
1099 UniqueIAPs.push_back(&LHS);
1100 }
1101
1102 if (UniqueIAPs.empty()) continue;
1103
1104 unsigned PatternStart = PatternCount;
1105
1106 // Insert the pattern start and opcode in the pattern list for debugging.
1107 PatternO << formatv(" // {0} - {1}\n", It->first, PatternStart);
1108
1109 for (IAPrinter *IAP : UniqueIAPs) {
1110 // Start each condition list with a comment of the resulting pattern that
1111 // we're trying to match.
1112 unsigned CondStart = CondCount;
1113 CondO << formatv(" // {0} - {1}\n", IAP->getResult(), CondStart);
1114 for (const auto &Cond : IAP->getConds())
1115 CondO << " {" << Cond << "},\n";
1116 CondCount += IAP->getCondCount();
1117
1118 // After operands have been examined, re-encode the alias string with
1119 // escapes indicating how operands should be printed.
1120 uint32_t UnescapedSize = 0;
1121 std::string EncodedAsmString = IAP->formatAliasString(UnescapedSize);
1122 auto Insertion =
1123 AsmStringOffsets.insert({EncodedAsmString, AsmStringsSize});
1124 if (Insertion.second) {
1125 // If the string is new, add it to the vector.
1126 AsmStrings.push_back({AsmStringsSize, EncodedAsmString});
1127 AsmStringsSize += UnescapedSize + 1;
1128 }
1129 unsigned AsmStrOffset = Insertion.first->second;
1130
1131 PatternO << formatv(" {{{0}, {1}, {2}, {3} },\n", AsmStrOffset,
1132 CondStart, IAP->getNumMIOps(), IAP->getCondCount());
1133 ++PatternCount;
1134 }
1135
1136 OpcodeO << formatv(" {{{0}, {1}, {2} },\n", It->first, PatternStart,
1137 PatternCount - PatternStart);
1138 }
1139
1140 if (OpcodeO.str().empty()) {
1141 O << HeaderO.str();
1142 O << " return false;\n";
1143 O << "}\n\n";
1144 O << "#endif // PRINT_ALIAS_INSTR\n";
1145 return;
1146 }
1147
1148 // Forward declare the validation method if needed.
1149 if (!MCOpPredicates.empty())
1150 O << "static bool " << Target.getName() << ClassName
1151 << "ValidateMCOperand(const MCOperand &MCOp,\n"
1152 << " const MCSubtargetInfo &STI,\n"
1153 << " unsigned PredicateIndex);\n";
1154
1155 O << HeaderO.str();
1156 O.indent(2) << "static const PatternsForOpcode OpToPatterns[] = {\n";
1157 O << OpcodeO.str();
1158 O.indent(2) << "};\n\n";
1159 O.indent(2) << "static const AliasPattern Patterns[] = {\n";
1160 O << PatternO.str();
1161 O.indent(2) << "};\n\n";
1162 O.indent(2) << "static const AliasPatternCond Conds[] = {\n";
1163 O << CondO.str();
1164 O.indent(2) << "};\n\n";
1165 O.indent(2) << "static const char AsmStrings[] =\n";
1166 for (const auto &P : AsmStrings) {
1167 O.indent(4) << "/* " << P.first << " */ \"" << P.second << "\\0\"\n";
1168 }
1169
1170 O.indent(2) << ";\n\n";
1171
1172 // Assert that the opcode table is sorted. Use a static local constructor to
1173 // ensure that the check only happens once on first run.
1174 O << "#ifndef NDEBUG\n";
1175 O.indent(2) << "static struct SortCheck {\n";
1176 O.indent(2) << " SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {\n";
1177 O.indent(2) << " assert(std::is_sorted(\n";
1178 O.indent(2) << " OpToPatterns.begin(), OpToPatterns.end(),\n";
1179 O.indent(2) << " [](const PatternsForOpcode &L, const "
1180 "PatternsForOpcode &R) {\n";
1181 O.indent(2) << " return L.Opcode < R.Opcode;\n";
1182 O.indent(2) << " }) &&\n";
1183 O.indent(2) << " \"tablegen failed to sort opcode patterns\");\n";
1184 O.indent(2) << " }\n";
1185 O.indent(2) << "} sortCheckVar(OpToPatterns);\n";
1186 O << "#endif\n\n";
1187
1188 O.indent(2) << "AliasMatchingData M {\n";
1189 O.indent(2) << " ArrayRef(OpToPatterns),\n";
1190 O.indent(2) << " ArrayRef(Patterns),\n";
1191 O.indent(2) << " ArrayRef(Conds),\n";
1192 O.indent(2) << " StringRef(AsmStrings, std::size(AsmStrings)),\n";
1193 if (MCOpPredicates.empty())
1194 O.indent(2) << " nullptr,\n";
1195 else
1196 O.indent(2) << " &" << Target.getName() << ClassName << "ValidateMCOperand,\n";
1197 O.indent(2) << "};\n";
1198
1199 O.indent(2) << "const char *AsmString = matchAliasPatterns(MI, "
1200 << (PassSubtarget ? "&STI" : "nullptr") << ", M);\n";
1201 O.indent(2) << "if (!AsmString) return false;\n\n";
1202
1203 // Code that prints the alias, replacing the operands with the ones from the
1204 // MCInst.
1205 O << " unsigned I = 0;\n";
1206 O << " while (AsmString[I] != ' ' && AsmString[I] != '\\t' &&\n";
1207 O << " AsmString[I] != '$' && AsmString[I] != '\\0')\n";
1208 O << " ++I;\n";
1209 O << " OS << '\\t' << StringRef(AsmString, I);\n";
1210
1211 O << " if (AsmString[I] != '\\0') {\n";
1212 O << " if (AsmString[I] == ' ' || AsmString[I] == '\\t') {\n";
1213 O << " OS << '\\t';\n";
1214 O << " ++I;\n";
1215 O << " }\n";
1216 O << " do {\n";
1217 O << " if (AsmString[I] == '$') {\n";
1218 O << " ++I;\n";
1219 O << " if (AsmString[I] == (char)0xff) {\n";
1220 O << " ++I;\n";
1221 O << " int OpIdx = AsmString[I++] - 1;\n";
1222 O << " int PrintMethodIdx = AsmString[I++] - 1;\n";
1223 O << " printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, ";
1224 O << (PassSubtarget ? "STI, " : "");
1225 O << "OS);\n";
1226 O << " } else\n";
1227 O << " printOperand(MI, unsigned(AsmString[I++]) - 1, ";
1228 O << (PassSubtarget ? "STI, " : "");
1229 O << "OS);\n";
1230 O << " } else {\n";
1231 O << " OS << AsmString[I++];\n";
1232 O << " }\n";
1233 O << " } while (AsmString[I] != '\\0');\n";
1234 O << " }\n\n";
1235
1236 O << " return true;\n";
1237 O << "}\n\n";
1238
1239 //////////////////////////////
1240 // Write out the printCustomAliasOperand function
1241 //////////////////////////////
1242
1243 O << "void " << Target.getName() << ClassName << "::"
1244 << "printCustomAliasOperand(\n"
1245 << " const MCInst *MI, uint64_t Address, unsigned OpIdx,\n"
1246 << " unsigned PrintMethodIdx,\n"
1247 << (PassSubtarget ? " const MCSubtargetInfo &STI,\n" : "")
1248 << " raw_ostream &OS) {\n";
1249 if (PrintMethods.empty())
1250 O << " llvm_unreachable(\"Unknown PrintMethod kind\");\n";
1251 else {
1252 O << " switch (PrintMethodIdx) {\n"
1253 << " default:\n"
1254 << " llvm_unreachable(\"Unknown PrintMethod kind\");\n"
1255 << " break;\n";
1256
1257 for (unsigned i = 0; i < PrintMethods.size(); ++i) {
1258 O << " case " << i << ":\n"
1259 << " " << PrintMethods[i].first << "(MI, "
1260 << (PrintMethods[i].second ? "Address, " : "") << "OpIdx, "
1261 << (PassSubtarget ? "STI, " : "") << "OS);\n"
1262 << " break;\n";
1263 }
1264 O << " }\n";
1265 }
1266 O << "}\n\n";
1267
1268 if (!MCOpPredicates.empty()) {
1269 O << "static bool " << Target.getName() << ClassName
1270 << "ValidateMCOperand(const MCOperand &MCOp,\n"
1271 << " const MCSubtargetInfo &STI,\n"
1272 << " unsigned PredicateIndex) {\n"
1273 << " switch (PredicateIndex) {\n"
1274 << " default:\n"
1275 << " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n"
1276 << " break;\n";
1277
1278 for (unsigned i = 0; i < MCOpPredicates.size(); ++i) {
1279 StringRef MCOpPred = MCOpPredicates[i]->getValueAsString("MCOperandPredicate");
1280 O << " case " << i + 1 << ": {\n"
1281 << MCOpPred.data() << "\n"
1282 << " }\n";
1283 }
1284 O << " }\n"
1285 << "}\n\n";
1286 }
1287
1288 O << "#endif // PRINT_ALIAS_INSTR\n";
1289 }
1290
AsmWriterEmitter(RecordKeeper & R)1291 AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) {
1292 Record *AsmWriter = Target.getAsmWriter();
1293 unsigned Variant = AsmWriter->getValueAsInt("Variant");
1294
1295 // Get the instruction numbering.
1296 NumberedInstructions = Target.getInstructionsByEnumValue();
1297
1298 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
1299 const CodeGenInstruction *I = NumberedInstructions[i];
1300 if (!I->AsmString.empty() && I->TheDef->getName() != "PHI")
1301 Instructions.emplace_back(*I, i, Variant);
1302 }
1303 }
1304
run(raw_ostream & O)1305 void AsmWriterEmitter::run(raw_ostream &O) {
1306 std::vector<std::vector<std::string>> TableDrivenOperandPrinters;
1307 unsigned BitsLeft = 0;
1308 unsigned AsmStrBits = 0;
1309 emitSourceFileHeader("Assembly Writer Source Fragment", O, Records);
1310 EmitGetMnemonic(O, TableDrivenOperandPrinters, BitsLeft, AsmStrBits);
1311 EmitPrintInstruction(O, TableDrivenOperandPrinters, BitsLeft, AsmStrBits);
1312 EmitGetRegisterName(O);
1313 EmitPrintAliasInstruction(O);
1314 }
1315
1316 static TableGen::Emitter::OptClass<AsmWriterEmitter>
1317 X("gen-asm-writer", "Generate assembly writer");
1318