xref: /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/SIDefines.h (revision d415bd75)
1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
12 
13 #include "llvm/MC/MCInstrDesc.h"
14 
15 namespace llvm {
16 
17 // This needs to be kept in sync with the field bits in SIRegisterClass.
18 enum SIRCFlags : uint8_t {
19   // For vector registers.
20   HasVGPR = 1 << 0,
21   HasAGPR = 1 << 1,
22   HasSGPR = 1 << 2
23 }; // enum SIRCFlags
24 
25 namespace SIInstrFlags {
26 // This needs to be kept in sync with the field bits in InstSI.
27 enum : uint64_t {
28   // Low bits - basic encoding information.
29   SALU = 1 << 0,
30   VALU = 1 << 1,
31 
32   // SALU instruction formats.
33   SOP1 = 1 << 2,
34   SOP2 = 1 << 3,
35   SOPC = 1 << 4,
36   SOPK = 1 << 5,
37   SOPP = 1 << 6,
38 
39   // VALU instruction formats.
40   VOP1 = 1 << 7,
41   VOP2 = 1 << 8,
42   VOPC = 1 << 9,
43 
44   // TODO: Should this be spilt into VOP3 a and b?
45   VOP3 = 1 << 10,
46   VOP3P = 1 << 12,
47 
48   VINTRP = 1 << 13,
49   SDWA = 1 << 14,
50   DPP = 1 << 15,
51   TRANS = 1 << 16,
52 
53   // Memory instruction formats.
54   MUBUF = 1 << 17,
55   MTBUF = 1 << 18,
56   SMRD = 1 << 19,
57   MIMG = 1 << 20,
58   EXP = 1 << 21,
59   FLAT = 1 << 22,
60   DS = 1 << 23,
61 
62   // Pseudo instruction formats.
63   VGPRSpill = 1 << 24,
64   SGPRSpill = 1 << 25,
65 
66   // LDSDIR instruction format.
67   LDSDIR = 1 << 26,
68 
69   // VINTERP instruction format.
70   VINTERP = 1 << 27,
71 
72   // High bits - other information.
73   VM_CNT = UINT64_C(1) << 32,
74   EXP_CNT = UINT64_C(1) << 33,
75   LGKM_CNT = UINT64_C(1) << 34,
76 
77   WQM = UINT64_C(1) << 35,
78   DisableWQM = UINT64_C(1) << 36,
79   Gather4 = UINT64_C(1) << 37,
80   SOPK_ZEXT = UINT64_C(1) << 38,
81   SCALAR_STORE = UINT64_C(1) << 39,
82   FIXED_SIZE = UINT64_C(1) << 40,
83   VOPAsmPrefer32Bit = UINT64_C(1) << 41,
84   VOP3_OPSEL = UINT64_C(1) << 42,
85   maybeAtomic = UINT64_C(1) << 43,
86   renamedInGFX9 = UINT64_C(1) << 44,
87 
88   // Is a clamp on FP type.
89   FPClamp = UINT64_C(1) << 45,
90 
91   // Is an integer clamp
92   IntClamp = UINT64_C(1) << 46,
93 
94   // Clamps lo component of register.
95   ClampLo = UINT64_C(1) << 47,
96 
97   // Clamps hi component of register.
98   // ClampLo and ClampHi set for packed clamp.
99   ClampHi = UINT64_C(1) << 48,
100 
101   // Is a packed VOP3P instruction.
102   IsPacked = UINT64_C(1) << 49,
103 
104   // Is a D16 buffer instruction.
105   D16Buf = UINT64_C(1) << 50,
106 
107   // FLAT instruction accesses FLAT_GLBL segment.
108   FlatGlobal = UINT64_C(1) << 51,
109 
110   // Uses floating point double precision rounding mode
111   FPDPRounding = UINT64_C(1) << 52,
112 
113   // Instruction is FP atomic.
114   FPAtomic = UINT64_C(1) << 53,
115 
116   // Is a MFMA instruction.
117   IsMAI = UINT64_C(1) << 54,
118 
119   // Is a DOT instruction.
120   IsDOT = UINT64_C(1) << 55,
121 
122   // FLAT instruction accesses FLAT_SCRATCH segment.
123   FlatScratch = UINT64_C(1) << 56,
124 
125   // Atomic without return.
126   IsAtomicNoRet = UINT64_C(1) << 57,
127 
128   // Atomic with return.
129   IsAtomicRet = UINT64_C(1) << 58,
130 
131   // Is a WMMA instruction.
132   IsWMMA = UINT64_C(1) << 59,
133 
134   // Whether tied sources will be read.
135   TiedSourceNotRead = UINT64_C(1) << 60,
136 };
137 
138 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
139 // The result is true if any of these tests are true.
140 enum ClassFlags : unsigned {
141   S_NAN = 1 << 0,        // Signaling NaN
142   Q_NAN = 1 << 1,        // Quiet NaN
143   N_INFINITY = 1 << 2,   // Negative infinity
144   N_NORMAL = 1 << 3,     // Negative normal
145   N_SUBNORMAL = 1 << 4,  // Negative subnormal
146   N_ZERO = 1 << 5,       // Negative zero
147   P_ZERO = 1 << 6,       // Positive zero
148   P_SUBNORMAL = 1 << 7,  // Positive subnormal
149   P_NORMAL = 1 << 8,     // Positive normal
150   P_INFINITY = 1 << 9    // Positive infinity
151 };
152 }
153 
154 namespace AMDGPU {
155 enum OperandType : unsigned {
156   /// Operands with register or 32-bit immediate
157   OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
158   OPERAND_REG_IMM_INT64,
159   OPERAND_REG_IMM_INT16,
160   OPERAND_REG_IMM_FP32,
161   OPERAND_REG_IMM_FP64,
162   OPERAND_REG_IMM_FP16,
163   OPERAND_REG_IMM_FP16_DEFERRED,
164   OPERAND_REG_IMM_FP32_DEFERRED,
165   OPERAND_REG_IMM_V2FP16,
166   OPERAND_REG_IMM_V2INT16,
167   OPERAND_REG_IMM_V2INT32,
168   OPERAND_REG_IMM_V2FP32,
169 
170   /// Operands with register or inline constant
171   OPERAND_REG_INLINE_C_INT16,
172   OPERAND_REG_INLINE_C_INT32,
173   OPERAND_REG_INLINE_C_INT64,
174   OPERAND_REG_INLINE_C_FP16,
175   OPERAND_REG_INLINE_C_FP32,
176   OPERAND_REG_INLINE_C_FP64,
177   OPERAND_REG_INLINE_C_V2INT16,
178   OPERAND_REG_INLINE_C_V2FP16,
179   OPERAND_REG_INLINE_C_V2INT32,
180   OPERAND_REG_INLINE_C_V2FP32,
181 
182   /// Operand with 32-bit immediate that uses the constant bus.
183   OPERAND_KIMM32,
184   OPERAND_KIMM16,
185 
186   /// Operands with an AccVGPR register or inline constant
187   OPERAND_REG_INLINE_AC_INT16,
188   OPERAND_REG_INLINE_AC_INT32,
189   OPERAND_REG_INLINE_AC_FP16,
190   OPERAND_REG_INLINE_AC_FP32,
191   OPERAND_REG_INLINE_AC_FP64,
192   OPERAND_REG_INLINE_AC_V2INT16,
193   OPERAND_REG_INLINE_AC_V2FP16,
194   OPERAND_REG_INLINE_AC_V2INT32,
195   OPERAND_REG_INLINE_AC_V2FP32,
196 
197   // Operand for source modifiers for VOP instructions
198   OPERAND_INPUT_MODS,
199 
200   // Operand for SDWA instructions
201   OPERAND_SDWA_VOPC_DST,
202 
203   OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
204   OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32,
205 
206   OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
207   OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32,
208 
209   OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16,
210   OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32,
211 
212   OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
213   OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
214 
215   OPERAND_KIMM_FIRST = OPERAND_KIMM32,
216   OPERAND_KIMM_LAST = OPERAND_KIMM16
217 
218 };
219 }
220 
221 // Input operand modifiers bit-masks
222 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
223 namespace SISrcMods {
224   enum : unsigned {
225    NEG = 1 << 0,   // Floating-point negate modifier
226    ABS = 1 << 1,   // Floating-point absolute modifier
227    SEXT = 1 << 0,  // Integer sign-extend modifier
228    NEG_HI = ABS,   // Floating-point negate high packed component modifier.
229    OP_SEL_0 = 1 << 2,
230    OP_SEL_1 = 1 << 3,
231    DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
232   };
233 }
234 
235 namespace SIOutMods {
236   enum : unsigned {
237     NONE = 0,
238     MUL2 = 1,
239     MUL4 = 2,
240     DIV2 = 3
241   };
242 }
243 
244 namespace AMDGPU {
245 namespace VGPRIndexMode {
246 
247 enum Id : unsigned { // id of symbolic names
248   ID_SRC0 = 0,
249   ID_SRC1,
250   ID_SRC2,
251   ID_DST,
252 
253   ID_MIN = ID_SRC0,
254   ID_MAX = ID_DST
255 };
256 
257 enum EncBits : unsigned {
258   OFF = 0,
259   SRC0_ENABLE = 1 << ID_SRC0,
260   SRC1_ENABLE = 1 << ID_SRC1,
261   SRC2_ENABLE = 1 << ID_SRC2,
262   DST_ENABLE = 1 << ID_DST,
263   ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE,
264   UNDEF = 0xFFFF
265 };
266 
267 } // namespace VGPRIndexMode
268 } // namespace AMDGPU
269 
270 namespace AMDGPUAsmVariants {
271   enum : unsigned {
272     DEFAULT = 0,
273     VOP3 = 1,
274     SDWA = 2,
275     SDWA9 = 3,
276     DPP = 4,
277     VOP3_DPP = 5
278   };
279 } // namespace AMDGPUAsmVariants
280 
281 namespace AMDGPU {
282 namespace EncValues { // Encoding values of enum9/8/7 operands
283 
284 enum : unsigned {
285   SGPR_MIN = 0,
286   SGPR_MAX_SI = 101,
287   SGPR_MAX_GFX10 = 105,
288   TTMP_VI_MIN = 112,
289   TTMP_VI_MAX = 123,
290   TTMP_GFX9PLUS_MIN = 108,
291   TTMP_GFX9PLUS_MAX = 123,
292   INLINE_INTEGER_C_MIN = 128,
293   INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
294   INLINE_INTEGER_C_MAX = 208,
295   INLINE_FLOATING_C_MIN = 240,
296   INLINE_FLOATING_C_MAX = 248,
297   LITERAL_CONST = 255,
298   VGPR_MIN = 256,
299   VGPR_MAX = 511,
300   IS_VGPR = 256  // Indicates VGPR or AGPR
301 };
302 
303 } // namespace EncValues
304 } // namespace AMDGPU
305 
306 namespace AMDGPU {
307 namespace CPol {
308 
309 enum CPol {
310   GLC = 1,
311   SLC = 2,
312   DLC = 4,
313   SCC = 16,
314   SC0 = GLC,
315   SC1 = SCC,
316   NT = SLC,
317   ALL = GLC | SLC | DLC | SCC
318 };
319 
320 } // namespace CPol
321 
322 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
323 
324 enum Id { // Message ID, width(4) [3:0].
325   ID_INTERRUPT = 1,
326 
327   ID_GS_PreGFX11 = 2,      // replaced in GFX11
328   ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11
329 
330   ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11
331   ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11
332 
333   ID_SAVEWAVE = 4,           // added in GFX8, removed in GFX11
334   ID_STALL_WAVE_GEN = 5,     // added in GFX9
335   ID_HALT_WAVES = 6,         // added in GFX9
336   ID_ORDERED_PS_DONE = 7,    // added in GFX9
337   ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
338   ID_GS_ALLOC_REQ = 9,       // added in GFX9
339   ID_GET_DOORBELL = 10,      // added in GFX9, removed in GFX11
340   ID_GET_DDID = 11,          // added in GFX10, removed in GFX11
341   ID_SYSMSG = 15,
342 
343   ID_RTN_GET_DOORBELL = 128,
344   ID_RTN_GET_DDID = 129,
345   ID_RTN_GET_TMA = 130,
346   ID_RTN_GET_REALTIME = 131,
347   ID_RTN_SAVE_WAVE = 132,
348   ID_RTN_GET_TBA = 133,
349 
350   ID_MASK_PreGFX11_ = 0xF,
351   ID_MASK_GFX11Plus_ = 0xFF
352 };
353 
354 enum Op { // Both GS and SYS operation IDs.
355   OP_UNKNOWN_ = -1,
356   OP_SHIFT_ = 4,
357   OP_NONE_ = 0,
358   // Bits used for operation encoding
359   OP_WIDTH_ = 3,
360   OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
361   // GS operations are encoded in bits 5:4
362   OP_GS_NOP = 0,
363   OP_GS_CUT = 1,
364   OP_GS_EMIT = 2,
365   OP_GS_EMIT_CUT = 3,
366   OP_GS_LAST_,
367   OP_GS_FIRST_ = OP_GS_NOP,
368   // SYS operations are encoded in bits 6:4
369   OP_SYS_ECC_ERR_INTERRUPT = 1,
370   OP_SYS_REG_RD = 2,
371   OP_SYS_HOST_TRAP_ACK = 3,
372   OP_SYS_TTRACE_PC = 4,
373   OP_SYS_LAST_,
374   OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
375 };
376 
377 enum StreamId : unsigned { // Stream ID, (2) [9:8].
378   STREAM_ID_NONE_ = 0,
379   STREAM_ID_DEFAULT_ = 0,
380   STREAM_ID_LAST_ = 4,
381   STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
382   STREAM_ID_SHIFT_ = 8,
383   STREAM_ID_WIDTH_=  2,
384   STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
385 };
386 
387 } // namespace SendMsg
388 
389 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
390 
391 enum Id { // HwRegCode, (6) [5:0]
392   ID_MODE = 1,
393   ID_STATUS = 2,
394   ID_TRAPSTS = 3,
395   ID_HW_ID = 4,
396   ID_GPR_ALLOC = 5,
397   ID_LDS_ALLOC = 6,
398   ID_IB_STS = 7,
399   ID_MEM_BASES = 15,
400   ID_TBA_LO = 16,
401   ID_TBA_HI = 17,
402   ID_TMA_LO = 18,
403   ID_TMA_HI = 19,
404   ID_XCC_ID = 20,
405   ID_SQ_PERF_SNAPSHOT_DATA = 21,
406   ID_SQ_PERF_SNAPSHOT_DATA1 = 22,
407   ID_SQ_PERF_SNAPSHOT_PC_LO = 23,
408   ID_SQ_PERF_SNAPSHOT_PC_HI = 24,
409   ID_FLAT_SCR_LO = 20,
410   ID_FLAT_SCR_HI = 21,
411   ID_XNACK_MASK = 22,
412   ID_HW_ID1 = 23,
413   ID_HW_ID2 = 24,
414   ID_POPS_PACKER = 25,
415   ID_SHADER_CYCLES = 29,
416 
417   ID_SHIFT_ = 0,
418   ID_WIDTH_ = 6,
419   ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
420 };
421 
422 enum Offset : unsigned { // Offset, (5) [10:6]
423   OFFSET_DEFAULT_ = 0,
424   OFFSET_SHIFT_ = 6,
425   OFFSET_WIDTH_ = 5,
426   OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_),
427 
428   OFFSET_MEM_VIOL = 8,
429 };
430 
431 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11]
432   WIDTH_M1_DEFAULT_ = 31,
433   WIDTH_M1_SHIFT_ = 11,
434   WIDTH_M1_WIDTH_ = 5,
435   WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_),
436 };
437 
438 // Some values from WidthMinusOne mapped into Width domain.
439 enum Width : unsigned {
440   WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1,
441 };
442 
443 enum ModeRegisterMasks : uint32_t {
444   FP_ROUND_MASK = 0xf << 0,  // Bits 0..3
445   FP_DENORM_MASK = 0xf << 4, // Bits 4..7
446   DX10_CLAMP_MASK = 1 << 8,
447   IEEE_MODE_MASK = 1 << 9,
448   LOD_CLAMP_MASK = 1 << 10,
449   DEBUG_MASK = 1 << 11,
450 
451   // EXCP_EN fields.
452   EXCP_EN_INVALID_MASK = 1 << 12,
453   EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13,
454   EXCP_EN_FLOAT_DIV0_MASK = 1 << 14,
455   EXCP_EN_OVERFLOW_MASK = 1 << 15,
456   EXCP_EN_UNDERFLOW_MASK = 1 << 16,
457   EXCP_EN_INEXACT_MASK = 1 << 17,
458   EXCP_EN_INT_DIV0_MASK = 1 << 18,
459 
460   GPR_IDX_EN_MASK = 1 << 27,
461   VSKIP_MASK = 1 << 28,
462   CSP_MASK = 0x7u << 29 // Bits 29..31
463 };
464 
465 } // namespace Hwreg
466 
467 namespace MTBUFFormat {
468 
469 enum DataFormat : int64_t {
470   DFMT_INVALID = 0,
471   DFMT_8,
472   DFMT_16,
473   DFMT_8_8,
474   DFMT_32,
475   DFMT_16_16,
476   DFMT_10_11_11,
477   DFMT_11_11_10,
478   DFMT_10_10_10_2,
479   DFMT_2_10_10_10,
480   DFMT_8_8_8_8,
481   DFMT_32_32,
482   DFMT_16_16_16_16,
483   DFMT_32_32_32,
484   DFMT_32_32_32_32,
485   DFMT_RESERVED_15,
486 
487   DFMT_MIN = DFMT_INVALID,
488   DFMT_MAX = DFMT_RESERVED_15,
489 
490   DFMT_UNDEF = -1,
491   DFMT_DEFAULT = DFMT_8,
492 
493   DFMT_SHIFT = 0,
494   DFMT_MASK = 0xF
495 };
496 
497 enum NumFormat : int64_t {
498   NFMT_UNORM = 0,
499   NFMT_SNORM,
500   NFMT_USCALED,
501   NFMT_SSCALED,
502   NFMT_UINT,
503   NFMT_SINT,
504   NFMT_RESERVED_6,                    // VI and GFX9
505   NFMT_SNORM_OGL = NFMT_RESERVED_6,   // SI and CI only
506   NFMT_FLOAT,
507 
508   NFMT_MIN = NFMT_UNORM,
509   NFMT_MAX = NFMT_FLOAT,
510 
511   NFMT_UNDEF = -1,
512   NFMT_DEFAULT = NFMT_UNORM,
513 
514   NFMT_SHIFT = 4,
515   NFMT_MASK = 7
516 };
517 
518 enum MergedFormat : int64_t {
519   DFMT_NFMT_UNDEF = -1,
520   DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) |
521                       ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT),
522 
523 
524   DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT),
525 
526   DFMT_NFMT_MAX = DFMT_NFMT_MASK
527 };
528 
529 enum UnifiedFormatCommon : int64_t {
530   UFMT_MAX = 127,
531   UFMT_UNDEF = -1,
532   UFMT_DEFAULT = 1
533 };
534 
535 } // namespace MTBUFFormat
536 
537 namespace UfmtGFX10 {
538 enum UnifiedFormat : int64_t {
539   UFMT_INVALID = 0,
540 
541   UFMT_8_UNORM,
542   UFMT_8_SNORM,
543   UFMT_8_USCALED,
544   UFMT_8_SSCALED,
545   UFMT_8_UINT,
546   UFMT_8_SINT,
547 
548   UFMT_16_UNORM,
549   UFMT_16_SNORM,
550   UFMT_16_USCALED,
551   UFMT_16_SSCALED,
552   UFMT_16_UINT,
553   UFMT_16_SINT,
554   UFMT_16_FLOAT,
555 
556   UFMT_8_8_UNORM,
557   UFMT_8_8_SNORM,
558   UFMT_8_8_USCALED,
559   UFMT_8_8_SSCALED,
560   UFMT_8_8_UINT,
561   UFMT_8_8_SINT,
562 
563   UFMT_32_UINT,
564   UFMT_32_SINT,
565   UFMT_32_FLOAT,
566 
567   UFMT_16_16_UNORM,
568   UFMT_16_16_SNORM,
569   UFMT_16_16_USCALED,
570   UFMT_16_16_SSCALED,
571   UFMT_16_16_UINT,
572   UFMT_16_16_SINT,
573   UFMT_16_16_FLOAT,
574 
575   UFMT_10_11_11_UNORM,
576   UFMT_10_11_11_SNORM,
577   UFMT_10_11_11_USCALED,
578   UFMT_10_11_11_SSCALED,
579   UFMT_10_11_11_UINT,
580   UFMT_10_11_11_SINT,
581   UFMT_10_11_11_FLOAT,
582 
583   UFMT_11_11_10_UNORM,
584   UFMT_11_11_10_SNORM,
585   UFMT_11_11_10_USCALED,
586   UFMT_11_11_10_SSCALED,
587   UFMT_11_11_10_UINT,
588   UFMT_11_11_10_SINT,
589   UFMT_11_11_10_FLOAT,
590 
591   UFMT_10_10_10_2_UNORM,
592   UFMT_10_10_10_2_SNORM,
593   UFMT_10_10_10_2_USCALED,
594   UFMT_10_10_10_2_SSCALED,
595   UFMT_10_10_10_2_UINT,
596   UFMT_10_10_10_2_SINT,
597 
598   UFMT_2_10_10_10_UNORM,
599   UFMT_2_10_10_10_SNORM,
600   UFMT_2_10_10_10_USCALED,
601   UFMT_2_10_10_10_SSCALED,
602   UFMT_2_10_10_10_UINT,
603   UFMT_2_10_10_10_SINT,
604 
605   UFMT_8_8_8_8_UNORM,
606   UFMT_8_8_8_8_SNORM,
607   UFMT_8_8_8_8_USCALED,
608   UFMT_8_8_8_8_SSCALED,
609   UFMT_8_8_8_8_UINT,
610   UFMT_8_8_8_8_SINT,
611 
612   UFMT_32_32_UINT,
613   UFMT_32_32_SINT,
614   UFMT_32_32_FLOAT,
615 
616   UFMT_16_16_16_16_UNORM,
617   UFMT_16_16_16_16_SNORM,
618   UFMT_16_16_16_16_USCALED,
619   UFMT_16_16_16_16_SSCALED,
620   UFMT_16_16_16_16_UINT,
621   UFMT_16_16_16_16_SINT,
622   UFMT_16_16_16_16_FLOAT,
623 
624   UFMT_32_32_32_UINT,
625   UFMT_32_32_32_SINT,
626   UFMT_32_32_32_FLOAT,
627   UFMT_32_32_32_32_UINT,
628   UFMT_32_32_32_32_SINT,
629   UFMT_32_32_32_32_FLOAT,
630 
631   UFMT_FIRST = UFMT_INVALID,
632   UFMT_LAST = UFMT_32_32_32_32_FLOAT,
633 };
634 
635 } // namespace UfmtGFX10
636 
637 namespace UfmtGFX11 {
638 enum UnifiedFormat : int64_t {
639   UFMT_INVALID = 0,
640 
641   UFMT_8_UNORM,
642   UFMT_8_SNORM,
643   UFMT_8_USCALED,
644   UFMT_8_SSCALED,
645   UFMT_8_UINT,
646   UFMT_8_SINT,
647 
648   UFMT_16_UNORM,
649   UFMT_16_SNORM,
650   UFMT_16_USCALED,
651   UFMT_16_SSCALED,
652   UFMT_16_UINT,
653   UFMT_16_SINT,
654   UFMT_16_FLOAT,
655 
656   UFMT_8_8_UNORM,
657   UFMT_8_8_SNORM,
658   UFMT_8_8_USCALED,
659   UFMT_8_8_SSCALED,
660   UFMT_8_8_UINT,
661   UFMT_8_8_SINT,
662 
663   UFMT_32_UINT,
664   UFMT_32_SINT,
665   UFMT_32_FLOAT,
666 
667   UFMT_16_16_UNORM,
668   UFMT_16_16_SNORM,
669   UFMT_16_16_USCALED,
670   UFMT_16_16_SSCALED,
671   UFMT_16_16_UINT,
672   UFMT_16_16_SINT,
673   UFMT_16_16_FLOAT,
674 
675   UFMT_10_11_11_FLOAT,
676 
677   UFMT_11_11_10_FLOAT,
678 
679   UFMT_10_10_10_2_UNORM,
680   UFMT_10_10_10_2_SNORM,
681   UFMT_10_10_10_2_UINT,
682   UFMT_10_10_10_2_SINT,
683 
684   UFMT_2_10_10_10_UNORM,
685   UFMT_2_10_10_10_SNORM,
686   UFMT_2_10_10_10_USCALED,
687   UFMT_2_10_10_10_SSCALED,
688   UFMT_2_10_10_10_UINT,
689   UFMT_2_10_10_10_SINT,
690 
691   UFMT_8_8_8_8_UNORM,
692   UFMT_8_8_8_8_SNORM,
693   UFMT_8_8_8_8_USCALED,
694   UFMT_8_8_8_8_SSCALED,
695   UFMT_8_8_8_8_UINT,
696   UFMT_8_8_8_8_SINT,
697 
698   UFMT_32_32_UINT,
699   UFMT_32_32_SINT,
700   UFMT_32_32_FLOAT,
701 
702   UFMT_16_16_16_16_UNORM,
703   UFMT_16_16_16_16_SNORM,
704   UFMT_16_16_16_16_USCALED,
705   UFMT_16_16_16_16_SSCALED,
706   UFMT_16_16_16_16_UINT,
707   UFMT_16_16_16_16_SINT,
708   UFMT_16_16_16_16_FLOAT,
709 
710   UFMT_32_32_32_UINT,
711   UFMT_32_32_32_SINT,
712   UFMT_32_32_32_FLOAT,
713   UFMT_32_32_32_32_UINT,
714   UFMT_32_32_32_32_SINT,
715   UFMT_32_32_32_32_FLOAT,
716 
717   UFMT_FIRST = UFMT_INVALID,
718   UFMT_LAST = UFMT_32_32_32_32_FLOAT,
719 };
720 
721 } // namespace UfmtGFX11
722 
723 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
724 
725 enum Id : unsigned { // id of symbolic names
726   ID_QUAD_PERM = 0,
727   ID_BITMASK_PERM,
728   ID_SWAP,
729   ID_REVERSE,
730   ID_BROADCAST
731 };
732 
733 enum EncBits : unsigned {
734 
735   // swizzle mode encodings
736 
737   QUAD_PERM_ENC         = 0x8000,
738   QUAD_PERM_ENC_MASK    = 0xFF00,
739 
740   BITMASK_PERM_ENC      = 0x0000,
741   BITMASK_PERM_ENC_MASK = 0x8000,
742 
743   // QUAD_PERM encodings
744 
745   LANE_MASK             = 0x3,
746   LANE_MAX              = LANE_MASK,
747   LANE_SHIFT            = 2,
748   LANE_NUM              = 4,
749 
750   // BITMASK_PERM encodings
751 
752   BITMASK_MASK          = 0x1F,
753   BITMASK_MAX           = BITMASK_MASK,
754   BITMASK_WIDTH         = 5,
755 
756   BITMASK_AND_SHIFT     = 0,
757   BITMASK_OR_SHIFT      = 5,
758   BITMASK_XOR_SHIFT     = 10
759 };
760 
761 } // namespace Swizzle
762 
763 namespace SDWA {
764 
765 enum SdwaSel : unsigned {
766   BYTE_0 = 0,
767   BYTE_1 = 1,
768   BYTE_2 = 2,
769   BYTE_3 = 3,
770   WORD_0 = 4,
771   WORD_1 = 5,
772   DWORD = 6,
773 };
774 
775 enum DstUnused : unsigned {
776   UNUSED_PAD = 0,
777   UNUSED_SEXT = 1,
778   UNUSED_PRESERVE = 2,
779 };
780 
781 enum SDWA9EncValues : unsigned {
782   SRC_SGPR_MASK = 0x100,
783   SRC_VGPR_MASK = 0xFF,
784   VOPC_DST_VCC_MASK = 0x80,
785   VOPC_DST_SGPR_MASK = 0x7F,
786 
787   SRC_VGPR_MIN = 0,
788   SRC_VGPR_MAX = 255,
789   SRC_SGPR_MIN = 256,
790   SRC_SGPR_MAX_SI = 357,
791   SRC_SGPR_MAX_GFX10 = 361,
792   SRC_TTMP_MIN = 364,
793   SRC_TTMP_MAX = 379,
794 };
795 
796 } // namespace SDWA
797 
798 namespace DPP {
799 
800 // clang-format off
801 enum DppCtrl : unsigned {
802   QUAD_PERM_FIRST   = 0,
803   QUAD_PERM_ID      = 0xE4, // identity permutation
804   QUAD_PERM_LAST    = 0xFF,
805   DPP_UNUSED1       = 0x100,
806   ROW_SHL0          = 0x100,
807   ROW_SHL_FIRST     = 0x101,
808   ROW_SHL_LAST      = 0x10F,
809   DPP_UNUSED2       = 0x110,
810   ROW_SHR0          = 0x110,
811   ROW_SHR_FIRST     = 0x111,
812   ROW_SHR_LAST      = 0x11F,
813   DPP_UNUSED3       = 0x120,
814   ROW_ROR0          = 0x120,
815   ROW_ROR_FIRST     = 0x121,
816   ROW_ROR_LAST      = 0x12F,
817   WAVE_SHL1         = 0x130,
818   DPP_UNUSED4_FIRST = 0x131,
819   DPP_UNUSED4_LAST  = 0x133,
820   WAVE_ROL1         = 0x134,
821   DPP_UNUSED5_FIRST = 0x135,
822   DPP_UNUSED5_LAST  = 0x137,
823   WAVE_SHR1         = 0x138,
824   DPP_UNUSED6_FIRST = 0x139,
825   DPP_UNUSED6_LAST  = 0x13B,
826   WAVE_ROR1         = 0x13C,
827   DPP_UNUSED7_FIRST = 0x13D,
828   DPP_UNUSED7_LAST  = 0x13F,
829   ROW_MIRROR        = 0x140,
830   ROW_HALF_MIRROR   = 0x141,
831   BCAST15           = 0x142,
832   BCAST31           = 0x143,
833   DPP_UNUSED8_FIRST = 0x144,
834   DPP_UNUSED8_LAST  = 0x14F,
835   ROW_NEWBCAST_FIRST= 0x150,
836   ROW_NEWBCAST_LAST = 0x15F,
837   ROW_SHARE0        = 0x150,
838   ROW_SHARE_FIRST   = 0x150,
839   ROW_SHARE_LAST    = 0x15F,
840   ROW_XMASK0        = 0x160,
841   ROW_XMASK_FIRST   = 0x160,
842   ROW_XMASK_LAST    = 0x16F,
843   DPP_LAST          = ROW_XMASK_LAST
844 };
845 // clang-format on
846 
847 enum DppFiMode {
848   DPP_FI_0  = 0,
849   DPP_FI_1  = 1,
850   DPP8_FI_0 = 0xE9,
851   DPP8_FI_1 = 0xEA,
852 };
853 
854 } // namespace DPP
855 
856 namespace Exp {
857 
858 enum Target : unsigned {
859   ET_MRT0 = 0,
860   ET_MRT7 = 7,
861   ET_MRTZ = 8,
862   ET_NULL = 9,             // Pre-GFX11
863   ET_POS0 = 12,
864   ET_POS3 = 15,
865   ET_POS4 = 16,            // GFX10+
866   ET_POS_LAST = ET_POS4,   // Highest pos used on any subtarget
867   ET_PRIM = 20,            // GFX10+
868   ET_DUAL_SRC_BLEND0 = 21, // GFX11+
869   ET_DUAL_SRC_BLEND1 = 22, // GFX11+
870   ET_PARAM0 = 32,          // Pre-GFX11
871   ET_PARAM31 = 63,         // Pre-GFX11
872 
873   ET_NULL_MAX_IDX = 0,
874   ET_MRTZ_MAX_IDX = 0,
875   ET_PRIM_MAX_IDX = 0,
876   ET_MRT_MAX_IDX = 7,
877   ET_POS_MAX_IDX = 4,
878   ET_DUAL_SRC_BLEND_MAX_IDX = 1,
879   ET_PARAM_MAX_IDX = 31,
880 
881   ET_INVALID = 255,
882 };
883 
884 } // namespace Exp
885 
886 namespace VOP3PEncoding {
887 
888 enum OpSel : uint64_t {
889   OP_SEL_HI_0 = UINT64_C(1) << 59,
890   OP_SEL_HI_1 = UINT64_C(1) << 60,
891   OP_SEL_HI_2 = UINT64_C(1) << 14,
892 };
893 
894 } // namespace VOP3PEncoding
895 
896 namespace ImplicitArg {
897 // Implicit kernel argument offset for code object version 5.
898 enum Offset_COV5 : unsigned {
899   HOSTCALL_PTR_OFFSET = 80,
900   MULTIGRID_SYNC_ARG_OFFSET = 88,
901   HEAP_PTR_OFFSET = 96,
902 
903   DEFAULT_QUEUE_OFFSET = 104,
904   COMPLETION_ACTION_OFFSET = 112,
905 
906   PRIVATE_BASE_OFFSET = 192,
907   SHARED_BASE_OFFSET = 196,
908   QUEUE_PTR_OFFSET = 200,
909 };
910 
911 } // namespace ImplicitArg
912 } // namespace AMDGPU
913 
914 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS                                0x00B028
915 #define   S_00B028_VGPRS(x)                                           (((x) & 0x3F) << 0)
916 #define   S_00B028_SGPRS(x)                                           (((x) & 0x0F) << 6)
917 #define   S_00B028_MEM_ORDERED(x)                                     (((x) & 0x1) << 25)
918 #define   G_00B028_MEM_ORDERED(x)                                     (((x) >> 25) & 0x1)
919 #define   C_00B028_MEM_ORDERED                                        0xFDFFFFFF
920 
921 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS                                0x00B02C
922 #define   S_00B02C_EXTRA_LDS_SIZE(x)                                  (((x) & 0xFF) << 8)
923 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS                                0x00B128
924 #define   S_00B128_MEM_ORDERED(x)                                     (((x) & 0x1) << 27)
925 #define   G_00B128_MEM_ORDERED(x)                                     (((x) >> 27) & 0x1)
926 #define   C_00B128_MEM_ORDERED                                        0xF7FFFFFF
927 
928 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS                                0x00B228
929 #define   S_00B228_WGP_MODE(x)                                        (((x) & 0x1) << 27)
930 #define   G_00B228_WGP_MODE(x)                                        (((x) >> 27) & 0x1)
931 #define   C_00B228_WGP_MODE                                           0xF7FFFFFF
932 #define   S_00B228_MEM_ORDERED(x)                                     (((x) & 0x1) << 25)
933 #define   G_00B228_MEM_ORDERED(x)                                     (((x) >> 25) & 0x1)
934 #define   C_00B228_MEM_ORDERED                                        0xFDFFFFFF
935 
936 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES                                0x00B328
937 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS                                0x00B428
938 #define   S_00B428_WGP_MODE(x)                                        (((x) & 0x1) << 26)
939 #define   G_00B428_WGP_MODE(x)                                        (((x) >> 26) & 0x1)
940 #define   C_00B428_WGP_MODE                                           0xFBFFFFFF
941 #define   S_00B428_MEM_ORDERED(x)                                     (((x) & 0x1) << 24)
942 #define   G_00B428_MEM_ORDERED(x)                                     (((x) >> 24) & 0x1)
943 #define   C_00B428_MEM_ORDERED                                        0xFEFFFFFF
944 
945 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS                                0x00B528
946 
947 #define R_00B84C_COMPUTE_PGM_RSRC2                                      0x00B84C
948 #define   S_00B84C_SCRATCH_EN(x)                                      (((x) & 0x1) << 0)
949 #define   G_00B84C_SCRATCH_EN(x)                                      (((x) >> 0) & 0x1)
950 #define   C_00B84C_SCRATCH_EN                                         0xFFFFFFFE
951 #define   S_00B84C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
952 #define   G_00B84C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
953 #define   C_00B84C_USER_SGPR                                          0xFFFFFFC1
954 #define   S_00B84C_TRAP_HANDLER(x)                                    (((x) & 0x1) << 6)
955 #define   G_00B84C_TRAP_HANDLER(x)                                    (((x) >> 6) & 0x1)
956 #define   C_00B84C_TRAP_HANDLER                                       0xFFFFFFBF
957 #define   S_00B84C_TGID_X_EN(x)                                       (((x) & 0x1) << 7)
958 #define   G_00B84C_TGID_X_EN(x)                                       (((x) >> 7) & 0x1)
959 #define   C_00B84C_TGID_X_EN                                          0xFFFFFF7F
960 #define   S_00B84C_TGID_Y_EN(x)                                       (((x) & 0x1) << 8)
961 #define   G_00B84C_TGID_Y_EN(x)                                       (((x) >> 8) & 0x1)
962 #define   C_00B84C_TGID_Y_EN                                          0xFFFFFEFF
963 #define   S_00B84C_TGID_Z_EN(x)                                       (((x) & 0x1) << 9)
964 #define   G_00B84C_TGID_Z_EN(x)                                       (((x) >> 9) & 0x1)
965 #define   C_00B84C_TGID_Z_EN                                          0xFFFFFDFF
966 #define   S_00B84C_TG_SIZE_EN(x)                                      (((x) & 0x1) << 10)
967 #define   G_00B84C_TG_SIZE_EN(x)                                      (((x) >> 10) & 0x1)
968 #define   C_00B84C_TG_SIZE_EN                                         0xFFFFFBFF
969 #define   S_00B84C_TIDIG_COMP_CNT(x)                                  (((x) & 0x03) << 11)
970 #define   G_00B84C_TIDIG_COMP_CNT(x)                                  (((x) >> 11) & 0x03)
971 #define   C_00B84C_TIDIG_COMP_CNT                                     0xFFFFE7FF
972 /* CIK */
973 #define   S_00B84C_EXCP_EN_MSB(x)                                     (((x) & 0x03) << 13)
974 #define   G_00B84C_EXCP_EN_MSB(x)                                     (((x) >> 13) & 0x03)
975 #define   C_00B84C_EXCP_EN_MSB                                        0xFFFF9FFF
976 /*     */
977 #define   S_00B84C_LDS_SIZE(x)                                        (((x) & 0x1FF) << 15)
978 #define   G_00B84C_LDS_SIZE(x)                                        (((x) >> 15) & 0x1FF)
979 #define   C_00B84C_LDS_SIZE                                           0xFF007FFF
980 #define   S_00B84C_EXCP_EN(x)                                         (((x) & 0x7F) << 24)
981 #define   G_00B84C_EXCP_EN(x)                                         (((x) >> 24) & 0x7F)
982 #define   C_00B84C_EXCP_EN
983 
984 #define R_0286CC_SPI_PS_INPUT_ENA                                       0x0286CC
985 #define R_0286D0_SPI_PS_INPUT_ADDR                                      0x0286D0
986 
987 #define R_00B848_COMPUTE_PGM_RSRC1                                      0x00B848
988 #define   S_00B848_VGPRS(x)                                           (((x) & 0x3F) << 0)
989 #define   G_00B848_VGPRS(x)                                           (((x) >> 0) & 0x3F)
990 #define   C_00B848_VGPRS                                              0xFFFFFFC0
991 #define   S_00B848_SGPRS(x)                                           (((x) & 0x0F) << 6)
992 #define   G_00B848_SGPRS(x)                                           (((x) >> 6) & 0x0F)
993 #define   C_00B848_SGPRS                                              0xFFFFFC3F
994 #define   S_00B848_PRIORITY(x)                                        (((x) & 0x03) << 10)
995 #define   G_00B848_PRIORITY(x)                                        (((x) >> 10) & 0x03)
996 #define   C_00B848_PRIORITY                                           0xFFFFF3FF
997 #define   S_00B848_FLOAT_MODE(x)                                      (((x) & 0xFF) << 12)
998 #define   G_00B848_FLOAT_MODE(x)                                      (((x) >> 12) & 0xFF)
999 #define   C_00B848_FLOAT_MODE                                         0xFFF00FFF
1000 #define   S_00B848_PRIV(x)                                            (((x) & 0x1) << 20)
1001 #define   G_00B848_PRIV(x)                                            (((x) >> 20) & 0x1)
1002 #define   C_00B848_PRIV                                               0xFFEFFFFF
1003 #define   S_00B848_DX10_CLAMP(x)                                      (((x) & 0x1) << 21)
1004 #define   G_00B848_DX10_CLAMP(x)                                      (((x) >> 21) & 0x1)
1005 #define   C_00B848_DX10_CLAMP                                         0xFFDFFFFF
1006 #define   S_00B848_DEBUG_MODE(x)                                      (((x) & 0x1) << 22)
1007 #define   G_00B848_DEBUG_MODE(x)                                      (((x) >> 22) & 0x1)
1008 #define   C_00B848_DEBUG_MODE                                         0xFFBFFFFF
1009 #define   S_00B848_IEEE_MODE(x)                                       (((x) & 0x1) << 23)
1010 #define   G_00B848_IEEE_MODE(x)                                       (((x) >> 23) & 0x1)
1011 #define   C_00B848_IEEE_MODE                                          0xFF7FFFFF
1012 #define   S_00B848_WGP_MODE(x)                                        (((x) & 0x1) << 29)
1013 #define   G_00B848_WGP_MODE(x)                                        (((x) >> 29) & 0x1)
1014 #define   C_00B848_WGP_MODE                                           0xDFFFFFFF
1015 #define   S_00B848_MEM_ORDERED(x)                                     (((x) & 0x1) << 30)
1016 #define   G_00B848_MEM_ORDERED(x)                                     (((x) >> 30) & 0x1)
1017 #define   C_00B848_MEM_ORDERED                                        0xBFFFFFFF
1018 #define   S_00B848_FWD_PROGRESS(x)                                    (((x) & 0x1) << 31)
1019 #define   G_00B848_FWD_PROGRESS(x)                                    (((x) >> 31) & 0x1)
1020 #define   C_00B848_FWD_PROGRESS                                       0x7FFFFFFF
1021 
1022 
1023 // Helpers for setting FLOAT_MODE
1024 #define FP_ROUND_ROUND_TO_NEAREST 0
1025 #define FP_ROUND_ROUND_TO_INF 1
1026 #define FP_ROUND_ROUND_TO_NEGINF 2
1027 #define FP_ROUND_ROUND_TO_ZERO 3
1028 
1029 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
1030 // precision.
1031 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1032 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1033 
1034 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1035 #define FP_DENORM_FLUSH_OUT 1
1036 #define FP_DENORM_FLUSH_IN 2
1037 #define FP_DENORM_FLUSH_NONE 3
1038 
1039 
1040 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
1041 // precision.
1042 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1043 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1044 
1045 #define R_00B860_COMPUTE_TMPRING_SIZE                                   0x00B860
1046 #define   S_00B860_WAVESIZE_PreGFX11(x)                               (((x) & 0x1FFF) << 12)
1047 #define   S_00B860_WAVESIZE_GFX11Plus(x)                              (((x) & 0x7FFF) << 12)
1048 
1049 #define R_0286E8_SPI_TMPRING_SIZE                                       0x0286E8
1050 #define   S_0286E8_WAVESIZE_PreGFX11(x)                               (((x) & 0x1FFF) << 12)
1051 #define   S_0286E8_WAVESIZE_GFX11Plus(x)                              (((x) & 0x7FFF) << 12)
1052 
1053 #define R_028B54_VGT_SHADER_STAGES_EN                                 0x028B54
1054 #define   S_028B54_HS_W32_EN(x)                                       (((x) & 0x1) << 21)
1055 #define   S_028B54_GS_W32_EN(x)                                       (((x) & 0x1) << 22)
1056 #define   S_028B54_VS_W32_EN(x)                                       (((x) & 0x1) << 23)
1057 #define R_0286D8_SPI_PS_IN_CONTROL                                    0x0286D8
1058 #define   S_0286D8_PS_W32_EN(x)                                       (((x) & 0x1) << 15)
1059 #define R_00B800_COMPUTE_DISPATCH_INITIATOR                           0x00B800
1060 #define   S_00B800_CS_W32_EN(x)                                       (((x) & 0x1) << 15)
1061 
1062 #define R_SPILLED_SGPRS         0x4
1063 #define R_SPILLED_VGPRS         0x8
1064 } // End namespace llvm
1065 
1066 #endif
1067