1 /* $NetBSD: ahbreg.h,v 1.19 2022/02/23 21:54:40 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Originally written by Julian Elischer (julian@tfs.com) 35 * for TRW Financial Systems for use under the MACH(2.5) operating system. 36 * 37 * TRW Financial Systems, in accordance with their agreement with Carnegie 38 * Mellon University, makes this software available to CMU to distribute 39 * or use in any manner that they see fit as long as this message is kept with 40 * the software. For this reason TFS also grants any other persons or 41 * organisations permission to use or modify this software. 42 * 43 * TFS supplies this software to be publicly redistributed 44 * on the understanding that TFS is not responsible for the correct 45 * functioning of this software in any circumstances. 46 */ 47 48 /* 49 * Offset of AHA1740 registers, relative from slot base. 50 */ 51 #define AHB_EISA_SLOT_OFFSET 0x0c80 52 #define AHB_EISA_IOSIZE 0x0080 53 54 /* 55 * AHA1740 EISA board mode registers (relative to port offset) 56 */ 57 #define PORTADDR 0x40 58 #define PORTADDR_ENHANCED 0x80 59 #define BIOSADDR 0x41 60 #define INTDEF 0x42 61 #define SCSIDEF 0x43 62 #define BUSDEF 0x44 63 /**** bit definitions for INTDEF ****/ 64 #define INT9 0x00 65 #define INT10 0x01 66 #define INT11 0x02 67 #define INT12 0x03 68 #define INT14 0x05 69 #define INT15 0x06 70 #define INTHIGH 0x08 /* interrupt signal is active-high */ 71 #define INTEN 0x10 72 /**** bit definitions for SCSIDEF ****/ 73 #define HSCSIID 0x0F /* our SCSI ID */ 74 #define RSTPWR 0x10 /* reset scsi bus on power up or reset */ 75 /**** bit definitions for BUSDEF ****/ 76 #define B0uS 0x00 /* give up bus immediately */ 77 #define B4uS 0x01 /* delay 4uSec. */ 78 #define B8uS 0x02 79 80 /* 81 * AHA1740 ENHANCED mode mailbox control regs (relative to port offset) 82 */ 83 #define MBOXOUT0 0x50 84 #define MBOXOUT1 0x51 85 #define MBOXOUT2 0x52 86 #define MBOXOUT3 0x53 87 88 #define ATTN 0x54 89 #define G2CNTRL 0x55 90 #define G2INTST 0x56 91 #define G2STAT 0x57 92 93 #define MBOXIN0 0x58 94 #define MBOXIN1 0x59 95 #define MBOXIN2 0x5A 96 #define MBOXIN3 0x5B 97 98 #define G2STAT2 0x5C 99 100 /* 101 * Bit definitions for the 5 control/status registers 102 */ 103 #define ATTN_TARGET 0x0F 104 #define ATTN_OPCODE 0xF0 105 #define OP_IMMED 0x10 106 #define AHB_TARG_RESET 0x80 107 #define OP_START_ECB 0x40 108 #define OP_ABORT_ECB 0x50 109 110 #define G2CNTRL_SET_HOST_READY 0x20 111 #define G2CNTRL_CLEAR_EISA_INT 0x40 112 #define G2CNTRL_HARD_RESET 0x80 113 114 #define G2INTST_TARGET 0x0F 115 #define G2INTST_INT_STAT 0xF0 116 #define AHB_ECB_OK 0x10 117 #define AHB_ECB_RECOVERED 0x50 118 #define AHB_HW_ERR 0x70 119 #define AHB_IMMED_OK 0xA0 120 #define AHB_ECB_ERR 0xC0 121 #define AHB_ASN 0xD0 /* for target mode */ 122 #define AHB_IMMED_ERR 0xE0 123 124 #define G2STAT_BUSY 0x01 125 #define G2STAT_INT_PEND 0x02 126 #define G2STAT_MBOX_EMPTY 0x04 127 128 #define G2STAT2_HOST_READY 0x01 129 130 #define AHB_NSEG 33 /* number of DMA segments supported */ 131 132 struct ahb_dma_seg { 133 uint32_t seg_addr; 134 uint32_t seg_len; 135 }; 136 137 struct ahb_ecb_status { 138 uint16_t status; 139 #define ST_DON 0x0001 140 #define ST_DU 0x0002 141 #define ST_QF 0x0008 142 #define ST_SC 0x0010 143 #define ST_DO 0x0020 144 #define ST_CH 0x0040 145 #define ST_INT 0x0080 146 #define ST_ASA 0x0100 147 #define ST_SNS 0x0200 148 #define ST_INI 0x0800 149 #define ST_ME 0x1000 150 #define ST_ECA 0x4000 151 uint8_t host_stat; 152 #define HS_OK 0x00 153 #define HS_CMD_ABORTED_HOST 0x04 154 #define HS_CMD_ABORTED_ADAPTER 0x05 155 #define HS_TIMED_OUT 0x11 156 #define HS_HARDWARE_ERR 0x20 157 #define HS_SCSI_RESET_ADAPTER 0x22 158 #define HS_SCSI_RESET_INCOMING 0x23 159 uint8_t target_stat; 160 uint32_t resid_count; 161 uint32_t resid_addr; 162 uint16_t addit_status; 163 uint8_t sense_len; 164 uint8_t unused[9]; 165 uint8_t cdb[6]; 166 }; 167 168 struct ahb_ecb { 169 uint8_t opcode; 170 #define ECB_SCSI_OP 0x01 171 uint8_t:4; 172 uint8_t options:3; 173 uint8_t:1; 174 uint16_t opt1; 175 #define ECB_CNE 0x0001 176 #define ECB_DI 0x0080 177 #define ECB_SES 0x0400 178 #define ECB_S_G 0x1000 179 #define ECB_DSB 0x4000 180 #define ECB_ARS 0x8000 181 uint16_t opt2; 182 #define ECB_LUN 0x0007 183 #define ECB_TAG 0x0008 184 #define ECB_TT 0x0030 185 #define ECB_ND 0x0040 186 #define ECB_DAT 0x0100 187 #define ECB_DIR 0x0200 188 #define ECB_ST 0x0400 189 #define ECB_CHK 0x0800 190 #define ECB_REC 0x4000 191 #define ECB_NRB 0x8000 192 uint16_t unused1; 193 uint32_t data_addr; 194 uint32_t data_length; 195 uint32_t status; 196 uint32_t link_addr; 197 uint16_t unused2; 198 uint16_t unused3; 199 uint32_t sense_ptr; 200 uint8_t req_sense_length; 201 uint8_t scsi_cmd_length; 202 uint16_t cksum; 203 uint8_t scsi_cmd[12]; 204 205 /*-----------------end of hardware supported fields----------------*/ 206 207 struct ahb_dma_seg ahb_dma[AHB_NSEG]; 208 struct ahb_ecb_status ecb_status; 209 struct scsi_sense_data ecb_sense; 210 211 TAILQ_ENTRY(ahb_ecb) chain; 212 struct ahb_ecb *nexthash; 213 uint32_t ecb_dma_addr; 214 struct scsipi_xfer *xs; /* the scsipi_xfer for this cmd */ 215 int flags; 216 #define ECB_ALLOC 0x01 217 #define ECB_ABORT 0x02 218 #define ECB_IMMED 0x04 219 #define ECB_IMMED_FAIL 0x08 220 int timeout; 221 222 /* 223 * This DMA map maps the buffer involved in the transfer. 224 * Its contents are loaded into "ahb_dma" above. 225 */ 226 bus_dmamap_t dmamap_xfer; 227 }; 228