1 /* $OpenBSD: rccosb4reg.h,v 1.3 2005/11/23 09:24:57 mickey Exp $ */ 2 3 /* 4 * Copyright (c) 2004,2005 Michael Shalayeff 5 * Copyright (c) 1999, by UCHIYAMA Yasushi 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. The name of the developer may NOT be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Register definitions for the RCC South Bridge interrupt controller. 31 */ 32 33 #define OSB4_LEGAL_LINK(link) ((link) >= 0 && (link) <= 0x1f) 34 35 #define OSB4_PIRQ_MASK 0xdefa 36 #define OSB4_LEGAL_IRQ(irq) ((irq) > 0 && (irq) <= 15 && \ 37 ((1 << (irq)) & OSB4_PIRQ_MASK) != 0) 38 39 /* 40 * PCI Interrupts Address Index Register 41 */ 42 #define OSB4_PIAIR 0xc00 43 #define OSB4_PIRR 0xc01 44 #define OSB4_PISP 3 /* special lines assumed to route thru ISA */ 45 46 /* 47 * ELCR - EDGE/LEVEL CONTROL REGISTER 48 * 49 * PCI I/O registers 0x4d0, 0x4d1 50 */ 51 #define OSB4_REG_ELCR 0x4d0 52 #define OSB4_REG_ELCR_SIZE 2 53