1 /* $OpenBSD: osiopreg.h,v 1.5 2005/11/21 21:52:47 miod Exp $ */ 2 /* $NetBSD: osiopreg.h,v 1.1 2001/04/30 04:47:51 tsutsui Exp $ */ 3 4 /* 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * @(#)siopreg.h 7.3 (Berkeley) 2/5/91 36 */ 37 38 /* 39 * NCR 53C710 SCSI interface hardware description. 40 * 41 * From the Mach scsi driver for the 53C710 and amiga siop driver 42 */ 43 44 /* byte lane definitions */ 45 #if BYTE_ORDER == LITTLE_ENDIAN 46 #define BL0 0 47 #define BL1 1 48 #define BL2 2 49 #define BL3 3 50 #else 51 #define BL0 3 52 #define BL1 2 53 #define BL2 1 54 #define BL3 0 55 #endif 56 57 #define OSIOP_SCNTL0 (0x00+BL0) /* rw: SCSI control reg 0 */ 58 #define OSIOP_SCNTL1 (0x00+BL1) /* rw: SCSI control reg 1 */ 59 #define OSIOP_SDID (0x00+BL2) /* rw: SCSI destination ID */ 60 #define OSIOP_SIEN (0x00+BL3) /* rw: SCSI interrupt enable */ 61 62 #define OSIOP_SCID (0x04+BL0) /* rw: SCSI Chip ID reg */ 63 #define OSIOP_SXFER (0x04+BL1) /* rw: SCSI Transfer reg */ 64 #define OSIOP_SODL (0x04+BL2) /* rw: SCSI Output Data Latch */ 65 #define OSIOP_SOCL (0x04+BL3) /* rw: SCSI Output Control Latch */ 66 67 #define OSIOP_SFBR (0x08+BL0) /* ro: SCSI First Byte Received */ 68 #define OSIOP_SIDL (0x08+BL1) /* ro: SCSI Input Data Latch */ 69 #define OSIOP_SBDL (0x08+BL2) /* ro: SCSI Bus Data Lines */ 70 #define OSIOP_SBCL (0x08+BL3) /* rw: SCSI Bus Control Lines */ 71 72 #define OSIOP_DSTAT (0x0c+BL0) /* ro: DMA status */ 73 #define OSIOP_SSTAT0 (0x0c+BL1) /* ro: SCSI status reg 0 */ 74 #define OSIOP_SSTAT1 (0x0c+BL2) /* ro: SCSI status reg 1 */ 75 #define OSIOP_SSTAT2 (0x0c+BL3) /* ro: SCSI status reg 2 */ 76 77 #define OSIOP_DSA 0x10 /* rw: Data Structure Address */ 78 79 #define OSIOP_CTEST0 (0x14+BL0) /* ro: Chip test register 0 */ 80 #define OSIOP_CTEST1 (0x14+BL1) /* ro: Chip test register 1 */ 81 #define OSIOP_CTEST2 (0x14+BL2) /* ro: Chip test register 2 */ 82 #define OSIOP_CTEST3 (0x14+BL3) /* ro: Chip test register 3 */ 83 84 #define OSIOP_CTEST4 (0x18+BL0) /* rw: Chip test register 4 */ 85 #define OSIOP_CTEST5 (0x18+BL1) /* rw: Chip test register 5 */ 86 #define OSIOP_CTEST6 (0x18+BL2) /* rw: Chip test register 6 */ 87 #define OSIOP_CTEST7 (0x18+BL3) /* rw: Chip test register 7 */ 88 89 #define OSIOP_TEMP 0x1c /* rw: Temporary Stack reg */ 90 91 #define OSIOP_DFIFO (0x20+BL0) /* rw: DMA FIFO */ 92 #define OSIOP_ISTAT (0x20+BL1) /* rw: Interrupt Status reg */ 93 #define OSIOP_CTEST8 (0x20+BL2) /* rw: Chip test register 8 */ 94 #define OSIOP_LCRC (0x20+BL3) /* rw: LCRC value */ 95 96 #define OSIOP_DBC 0x24 /* rw: DMA Counter reg (longword) */ 97 #define OSIOP_DBC0 (0x24+BL0) /* rw: DMA Byte Counter reg 0 */ 98 #define OSIOP_DBC1 (0x24+BL1) /* rw: DMA Byte Counter reg 1 */ 99 #define OSIOP_DBC2 (0x24+BL2) /* rw: DMA Byte Counter reg 2 */ 100 #define OSIOP_DCMD (0x24+BL3) /* rw: DMA Command Register */ 101 102 #define OSIOP_DNAD 0x28 /* rw: DMA Next Data Address */ 103 104 #define OSIOP_DSP 0x2c /* rw: DMA SCRIPTS Pointer reg */ 105 106 #define OSIOP_DSPS 0x30 /* rw: DMA SCRIPTS Pointer Save reg */ 107 108 #define OSIOP_SCRATCH 0x34 /* rw: Scratch register */ 109 110 #define OSIOP_DMODE (0x38+BL0) /* rw: DMA Mode reg */ 111 #define OSIOP_DIEN (0x38+BL1) /* rw: DMA Interrupt Enable */ 112 #define OSIOP_DWT (0x38+BL2) /* rw: DMA Watchdog Timer */ 113 #define OSIOP_DCNTL (0x38+BL3) /* rw: DMA Control reg */ 114 115 #define OSIOP_ADDER 0x3c /* ro: Adder Sum Output */ 116 117 #define OSIOP_NREGS 0x40 118 119 120 /* 121 * Register defines 122 */ 123 124 /* Scsi control register 0 (scntl0) */ 125 126 #define OSIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */ 127 #define OSIOP_ARB_SIMPLE 0x00 128 #define OSIOP_ARB_FULL 0xc0 129 #define OSIOP_SCNTL0_START 0x20 /* Start Sequence */ 130 #define OSIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */ 131 #define OSIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */ 132 #define OSIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */ 133 #define OSIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */ 134 #define OSIOP_SCNTL0_TRG 0x01 /* Target Mode */ 135 136 /* Scsi control register 1 (scntl1) */ 137 138 #define OSIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */ 139 #define OSIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */ 140 #define OSIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */ 141 #define OSIOP_SCNTL1_CON 0x10 /* Connected */ 142 #define OSIOP_SCNTL1_RST 0x08 /* Assert RST */ 143 #define OSIOP_SCNTL1_AESP 0x04 /* Assert even SCSI parity */ 144 #define OSIOP_SCNTL1_PAR 0x04 /* Force bad Parity */ 145 #define OSIOP_SCNTL1_RES0 0x02 /* Reserved */ 146 #define OSIOP_SCNTL1_RES1 0x01 /* Reserved */ 147 148 /* Scsi interrupt enable register (sien) */ 149 150 #define OSIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */ 151 #define OSIOP_SIEN_FCMP 0x40 /* Function Complete */ 152 #define OSIOP_SIEN_STO 0x20 /* (Re)Selection timeout */ 153 #define OSIOP_SIEN_SEL 0x10 /* (Re)Selected */ 154 #define OSIOP_SIEN_SGE 0x08 /* SCSI Gross Error */ 155 #define OSIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */ 156 #define OSIOP_SIEN_RST 0x02 /* RST asserted */ 157 #define OSIOP_SIEN_PAR 0x01 /* Parity Error */ 158 159 /* Scsi chip ID (scid) */ 160 161 #define OSIOP_SCID_VALUE(i) (1 << (i)) 162 163 /* Scsi transfer register (sxfer) */ 164 165 #define OSIOP_SXFER_DHP 0x80 /* Disable Halt on Parity error/ 166 ATN asserted */ 167 #define OSIOP_SXFER_TP 0x70 /* Synch Transfer Period */ 168 /* see specs for formulas: 169 Period = TCP * (4 + XFERP ) 170 TCP = 1 + CLK + 1..2; 171 */ 172 #define OSIOP_SXFER_MO 0x0f /* Synch Max Offset */ 173 #define OSIOP_MAX_OFFSET 8 174 175 /* Scsi output data latch register (sodl) */ 176 177 /* Scsi output control latch register (socl) */ 178 179 #define OSIOP_REQ 0x80 /* SCSI signal <x> asserted */ 180 #define OSIOP_ACK 0x40 181 #define OSIOP_BSY 0x20 182 #define OSIOP_SEL 0x10 183 #define OSIOP_ATN 0x08 184 #define OSIOP_MSG 0x04 185 #define OSIOP_CD 0x02 186 #define OSIOP_IO 0x01 187 188 #define OSIOP_PHASE(x) ((x) & (OSIOP_MSG|OSIOP_CD|OSIOP_IO)) 189 #define DATA_OUT_PHASE 0x00 190 #define DATA_IN_PHASE OSIOP_IO 191 #define COMMAND_PHASE OSIOP_CD 192 #define STATUS_PHASE (OSIOP_CD|OSIOP_IO) 193 #define MSG_OUT_PHASE (OSIOP_MSG|OSIOP_CD) 194 #define MSG_IN_PHASE (OSIOP_MSG|OSIOP_CD|OSIOP_IO) 195 196 /* Scsi first byte received register (sfbr) */ 197 198 /* Scsi input data latch register (sidl) */ 199 200 /* Scsi bus data lines register (sbdl) */ 201 202 /* Scsi bus control lines register (sbcl). Same as socl */ 203 204 #define OSIOP_SBCL_SSCF1 0x02 /* wo */ 205 #define OSIOP_SBCL_SSCF0 0x01 /* wo */ 206 207 /* DMA status register (dstat) */ 208 209 #define OSIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */ 210 #define OSIOP_DSTAT_RES 0x40 211 #define OSIOP_DSTAT_BF 0x20 /* Bus fault */ 212 #define OSIOP_DSTAT_ABRT 0x10 /* Aborted */ 213 #define OSIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */ 214 #define OSIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */ 215 #define OSIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */ 216 #define OSIOP_DSTAT_IID 0x01 /* Invalid Instruction Detected */ 217 218 /* Scsi status register 0 (sstat0) */ 219 220 #define OSIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */ 221 #define OSIOP_SSTAT0_FCMP 0x40 /* Function Complete */ 222 #define OSIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */ 223 #define OSIOP_SSTAT0_SEL 0x10 /* (Re)Selected */ 224 #define OSIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */ 225 #define OSIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */ 226 #define OSIOP_SSTAT0_RST 0x02 /* RST asserted */ 227 #define OSIOP_SSTAT0_PAR 0x01 /* Parity Error */ 228 229 /* Scsi status register 1 (sstat1) */ 230 231 #define OSIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */ 232 #define OSIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */ 233 #define OSIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */ 234 #define OSIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */ 235 #define OSIOP_SSTAT1_LOA 0x08 /* Lost arbitration */ 236 #define OSIOP_SSTAT1_WOA 0x04 /* Won arbitration */ 237 #define OSIOP_SSTAT1_RST 0x02 /* SCSI RST current value */ 238 #define OSIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */ 239 240 /* Scsi status register 2 (sstat2) */ 241 242 #define OSIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */ 243 #define OSIOP_SCSI_FIFO_DEEP 8 244 #define OSIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */ 245 #define OSIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */ 246 #define OSIOP_SSTAT2_CD 0x02 247 #define OSIOP_SSTAT2_IO 0x01 248 249 /* Chip test register 0 (ctest0) */ 250 251 #define OSIOP_CTEST0_RES0 0x80 252 #define OSIOP_CTEST0_BTD 0x40 /* Byte-to-byte Timer Disable */ 253 #define OSIOP_CTEST0_GRP 0x20 /* Generate Receive Parity */ 254 #define OSIOP_CTEST0_EAN 0x10 /* Enable Active Negation */ 255 #define OSIOP_CTEST0_HSC 0x08 /* Halt SCSI clock */ 256 #define OSIOP_CTEST0_ERF 0x04 /* Extend REQ/ACK Filtering */ 257 #define OSIOP_CTEST0_RES1 0x02 258 #define OSIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */ 259 260 261 /* Chip test register 1 (ctest1) */ 262 263 #define OSIOP_CTEST1_FMT 0xf0 /* Byte empty in DMA FIFO bottom 264 (high->byte3) */ 265 #define OSIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */ 266 267 /* Chip test register 2 (ctest2) */ 268 269 #define OSIOP_CTEST2_RES 0x80 270 #define OSIOP_CTEST2_SIGP 0x40 /* Signal process */ 271 #define OSIOP_CTEST2_SOFF 0x20 /* Synch Offset compare 272 (1-> zero Init, max Tgt */ 273 #define OSIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */ 274 #define OSIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */ 275 #define OSIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */ 276 #define OSIOP_CTEST2_DREQ 0x02 /* DREQ status */ 277 #define OSIOP_CTEST2_DACK 0x01 /* DACK status */ 278 279 /* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */ 280 281 /* Chip test register 4 (ctest4) */ 282 283 #define OSIOP_CTEST4_MUX 0x80 /* Host bus multiplex mode */ 284 #define OSIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */ 285 #define OSIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */ 286 #define OSIOP_CTEST4_SLBE 0x10 /* SCSI loopback enable */ 287 #define OSIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */ 288 #define OSIOP_CTEST4_FBL 0x07 /* DMA FIFO Byte Lane select 289 (from ctest6) 4->0, .. 7->3 */ 290 291 /* Chip test register 5 (ctest5) */ 292 293 #define OSIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */ 294 #define OSIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */ 295 #define OSIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */ 296 #define OSIOP_CTEST5_MASR 0x10 /* Master set/reset pulses 297 (of bits 3-0) */ 298 #define OSIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */ 299 #define OSIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */ 300 #define OSIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */ 301 #define OSIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */ 302 303 /* Chip test register 6 (ctest6) DMA FIFO access */ 304 305 /* Chip test register 7 (ctest7) */ 306 307 #define OSIOP_CTEST7_CDIS 0x80 /* Cache burst disable */ 308 #define OSIOP_CTEST7_SC1 0x40 /* Snoop control 1 */ 309 #define OSIOP_CTEST7_SC0 0x20 /* Snoop control 0 */ 310 #define OSIOP_CTEST7_STD 0x10 /* Selection timeout disable */ 311 #define OSIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */ 312 #define OSIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */ 313 #define OSIOP_CTEST7_TT1 0x02 /* Transfer type bit */ 314 #define OSIOP_CTEST7_DIFF 0x01 /* Differential mode */ 315 316 /* DMA FIFO register (dfifo) */ 317 318 #define OSIOP_DFIFO_FLF 0x80 /* Flush (spill) DMA FIFO */ 319 #define OSIOP_DFIFO_BO 0x7f /* FIFO byte offset counter */ 320 321 /* Interrupt status register (istat) */ 322 323 #define OSIOP_ISTAT_ABRT 0x80 /* Abort operation */ 324 #define OSIOP_ISTAT_RST 0x40 /* Software reset */ 325 #define OSIOP_ISTAT_SIGP 0x20 /* Signal process */ 326 #define OSIOP_ISTAT_RES 0x10 327 #define OSIOP_ISTAT_CON 0x08 /* Connected */ 328 #define OSIOP_ISTAT_RES1 0x04 329 #define OSIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */ 330 #define OSIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */ 331 332 /* Chip test register 8 (ctest8) */ 333 334 #define OSIOP_CTEST8_V 0xf0 /* Chip revision level */ 335 #define OSIOP_CTEST8_FLF 0x08 /* Flush DMA FIFO */ 336 #define OSIOP_CTEST8_CLF 0x04 /* Clear DMA and SCSI FIFOs */ 337 #define OSIOP_CTEST8_FM 0x02 /* Fetch pin mode */ 338 #define OSIOP_CTEST8_SM 0x01 /* Snoop pins mode */ 339 340 /* DMA Mode register (dmode) */ 341 342 #define OSIOP_DMODE_BL_MASK 0xc0 /* DMA burst length */ 343 #define OSIOP_DMODE_BL8 0xc0 /* 8 bytes */ 344 #define OSIOP_DMODE_BL4 0x80 /* 4 bytes */ 345 #define OSIOP_DMODE_BL2 0x40 /* 2 bytes */ 346 #define OSIOP_DMODE_BL1 0x00 /* 1 byte */ 347 #define OSIOP_DMODE_FC 0x30 /* Function code */ 348 #define OSIOP_DMODE_PD 0x08 /* Program/data */ 349 #define OSIOP_DMODE_FAM 0x04 /* fixed address mode */ 350 #define OSIOP_DMODE_U0 0x02 /* User programmable transfer type */ 351 #define OSIOP_DMODE_MAN 0x01 /* SCRIPTS in Manual start mode */ 352 353 /* DMA interrupt enable register (dien) */ 354 355 #define OSIOP_DIEN_RES 0xc0 356 #define OSIOP_DIEN_BF 0x20 /* On Bus Fault */ 357 #define OSIOP_DIEN_ABRT 0x10 /* On Abort */ 358 #define OSIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */ 359 #define OSIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */ 360 #define OSIOP_DIEN_WTD 0x02 /* On watchdog timeout */ 361 #define OSIOP_DIEN_IID 0x01 /* On illegal instruction detected */ 362 363 /* DMA control register (dcntl) */ 364 365 #define OSIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers: */ 366 #define OSIOP_DCNTL_CF_2 0x00 /* 0 --> 37.51..50.00 MHz, div=2 */ 367 #define OSIOP_DCNTL_CF_1_5 0x40 /* 1 --> 25.01..37.50 MHz, div=1.5 */ 368 #define OSIOP_DCNTL_CF_1 0x80 /* 2 --> 16.67..25.00 MHz, div=1 */ 369 #define OSIOP_DCNTL_CF_3 0xc0 /* 3 --> 50.01..66.67 MHz, div=3 */ 370 #define OSIOP_DCNTL_EA 0x20 /* Enable ACK */ 371 #define OSIOP_DCNTL_SSM 0x10 /* Single step mode */ 372 #define OSIOP_DCNTL_LLM 0x08 /* Enable SCSI Low-level mode */ 373 #define OSIOP_DCNTL_STD 0x04 /* Start DMA operation */ 374 #define OSIOP_DCNTL_FA 0x02 /* Fast arbitration */ 375 #define OSIOP_DCNTL_COM 0x01 /* 53C700 Compatibility */ 376