1 #ifndef _G_OS_NVOC_H_
2 #define _G_OS_NVOC_H_
3 #include "nvoc/runtime.h"
4
5 #ifdef __cplusplus
6 extern "C" {
7 #endif
8
9 /*
10 * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
11 * SPDX-License-Identifier: MIT
12 *
13 * Permission is hereby granted, free of charge, to any person obtaining a
14 * copy of this software and associated documentation files (the "Software"),
15 * to deal in the Software without restriction, including without limitation
16 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
17 * and/or sell copies of the Software, and to permit persons to whom the
18 * Software is furnished to do so, subject to the following conditions:
19 *
20 * The above copyright notice and this permission notice shall be included in
21 * all copies or substantial portions of the Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
28 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
29 * DEALINGS IN THE SOFTWARE.
30 */
31
32 #include "g_os_nvoc.h"
33
34
35 #ifndef _OS_H_
36 #define _OS_H_
37
38 /*!
39 * @file os.h
40 * @brief Interface for Operating System module
41 */
42
43 /* ------------------------ Core & Library Includes ------------------------- */
44 #include "core/core.h"
45 #include "containers/btree.h"
46 #include "ctrl/ctrl0073/ctrl0073dfp.h"
47
48 /* ------------------------ SDK & Interface Includes ------------------------ */
49 #include "nvsecurityinfo.h"
50 #include "nvacpitypes.h"
51 #include "nvimpshared.h" // TODO - should move from sdk to resman/interface
52 #include "nvi2c.h" // TODO - should move from sdk to resman/interface
53
54 /* ------------------------ OS Includes ------------------------------------- */
55 #include "os/nv_memory_type.h"
56 #include "os/capability.h"
57
58 /* ------------------------ Forward Declarations ---------------------------- */
59 struct OBJOS;
60
61 #ifndef __NVOC_CLASS_OBJOS_TYPEDEF__
62 #define __NVOC_CLASS_OBJOS_TYPEDEF__
63 typedef struct OBJOS OBJOS;
64 #endif /* __NVOC_CLASS_OBJOS_TYPEDEF__ */
65
66 #ifndef __nvoc_class_id_OBJOS
67 #define __nvoc_class_id_OBJOS 0xaa1d70
68 #endif /* __nvoc_class_id_OBJOS */
69
70
71
72 //
73 // The OS module should NOT depend on RM modules. The only exception is
74 // core/core.h.
75 //
76 // DO NOT ADD INCLUDES TO RM MODULE HEADERS FROM THIS FILE. OS module should be
77 // a leaf module. Dependencies on RM headers in this files results in circular
78 // dependencies as most modules depend on the OS module.
79 //
80 // Ideally, all types used by the OS module's interface are from the SDK,
81 // resman/interface or self-contained within the OS module header. For now,
82 // since the OS module depends on a few RM internal types we forward declare to
83 // avoid the need to pull in headers from across RM.
84 //
85 typedef struct SYS_STATIC_CONFIG SYS_STATIC_CONFIG;
86 typedef struct MEMORY_DESCRIPTOR MEMORY_DESCRIPTOR;
87 typedef struct IOVAMAPPING *PIOVAMAPPING;
88 typedef struct OBJGPUMGR OBJGPUMGR;
89 typedef struct EVENTNOTIFICATION EVENTNOTIFICATION, *PEVENTNOTIFICATION;
90 typedef struct DEVICE_MAPPING DEVICE_MAPPING;
91 typedef void *PUID_TOKEN;
92 typedef struct OBJTMR OBJTMR;
93 typedef struct OBJCL OBJCL;
94 typedef struct _GUID *LPGUID;
95
96 //
97 // Forward declare OS_GPU_INFO type
98 //
99 // TODO - We shouldn't need a special definition per-OS. OS implementations
100 // should use a consistent type
101 //
102 typedef struct nv_state_t OS_GPU_INFO;
103
104 /* ------------------------ OS Interface ------------------------------------ */
105
106 typedef struct os_wait_queue OS_WAIT_QUEUE;
107
108 //
109 // Defines and Typedefs used by the OS
110 //
111 typedef NvU64 OS_THREAD_HANDLE;
112
113 //
114 // Forward references for OS1HZTIMERENTRY symbols
115 //
116 typedef struct OS1HZTIMERENTRY *POS1HZTIMERENTRY;
117 typedef struct OS1HZTIMERENTRY OS1HZTIMERENTRY;
118
119 //
120 // Simple 1 second callback facility. Schedules the given routine to be called with the supplied data
121 // in approximately 1 second. Might be called from an elevated IRQL.
122 // Unlike the tmr facilities (tmrScheduleCallbackXXX), this does not rely on the hardware.
123 //
124 typedef void (*OS1HZPROC)(OBJGPU *, void *);
125
126 #define NV_OS_1HZ_ONESHOT 0x00000000
127 #define NV_OS_1HZ_REPEAT 0x00000001
128
129 struct OS1HZTIMERENTRY
130 {
131 OS1HZPROC callback;
132 void* data;
133 NvU32 flags;
134 POS1HZTIMERENTRY next;
135 };
136
137 typedef struct RM_PAGEABLE_SECTION {
138 void *osHandle; // handle returned from OS API
139 void *pDataSection; // pointer to a date inside the target data/bss/const segment
140 } RM_PAGEABLE_SECTION;
141
142
143 // OSSetVideoSource defines
144 #define NV_OS_VIDEO_SOURCE_MCE 0x0
145 #define NV_OS_VIDEO_SOURCE_WINDVR 0x1
146 #define NV_OS_VIDEO_SOURCE_WMP9 0x2
147 #define NV_OS_VIDEO_SOURCE_VMR9 0x3
148 #define NV_OS_VIDEO_SOURCE_WINDVD 0x4
149
150 // OSPollHotkeyState return values
151 #define NV_OS_HOTKEY_STATE_DISPLAY_CHANGE 0:0
152 #define NV_OS_HOTKEY_STATE_DISPLAY_CHANGE_NOT_FOUND 0x00000000
153 #define NV_OS_HOTKEY_STATE_DISPLAY_CHANGE_FOUND 0x00000001
154 #define NV_OS_HOTKEY_STATE_SCALE_EVENT 1:1
155 #define NV_OS_HOTKEY_STATE_SCALE_EVENT_NOT_FOUND 0x00000000
156 #define NV_OS_HOTKEY_STATE_SCALE_EVENT_FOUND 0x00000001
157 #define NV_OS_HOTKEY_STATE_LID_EVENT 2:2
158 #define NV_OS_HOTKEY_STATE_LID_EVENT_NOT_FOUND 0x00000000
159 #define NV_OS_HOTKEY_STATE_LID_EVENT_FOUND 0x00000001
160 #define NV_OS_HOTKEY_STATE_POWER_EVENT 3:3
161 #define NV_OS_HOTKEY_STATE_POWER_EVENT_NOT_FOUND 0x00000000
162 #define NV_OS_HOTKEY_STATE_POWER_EVENT_FOUND 0x00000001
163 #define NV_OS_HOTKEY_STATE_DOCK_EVENT 4:4
164 #define NV_OS_HOTKEY_STATE_DOCK_EVENT_NOT_FOUND 0x00000000
165 #define NV_OS_HOTKEY_STATE_DOCK_EVENT_FOUND 0x00000001
166
167 #define MAX_BRIGHTNESS_BCL_ELEMENTS 103
168
169 // ACPI _DOD Bit defines
170 // These bits are defined in the Hybrid SAS
171 #define NV_ACPI_DOD_DISPLAY_OWNER 20:18
172 #define NV_ACPI_DOD_DISPLAY_OWNER_ALL 0x00000000
173 #define NV_ACPI_DOD_DISPLAY_OWNER_MGPU 0x00000001
174 #define NV_ACPI_DOD_DISPLAY_OWNER_DGPU1 0x00000002
175
176 #define NV_OS_ALLOCFLAGS_LOCKPAGES NVBIT(0)
177 #define NV_OS_ALLOCFLAGS_PAGEDPOOL NVBIT(1)
178 #define NV_OS_ALLOCFLAGS_NONPAGEDPOOL 0
179
180 // ACPI 3.0a definitions for requested data length
181 #define NV_ACPI_DDC_REQUESTED_DATA_LENGTH_128B 0x00000001
182 #define NV_ACPI_DDC_REQUESTED_DATA_LENGTH_256B 0x00000002
183 #define NV_ACPI_DDC_REQUESTED_DATA_LENGTH_384B 0x00000003
184 #define NV_ACPI_DDC_REQUESTED_DATA_LENGTH_512B 0x00000004
185 #define NV_ACPI_DDC_REQUESTED_DATA_LENGTH_DEFAULT 0x00000001
186
187 typedef enum _OS_PEX_RECOVERY_STATUS
188 {
189 OS_PEX_RECOVERY_GPU_RESET_PENDING = 0,
190 OS_PEX_RECOVERY_GPU_RESTORED,
191 OS_PEX_RECOVERY_GPU_REMOVED
192 } OS_PEX_RECOVERY_STATUS;
193
194 // osBugCheck bugcode defines
195 #define OS_BUG_CHECK_BUGCODE_UNKNOWN (0)
196 #define OS_BUG_CHECK_BUGCODE_INTERNAL_TEST (1)
197 #define OS_BUG_CHECK_BUGCODE_BUS (2)
198 #define OS_BUG_CHECK_BUGCODE_ECC_DBE (3)
199 #define OS_BUG_CHECK_BUGCODE_NVLINK_TL_ERR (4)
200 #define OS_BUG_CHECK_BUGCODE_PAGED_SEGMENT (5)
201 #define OS_BUG_CHECK_BUGCODE_BSOD_ON_ASSERT (6)
202 #define OS_BUG_CHECK_BUGCODE_DISPLAY_UNDERFLOW (7)
203 #define OS_BUG_CHECK_BUGCODE_LAST OS_BUG_CHECK_BUGCODE_DISPLAY_UNDERFLOW
204
205 #define OS_BUG_CHECK_BUGCODE_STR \
206 { \
207 "Unknown Error", \
208 "Nv Internal Testing", \
209 "Bus Error", \
210 "Double Bit Error", \
211 "NVLink TL Error", \
212 "Invalid Bindata Access", \
213 "BSOD on Assert or Breakpoint", \
214 "Display Underflow" \
215 }
216
217 // Flags needed by OSAllocPagesNode
218 #define OS_ALLOC_PAGES_NODE_NONE 0x0
219 #define OS_ALLOC_PAGES_NODE_SKIP_RECLAIM 0x1
220
221 //
222 // Structures for osPackageRegistry and osUnpackageRegistry
223 //
224 typedef struct PACKED_REGISTRY_ENTRY
225 {
226 NvU32 nameOffset;
227 NvU8 type;
228 NvU32 data;
229 NvU32 length;
230 } PACKED_REGISTRY_ENTRY;
231
232 typedef struct PACKED_REGISTRY_TABLE
233 {
234 NvU32 size;
235 NvU32 numEntries;
236 PACKED_REGISTRY_ENTRY entries[0];
237 } PACKED_REGISTRY_TABLE;
238
239 // TODO: Merge with NV_REGISTRY_ENTRY_TYPE
240 //
241 // Values for PACKED_REGISTRY_ENTRY::type
242 //
243 #define REGISTRY_TABLE_ENTRY_TYPE_UNKNOWN 0
244 #define REGISTRY_TABLE_ENTRY_TYPE_DWORD 1
245 #define REGISTRY_TABLE_ENTRY_TYPE_BINARY 2
246 #define REGISTRY_TABLE_ENTRY_TYPE_STRING 3
247
248 typedef enum
249 {
250 NV_REGISTRY_ENTRY_TYPE_UNKNOWN = 0,
251 NV_REGISTRY_ENTRY_TYPE_DWORD,
252 NV_REGISTRY_ENTRY_TYPE_BINARY,
253 NV_REGISTRY_ENTRY_TYPE_STRING
254 } nv_reg_type_t;
255
256 /*
257 * nv_reg_entry_t
258 *
259 * regParmStr/regName
260 * Name of key
261 * type
262 * One of nv_reg_type_t enum
263 * data
264 * Integer data of key. Only used with DWORD type
265 * pdata
266 * Pointer to data of key. Only used with BINARY or STRING type
267 * len
268 * Length of pdata buffer. Only used with BINARY or STRING type
269 * next
270 * Next entry in linked list
271 */
272 typedef struct nv_reg_entry_s
273 {
274 char *regParmStr;
275 NvU32 type;
276 NvU32 data;
277 NvU8 *pdata;
278 NvU32 len;
279 struct nv_reg_entry_s *next;
280 } nv_reg_entry_t;
281
282 /*
283 * OS_DRIVER_BLOCK
284 *
285 * driverStart
286 * CPU VA of where the driver is loaded
287 * unique_id
288 * Debug GUID of the Driver. Used to match with Pdb
289 * age
290 * Additional GUID information
291 * offset
292 * Offset from VA to start of text
293 */
294 typedef struct {
295 NvP64 driverStart NV_ALIGN_BYTES(8);
296 NvU8 unique_id[16];
297 NvU32 age;
298 NvU32 offset;
299 } OS_DRIVER_BLOCK;
300
301 // Basic OS interface functions
302 typedef NvU32 OSSetEvent(OBJGPU *, NvP64);
303 typedef NV_STATUS OSEventNotification(OBJGPU *, PEVENTNOTIFICATION, NvU32, void *, NvU32);
304 typedef NV_STATUS OSEventNotificationWithInfo(OBJGPU *, PEVENTNOTIFICATION, NvU32, NvU32, NvU16, void *, NvU32);
305 typedef NV_STATUS OSObjectEventNotification(NvHandle, NvHandle, NvU32, PEVENTNOTIFICATION, NvU32, void *, NvU32);
306 typedef NV_STATUS NV_FORCERESULTCHECK OSAllocPages(MEMORY_DESCRIPTOR *);
307 typedef NV_STATUS NV_FORCERESULTCHECK OSAllocPagesInternal(MEMORY_DESCRIPTOR *);
308 typedef void OSFreePages(MEMORY_DESCRIPTOR *);
309 typedef void OSFreePagesInternal(MEMORY_DESCRIPTOR *);
310 typedef NV_STATUS NV_FORCERESULTCHECK OSLockMem(MEMORY_DESCRIPTOR *);
311 typedef NV_STATUS OSUnlockMem(MEMORY_DESCRIPTOR *);
312 typedef NV_STATUS NV_FORCERESULTCHECK OSMapGPU(OBJGPU *, RS_PRIV_LEVEL, NvU64, NvU64, NvU32, NvP64 *, NvP64 *);
313 typedef void OSUnmapGPU(OS_GPU_INFO *, RS_PRIV_LEVEL, NvP64, NvU64, NvP64);
314 typedef NV_STATUS NV_FORCERESULTCHECK OSNotifyEvent(OBJGPU *, PEVENTNOTIFICATION, NvU32, NvU32, NV_STATUS);
315 typedef NV_STATUS OSReadRegistryString(OBJGPU *, const char *, NvU8 *, NvU32 *);
316 typedef NV_STATUS OSWriteRegistryBinary(OBJGPU *, const char *, NvU8 *, NvU32);
317 typedef NV_STATUS OSWriteRegistryVolatile(OBJGPU *, const char *, NvU8 *, NvU32);
318 typedef NV_STATUS OSReadRegistryVolatile(OBJGPU *, const char *, NvU8 *, NvU32);
319 typedef NV_STATUS OSReadRegistryVolatileSize(OBJGPU *, const char *, NvU32 *);
320 typedef NV_STATUS OSReadRegistryBinary(OBJGPU *, const char *, NvU8 *, NvU32 *);
321 typedef NV_STATUS OSWriteRegistryDword(OBJGPU *, const char *, NvU32);
322 typedef NV_STATUS OSReadRegistryDword(OBJGPU *, const char *, NvU32 *);
323 typedef NV_STATUS OSReadRegistryDwordBase(OBJGPU *, const char *, NvU32 *);
324 typedef NV_STATUS OSReadRegistryStringBase(OBJGPU *, const char *, NvU8 *, NvU32 *);
325 typedef NV_STATUS OSPackageRegistry(OBJGPU *, PACKED_REGISTRY_TABLE *, NvU32 *);
326 typedef NV_STATUS OSUnpackageRegistry(PACKED_REGISTRY_TABLE *);
327 typedef NvBool OSQueueDpc(OBJGPU *);
328 typedef void OSFlushCpuWriteCombineBuffer(void);
329 typedef NV_STATUS OSNumaMemblockSize(NvU64 *);
330 typedef NvBool OSNumaOnliningEnabled(OS_GPU_INFO *);
331 typedef NV_STATUS OSAllocPagesNode(NvS32, NvLength, NvU32, NvU64 *);
332 typedef void OSAllocAcquirePage(NvU64, NvU32);
333 typedef void OSAllocReleasePage(NvU64, NvU32);
334 typedef NvU32 OSGetPageRefcount(NvU64);
335 typedef NvU32 OSCountTailPages(NvU64);
336 typedef NvU64 OSGetPageSize(void);
337 typedef NvU8 OSGetPageShift(void);
338
339
340 // We use osAcquireRmSema to catch "unported" sema code to new lock model
341 typedef NV_STATUS NV_FORCERESULTCHECK OSAcquireRmSema(void *);
342 typedef NvBool NV_FORCERESULTCHECK OSIsRmSemaOwner(void *);
343
344 #define DPC_RELEASE_ALL_GPU_LOCKS (1)
345 #define DPC_RELEASE_SINGLE_GPU_LOCK (2)
346
347 typedef NV_STATUS OSGpuLocksQueueRelease(OBJGPU *pGpu, NvU32 dpcGpuLockRelease);
348 typedef NvU32 OSApiLockAcquireConfigureFlags(NvU32 flags);
349 typedef NV_STATUS NV_FORCERESULTCHECK OSCondAcquireRmSema(void *);
350 typedef NvU32 OSReleaseRmSema(void *, OBJGPU *);
351
352 typedef NvU32 OSGetCpuCount(void);
353 typedef NvU32 OSGetMaximumCoreCount(void);
354 typedef NvU32 OSGetCurrentProcessorNumber(void);
355 typedef NV_STATUS OSDelay(NvU32);
356 typedef NV_STATUS OSDelayUs(NvU32);
357 typedef NV_STATUS OSDelayNs(NvU32);
358 typedef void OSSpinLoop(void);
359 typedef NvU64 OSGetMaxUserVa(void);
360 typedef NvU32 OSGetCpuVaAddrShift(void);
361 typedef NvU32 OSGetCurrentProcess(void);
362 typedef void OSGetCurrentProcessName(char *, NvU32);
363 typedef NvU32 OSGetCurrentPasid(void);
364 typedef NV_STATUS OSGetCurrentThread(OS_THREAD_HANDLE *);
365 typedef NV_STATUS OSAttachToProcess(void **, NvU32);
366 typedef void OSDetachFromProcess(void*);
367 typedef NV_STATUS OSVirtualToPhysicalAddr(MEMORY_DESCRIPTOR *, NvP64, RmPhysAddr *);
368 typedef NV_STATUS NV_FORCERESULTCHECK OSMapPciMemoryUser(OS_GPU_INFO *, RmPhysAddr, NvU64, NvU32, NvP64 *, NvP64 *, NvU32);
369 typedef void OSUnmapPciMemoryUser(OS_GPU_INFO *, NvP64, NvU64, NvP64);
370 typedef NV_STATUS NV_FORCERESULTCHECK OSMapPciMemoryKernelOld(OBJGPU *, RmPhysAddr, NvU64, NvU32, void **, NvU32);
371 typedef void OSUnmapPciMemoryKernelOld(OBJGPU *, void *);
372 typedef NV_STATUS NV_FORCERESULTCHECK OSMapPciMemoryKernel64(OBJGPU *, RmPhysAddr, NvU64, NvU32, NvP64 *, NvU32);
373 typedef void OSUnmapPciMemoryKernel64(OBJGPU *, NvP64);
374 typedef NV_STATUS NV_FORCERESULTCHECK OSMapSystemMemory(MEMORY_DESCRIPTOR *, NvU64, NvU64, NvBool, NvU32, NvP64*, NvP64*);
375 typedef void OSUnmapSystemMemory(MEMORY_DESCRIPTOR *, NvBool, NvU32, NvP64, NvP64);
376 typedef NvBool OSLockShouldToggleInterrupts(OBJGPU *);
377 typedef NV_STATUS OSGetPerformanceCounter(NvU64 *);
378 NvBool osDbgBreakpointEnabled(void);
379 typedef NV_STATUS OSAttachGpu(OBJGPU *, void *);
380 typedef NV_STATUS OSDpcAttachGpu(OBJGPU *, void *);
381 typedef void OSDpcDetachGpu(OBJGPU *);
382 typedef NV_STATUS OSHandleGpuLost(OBJGPU *);
383 typedef void OSHandleGpuSurpriseRemoval(OBJGPU *);
384 typedef void OSInitScalabilityOptions(OBJGPU *, void *);
385 typedef void OSHandleDeferredRecovery(OBJGPU *);
386 typedef NvBool OSIsSwPreInitOnly(OS_GPU_INFO *);
387
388 #define NVRM_MAX_FILE_NAME_LENGTH (128)
389 #define NVRM_FILE_ACCESS_READ NVBIT(0)
390 #define NVRM_FILE_ACCESS_WRITE NVBIT(1)
391
392 typedef void OSGetTimeoutParams(OBJGPU *, NvU32 *, NvU32 *, NvU32 *);
393 typedef NvBool OSIsRaisedIRQL(void);
394 typedef NvBool OSIsISR(void);
395 typedef NV_STATUS OSGetDriverBlock(OS_GPU_INFO *, OS_DRIVER_BLOCK *);
396 typedef NvBool OSIsEqualGUID(void *, void *);
397
398 #define OS_QUEUE_WORKITEM_FLAGS_NONE 0x00000000
399 #define OS_QUEUE_WORKITEM_FLAGS_DONT_FREE_PARAMS NVBIT(0)
400 #define OS_QUEUE_WORKITEM_FLAGS_FALLBACK_TO_DPC NVBIT(1)
401 //
402 // Lock flags:
403 // Only one of the LOCK_GPU flags should be provided. If multiple are,
404 // the priority ordering should be GPUS > GROUP_DEVICE > GROUP_SUBDEVICE
405 //
406 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA NVBIT(8)
407 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RW NVBIT(9)
408 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RO NVBIT(10)
409 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW NVBIT(11)
410 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RO NVBIT(12)
411 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_DEVICE_RW NVBIT(13)
412 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_DEVICE_RO NVBIT(14)
413 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW NVBIT(15)
414 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RO NVBIT(16)
415 //
416 // Perform a GPU full power sanity after getting GPU locks.
417 // One of the above LOCK_GPU flags must be provided when using this flag.
418 //
419 #define OS_QUEUE_WORKITEM_FLAGS_FULL_GPU_SANITY NVBIT(17)
420 #define OS_QUEUE_WORKITEM_FLAGS_FOR_PM_RESUME NVBIT(18)
421 typedef void OSWorkItemFunction(NvU32 gpuInstance, void *);
422 typedef void OSSystemWorkItemFunction(void *);
423 NV_STATUS osQueueWorkItemWithFlags(OBJGPU *, OSWorkItemFunction, void *, NvU32);
424
osQueueWorkItem(OBJGPU * pGpu,OSWorkItemFunction pFunction,void * pParams)425 static NV_INLINE NV_STATUS osQueueWorkItem(OBJGPU *pGpu, OSWorkItemFunction pFunction, void *pParams)
426 {
427 return osQueueWorkItemWithFlags(pGpu, pFunction, pParams, OS_QUEUE_WORKITEM_FLAGS_NONE);
428 }
429
430 NV_STATUS osQueueSystemWorkItem(OSSystemWorkItemFunction, void *);
431
432 // MXM ACPI calls
433 NV_STATUS osCallACPI_MXMX(OBJGPU *, NvU32, NvU8 *);
434 NV_STATUS osCallACPI_DDC(OBJGPU *, NvU32, NvU8*,NvU32*, NvBool);
435 NV_STATUS osCallACPI_BCL(OBJGPU *, NvU32, NvU32 *, NvU16 *);
436
437 // Display MUX ACPI calls
438 NV_STATUS osCallACPI_MXDS(OBJGPU *, NvU32, NvU32 *);
439 NV_STATUS osCallACPI_MXDM(OBJGPU *, NvU32, NvU32 *);
440 NV_STATUS osCallACPI_MXID(OBJGPU *, NvU32, NvU32 *);
441 NV_STATUS osCallACPI_LRST(OBJGPU *, NvU32, NvU32 *);
442
443 // Hybrid GPU ACPI calls
444 NV_STATUS osCallACPI_NVHG_GPUON(OBJGPU *, NvU32 *);
445 NV_STATUS osCallACPI_NVHG_GPUOFF(OBJGPU *, NvU32 *);
446 NV_STATUS osCallACPI_NVHG_GPUSTA(OBJGPU *, NvU32 *);
447 NV_STATUS osCallACPI_NVHG_MXDS(OBJGPU *, NvU32, NvU32 *);
448 NV_STATUS osCallACPI_NVHG_MXMX(OBJGPU *, NvU32, NvU32 *);
449 NV_STATUS osCallACPI_NVHG_DOS(OBJGPU *, NvU32, NvU32 *);
450 NV_STATUS osCallACPI_NVHG_ROM(OBJGPU *, NvU32 *, NvU32 *);
451 NV_STATUS osCallACPI_NVHG_DCS(OBJGPU *, NvU32, NvU32 *);
452 NV_STATUS osCallACPI_DOD(OBJGPU *, NvU32 *, NvU32 *);
453
454 // Optimus WMI ACPI calls
455 NV_STATUS osCallACPI_OPTM_GPUON(OBJGPU *);
456
457 // Generic ACPI _DSM call
458 NV_STATUS osCallACPI_DSM(OBJGPU *pGpu, ACPI_DSM_FUNCTION acpiDSMFunction,
459 NvU32 NVHGDSMSubfunction, NvU32 *pInOut, NvU16 *size);
460
461 // UEFI variable calls
462 NV_STATUS osGetUefiVariable(const char *, LPGUID, NvU8 *, NvU32 *);
463
464 // The following functions are also implemented in WinNT
465 void osQADbgRegistryInit(void);
466 typedef NV_STATUS OSGetVersionDump(void *);
467 // End of WinNT
468
469 // OS functions typically only implemented for MacOS core
470 // These next functions also appear on UNIX
471 typedef NvU32 OSnv_rdcr4(struct OBJOS *);
472 typedef NvU64 OSnv_rdxcr0(struct OBJOS *);
473 typedef int OSnv_cpuid(struct OBJOS *, int, int, NvU32 *, NvU32 *, NvU32 *, NvU32 *);
474 // end of functions shared between MacOSX and UNIX
475
476 // These next functions also appear on UNIX
477 typedef NvU32 OSnv_rdmsr(struct OBJOS *, NvU32, NvU32 *, NvU32 *);
478 typedef NvU32 OSnv_wrmsr(struct OBJOS *, NvU32, NvU32, NvU32);
479 // end functions shared by MacOS and UNIX
480
481 // NOTE: The following functions are also implemented in MODS
482 NV_STATUS osSimEscapeWrite(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, NvU32 Value);
483 NV_STATUS osSimEscapeWriteBuffer(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, void* pBuffer);
484 NV_STATUS osSimEscapeRead(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, NvU32 *Value);
485 NV_STATUS osSimEscapeReadBuffer(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, void* pBuffer);
486 NvU32 osGetSimulationMode(void);
487 typedef void OSLogString(const char*, ...);
488 typedef void OSFlushLog(void);
489 typedef void OSSetSurfaceName(void *pDescriptor, char *name);
490
491 // End of MODS functions
492
493 //Vista Specific Functions
494
495 NV_STATUS osSetupVBlank(OBJGPU *pGpu, void * pProc,
496 void * pParm1, void * pParm2, NvU32 Head, void * pParm3);
497
498 // Heap reserve tracking functions
499 typedef void OSInternalReserveAllocCallback(NvU64 offset, NvU64 size, NvU32 gpuId);
500 typedef void OSInternalReserveFreeCallback(NvU64 offset, NvU32 gpuId);
501
502
503 //
504 // SPB_GPS (Vista) specific defines
505 //
506 typedef struct
507 {
508 NvU64 cpuFPCounter1; // CPU Fixed Performance Counter 1
509 NvU64 cpuFPCounter2; // CPU Fixed Performance Counter 2
510 NvU64 cpuC0Counter; // C0 Counter
511 NvU64 cpuCoreTSC; // per core Time Stamp Counter value
512 NvU8 cpuCoreC0Value; // average C0 residency per core
513 NvU8 cpuCoreAperf; // CPU Aperf value per core
514
515 }OS_CPU_CORE_PERF_COUNTERS, *POS_CPU_CORE_PERF_COUNTERS;
516
517 typedef NV_STATUS OsGetSystemCpuLogicalCoreCounts(NvU32 *pCpuCoreCount);
518 typedef NV_STATUS OsGetSystemCpuC0AndAPerfCounters(NvU32 coreIndex, POS_CPU_CORE_PERF_COUNTERS pCpuPerfData);
519 typedef void OsEnableCpuPerformanceCounters(struct OBJOS *pOS);
520 typedef NV_STATUS OsCpuDpcObjInit(void **ppCpuDpcObj, OBJGPU *pGpu, NvU32 coreCount);
521 typedef void OsCpuDpcObjQueue(void **ppCpuDpcObj, NvU32 coreCount, POS_CPU_CORE_PERF_COUNTERS pCpuPerfData);
522 typedef void OsCpuDpcObjFree(void **ppCpuDpcObj);
523 typedef NV_STATUS OsSystemGetBatteryDrain(NvS32 *pChargeRate);
524
525 // OSDRIVERERROR structure
526 typedef struct
527 {
528 enum {
529 OS_DRIVER_ERROR_CODE_NONE = 0,
530 OS_DRIVER_ERROR_CODE_HP_GT216_VBIOS_BUG_587560,
531 OS_DRIVER_ERROR_CODE_COUNT, // Must always be last
532 } code;
533
534 union
535 {
536 void *osDriverErrorContextNone;
537
538 } context;
539
540 } OSDRIVERERROR, * POSDRIVERERROR;
541
542 typedef NV_STATUS OSPexRecoveryCallback(OS_GPU_INFO *, OS_PEX_RECOVERY_STATUS);
543
544 //
545 // Function pointer typedef for use as callback prototype when filtering
546 // address ranges in os memory access routines
547 //
548 typedef NV_STATUS (OSMemFilterCb)(void *pPriv, NvU64 addr, void *pData, NvU64 size, NvBool bRead);
549
550 // Structure typedef for storing the callback pointer and priv data
551 typedef struct
552 {
553 NODE node;
554 OSMemFilterCb *pFilterCb;
555 void *pPriv;
556 } OSMEMFILTERDATA, *POSMEMFILTERDATA;
557
558 //
559 // OS Functions typically only implemented for MODS
560 // Note: See comments above for other functions that
561 // are also implemented on MODS as well as other
562 // OS's.
563 //
564
565 typedef NvBool OSRmInitRm(struct OBJOS *);
566 typedef NV_STATUS OSGetPanelStrapAndIndex(struct OBJOS *, OBJGPU *, NvU32 *, NvU32 *);
567 typedef NV_STATUS OSNotifySbiosDisplayChangeEnd(OBJGPU *, NvU32);
568 typedef NvU32 OSGetDfpScalerFromSbios(OBJGPU *);
569 typedef NvU32 OSPollHotkeyState(OBJGPU *);
570
571 typedef NV_STATUS OSInitGpuMgr(OBJGPUMGR *);
572 typedef void OSSyncWithRmDestroy(void);
573 typedef void OSSyncWithGpuDestroy(NvBool);
574
575 typedef void OSModifyGpuSwStatePersistence(OS_GPU_INFO *, NvBool);
576
577 typedef NV_STATUS OSMemAddFilter(NvU64, NvU64, OSMemFilterCb*, void *);
578 typedef NV_STATUS OSMemRemoveFilter(NvU64);
579 typedef POSMEMFILTERDATA OSMemGetFilter(NvUPtr);
580
581 typedef NV_STATUS OSGetCarveoutInfo(NvU64*, NvU64*);
582 typedef NV_STATUS OSGetVPRInfo(NvU64*, NvU64*);
583 typedef NV_STATUS OSAllocInVPR(MEMORY_DESCRIPTOR*);
584 typedef NV_STATUS OSGetGenCarveout(NvU64*, NvU64 *, NvU32, NvU64);
585
586 typedef NvU32 OSPepReadReg(OBJGPU *, NvU32);
587 typedef void OSPepWriteReg(OBJGPU *, NvU32, NvU32);
588
589 typedef NV_STATUS OSI2CClosePorts(OS_GPU_INFO *, NvU32);
590 typedef NV_STATUS OSWriteI2CBufferDirect(OBJGPU *, NvU32, NvU8, void *, NvU32, void *, NvU32);
591 typedef NV_STATUS OSReadI2CBufferDirect(OBJGPU *, NvU32, NvU8, void *, NvU32, void *, NvU32);
592 typedef NV_STATUS OSI2CTransfer(OBJGPU *, NvU32, NvU8, nv_i2c_msg_t *, NvU32);
593 typedef NV_STATUS OSSetGpuRailVoltage(OBJGPU *, NvU32, NvU32*);
594 typedef NV_STATUS OSGetGpuRailVoltage(OBJGPU *, NvU32*);
595 typedef NV_STATUS OSGetGpuRailVoltageInfo(OBJGPU *, NvU32 *, NvU32 *, NvU32 *);
596 typedef NV_STATUS OSTegraSocGetImpImportData(TEGRA_IMP_IMPORT_DATA *);
597 typedef NV_STATUS OSTegraSocEnableDisableRfl(OS_GPU_INFO *, NvBool);
598 typedef NV_STATUS OSTegraAllocateDisplayBandwidth(OS_GPU_INFO *, NvU32, NvU32);
599
600 typedef NV_STATUS OSMemdrvQueryInterface(OS_GPU_INFO *);
601 typedef void OSMemdrvReleaseInterface(void);
602 typedef NV_STATUS OSMemdrvGetAsid(NvU32, NvU32 *);
603 typedef NV_STATUS OSMemdrvGetStreamId(NvU32, NvU32 *);
604
605 typedef NV_STATUS OSGC6PowerControl(OBJGPU *, NvU32, NvU32 *);
606
607 typedef RmPhysAddr OSPageArrayGetPhysAddr(OS_GPU_INFO *pOsGpuInfo, void* pPageData, NvU32 pageIndex);
608 typedef NV_STATUS OSGetChipInfo(OBJGPU *, NvU32*, NvU32*, NvU32*, NvU32*);
609 typedef NV_STATUS OSGetCurrentIrqPrivData(OS_GPU_INFO *, NvU32*);
610
611 typedef enum
612 {
613 RC_CALLBACK_IGNORE,
614 RC_CALLBACK_ISOLATE,
615 RC_CALLBACK_ISOLATE_NO_RESET,
616 } RC_CALLBACK_STATUS;
617 RC_CALLBACK_STATUS osRCCallback(OBJGPU *, NvHandle, NvHandle, NvHandle, NvHandle, NvU32, NvU32, NvU32 *, void *);
618 NvBool osCheckCallback(OBJGPU *);
619 RC_CALLBACK_STATUS osRCCallback_v2(OBJGPU *, NvHandle, NvHandle, NvHandle, NvHandle, NvU32, NvU32, NvBool, NvU32 *, void *);
620 NvBool osCheckCallback_v2(OBJGPU *);
621 typedef NV_STATUS OSReadPFPciConfigInVF(NvU32, NvU32*);
622
623 // Actual definition of the OBJOS structure
624
625 // Private field names are wrapped in PRIVATE_FIELD, which does nothing for
626 // the matching C source file, but causes diagnostics to be issued if another
627 // source file references the field.
628 #ifdef NVOC_OS_H_PRIVATE_ACCESS_ALLOWED
629 #define PRIVATE_FIELD(x) x
630 #else
631 #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x)
632 #endif
633
634 struct OBJOS {
635 const struct NVOC_RTTI *__nvoc_rtti;
636 struct Object __nvoc_base_Object;
637 struct Object *__nvoc_pbase_Object;
638 struct OBJOS *__nvoc_pbase_OBJOS;
639 NvBool PDB_PROP_OS_PAT_UNSUPPORTED;
640 NvBool PDB_PROP_OS_SLI_ALLOWED;
641 NvBool PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED;
642 NvBool PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT;
643 NvBool PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM;
644 NvBool PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED;
645 NvBool PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE;
646 NvBool PDB_PROP_OS_LIMIT_GPU_RESET;
647 NvBool PDB_PROP_OS_SUPPORTS_TDR;
648 NvBool PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI;
649 NvBool PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER;
650 NvBool PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS;
651 NvBool PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS;
652 OSnv_rdcr4 *osNv_rdcr4;
653 OSnv_rdxcr0 *osNv_rdxcr0;
654 OSnv_cpuid *osNv_cpuid;
655 OSnv_rdmsr *osNv_rdmsr;
656 OSnv_wrmsr *osNv_wrmsr;
657 OSRmInitRm *osRmInitRm;
658 OSPexRecoveryCallback *osPexRecoveryCallback;
659 OSInternalReserveAllocCallback *osInternalReserveAllocCallback;
660 OSInternalReserveFreeCallback *osInternalReserveFreeCallback;
661 OSPageArrayGetPhysAddr *osPageArrayGetPhysAddr;
662 NvU32 dynamicPowerSupportGpuMask;
663 NvBool bIsSimMods;
664 };
665
666 #ifndef __NVOC_CLASS_OBJOS_TYPEDEF__
667 #define __NVOC_CLASS_OBJOS_TYPEDEF__
668 typedef struct OBJOS OBJOS;
669 #endif /* __NVOC_CLASS_OBJOS_TYPEDEF__ */
670
671 #ifndef __nvoc_class_id_OBJOS
672 #define __nvoc_class_id_OBJOS 0xaa1d70
673 #endif /* __nvoc_class_id_OBJOS */
674
675 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJOS;
676
677 #define __staticCast_OBJOS(pThis) \
678 ((pThis)->__nvoc_pbase_OBJOS)
679
680 #ifdef __nvoc_os_h_disabled
681 #define __dynamicCast_OBJOS(pThis) ((OBJOS*)NULL)
682 #else //__nvoc_os_h_disabled
683 #define __dynamicCast_OBJOS(pThis) \
684 ((OBJOS*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(OBJOS)))
685 #endif //__nvoc_os_h_disabled
686
687 #define PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER_BASE_CAST
688 #define PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER_BASE_NAME PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER
689 #define PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS_BASE_CAST
690 #define PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS_BASE_NAME PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS
691 #define PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM_BASE_CAST
692 #define PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM_BASE_NAME PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM
693 #define PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED_BASE_CAST
694 #define PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED_BASE_NAME PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED
695 #define PDB_PROP_OS_LIMIT_GPU_RESET_BASE_CAST
696 #define PDB_PROP_OS_LIMIT_GPU_RESET_BASE_NAME PDB_PROP_OS_LIMIT_GPU_RESET
697 #define PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT_BASE_CAST
698 #define PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT_BASE_NAME PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT
699 #define PDB_PROP_OS_PAT_UNSUPPORTED_BASE_CAST
700 #define PDB_PROP_OS_PAT_UNSUPPORTED_BASE_NAME PDB_PROP_OS_PAT_UNSUPPORTED
701 #define PDB_PROP_OS_SLI_ALLOWED_BASE_CAST
702 #define PDB_PROP_OS_SLI_ALLOWED_BASE_NAME PDB_PROP_OS_SLI_ALLOWED
703 #define PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS_BASE_CAST
704 #define PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS_BASE_NAME PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS
705 #define PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE_BASE_CAST
706 #define PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE_BASE_NAME PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE
707 #define PDB_PROP_OS_SUPPORTS_TDR_BASE_CAST
708 #define PDB_PROP_OS_SUPPORTS_TDR_BASE_NAME PDB_PROP_OS_SUPPORTS_TDR
709 #define PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI_BASE_CAST
710 #define PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI_BASE_NAME PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI
711 #define PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED_BASE_CAST
712 #define PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED_BASE_NAME PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED
713
714 NV_STATUS __nvoc_objCreateDynamic_OBJOS(OBJOS**, Dynamic*, NvU32, va_list);
715
716 NV_STATUS __nvoc_objCreate_OBJOS(OBJOS**, Dynamic*, NvU32);
717 #define __objCreate_OBJOS(ppNewObj, pParent, createFlags) \
718 __nvoc_objCreate_OBJOS((ppNewObj), staticCast((pParent), Dynamic), (createFlags))
719
720 #undef PRIVATE_FIELD
721
722
723 NV_STATUS addProbe(OBJGPU *, NvU32);
724
725
726 typedef NV_STATUS OSFlushCpuCache(void);
727 typedef void OSAddRecordForCrashLog(void *, NvU32);
728 typedef void OSDeleteRecordForCrashLog(void *);
729
730 OSFlushCpuCache osFlushCpuCache;
731 OSAddRecordForCrashLog osAddRecordForCrashLog;
732 OSDeleteRecordForCrashLog osDeleteRecordForCrashLog;
733
734
735 //
736 // This file should only contain the most common OS functions that provide
737 // direct call. Ex. osDelay, osIsAdministrator
738 //
739 NV_STATUS osTegraSocPmPowergate(OS_GPU_INFO *pOsGpuInfo);
740 NV_STATUS osTegraSocPmUnpowergate(OS_GPU_INFO *pOsGpuInfo);
741 NV_STATUS osTegraSocDeviceReset(OS_GPU_INFO *pOsGpuInfo);
742 NV_STATUS osTegraSocBpmpSendMrq(OS_GPU_INFO *pOsGpuInfo,
743 NvU32 mrq,
744 const void *pRequestData,
745 NvU32 requestDataSize,
746 void *pResponseData,
747 NvU32 responseDataSize,
748 NvS32 *pRet,
749 NvS32 *pApiRet);
750 NV_STATUS osTegraSocGetImpImportData(TEGRA_IMP_IMPORT_DATA *pTegraImpImportData);
751 NV_STATUS osTegraSocEnableDisableRfl(OS_GPU_INFO *pOsGpuInfo, NvBool bEnable);
752 NV_STATUS osTegraAllocateDisplayBandwidth(OS_GPU_INFO *pOsGpuInfo,
753 NvU32 averageBandwidthKBPS,
754 NvU32 floorBandwidthKBPS);
755
756 NV_STATUS osGetCurrentProcessGfid(NvU32 *pGfid);
757 NvBool osIsAdministrator(void);
758 NvBool osAllowPriorityOverride(void);
759 NV_STATUS osGetCurrentTime(NvU32 *pSec,NvU32 *puSec);
760 NV_STATUS osGetCurrentTick(NvU64 *pTimeInNs);
761 NvU64 osGetTickResolution(void);
762 NvU64 osGetTimestamp(void);
763 NvU64 osGetTimestampFreq(void);
764
765 NV_STATUS osDeferredIsr(OBJGPU *pGpu);
766
767 void osEnableInterrupts(OBJGPU *pGpu);
768
769 void osDisableInterrupts(OBJGPU *pGpu,
770 NvBool bIsr);
771
772 void osBugCheck(NvU32 bugCode);
773 void osAssertFailed(void);
774
775 // OS PCI R/W functions
776 void *osPciInitHandle(NvU32 domain, NvU8 bus, NvU8 slot, NvU8 function,
777 NvU16 *pVendor, NvU16 *pDevice);
778 NvU32 osPciReadDword(void *pHandle, NvU32 offset);
779 NvU16 osPciReadWord(void *pHandle, NvU32 offset);
780 NvU8 osPciReadByte(void *pHandle, NvU32 offset);
781 void osPciWriteDword(void *pHandle, NvU32 offset, NvU32 value);
782 void osPciWriteWord(void *pHandle, NvU32 offset, NvU16 value);
783 void osPciWriteByte(void *pHandle, NvU32 offset, NvU8 value);
784
785 // OS RM capabilities calls
786
787 void osRmCapInitDescriptor(NvU64 *pCapDescriptor);
788 NV_STATUS osRmCapAcquire(OS_RM_CAPS *pOsRmCaps, NvU32 rmCap,
789 NvU64 capDescriptor,
790 NvU64 *dupedCapDescriptor);
791 void osRmCapRelease(NvU64 dupedCapDescriptor);
792 NV_STATUS osRmCapRegisterGpu(OS_GPU_INFO *pOsGpuInfo, OS_RM_CAPS **ppOsRmCaps);
793 void osRmCapUnregister(OS_RM_CAPS **ppOsRmCaps);
794 NV_STATUS osRmCapRegisterSmcPartition(OS_RM_CAPS *pGpuOsRmCaps,
795 OS_RM_CAPS **ppPartitionOsRmCaps,
796 NvU32 partitionId);
797 NV_STATUS osRmCapRegisterSmcExecutionPartition(
798 OS_RM_CAPS *pPartitionOsRmCaps,
799 OS_RM_CAPS **ppExecPartitionOsRmCaps,
800 NvU32 execPartitionId);
801 NV_STATUS osRmCapRegisterSys(OS_RM_CAPS **ppOsRmCaps);
802
803 NvBool osImexChannelIsSupported(void);
804 NvS32 osImexChannelGet(NvU64 descriptor);
805 NvS32 osImexChannelCount(void);
806
807 NV_STATUS osGetRandomBytes(NvU8 *pBytes, NvU16 numBytes);
808
809 NV_STATUS osAllocWaitQueue(OS_WAIT_QUEUE **ppWq);
810 void osFreeWaitQueue(OS_WAIT_QUEUE *pWq);
811 void osWaitUninterruptible(OS_WAIT_QUEUE *pWq);
812 void osWaitInterruptible(OS_WAIT_QUEUE *pWq);
813 void osWakeUp(OS_WAIT_QUEUE *pWq);
814
815 NvU32 osGetDynamicPowerSupportMask(void);
816
817 void osUnrefGpuAccessNeeded(OS_GPU_INFO *pOsGpuInfo);
818 NV_STATUS osRefGpuAccessNeeded(OS_GPU_INFO *pOsGpuInfo);
819
820 NvU32 osGetGridCspSupport(void);
821
822 NV_STATUS osIovaMap(PIOVAMAPPING pIovaMapping);
823 void osIovaUnmap(PIOVAMAPPING pIovaMapping);
824 NV_STATUS osGetAtsTargetAddressRange(OBJGPU *pGpu,
825 NvU64 *pAddr,
826 NvU32 *pAddrWidth,
827 NvU32 *pMask,
828 NvU32 *pMaskWidth,
829 NvBool bIsPeer,
830 NvU32 peerIndex);
831 NV_STATUS osGetFbNumaInfo(OBJGPU *pGpu,
832 NvU64 *pAddrPhys,
833 NvU64 *pAddrRsvdPhys,
834 NvS32 *pNodeId);
835 NV_STATUS osGetEgmInfo(OBJGPU *pGpu,
836 NvU64 *pPhysAddr,
837 NvU64 *pSize,
838 NvS32 *pNodeId);
839 NV_STATUS osGetForcedNVLinkConnection(OBJGPU *pGpu,
840 NvU32 maxLinks,
841 NvU32 *pLinkConnection);
842 NV_STATUS osGetForcedC2CConnection(OBJGPU *pGpu,
843 NvU32 maxLinks,
844 NvU32 *pLinkConnection);
845 void osSetNVLinkSysmemLinkState(OBJGPU *pGpu,NvBool enabled);
846 NV_STATUS osGetPlatformNvlinkLinerate(OBJGPU *pGpu,NvU32 *lineRate);
847 const struct nvlink_link_handlers* osGetNvlinkLinkCallbacks(void);
848
849 void osRemoveGpu(NvU32 domain, NvU8 bus, NvU8 device);
850 NvBool osRemoveGpuSupported(void);
851
852 void initVGXSpecificRegistry(OBJGPU *);
853
854 NV_STATUS nv_vgpu_rm_get_bar_info(OBJGPU *pGpu, const NvU8 *pMdevUuid, NvU64 *barSizes,
855 NvU64 *sparseOffsets, NvU64 *sparseSizes,
856 NvU32 *sparseCount, NvBool *isBar064bit,
857 NvU8 *configParams);
858 NV_STATUS osIsVgpuVfioPresent(void);
859 NV_STATUS osIsVfioPciCorePresent(void);
860 void osWakeRemoveVgpu(NvU32, NvU32);
861 NV_STATUS rm_is_vgpu_supported_device(OS_GPU_INFO *pNv, NvU32 pmc_boot_1,
862 NvU32 pmc_boot_42);
863 NV_STATUS osLockPageableDataSection(RM_PAGEABLE_SECTION *pSection);
864 NV_STATUS osUnlockPageableDataSection(RM_PAGEABLE_SECTION *pSection);
865
866 void osFlushGpuCoherentCpuCacheRange(OS_GPU_INFO *pOsGpuInfo,
867 NvU64 cpuVirtual,
868 NvU64 size);
869 NvBool osUidTokensEqual(PUID_TOKEN arg1, PUID_TOKEN arg2);
870
871 NV_STATUS osValidateClientTokens(PSECURITY_TOKEN arg1,
872 PSECURITY_TOKEN arg2);
873 PUID_TOKEN osGetCurrentUidToken(void);
874 PSECURITY_TOKEN osGetSecurityToken(void);
875
876 NV_STATUS osIsKernelBuffer(void *pArg1, NvU32 arg2);
877
878 NV_STATUS osMapViewToSection(OS_GPU_INFO *pArg1,
879 void *pSectionHandle,
880 void **ppAddress,
881 NvU64 actualSize,
882 NvU64 sectionOffset,
883 NvBool bIommuEnabled);
884 NV_STATUS osUnmapViewFromSection(OS_GPU_INFO *pArg1,
885 void *pAddress,
886 NvBool bIommuEnabled);
887
888 NV_STATUS osOpenTemporaryFile(void **ppFile);
889 void osCloseFile(void *pFile);
890 NV_STATUS osWriteToFile(void *pFile, NvU8 *buffer,
891 NvU64 size, NvU64 offset);
892 NV_STATUS osReadFromFile(void *pFile, NvU8 *buffer,
893 NvU64 size, NvU64 offset);
894
895 NV_STATUS osSrPinSysmem(OS_GPU_INFO *pArg1,
896 NvU64 commitSize,
897 void *pMdl);
898 NV_STATUS osSrUnpinSysmem(OS_GPU_INFO *pArg1);
899
900 void osPagedSegmentAccessCheck(void);
901
902 NV_STATUS osCreateMemFromOsDescriptorInternal(OBJGPU *pGpu, void *pAddress,
903 NvU32 flags, NvU64 size,
904 MEMORY_DESCRIPTOR **ppMemDesc,
905 NvBool bCachedKernel,
906 RS_PRIV_LEVEL privilegeLevel);
907
908 NV_STATUS osReserveCpuAddressSpaceUpperBound(void **ppSectionHandle,
909 NvU64 maxSectionSize);
910 void osReleaseCpuAddressSpaceUpperBound(void *pSectionHandle);
911
912 void* osGetPidInfo(void);
913 void osPutPidInfo(void *pOsPidInfo);
914 NV_STATUS osFindNsPid(void *pOsPidInfo, NvU32 *pNsPid);
915
916 // OS Tegra IPC functions
917 NV_STATUS osTegraDceRegisterIpcClient(NvU32 interfaceType, void *usrCtx,
918 NvU32 *clientId);
919 NV_STATUS osTegraDceClientIpcSendRecv(NvU32 clientId, void *msg,
920 NvU32 msgLength);
921 NV_STATUS osTegraDceUnregisterIpcClient(NvU32 clientId);
922
923 //
924 // Define OS-layer specific type instead of #include "clk_domains.h" for
925 // CLKWHICH, avoids upwards dependency from OS interface on higher level
926 // RM modules
927 //
928 typedef NvU32 OS_CLKWHICH;
929
930 NV_STATUS osTegraSocEnableClk(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM);
931 NV_STATUS osTegraSocDisableClk(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM);
932 NV_STATUS osTegraSocGetCurrFreqKHz(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM, NvU32 *pCurrFreqKHz);
933 NV_STATUS osTegraSocGetMaxFreqKHz(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM, NvU32 *pMaxFreqKHz);
934 NV_STATUS osTegraSocGetMinFreqKHz(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM, NvU32 *pMinFreqKHz);
935 NV_STATUS osTegraSocSetFreqKHz(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM, NvU32 reqFreqKHz);
936 NV_STATUS osTegraSocSetParent(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRMsource, OS_CLKWHICH whichClkRMparent);
937 NV_STATUS osTegraSocGetParent(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRMsource, OS_CLKWHICH *pWhichClkRMparent);
938
939 NV_STATUS osTegraSocDeviceReset(OS_GPU_INFO *pOsGpuInfo);
940 NV_STATUS osTegraSocPmPowergate(OS_GPU_INFO *pOsGpuInfo);
941 NV_STATUS osTegraSocPmUnpowergate(OS_GPU_INFO *pOsGpuInfo);
942 NV_STATUS osGetSyncpointAperture(OS_GPU_INFO *pOsGpuInfo,
943 NvU32 syncpointId,
944 NvU64 *physAddr,
945 NvU64 *limit,
946 NvU32 *offset);
947 NV_STATUS osTegraI2CGetBusState(OS_GPU_INFO *pOsGpuInfo, NvU32 port, NvS32 *scl, NvS32 *sda);
948 NV_STATUS osTegraSocParseFixedModeTimings(OS_GPU_INFO *pOsGpuInfo,
949 NvU32 dcbIndex,
950 NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS *pTimingsPerStream,
951 NvU8 *pNumTimings);
952
953 NV_STATUS osGetVersion(NvU32 *pMajorVer,
954 NvU32 *pMinorVer,
955 NvU32 *pBuildNum,
956 NvU16 *pServicePackMaj,
957 NvU16 *pProductType);
958
959 NvBool osGrService(OS_GPU_INFO *pOsGpuInfo, NvU32 grIdx, NvU32 intr, NvU32 nstatus, NvU32 addr, NvU32 dataLo);
960
961 NvBool osDispService(NvU32 Intr0, NvU32 Intr1);
962
963 NV_STATUS osReferenceObjectCount(void *pEvent);
964
965 NV_STATUS osDereferenceObjectCount(void *pEvent);
966
967 //
968 // Perform OS-specific error logging.
969 // Like libc's vsnprintf(), osErrorLogV() invalidates its va_list argument. The va_list argument
970 // may not be reused after osErrorLogV() returns. If the va_list is needed after the
971 // osErrorLogV() call, create a copy of the va_list using va_copy().
972 // The caller controls the lifetime of the va_list argument, and should free it using va_end.
973 //
974 void osErrorLogV(OBJGPU *pGpu, NvU32 num, const char * pFormat, va_list arglist);
975 void osErrorLog(OBJGPU *pGpu, NvU32 num, const char* pFormat, ...);
976
977 NV_STATUS osNvifInitialize(OBJGPU *pGpu);
978
979 NV_STATUS osNvifMethod(OBJGPU *pGpu, NvU32 func,
980 NvU32 subFunc, void *pInParam,
981 NvU16 inParamSize, NvU32 *pOutStatus,
982 void *pOutData, NvU16 *pOutDataSize);
983
984 NV_STATUS osCreateMemFromOsDescriptor(OBJGPU *pGpu, NvP64 pDescriptor,
985 NvHandle hClient, NvU32 flags,
986 NvU64 *pLimit,
987 MEMORY_DESCRIPTOR **ppMemDesc,
988 NvU32 descriptorType,
989 RS_PRIV_LEVEL privilegeLevel);
990
991 void* osMapKernelSpace(RmPhysAddr Start,
992 NvU64 Size,
993 NvU32 Mode,
994 NvU32 Protect);
995
996 void osUnmapKernelSpace(void *addr, NvU64 size);
997
998 NvBool osTestPcieExtendedConfigAccess(void *handle, NvU32 offset);
999
1000 NvU32 osGetCpuFrequency(void);
1001
1002 void osIoWriteByte(NvU32 Address, NvU8 Value);
1003
1004 NvU8 osIoReadByte(NvU32 Address);
1005
1006 void osIoWriteWord(NvU32 Address, NvU16 Value);
1007
1008 NvU16 osIoReadWord(NvU32 Address);
1009
1010 void osIoWriteDword(NvU32 port, NvU32 data);
1011
1012 NvU32 osIoReadDword(NvU32 port);
1013
1014 // OS functions to get memory pages
1015
1016 NV_STATUS osGetNumMemoryPages (MEMORY_DESCRIPTOR *pMemDesc, NvU32 *pNumPages);
1017 NV_STATUS osGetMemoryPages (MEMORY_DESCRIPTOR *pMemDesc, void *pPages, NvU32 *pNumPages);
1018
1019 NV_STATUS osGetAcpiTable(NvU32 tableSignature,
1020 void **ppTable,
1021 NvU32 tableSize,
1022 NvU32 *retSize);
1023
1024 NV_STATUS osInitGetAcpiTable(void);
1025
1026 // Read NvGlobal regkey
1027 NV_STATUS osGetNvGlobalRegistryDword(OBJGPU *, const char *pRegParmStr, NvU32 *pData);
1028
1029 NV_STATUS osGetIbmnpuGenregInfo(OS_GPU_INFO *pArg1,
1030 NvU64 *pArg2,
1031 NvU64 *pArg3);
1032
1033 NV_STATUS osGetIbmnpuRelaxedOrderingMode(OS_GPU_INFO *pArg1,
1034 NvBool *pArg2);
1035
1036 void osWaitForIbmnpuRsync(OS_GPU_INFO *pArg1);
1037
1038 NV_STATUS osGetAcpiRsdpFromUefi(NvU32 *pRsdpAddr);
1039
1040 NV_STATUS osCreateNanoTimer(OS_GPU_INFO *pArg1,
1041 void *tmrEvent,
1042 void **tmrUserData);
1043
1044 NV_STATUS osStartNanoTimer(OS_GPU_INFO *pArg1,
1045 void *pTimer,
1046 NvU64 timeNs);
1047
1048 NV_STATUS osCancelNanoTimer(OS_GPU_INFO *pArg1,
1049 void *pArg2);
1050
1051 NV_STATUS osDestroyNanoTimer(OS_GPU_INFO *pArg1,
1052 void *pArg2);
1053
1054 NV_STATUS osGetValidWindowHeadMask(OS_GPU_INFO *pArg1,
1055 NvU64 *pWindowHeadMask);
1056
1057 NV_STATUS osSchedule(void);
1058
1059 void osDmaSetAddressSize(OS_GPU_INFO *pArg1,
1060 NvU32 bits);
1061
1062 void osClientGcoffDisallowRefcount(OS_GPU_INFO *pArg1,
1063 NvBool arg2);
1064
1065 NV_STATUS osTegraSocGpioGetPinState(OS_GPU_INFO *pArg1,
1066 NvU32 arg2,
1067 NvU32 *pArg3);
1068
1069 void osTegraSocGpioSetPinState(OS_GPU_INFO *pArg1,
1070 NvU32 arg2,
1071 NvU32 arg3);
1072
1073 NV_STATUS osTegraSocGpioSetPinDirection(OS_GPU_INFO *pArg1,
1074 NvU32 arg2,
1075 NvU32 arg3);
1076
1077 NV_STATUS osTegraSocGpioGetPinDirection(OS_GPU_INFO *pArg1,
1078 NvU32 arg2,
1079 NvU32 *pArg3);
1080
1081 NV_STATUS osTegraSocGpioGetPinNumber(OS_GPU_INFO *pArg1,
1082 NvU32 arg2,
1083 NvU32 *pArg3);
1084
1085 NV_STATUS osTegraSocGpioGetPinInterruptStatus(OS_GPU_INFO *pArg1,
1086 NvU32 arg2,
1087 NvU32 arg3,
1088 NvBool *pArg4);
1089
1090 NV_STATUS osTegraSocGpioSetPinInterrupt(OS_GPU_INFO *pArg1,
1091 NvU32 arg2,
1092 NvU32 arg3);
1093
1094 NV_STATUS osTegraSocDsiParsePanelProps(OS_GPU_INFO *pArg1,
1095 void *pArg2);
1096
1097 NvBool osTegraSocIsDsiPanelConnected(OS_GPU_INFO *pArg1);
1098
1099 NV_STATUS osTegraSocDsiPanelEnable(OS_GPU_INFO *pArg1,
1100 void *pArg2);
1101
1102 NV_STATUS osTegraSocDsiPanelReset(OS_GPU_INFO *pArg1,
1103 void *pArg2);
1104
1105 void osTegraSocDsiPanelDisable(OS_GPU_INFO *pArg1,
1106 void *pArg2);
1107
1108 void osTegraSocDsiPanelCleanup(OS_GPU_INFO *pArg1,
1109 void *pArg2);
1110
1111 NV_STATUS osTegraSocResetMipiCal(OS_GPU_INFO *pArg1);
1112
1113 NV_STATUS osGetTegraNumDpAuxInstances(OS_GPU_INFO *pArg1,
1114 NvU32 *pArg2);
1115
1116 NvU32 osTegraSocFuseRegRead(NvU32 addr);
1117
1118 typedef void (*osTegraTsecCbFunc)(void*, void*);
1119
1120 NvU32 osTegraSocTsecSendCmd(void* cmd, osTegraTsecCbFunc cbFunc, void* cbContext);
1121
1122 NvU32 osTegraSocTsecEventRegister(osTegraTsecCbFunc cbFunc, void* cbContext, NvBool isInitEvent);
1123
1124 NvU32 osTegraSocTsecEventUnRegister(NvBool isInitEvent);
1125
1126 void* osTegraSocTsecAllocMemDesc(NvU32 numBytes, NvU32 *flcnAddr);
1127
1128 void osTegraSocTsecFreeMemDesc(void *memDesc);
1129
1130 NV_STATUS osTegraSocHspSemaphoreAcquire(NvU32 ownerId, NvBool bAcquire, NvU64 timeout);
1131
1132 NV_STATUS osTegraSocDpUphyPllInit(OS_GPU_INFO *pArg1, NvU32, NvU32);
1133
1134 NV_STATUS osTegraSocDpUphyPllDeInit(OS_GPU_INFO *pArg1);
1135
1136 NV_STATUS osGetCurrentIrqPrivData(OS_GPU_INFO *pArg1,
1137 NvU32 *pArg2);
1138
1139 NV_STATUS osGetTegraBrightnessLevel(OS_GPU_INFO *pArg1,
1140 NvU32 *pArg2);
1141
1142 NV_STATUS osSetTegraBrightnessLevel(OS_GPU_INFO *pArg1,
1143 NvU32 arg2);
1144
1145 NvBool osTegraSocGetHdcpEnabled(OS_GPU_INFO *pOsGpuInfo);
1146
1147 void osTegraGetDispSMMUStreamIds(
1148 OS_GPU_INFO *pOsGpuInfo,
1149 NvU32 *dispIsoStreamId,
1150 NvU32 *dispNisoStreamId
1151 );
1152
1153 NvBool osIsVga(OS_GPU_INFO *pArg1,
1154 NvBool bIsGpuPrimaryDevice);
1155
1156 void osInitOSHwInfo(OBJGPU *pGpu);
1157
1158 void osDestroyOSHwInfo(OBJGPU *pGpu);
1159
1160 NV_STATUS osUserHandleToKernelPtr(NvU32 hClient,
1161 NvP64 Handle,
1162 NvP64 *pHandle);
1163
1164 NV_STATUS osGetSmbiosTable(void **pBaseVAddr, NvU64 *pLength,
1165 NvU64 *pNumSubTypes, NvU32 *pVersion);
1166
1167 void osPutSmbiosTable(void *pBaseVAddr, NvU64 length);
1168
1169 NvBool osIsNvswitchPresent(void);
1170
1171 void osQueueMMUFaultHandler(OBJGPU *);
1172
1173 NvBool osIsGpuAccessible(OBJGPU *pGpu);
1174 NvBool osIsGpuShutdown(OBJGPU *pGpu);
1175
1176 NvBool osMatchGpuOsInfo(OBJGPU *pGpu, void *pOsInfo);
1177
1178 void osReleaseGpuOsInfo(void *pOsInfo);
1179
1180 void osGpuWriteReg008(OBJGPU *pGpu,
1181 NvU32 thisAddress,
1182 NvV8 thisValue);
1183
1184 void osDevWriteReg008(OBJGPU *pGpu,
1185 DEVICE_MAPPING *pMapping,
1186 NvU32 thisAddress,
1187 NvV8 thisValue);
1188
1189 NvU8 osGpuReadReg008(OBJGPU *pGpu,
1190 NvU32 thisAddress);
1191
1192 NvU8 osDevReadReg008(OBJGPU *pGpu,
1193 DEVICE_MAPPING *pMapping,
1194 NvU32 thisAddress);
1195
1196 void osGpuWriteReg016(OBJGPU *pGpu,
1197 NvU32 thisAddress,
1198 NvV16 thisValue);
1199
1200 void osDevWriteReg016(OBJGPU *pGpu,
1201 DEVICE_MAPPING *pMapping,
1202 NvU32 thisAddress,
1203 NvV16 thisValue);
1204
1205 NvU16 osGpuReadReg016(OBJGPU *pGpu,
1206 NvU32 thisAddress);
1207
1208 NvU16 osDevReadReg016(OBJGPU *pGpu,
1209 DEVICE_MAPPING *pMapping,
1210 NvU32 thisAddress);
1211
1212 void osGpuWriteReg032(OBJGPU *pGpu,
1213 NvU32 thisAddress,
1214 NvV32 thisValue);
1215
1216 void osDevWriteReg032(OBJGPU *pGpu,
1217 DEVICE_MAPPING *pMapping,
1218 NvU32 thisAddress,
1219 NvV32 thisValue);
1220
1221 NvU32 osGpuReadReg032(OBJGPU *pGpu,
1222 NvU32 thisAddress);
1223
1224 NvU32 osDevReadReg032(OBJGPU *pGpu,
1225 DEVICE_MAPPING *pMapping,
1226 NvU32 thisAddress);
1227
1228 NV_STATUS osIsr(OBJGPU *pGpu);
1229
1230 NV_STATUS osSanityTestIsr(OBJGPU *pGpu);
1231
1232 NV_STATUS osInitMapping(OBJGPU *pGpu);
1233
1234 NV_STATUS osVerifySystemEnvironment(OBJGPU *pGpu);
1235
1236 NV_STATUS osSanityTestIsr(OBJGPU *pGpu);
1237
1238 void osAllocatedRmClient(void* pOSInfo);
1239
1240 NvBool osTegraSocIsSimNetlistNet07(OS_GPU_INFO *pArg1);
1241
1242 NV_STATUS osConfigurePcieReqAtomics(OS_GPU_INFO *pOsGpuInfo, NvU32 *pMask);
1243
1244 NvBool osDmabufIsSupported(void);
1245
isrWrapper(NvBool testIntr,OBJGPU * pGpu)1246 static NV_INLINE NV_STATUS isrWrapper(NvBool testIntr, OBJGPU *pGpu)
1247 {
1248 //
1249 // If pGpu->testIntr is not true then use original osIsr function.
1250 // On VMware Esxi 6.0, both rm isr and dpc handlers are called from Esxi 6.0
1251 // dpc handler. Because of this when multiple GPU are present in the system,
1252 // we may get a call to rm_isr routine for a hw interrupt corresponding to a
1253 // previously initialized GPU. In that case we need to call original osIsr
1254 // function.
1255 //
1256
1257 NV_STATUS status = NV_OK;
1258
1259 if (testIntr)
1260 {
1261 status = osSanityTestIsr(pGpu);
1262 }
1263 else
1264 {
1265 status = osIsr(pGpu);
1266 }
1267
1268 return status;
1269 }
1270
1271 #define OS_PCIE_CAP_MASK_REQ_ATOMICS_32 NVBIT(0)
1272 #define OS_PCIE_CAP_MASK_REQ_ATOMICS_64 NVBIT(1)
1273 #define OS_PCIE_CAP_MASK_REQ_ATOMICS_128 NVBIT(2)
1274
1275 void osGetNumaMemoryUsage(NvS32 numaId, NvU64 *free_memory_bytes, NvU64 *total_memory_bytes);
1276
1277 NV_STATUS osNumaAddGpuMemory(OS_GPU_INFO *pOsGpuInfo, NvU64 offset,
1278 NvU64 size, NvU32 *pNumaNodeId);
1279 void osNumaRemoveGpuMemory(OS_GPU_INFO *pOsGpuInfo, NvU64 offset,
1280 NvU64 size, NvU32 numaNodeId);
1281
1282 NV_STATUS osOfflinePageAtAddress(NvU64 address);
1283
1284 //
1285 // Os 1Hz timer callback functions
1286 //
1287 // 1 second is the median and mean time between two callback runs, but the worst
1288 // case can be anywhere between 0 (back-to-back) or (1s+RMTIMEOUT).
1289 // N callbacks are at least (N-2) seconds apart.
1290 //
1291 // Callbacks can run at either DISPATCH_LEVEL or PASSIVE_LEVEL
1292 //
1293 NV_STATUS osInit1HzCallbacks(OBJTMR *pTmr);
1294 NV_STATUS osDestroy1HzCallbacks(OBJTMR *pTmr);
1295 NV_STATUS osSchedule1HzCallback(OBJGPU *pGpu, OS1HZPROC callback, void *pData, NvU32 flags);
1296 void osRemove1HzCallback(OBJGPU *pGpu, OS1HZPROC callback, void *pData);
1297 NvBool osRun1HzCallbacksNow(OBJGPU *pGpu);
1298 void osRunQueued1HzCallbacksUnderLock(OBJGPU *pGpu);
1299
1300 NV_STATUS osDoFunctionLevelReset(OBJGPU *pGpu);
1301
1302 void vgpuDevWriteReg032(
1303 OBJGPU *pGpu,
1304 NvU32 thisAddress,
1305 NvV32 thisValue,
1306 NvBool *vgpuHandled
1307 );
1308
1309 NvU32 vgpuDevReadReg032(
1310 OBJGPU *pGpu,
1311 NvU32 thisAddress,
1312 NvBool *vgpuHandled
1313 );
1314
1315 void osInitSystemStaticConfig(SYS_STATIC_CONFIG *);
1316
1317 void osDbgBugCheckOnAssert(void);
1318
1319 NvBool osBugCheckOnTimeoutEnabled(void);
1320
1321 //
1322 // TODO: to clean-up the rest of the list
1323 //
1324 OSAttachGpu osAttachGpu;
1325 OSDpcAttachGpu osDpcAttachGpu;
1326 OSDpcDetachGpu osDpcDetachGpu;
1327 OSHandleGpuLost osHandleGpuLost;
1328 OSHandleGpuSurpriseRemoval osHandleGpuSurpriseRemoval;
1329 OSInitScalabilityOptions osInitScalabilityOptions;
1330 OSQueueDpc osQueueDpc;
1331 OSRmInitRm osRmInitRm;
1332 OSSetEvent osSetEvent;
1333 OSEventNotification osEventNotification;
1334 OSEventNotificationWithInfo osEventNotificationWithInfo;
1335 OSObjectEventNotification osObjectEventNotification;
1336 OSNotifyEvent osNotifyEvent;
1337 OSFlushCpuWriteCombineBuffer osFlushCpuWriteCombineBuffer;
1338 OSDelay osDelay;
1339 OSSpinLoop osSpinLoop;
1340 OSDelayUs osDelayUs;
1341 OSDelayNs osDelayNs;
1342 OSGetCpuCount osGetCpuCount;
1343 OSGetMaximumCoreCount osGetMaximumCoreCount;
1344 OSGetCurrentProcessorNumber osGetCurrentProcessorNumber;
1345 OSGetVersionDump osGetVersionDump;
1346
1347 OSGetMaxUserVa osGetMaxUserVa;
1348 OSGetCpuVaAddrShift osGetCpuVaAddrShift;
1349 OSMemAddFilter osMemAddFilter;
1350 OSMemRemoveFilter osMemRemoveFilter;
1351 OSMemGetFilter osMemGetFilter;
1352
1353 OSAllocPagesInternal osAllocPagesInternal;
1354 OSFreePagesInternal osFreePagesInternal;
1355
1356 OSGetPageSize osGetPageSize;
1357 OSGetPageShift osGetPageShift;
1358 OSNumaMemblockSize osNumaMemblockSize;
1359 OSNumaOnliningEnabled osNumaOnliningEnabled;
1360 OSAllocPagesNode osAllocPagesNode;
1361 OSAllocAcquirePage osAllocAcquirePage;
1362 OSAllocReleasePage osAllocReleasePage;
1363 OSGetPageRefcount osGetPageRefcount;
1364 OSCountTailPages osCountTailPages;
1365 OSVirtualToPhysicalAddr osKernVirtualToPhysicalAddr;
1366 OSLockMem osLockMem;
1367 OSUnlockMem osUnlockMem;
1368 OSMapSystemMemory osMapSystemMemory;
1369 OSUnmapSystemMemory osUnmapSystemMemory;
1370 OSWriteRegistryDword osWriteRegistryDword;
1371 OSReadRegistryDword osReadRegistryDword;
1372 OSReadRegistryString osReadRegistryString;
1373 OSWriteRegistryBinary osWriteRegistryBinary;
1374 OSWriteRegistryVolatile osWriteRegistryVolatile;
1375 OSReadRegistryVolatile osReadRegistryVolatile;
1376 OSReadRegistryVolatileSize osReadRegistryVolatileSize;
1377 OSReadRegistryBinary osReadRegistryBinary;
1378 OSReadRegistryDwordBase osReadRegistryDwordBase;
1379 OSReadRegistryStringBase osReadRegistryStringBase;
1380 OSPackageRegistry osPackageRegistry;
1381 OSUnpackageRegistry osUnpackageRegistry;
1382 NV_STATUS osDestroyRegistry(void);
1383 nv_reg_entry_t* osGetRegistryList(void);
1384 NV_STATUS osSetRegistryList(nv_reg_entry_t *pRegList);
1385 OSMapPciMemoryUser osMapPciMemoryUser;
1386 OSUnmapPciMemoryUser osUnmapPciMemoryUser;
1387 OSMapPciMemoryKernelOld osMapPciMemoryKernelOld;
1388 OSMapPciMemoryKernel64 osMapPciMemoryKernel64;
1389 OSUnmapPciMemoryKernelOld osUnmapPciMemoryKernelOld;
1390 OSUnmapPciMemoryKernel64 osUnmapPciMemoryKernel64;
1391 OSMapGPU osMapGPU;
1392 OSUnmapGPU osUnmapGPU;
1393 OSLockShouldToggleInterrupts osLockShouldToggleInterrupts;
1394
1395 OSGetPerformanceCounter osGetPerformanceCounter;
1396
1397 OSI2CClosePorts osI2CClosePorts;
1398 OSWriteI2CBufferDirect osWriteI2CBufferDirect;
1399 OSReadI2CBufferDirect osReadI2CBufferDirect;
1400 OSI2CTransfer osI2CTransfer;
1401 OSSetGpuRailVoltage osSetGpuRailVoltage;
1402 OSGetGpuRailVoltage osGetGpuRailVoltage;
1403 OSGetChipInfo osGetChipInfo;
1404 OSGetGpuRailVoltageInfo osGetGpuRailVoltageInfo;
1405
1406 OSGetCurrentProcess osGetCurrentProcess;
1407 OSGetCurrentProcessName osGetCurrentProcessName;
1408 OSGetCurrentThread osGetCurrentThread;
1409 OSAttachToProcess osAttachToProcess;
1410 OSDetachFromProcess osDetachFromProcess;
1411 OSPollHotkeyState osPollHotkeyState;
1412
1413 OSIsRaisedIRQL osIsRaisedIRQL;
1414 OSIsISR osIsISR;
1415 OSGetDriverBlock osGetDriverBlock;
1416
1417 OSInitGpuMgr osInitGpuMgr;
1418
1419 OSSyncWithRmDestroy osSyncWithRmDestroy;
1420 OSSyncWithGpuDestroy osSyncWithGpuDestroy;
1421
1422 OSModifyGpuSwStatePersistence osModifyGpuSwStatePersistence;
1423
1424 OSPexRecoveryCallback osPexRecoveryCallback;
1425 OSHandleDeferredRecovery osHandleDeferredRecovery;
1426 OSIsSwPreInitOnly osIsSwPreInitOnly;
1427 OSGetCarveoutInfo osGetCarveoutInfo;
1428 OSGetVPRInfo osGetVPRInfo;
1429 OSAllocInVPR osAllocInVPR;
1430 OSGetGenCarveout osGetGenCarveout;
1431 OsGetSystemCpuLogicalCoreCounts osGetSystemCpuLogicalCoreCounts;
1432 OsGetSystemCpuC0AndAPerfCounters osGetSystemCpuC0AndAPerfCounters;
1433 OsEnableCpuPerformanceCounters osEnableCpuPerformanceCounters;
1434 OsCpuDpcObjInit osCpuDpcObjInit;
1435 OsCpuDpcObjQueue osCpuDpcObjQueue;
1436 OsCpuDpcObjFree osCpuDpcObjFree;
1437 OsSystemGetBatteryDrain osSystemGetBatteryDrain;
1438 OSGC6PowerControl osGC6PowerControl;
1439 OSReadPFPciConfigInVF osReadPFPciConfigInVF;
1440
1441 //
1442 // When the new basic lock model is enabled then the following legacy RM
1443 // system semaphore routines are stubbed.
1444 //
1445 #define osAllocRmSema(s) (NV_OK)
1446 #define osFreeRmSema(s)
1447 #define osIsAcquiredRmSema(s) (NV_TRUE)
1448 #define osIsRmSemaOwner(s) (NV_TRUE)
1449 #define osCondReleaseRmSema(s) (NV_TRUE)
1450 #define osAcquireRmSemaForced(s) osAcquireRmSema(s)
1451 #define osGpuLockSetOwner(s,t) (NV_OK)
1452
1453 //
1454 // This version of osAcquireRmSema asserts that the GPUs lock is held when the
1455 // basic lock model is enabled. This should help catch newly introduced
1456 // dependencies on the legacy RM system semaphore that do not have
1457 // corresponding corresponding basic lock model support.
1458 //
1459 OSAcquireRmSema osAcquireRmSema;
1460 OSAcquireRmSema osAcquireRmSemaForced;
1461
1462 OSApiLockAcquireConfigureFlags osApiLockAcquireConfigureFlags;
1463 OSGpuLocksQueueRelease osGpuLocksQueueRelease;
1464 OSCondAcquireRmSema osCondAcquireRmSema;
1465 OSReleaseRmSema osReleaseRmSema;
1466
1467 OSFlushLog osFlushLog;
1468 OSSetSurfaceName osSetSurfaceName;
1469
1470 #define MODS_ARCH_ERROR_PRINTF(format, ...)
1471 #define MODS_ARCH_INFO_PRINTF(format, ...)
1472 #define MODS_ARCH_REPORT(event, format, ...)
1473
1474
1475 #define osAllocPages(a) osAllocPagesInternal(a)
1476 #define osFreePages(a) osFreePagesInternal(a)
1477
1478 extern NV_STATUS constructObjOS(struct OBJOS *);
1479 extern void osInitObjOS(struct OBJOS *);
1480
1481 extern OSGetTimeoutParams osGetTimeoutParams;
1482
1483 //
1484 // NV OS simulation mode defines
1485 // Keep in sync with gpu.h SIM MODE defines until osGetSimulationMode is deprecated.
1486 //
1487 #ifndef NV_SIM_MODE_DEFS
1488 #define NV_SIM_MODE_DEFS
1489 #define NV_SIM_MODE_HARDWARE 0U
1490 #define NV_SIM_MODE_RTL 1U
1491 #define NV_SIM_MODE_CMODEL 2U
1492 #define NV_SIM_MODE_MODS_AMODEL 3U
1493 #define NV_SIM_MODE_TEGRA_FPGA 4U
1494 #define NV_SIM_MODE_INVALID (~0x0U)
1495 #endif
1496
1497 //
1498 // NV Heap control defines
1499 //
1500 #define NV_HEAP_CONTROL_INTERNAL 0
1501 #define NV_HEAP_CONTROL_EXTERNAL 1
1502
1503 // osDelayUs flags
1504 #define OSDELAYUS_FLAGS_USE_TMR_DELAY NVBIT(0)
1505
1506 // osEventNotification notifyIndex all value
1507 #define OS_EVENT_NOTIFICATION_INDEX_ALL (0xffffffff)
1508
1509 // tells osEventNotification to only issue notifies/events on this subdev
1510 #define OS_EVENT_NOTIFICATION_INDEX_MATCH_SUBDEV (0x10000000)
1511
1512 // Notify callback action
1513 #define NV_OS_WRITE_THEN_AWAKEN 0x00000001
1514
1515 //
1516 // Include per-OS definitions
1517 //
1518 // #ifdef out for nvoctrans, this hides include to system headers which
1519 // breaks the tool.
1520 //
1521 // TODO - we should delete the per-OS os_custom.h files exposed to
1522 // OS-agnostic code. Cross-OS code shouldn't pull in per-OS headers or
1523 // per-OS definitions.
1524 //
1525 #include "os_custom.h"
1526
1527 #define NV_SEMA_RELEASE_SUCCEED 0 // lock released, no waiting thread to notify
1528 #define NV_SEMA_RELEASE_FAILED 1 // failed to lock release
1529 #define NV_SEMA_RELEASE_NOTIFIED 2 // lock released, notify waiting thread
1530 #define NV_SEMA_RELEASE_DPC_QUEUED 3 // lock released, queue DPC to notify waiting thread
1531 #define NV_SEMA_RELEASE_DPC_FAILED 4 // lock released, but failed to queue a DPC to notify waiting thread
1532
1533 #define ADD_PROBE(pGpu, probeId)
1534
1535 #define IS_SIM_MODS(pOS) (pOS->bIsSimMods)
1536
1537 #endif // _OS_H_
1538
1539 #ifdef __cplusplus
1540 } // extern "C"
1541 #endif
1542
1543 #endif // _G_OS_NVOC_H_
1544