1 /** @file
2   Header file with all common HSIO information
3 
4   Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
5 
6   SPDX-License-Identifier: BSD-2-Clause-Patent
7 **/
8 
9 #ifndef _PCH_HSIO_H_
10 #define _PCH_HSIO_H_
11 
12 #define PCH_LANE_OWN_COMMON                      0x10
13 #define PCH_LANE_BDCAST                          0x11
14 #define PCH_HSIO_LANE_GROUP_NO                   0x09
15 #define PCH_HSIO_LANE_GROUP_COMMON_LANE          0x00
16 #define PCH_HSIO_LANE_GROUP_PCIE                 0x01
17 #define PCH_HSIO_LANE_GROUP_DMI                  0x02
18 #define PCH_HSIO_LANE_GROUP_GBE                  0x03
19 #define PCH_HSIO_LANE_GROUP_USB3                 0x04
20 #define PCH_HSIO_LANE_GROUP_SATA                 0x05
21 #define PCH_HSIO_LANE_GROUP_SSIC                 0x06
22 
23 
24 /**
25   PCH HSIO ChipsetInit Version Information
26 **/
27 typedef struct {
28   UINT16 BaseCrc;
29   UINT16 SusCrc;
30   UINT16 OemCrc;
31   UINT8  Version;
32   UINT8  Product;
33   UINT8  MetalLayer : 4;
34   UINT8  BaseLayer : 4;
35   UINT8  OemVersion;
36   UINT16 DebugMode : 1;
37   UINT16 OemCrcValid : 1;
38   UINT16 SusCrcValid : 1;
39   UINT16 BaseCrcValid : 1;
40   UINT16 Reserved : 12;
41 } PCH_HSIO_VER_INFO;
42 
43 #define PMC_DATA_CMD_SIZE   ((12/sizeof(UINT16))-1)
44 #define PMC_DATA_DELAY_CMD_SIZE ((4/sizeof(UINT16))-1)
45 
46 #define RECORD_OFFSET(X, Y)  ((X << 4) | Y)
47 /**
48   PCH HSIO ChipsetInit Command Field
49 **/
50 typedef struct {
51   UINT8 Command : 3;
52   UINT8 Size : 5;
53   UINT8 Pid;
54   UINT8 OpCode; //PrivateControlWrite
55   UINT8 Bar; //0
56   UINT8 Fbe; //First Byte Enable  : 0x0F
57   UINT8 Fid; //0
58   UINT16 Offset;
59   UINT32 Value;
60 } PCH_HSIO_CMD_FIELD;
61 
62 /**
63 PCH HSIO Delay XRAM Data
64 **/
65 typedef struct {
66   UINT8 Command : 3;
67   UINT8 Size : 5;
68   UINT8 DelayPeriod; //(00h = 1us, 01h = 10us, 02h = 100us, ..., 07h = 10s; others reserved)
69   UINT8 DelayCount; //(0 - 255); total delay = Delay period * Delay count
70   UINT8 Padding;
71 } PCH_HSIO_DELAY_CMD_FIELD;
72 
73 typedef enum {
74   Delay1us = 0x0,
75   Delay10us,
76   Delay100us,
77   Delay1ms,
78   Delay10ms,
79   Delay100ms,
80   Delay1s,
81   Delay10s
82 } PCH_HSIO_DELAY;
83 
84 /**
85 PCH PCIE PLL SSC Data
86 **/
87 #define MAX_PCIE_PLL_SSC_PERCENT  20
88 
89 #include <Private/CnlPchLpHsioDx.h>
90 
91 #endif //_PCH_HSIO_H_
92 
93