| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFrameLowering.cpp | 248 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
300 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 1018 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1032 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1101 unsigned OffsetReg, in buildIndirectWrite()
1133 unsigned OffsetReg, in buildIndirectRead()
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| H A D | AMDGPUCallLowering.cpp | 203 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset); in getStackAddress() local
408 auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset); in lowerParameterPtr() local
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| H A D | SIRegisterInfo.cpp | 694 Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in materializeFrameBaseRegister() local
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| H A D | AMDGPURegisterBankInfo.cpp | 1558 Register OffsetReg = MI.getOperand(3).getReg(); in applyMappingBFEIntrinsic() local
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| H A D | AMDGPUInstructionSelector.cpp | 3434 Register OffsetReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectSmrdSgpr() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 99 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
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| H A D | X86ISelLowering.cpp | 32161 unsigned OffsetReg = 0; in EmitVAARGWithCustomInserter() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 132 unsigned OffsetReg; member
626 unsigned OffsetReg = Op->getReg(); in MorphToMemRegReg() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 103 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress() local
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| H A D | Thumb2InstrInfo.cpp | 611 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg(); in rewriteT2FrameIndex() local
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| H A D | Thumb2SizeReduction.cpp | 567 unsigned OffsetReg = 0; in ReduceLoadStore() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 895 Register OffsetReg = I->getOperand(0).getReg(); in expandEhReturn() local
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| H A D | MipsCallLowering.cpp | 269 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress() local
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| H A D | MipsISelLowering.cpp | 2545 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; in lowerEH_RETURN() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOptAddrMode.cpp | 166 Register OffsetReg = MI.getOperand(2).getReg(); in canRemoveAddasl() local
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| H A D | HexagonISelLowering.cpp | 3101 unsigned OffsetReg = Hexagon::R28; in LowerEH_RETURN() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 248 unsigned OffsetReg; member
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 255 auto OffsetReg = MIRBuilder.buildConstant(s64, Offset); in getStackAddress() local
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| H A D | AArch64InstructionSelector.cpp | 5252 Register OffsetReg = OffsetInst->getOperand(1).getReg(); in selectExtendedSHL() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 94 unsigned OffsetReg = 0; member in __anond16a47630111::AArch64FastISel::Address
|