| /dports/audio/visp-go/visp-2585747/vendor/golang.org/x/text/unicode/bidi/ |
| H A D | bidi.go | 206 o.runes = append(o.runes, runes[prevI:])
299 // Bytes returns the text of the run in its original order.
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 Register OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
296 Register OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 Register OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
296 Register OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 Register OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
296 Register OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 Register OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
296 Register OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 Register OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
296 Register OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 Register OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
296 Register OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 Register OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
296 Register OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 Register OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
296 Register OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 Register OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
296 Register OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 Register OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
296 Register OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 Register OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
296 Register OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 Register OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
296 Register OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 Register OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
296 Register OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 Register OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
296 Register OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 unsigned OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
296 unsigned OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 205 unsigned OrigSrc0 = MI.getOperand(1).getReg(); in isProfitableToTransform() local
297 unsigned OrigSrc0 = MI.getOperand(1).getReg(); in transformInstruction() local
|