xref: /netbsd/sys/arch/amiga/dev/grf_clreg.h (revision bf3440b2)
1 /*	$NetBSD: grf_clreg.h,v 1.10 2008/12/18 05:04:22 mhitch Exp $	*/
2 
3 /*
4  * Copyright (c) 1995 Ezra Story
5  * Copyright (c) 1995 Kari Mettinen
6  * Copyright (c) 1994 Markus Wild
7  * Copyright (c) 1994 Lutz Vieweg
8  * All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *      This product includes software developed by Lutz Vieweg.
21  * 4. The name of the author may not be used to endorse or promote products
22  *    derived from this software without specific prior written permission
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  */
35 
36 #ifndef _GRF_CLREG_H
37 #define _GRF_CLREG_H
38 
39 /*
40  * Written & Copyright by Kari Mettinen, Ezra Story.
41  *
42  * This is derived from retina driver source
43  */
44 
45 /* Extension to grfvideo_mode to support text modes.
46  * This can be passed to both text & gfx functions
47  * without worry.  If gv.depth == 4, then the extended
48  * fields for a text mode are present.
49  */
50 struct grfcltext_mode {
51     	struct grfvideo_mode gv;
52     	unsigned short	fx; 	    /* font x dimension */
53     	unsigned short	fy; 	    /* font y dimension */
54     	unsigned short  cols;       /* screen dimensions */
55     	unsigned short	rows;
56     	void	    	*fdata;     /* font data */
57     	unsigned short	fdstart;
58     	unsigned short	fdend;
59 };
60 
61 
62 /* 5426 boards types, stored in  cltype in grf_cl.c .
63  * used to decide how to handle SR7 and Pass-through
64  */
65 
66 #define PICASSO		2167
67 #define SPECTRUM 	2193
68 #define PICCOLO		2195
69 
70 /* read VGA register */
71 #define vgar(ba, reg) (*(((volatile unsigned char *)ba)+reg))
72 
73 /* write VGA register */
74 #define vgaw(ba, reg, val) \
75 	*(((volatile unsigned char *)ba)+reg) = ((val) & 0xff)
76 
77 /*
78  * defines for the used register addresses (mw)
79  *
80  * NOTE: there are some registers that have different addresses when
81  *       in mono or color mode. We only support color mode, and thus
82  *       some addresses won't work in mono-mode!
83  *
84  * General and VGA-registers taken from retina driver. Fixed a few
85  * bugs in it. (SR and GR read address is Port + 1, NOT Port)
86  *
87  */
88 
89 
90 
91 
92 /* General Registers: */
93 #define GREG_STATUS0_R		0x03C2
94 #define GREG_STATUS1_R		0x03DA
95 #define GREG_MISC_OUTPUT_R	0x03CC
96 #define GREG_MISC_OUTPUT_W	0x03C2
97 #define GREG_FEATURE_CONTROL_R	0x03CA
98 #define GREG_FEATURE_CONTROL_W	0x03DA
99 #define GREG_POS		0x0102
100 
101 /* Attribute Controller: */
102 #define ACT_ADDRESS		0x03C0
103 #define ACT_ADDRESS_R		0x03C1
104 #define ACT_ADDRESS_W		0x03C0
105 #define ACT_ADDRESS_RESET	0x03DA
106 #define ACT_ID_PALETTE0		0x00
107 #define ACT_ID_PALETTE1		0x01
108 #define ACT_ID_PALETTE2		0x02
109 #define ACT_ID_PALETTE3		0x03
110 #define ACT_ID_PALETTE4		0x04
111 #define ACT_ID_PALETTE5		0x05
112 #define ACT_ID_PALETTE6		0x06
113 #define ACT_ID_PALETTE7		0x07
114 #define ACT_ID_PALETTE8		0x08
115 #define ACT_ID_PALETTE9		0x09
116 #define ACT_ID_PALETTE10	0x0A
117 #define ACT_ID_PALETTE11	0x0B
118 #define ACT_ID_PALETTE12	0x0C
119 #define ACT_ID_PALETTE13	0x0D
120 #define ACT_ID_PALETTE14	0x0E
121 #define ACT_ID_PALETTE15	0x0F
122 #define ACT_ID_ATTR_MODE_CNTL	0x10
123 #define ACT_ID_OVERSCAN_COLOR	0x11
124 #define ACT_ID_COLOR_PLANE_ENA	0x12
125 #define ACT_ID_HOR_PEL_PANNING	0x13
126 #define ACT_ID_COLOR_SELECT	0x14
127 
128 /* Graphics Controller: */
129 #define GCT_ADDRESS		0x03CE
130 #define GCT_ADDRESS_R		0x03CF
131 #define GCT_ADDRESS_W		0x03CF
132 #define GCT_ID_SET_RESET	0x00
133 #define GCT_WR5_BG_EXT		0x00
134 #define GCT_ID_ENABLE_SET_RESET	0x01
135 #define GCT_ID_WR45_FG_EXT	0x01
136 #define GCT_ID_COLOR_COMPARE	0x02
137 #define GCT_ID_DATA_ROTATE	0x03
138 #define GCT_ID_READ_MAP_SELECT	0x04
139 #define GCT_ID_GRAPHICS_MODE	0x05
140 #define GCT_ID_MISC		0x06
141 #define GCT_ID_COLOR_XCARE	0x07
142 #define GCT_ID_BITMASK		0x08
143 #define GCT_ID_OFFSET_0		0x09
144 #define GCT_ID_OFFSET_1		0x0A
145 #define GCT_ID_MODE_EXT	0x0B
146 #define GCT_ID_COLOR_KEY	0x0C
147 #define GCT_ID_COLOR_KEY_MASK	0x0D
148 #define GCT_ID_MISC_CNTL	0x0E
149 #define GCT_ID_16BIT_BG_HIGH	0x10
150 #define GCT_ID_16BIT_FG_HIGH	0x11
151 #define GCT_ID_BLT_WIDTH_LOW	0x20
152 #define GCT_ID_BLT_WIDTH_HIGH	0x21
153 #define GCT_ID_BLT_HEIGHT_LOW	0x22
154 #define GCT_ID_BLT_HEIGHT_HIGH	0x23
155 #define GCT_ID_DST_PITCH_LOW	0x24
156 #define GCT_ID_DST_PITCH_HIGH	0x25
157 #define GCT_ID_SRC_PITCH_LOW	0x26
158 #define GCT_ID_SRC_PITCH_HIGH	0x27
159 #define GCT_ID_DST_START_LOW	0x28
160 #define GCT_ID_DST_START_MID	0x29
161 #define GCT_ID_DST_START_HIGH	0x2A
162 #define GCT_ID_SRC_START_LOW	0x2C
163 #define GCT_ID_SRC_START_MID	0x2D
164 #define GCT_ID_SRC_START_HIGH	0x2E
165 #define GCT_ID_BLT_MODE		0x30
166 #define GCT_ID_BLT_STAT_START	0x31
167 #define GCT_ID_BLT_ROP		0x32
168 #define GCT_ID_RESERVED		0x33
169 #define GCT_ID_TRP_COL_LOW	0x34	/* transparent color */
170 #define GCT_ID_TRP_COL_HIGH	0x35
171 #define GCT_ID_TRP_MASK_LOW	0x38
172 #define GCT_ID_TRP_MASK_HIGH	0x39
173 
174 
175 /* Sequencer: */
176 #define SEQ_ADDRESS		0x03C4
177 #define SEQ_ADDRESS_R		0x03C5
178 #define SEQ_ADDRESS_W		0x03C5
179 #define SEQ_ID_RESET		0x00
180 #define SEQ_ID_CLOCKING_MODE	0x01
181 #define SEQ_ID_MAP_MASK		0x02
182 #define SEQ_ID_CHAR_MAP_SELECT	0x03
183 
184 #define TEXT_PLANE_CHAR	    0x01
185 #define TEXT_PLANE_ATTR	    0x02
186 #define TEXT_PLANE_FONT	    0x04
187 
188 #define SEQ_ID_MEMORY_MODE	0x04
189 #define SEQ_ID_UNLOCK_EXT	0x06	/* down from here, all seq registers are Cirrus extensions */
190 #define SEQ_ID_EXT_SEQ_MODE     0x07
191 #define SEQ_ID_EEPROM_CNTL	0x08
192 #define SEQ_ID_SCRATCH_0        0x09
193 #define SEQ_ID_SCRATCH_1	0x0A
194 #define SEQ_ID_VCLK_0_NUM	0x0B
195 #define SEQ_ID_VCLK_1_NUM	0x0C
196 #define SEQ_ID_VCLK_2_NUM	0x0D
197 #define SEQ_ID_VCLK_3_NUM	0x0E
198 #define SEQ_ID_DRAM_CNTL	0x0F
199 #define SEQ_ID_CURSOR_X		0x10	/* Cursor position can't be set with WSeq
200 */
201 #define SEQ_ID_CURSOR_Y		0x11
202 #define SEQ_ID_CURSOR_ATTR	0x12
203 #define SEQ_ID_CURSOR_STORE	0x13
204 #define SEQ_ID_SCRATCH_2	0x14
205 #define SEQ_ID_SCRATCH_3	0x15
206 #define SEQ_ID_PERF_TUNE	0x16
207 #define SEQ_ID_CONF_RBACK	0x17
208 #define SEQ_ID_SIG_CNTL		0x18
209 #define SEQ_ID_SIG_RES_LOW	0x19
210 #define SEQ_ID_SIG_RES_HIGH	0x1A
211 #define SEQ_ID_VCLK_0_DENOM	0x1B
212 #define SEQ_ID_VCLK_1_DENOM	0x1C
213 #define SEQ_ID_VCLK_2_DENOM	0x1D
214 #define SEQ_ID_VCLK_3_DENOM	0x1E
215 #define SEQ_ID_MCLK_SELECT	0x1F
216 
217 /* CRT Controller: */
218 #define CRT_ADDRESS		0x03D4
219 #define CRT_ADDRESS_R		0x03D5
220 #define CRT_ADDRESS_W		0x03D5
221 #define CRT_ID_HOR_TOTAL	0x00
222 #define CRT_ID_HOR_DISP_ENA_END	0x01
223 #define CRT_ID_START_HOR_BLANK	0x02
224 #define CRT_ID_END_HOR_BLANK	0x03
225 #define CRT_ID_START_HOR_RETR	0x04
226 #define CRT_ID_END_HOR_RETR	0x05
227 #define CRT_ID_VER_TOTAL	0x06
228 #define CRT_ID_OVERFLOW		0x07
229 #define CRT_ID_PRESET_ROW_SCAN	0x08
230 #define CRT_ID_CHAR_HEIGHT	0x09	/* was MAX_SCANLINES on retina, weird, eh? */
231 #define CRT_ID_CURSOR_START	0x0A
232 #define CRT_ID_CURSOR_END	0x0B
233 #define CRT_ID_START_ADDR_HIGH	0x0C
234 #define CRT_ID_START_ADDR_LOW	0x0D
235 #define CRT_ID_CURSOR_LOC_HIGH	0x0E
236 #define CRT_ID_CURSOR_LOC_LOW	0x0F
237 #define CRT_ID_START_VER_RETR	0x10
238 #define CRT_ID_END_VER_RETR	0x11
239 #define CRT_ID_VER_DISP_ENA_END	0x12
240 #define CRT_ID_OFFSET		0x13
241 #define CRT_ID_UNDERLINE_LOC	0x14
242 #define CRT_ID_START_VER_BLANK	0x15
243 #define CRT_ID_END_VER_BLANK	0x16
244 #define CRT_ID_MODE_CONTROL	0x17
245 #define CRT_ID_LINE_COMPARE	0x18
246 #define CRT_ID_LACE_END         0x19
247 #define CRT_ID_LACE_CNTL        0x1A
248 #define CRT_ID_EXT_DISP_CNTL    0x1B
249 #define CRT_ID_SYNC_ADJ_GENLOCK 0x1C
250 #define CRT_ID_OVERLAY_EXT_CTRL_REG    0x1D
251 
252 #define CRT_ID_GD_LATCH_RBACK	0x22
253 
254 #define CRT_ID_ACT_TOGGLE_RBACK	0x24
255 #define CRT_ID_ACT_INDEX_RBACK 	0x26
256 
257 /* Pass-through */
258 #define PASS_ADDRESS		0x8000
259 #define PASS_ADDRESS_W		0x8000
260 /* Special Picasso Address */
261 #define PASS_ADDRESS_WP		0x9000
262 
263 /* Video DAC */
264 #define VDAC_ADDRESS	0x03c8
265 #define VDAC_ADDRESS_W	0x03c8
266 #define VDAC_ADDRESS_R	(((cltype==PICASSO)&&(cl_64bit==0))?0x03c7+0xfff:0x3c7)
267 #define VDAC_STATE	0x03c7
268 #define VDAC_DATA	(((cltype==PICASSO)&&(cl_64bit==0))?0x03c9+0xfff:0x3c9)
269 #define VDAC_MASK       0x03c6
270 #define HDR	        0x03c6	/* Hidden DAC register, 4 reads to access */
271 
272 
273 #define WGfx(ba, idx, val) \
274 	do { \
275 		vgaw(ba, GCT_ADDRESS, idx); \
276 		vgaw(ba, GCT_ADDRESS_W , val); \
277 	} while (0)
278 
279 #define WSeq(ba, idx, val) \
280 	do { \
281 		vgaw(ba, SEQ_ADDRESS, idx); \
282 		vgaw(ba, SEQ_ADDRESS_W , val); \
283 	} while (0) \
284 
285 /*		__asm volatile ("nop"); \ */
286 
287 #define WCrt(ba, idx, val) \
288 	do { \
289 		vgaw(ba, CRT_ADDRESS, idx); \
290 		vgaw(ba, CRT_ADDRESS_W , val); \
291 	} while (0)
292 
293 #define WAttr(ba, idx, val) \
294 	do {	\
295 		vgar(ba, ACT_ADDRESS_RESET); \
296 		vgaw(ba, ACT_ADDRESS_W, idx); \
297 		vgaw(ba, ACT_ADDRESS_W, val); \
298 	} while (0)
299 
300 #define SetTextPlane(ba, m) \
301 	do { \
302 		WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 ); \
303 		WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3))); \
304 	} while (0)
305 
306 #ifdef _KERNEL
307 int cl_mode(register struct grf_softc *gp, u_long cmd, void *arg,
308 			u_long a2, int a3);
309 int cl_load_mon(struct grf_softc *gp, struct grfcltext_mode *gv);
310 int grfcl_cnprobe(void);
311 void grfcl_iteinit(struct grf_softc *gp);
312 #endif
313 
314 #endif /* _GRF_RHREG_H */
315