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Searched defs:PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT (Results 1 – 3 of 3) sorted by path

/dragonfly/sys/dev/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h2201 #define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0x0000000d macro
H A Dbif_4_1_sh_mask.h4420 #define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd macro
H A Dbif_5_0_sh_mask.h4902 #define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd macro