Home
last modified time | relevance | path

Searched defs:PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT (Results 1 – 2 of 2) sorted by last modified time

/dragonfly/sys/dev/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h4669 #define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x00000000 macro
H A Dbif_4_1_sh_mask.h9644 #define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x0 macro