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Searched defs:PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK (Results 1 – 3 of 3) sorted by last modified time

/dragonfly/sys/dev/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_sh_mask.h7365 #define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000 macro
H A Dbif_3_0_sh_mask.h5468 #define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x00002000L macro
H A Dbif_4_1_sh_mask.h6807 #define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000 macro