1 /* $OpenBSD: stfpciephy.c,v 1.2 2024/10/17 01:57:18 jsg Exp $ */
2 /*
3 * Copyright (c) 2023 Mark Kettenis <kettenis@openbsd.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <sys/param.h>
19 #include <sys/systm.h>
20 #include <sys/device.h>
21
22 #include <machine/bus.h>
23 #include <machine/fdt.h>
24
25 #include <dev/ofw/openfirm.h>
26 #include <dev/ofw/ofw_misc.h>
27 #include <dev/ofw/fdt.h>
28
29 #define PCIE_KVO_LEVEL 0x28
30 #define PCIE_KVO_FINE_TUNE_LEVEL 0x91
31 #define PCIE_KVO_TUNE_SIGNAL 0x80
32 #define PCIE_KVO_FINE_TUNE_SIGNAL 0x0c
33
34 #define HREAD4(sc, reg) \
35 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
36 #define HWRITE4(sc, reg, val) \
37 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
38 #define HSET4(sc, reg, bits) \
39 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
40 #define HCLR4(sc, reg, bits) \
41 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
42
43 struct stfpciephy_softc {
44 struct device sc_dev;
45 bus_space_tag_t sc_iot;
46 bus_space_handle_t sc_ioh;
47
48 struct phy_device sc_pd;
49 };
50
51 int stfpciephy_match(struct device *, void *, void *);
52 void stfpciephy_attach(struct device *, struct device *, void *);
53
54 const struct cfattach stfpciephy_ca = {
55 sizeof (struct stfpciephy_softc), stfpciephy_match, stfpciephy_attach
56 };
57
58 struct cfdriver stfpciephy_cd = {
59 NULL, "stfpciephy", DV_DULL
60 };
61
62 int stfpciephy_enable(void *, uint32_t *);
63
64 int
stfpciephy_match(struct device * parent,void * match,void * aux)65 stfpciephy_match(struct device *parent, void *match, void *aux)
66 {
67 struct fdt_attach_args *faa = aux;
68
69 return OF_is_compatible(faa->fa_node, "starfive,jh7110-pcie-phy");
70 }
71
72 void
stfpciephy_attach(struct device * parent,struct device * self,void * aux)73 stfpciephy_attach(struct device *parent, struct device *self, void *aux)
74 {
75 struct stfpciephy_softc *sc = (struct stfpciephy_softc *)self;
76 struct fdt_attach_args *faa = aux;
77
78 if (faa->fa_nreg < 1) {
79 printf(": no registers\n");
80 return;
81 }
82
83 sc->sc_iot = faa->fa_iot;
84 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
85 faa->fa_reg[0].size, 0, &sc->sc_ioh)) {
86 printf(": can't map registers\n");
87 return;
88 }
89
90 printf("\n");
91
92 HWRITE4(sc, PCIE_KVO_LEVEL, PCIE_KVO_FINE_TUNE_LEVEL);
93 HWRITE4(sc, PCIE_KVO_TUNE_SIGNAL, PCIE_KVO_FINE_TUNE_SIGNAL);
94
95 sc->sc_pd.pd_node = faa->fa_node;
96 sc->sc_pd.pd_cookie = sc;
97 sc->sc_pd.pd_enable = stfpciephy_enable;
98 phy_register(&sc->sc_pd);
99 }
100
101 int
stfpciephy_enable(void * cookie,uint32_t * cells)102 stfpciephy_enable(void *cookie, uint32_t *cells)
103 {
104 return 0;
105 }
106