| /dports/sysutils/rovclock/rovclock-0.6e/ |
| H A D | pci.h | 60 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
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| /dports/lang/gnatdroid-sysroot-x86/android-19-x86/usr/include/linux/ |
| H A D | pci_regs.h | 60 #define PCI_BIST_START 0x40 macro
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| /dports/lang/gnatdroid-sysroot/android-19-arm/usr/include/linux/ |
| H A D | pci_regs.h | 60 #define PCI_BIST_START 0x40 macro
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/include/ |
| H A D | pci.h | 81 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/include/ |
| H A D | pci.h | 81 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/include/ |
| H A D | pci.h | 81 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/include/ |
| H A D | pci.h | 81 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/include/ |
| H A D | pci.h | 81 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/include/ |
| H A D | pci.h | 81 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/include/ |
| H A D | pci.h | 81 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/seabios-hppa/src/hw/ |
| H A D | pci_regs.h | 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/qemu-palcode/ |
| H A D | pci_regs.h | 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/seabios/src/hw/ |
| H A D | pci_regs.h | 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/qemu-palcode/ |
| H A D | pci_regs.h | 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/seabios-hppa/src/hw/ |
| H A D | pci_regs.h | 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/seabios/src/hw/ |
| H A D | pci_regs.h | 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/qemu-palcode/ |
| H A D | pci_regs.h | 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/seabios/src/hw/ |
| H A D | pci_regs.h | 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/seabios-hppa/src/hw/ |
| H A D | pci_regs.h | 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/seabios/src/hw/ |
| H A D | pci_regs.h | 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/seabios-hppa/src/hw/ |
| H A D | pci_regs.h | 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/misc/seabios/seabios-1.14.0/src/hw/ |
| H A D | pci_regs.h | 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/seabios-hppa/src/hw/ |
| H A D | pci_regs.h | 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/seabios/src/hw/ |
| H A D | pci_regs.h | 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/qemu-palcode/ |
| H A D | pci_regs.h | 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ macro
|