/dports/emulators/qemu42/qemu-4.2.1/roms/openbios/drivers/ |
H A D | pci.h | 34 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ macro
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/dports/emulators/qemu5/qemu-5.2.0/roms/openbios/drivers/ |
H A D | pci.h | 34 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ macro
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/openbios/drivers/ |
H A D | pci.h | 34 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ macro
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/openbios/drivers/ |
H A D | pci.h | 34 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ macro
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/openbios/drivers/ |
H A D | pci.h | 34 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ macro
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/dports/emulators/qemu/qemu-6.2.0/roms/openbios/drivers/ |
H A D | pci.h | 34 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ macro
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/dports/emulators/qemu60/qemu-6.0.0/roms/openbios/drivers/ |
H A D | pci.h | 34 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ macro
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/dports/emulators/qemu42/qemu-4.2.1/roms/ipxe/src/include/ipxe/ |
H A D | pci.h | 46 #define PCI_CACHE_LINE_SIZE 0x0c macro
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/ipxe/src/include/ipxe/ |
H A D | pci.h | 46 #define PCI_CACHE_LINE_SIZE 0x0c macro
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/ipxe/src/include/ipxe/ |
H A D | pci.h | 46 #define PCI_CACHE_LINE_SIZE 0x0c macro
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/ipxe/src/include/ipxe/ |
H A D | pci.h | 46 #define PCI_CACHE_LINE_SIZE 0x0c macro
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/dports/emulators/qemu5/qemu-5.2.0/roms/ipxe/src/include/ipxe/ |
H A D | pci.h | 46 #define PCI_CACHE_LINE_SIZE 0x0c macro
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/dports/net/ipxe/ipxe-2265a65/src/include/ipxe/ |
H A D | pci.h | 47 #define PCI_CACHE_LINE_SIZE 0x0c macro
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/dports/emulators/qemu/qemu-6.2.0/roms/ipxe/src/include/ipxe/ |
H A D | pci.h | 46 #define PCI_CACHE_LINE_SIZE 0x0c macro
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/dports/emulators/qemu60/qemu-6.0.0/roms/ipxe/src/include/ipxe/ |
H A D | pci.h | 46 #define PCI_CACHE_LINE_SIZE 0x0c macro
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/dports/sysutils/syslinux/syslinux-6.03/gpxe/src/include/gpxe/ |
H A D | pci.h | 36 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ macro
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/dports/sysutils/rovclock/rovclock-0.6e/ |
H A D | pci.h | 51 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ macro
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/dports/lang/gnatdroid-sysroot-x86/android-19-x86/usr/include/linux/ |
H A D | pci_regs.h | 51 #define PCI_CACHE_LINE_SIZE 0x0c macro
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/dports/lang/gnatdroid-sysroot/android-19-arm/usr/include/linux/ |
H A D | pci_regs.h | 51 #define PCI_CACHE_LINE_SIZE 0x0c macro
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/include/ |
H A D | pci.h | 72 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ macro
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/include/ |
H A D | pci.h | 72 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ macro
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/include/ |
H A D | pci.h | 72 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ macro
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/include/ |
H A D | pci.h | 72 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ macro
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/include/ |
H A D | pci.h | 72 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ macro
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/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/include/ |
H A D | pci.h | 72 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ macro
|