1 /* $NetBSD: if_wmreg.h,v 1.130 2023/05/11 07:19:02 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /****************************************************************************** 39 40 Copyright (c) 2001-2012, Intel Corporation 41 All rights reserved. 42 43 Redistribution and use in source and binary forms, with or without 44 modification, are permitted provided that the following conditions are met: 45 46 1. Redistributions of source code must retain the above copyright notice, 47 this list of conditions and the following disclaimer. 48 49 2. Redistributions in binary form must reproduce the above copyright 50 notice, this list of conditions and the following disclaimer in the 51 documentation and/or other materials provided with the distribution. 52 53 3. Neither the name of the Intel Corporation nor the names of its 54 contributors may be used to endorse or promote products derived from 55 this software without specific prior written permission. 56 57 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 58 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 61 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 POSSIBILITY OF SUCH DAMAGE. 68 69 ******************************************************************************/ 70 71 /* 72 * Register description for the Intel i82542 (``Wiseman''), 73 * i82543 (``Livengood''), and i82544 (``Cordova'') Gigabit 74 * Ethernet chips. 75 */ 76 77 /* 78 * The wiseman supports 64-bit PCI addressing. This structure 79 * describes the address in descriptors. 80 */ 81 typedef struct wiseman_addr { 82 uint32_t wa_low; /* low-order 32 bits */ 83 uint32_t wa_high; /* high-order 32 bits */ 84 } __packed wiseman_addr_t; 85 86 /* 87 * The Wiseman receive descriptor. 88 * 89 * The receive descriptor ring must be aligned to a 4K boundary, 90 * and there must be an even multiple of 8 descriptors in the ring. 91 */ 92 typedef struct wiseman_rxdesc { 93 volatile wiseman_addr_t wrx_addr; /* buffer address */ 94 95 volatile uint16_t wrx_len; /* buffer length */ 96 volatile uint16_t wrx_cksum; /* checksum (starting at PCSS)*/ 97 98 volatile uint8_t wrx_status; /* Rx status */ 99 volatile uint8_t wrx_errors; /* Rx errors */ 100 volatile uint16_t wrx_special; /* special field (VLAN, etc.) */ 101 } __packed wiseman_rxdesc_t; 102 103 /* wrx_status bits */ 104 #define WRX_ST_DD __BIT(0) /* descriptor done */ 105 #define WRX_ST_EOP __BIT(1) /* end of packet */ 106 #define WRX_ST_IXSM __BIT(2) /* ignore checksum indication */ 107 #define WRX_ST_VP __BIT(3) /* VLAN packet */ 108 #define WRX_ST_BPDU __BIT(4) /* ??? */ 109 #define WRX_ST_TCPCS __BIT(5) /* TCP checksum performed */ 110 #define WRX_ST_IPCS __BIT(6) /* IP checksum performed */ 111 #define WRX_ST_PIF __BIT(7) /* passed in-exact filter */ 112 113 /* wrx_error bits */ 114 #define WRX_ER_CE __BIT(0) /* CRC error */ 115 #define WRX_ER_SE __BIT(1) /* symbol error */ 116 #define WRX_ER_SEQ __BIT(2) /* sequence error */ 117 #define WRX_ER_ICE __BIT(3) /* ??? */ 118 #define WRX_ER_CXE __BIT(4) /* carrier extension error */ 119 #define WRX_ER_TCPE __BIT(5) /* TCP checksum error */ 120 #define WRX_ER_IPE __BIT(6) /* IP checksum error */ 121 #define WRX_ER_RXE __BIT(7) /* Rx data error */ 122 123 /* wrx_special field for VLAN packets */ 124 #define WRX_VLAN_ID(x) ((x) & 0x0fff) /* VLAN identifier */ 125 #define WRX_VLAN_CFI __BIT(12) /* Canonical Form Indicator */ 126 #define WRX_VLAN_PRI(x) (((x) >> 13) & 7)/* VLAN priority field */ 127 128 /* extended RX descriptor for 82574 */ 129 typedef union ext_rxdesc { 130 struct { 131 uint64_t erxd_addr; /* Packet Buffer Address */ 132 uint64_t erxd_dd; /* 63:1 reserved, 0 DD */ 133 } erx_data; 134 struct { 135 uint32_t erxc_mrq; /* 136 * 31:13 reserved 137 * 12:8 Rx queue associated with the packet 138 * 7:4 reserved 3:0 RSS Type 139 */ 140 uint32_t erxc_rsshash; /* RSS Hash or {Fragment Checksum, IP identification } */ 141 uint32_t erxc_err_stat; /* 31:20 Extended Error, 19:0 Extened Status */ 142 uint16_t erxc_pktlen; /* PKT_LEN */ 143 uint16_t erxc_vlan; /* VLAN Tag */ 144 } erx_ctx; 145 } __packed ext_rxdesc_t; 146 147 #define EXTRXD_DD_MASK __BIT(0) 148 149 /* 150 * erxc_rsshash is used for below 2 patterns 151 * (1) Fragment Checksum and IP identification 152 * - Fragment Checksum is valid 153 * when RXCSUM.PCSD cleared and RXCSUM.IPPCSE bit is set 154 * - IP identification is valid 155 * when RXCSUM.PCSD cleared and RXCSUM.IPPCSE bit is set 156 * (2) RSS Hash 157 * when RXCSUM.PCSD bit is set 158 */ 159 #define EXTRXC_IP_ID_MASK __BITS(15,0) 160 #define EXTRXC_FRAG_CSUM_MASK __BITS(31,16) 161 #define EXTRXC_IP_ID(rsshash) __SHIFTOUT(rsshash,ERXC_IP_ID_MASK) 162 #define EXTRXC_FRAG_CSUM(rsshash) __SHIFTOUT(rsshash,ERXC_FRAG_CSUM_MASK) 163 164 /* macros for nrxc_mrq */ 165 #define EXTRXC_RSS_TYPE_MASK __BITS(3,0) 166 /* __BITS(7,4) is reserved */ 167 #define EXTRXC_QUEUE_MASK __BITS(12,8) 168 /* __BITS(31,13) is reserved */ 169 #define EXTRXC_RSS_TYPE(mrq) __SHIFTOUT(mrq,EXTRXC_RSS_TYPE_MASK) 170 #define EXTRXC_QUEUE(mrq) __SHIFTOUT(mrq,EXTRXC_QUEUE_MASK) 171 172 #define EXTRXC_RSS_TYPE_NONE 0x0 /* No hash computation done. */ 173 #define EXTRXC_RSS_TYPE_TCP_IPV4 0x1 174 #define EXTRXC_RSS_TYPE_IPV4 0x2 175 #define EXTRXC_RSS_TYPE_TCP_IPV6 0x3 176 #define EXTRXC_RSS_TYPE_IPV6_EX 0x4 177 #define EXTRXC_RSS_TYPE_IPV6 0x5 178 /*0x6:0xF is reserved. */ 179 180 #define EXTRXC_STATUS_MASK __BITS(19,0) 181 #define EXTRXC_ERROR_MASK __BITS(31,20) 182 #define EXTRXC_STATUS(err_stat) __SHIFTOUT(err_stat,EXTRXC_STATUS_MASK) 183 #define EXTRXC_ERROR(err_stat) __SHIFTOUT(err_stat,EXTRXC_ERROR_MASK) 184 185 /* 3:0 is reserved. */ 186 #define EXTRXC_ERROR_CE __BIT(4) /* The same as WRX_ER_CE. */ 187 #define EXTRXC_ERROR_SE __BIT(5) /* The same as WRX_ER_SE. */ 188 #define EXTRXC_ERROR_SEQ __BIT(6) /* The same as WRX_ER_SEQ. */ 189 /* 7 is reserved. */ 190 #define EXTRXC_ERROR_CXE __BIT(8) /* The same as WRX_ER_CXE. */ 191 #define EXTRXC_ERROR_TCPE __BIT(9) /* The same as WRX_ER_TCPE. */ 192 #define EXTRXC_ERROR_IPE __BIT(10) /* The same as WRX_ER_IPE. */ 193 #define EXTRXC_ERROR_RXE __BIT(11) /* The same as WRX_ER_RXE. */ 194 195 #define EXTRXC_STATUS_DD __BIT(0) /* The same as WRX_ST_DD. */ 196 #define EXTRXC_STATUS_EOP __BIT(1) /* The same as WRX_ST_EOP. */ 197 /* 2 is reserved. */ 198 #define EXTRXC_STATUS_VP __BIT(3) /* The same as WRX_ST_VP. */ 199 #define EXTRXC_STATUS_UDPCS __BIT(4) /* UDP checksum calculated on packet. */ 200 #define EXTRXC_STATUS_TCPCS __BIT(5) /* The same as WRX_ST_TCPCS. */ 201 #define EXTRXC_STATUS_IPCS __BIT(6) /* The same as WRX_ST_IPCS. */ 202 /* 7 is reserved. */ 203 #define EXTRXC_STATUS_TST __BIT(8) /* Time stamp taken. */ 204 #define EXTRXC_STATUS_IPIDV __BIT(9) /* IP identification valid. */ 205 #define EXTRXC_STATUS_UDPV __BIT(10) /* Valid UDP XSUM. */ 206 /* 14:11 is reserved. */ 207 #define EXTRXC_STATUS_ACK __BIT(15) /* ACK packet indication. */ 208 #define EXTRXC_STATUS_PKTTYPE_MASK __BITS(19,16) 209 #define EXTRXC_STATUS_PKTTYPE(status) __SHIFTOUT(status,EXTRXC_STATUS_PKTTYPE_MASK) 210 211 /* advanced RX descriptor for 82575 and newer */ 212 typedef union nq_rxdesc { 213 struct { 214 uint64_t nrxd_paddr; /* 63:1 Packet Buffer Address, 0 A0/NSE */ 215 uint64_t nrxd_haddr; /* 63:1 HEader Buffer Address, 0 DD */ 216 } nqrx_data; 217 struct { 218 uint32_t nrxc_misc; /* 219 * 31: SPH, 30:21 HDR_LEN[9:0], 220 * 20:19 HDR_LEN[11:10], 18:17 RSV, 221 * 16:4 Packet Type 3:0 RSS Type 222 */ 223 uint32_t nrxc_rsshash; /* RSS Hash or {Fragment Checksum, IP identification } */ 224 uint32_t nrxc_err_stat; /* 31:20 Extended Error, 19:0 Extened Status */ 225 uint16_t nrxc_pktlen; /* PKT_LEN */ 226 uint16_t nrxc_vlan; /* VLAN Tag */ 227 } nqrx_ctx; 228 } __packed nq_rxdesc_t; 229 230 /* for nrxd_paddr macros */ 231 #define NQRXD_A0_MASK __BIT(0) 232 #define NQRXD_NSE_MASK __BIT(0) 233 #define NQRXD_ADDR_MASK __BITS(63,1) 234 /* for nrxd_haddr macros */ 235 #define NQRXD_DD_MASK __BIT(0) 236 237 /* 238 * nrxc_rsshash is used for below 2 patterns 239 * (1) Fragment Checksum and IP identification 240 * - Fragment Checksum is valid 241 * when RXCSUM.PCSD cleared and RXCSUM.IPPCSE bit is set 242 * - IP identification is valid 243 * when RXCSUM.PCSD cleared and RXCSUM.IPPCSE bit is set 244 * (2) RSS Hash 245 * when RXCSUM.PCSD bit is set 246 */ 247 #define NQRXC_IP_ID_MASK __BITS(15,0) 248 #define NQRXC_FRAG_CSUM_MASK __BITS(31,16) 249 #define NQRXC_IP_ID(rsshash) __SHIFTOUT(rsshash,NRXC_IP_ID_MASK) 250 #define NQRXC_FRAG_CSUM(rsshash) __SHIFTOUT(rsshash,NRXC_FRAG_CSUM_MASK) 251 252 /* macros for nrxc_misc */ 253 #define NQRXC_RSS_TYPE_MASK __BITS(3,0) 254 #define NQRXC_PKT_TYPE_ID_MASK __BITS(11,4) 255 #define NQRXC_PKT_TYPE_ETQF_INDEX_MASK __BITS(11,4) 256 #define NQRXC_PKT_TYPE_ETQF_VALID_MASK __BIT(15) 257 #define NQRXC_PKT_TYPE_VLAN_MASK __BIT(16) 258 #define NQRXC_PKT_TYPE_MASK __BITS(16,4) 259 /* __BITS(18,17) is reserved */ 260 #define NQRXC_HDRLEN_HIGH_MASK __BITS(20,19) 261 #define NQRXC_HDRLEN_LOW_MASK __BITS(30,21) 262 #define NQRXC_SPH_MASK __BIT(31) 263 264 #define NQRXC_RSS_TYPE(misc) __SHIFTOUT(misc,NQRXC_RSS_TYPE_MASK) 265 #define NQRXC_PKT_TYPE_ID(pkttype) \ 266 __SHIFTOUT(pkttype,NQRXC_PKT_TYPE_ID_MASK) 267 #define NQRXC_PKT_TYPE(misc) __SHIFTOUT(misc,NQRXC_PKT_TYPE_MASK) 268 #define NQRXC_PKT_TYPE_ETQF_INDEX(pkttype) \ 269 __SHIFTOUT(pkttype,NQRXC_PKT_TYPE_ETQF_INDEX_MASK) 270 #define NQRXC_PKT_TYPE_ETQF_VALID NQRXC_PKT_TYPE_ETQF_VALID_MASK 271 #define NQRXC_PKT_TYPE_VLAN NQRXC_PKT_TYPE_VLAN_MASK 272 #define NQRXC_HEADER_LEN(misc) (__SHIFTOUT(misc,NQRXC_HDRLEN_LOW_MASK) \ 273 | __SHIFTOUT(misc,NQRXC_HDRLEN_HIGH_MASK) << 10) 274 #define NQRXC_SPH NQRXC_SPH_MASK 275 276 #define NQRXC_RSS_TYPE_NONE 0x0 /* No hash computation done. */ 277 #define NQRXC_RSS_TYPE_TCP_IPV4 0x1 278 #define NQRXC_RSS_TYPE_IPV4 0x2 279 #define NQRXC_RSS_TYPE_TCP_IPV6 0x3 280 #define NQRXC_RSS_TYPE_IPV6_EX 0x4 281 #define NQRXC_RSS_TYPE_IPV6 0x5 282 #define NQRXC_RSS_TYPE_TCP_IPV6_EX 0x6 283 #define NQRXC_RSS_TYPE_UDP_IPV4 0x7 284 #define NQRXC_RSS_TYPE_UDP_IPV6 0x8 285 #define NQRXC_RSS_TYPE_UDP_IPV6_EX 0x9 286 /*0xA:0xF is reserved. */ 287 288 #define NQRXC_PKT_TYPE_IPV4 __BIT(0) 289 #define NQRXC_PKT_TYPE_IPV4E __BIT(1) 290 #define NQRXC_PKT_TYPE_IPV6 __BIT(2) 291 #define NQRXC_PKT_TYPE_IPV6E __BIT(3) 292 #define NQRXC_PKT_TYPE_TCP __BIT(4) 293 #define NQRXC_PKT_TYPE_UDP __BIT(5) 294 #define NQRXC_PKT_TYPE_SCTP __BIT(6) 295 #define NQRXC_PKT_TYPE_NFS __BIT(7) 296 297 #define NQRXC_STATUS_MASK __BITS(19,0) 298 #define NQRXC_ERROR_MASK __BITS(31,20) 299 #define NQRXC_STATUS(err_stat) __SHIFTOUT(err_stat,NQRXC_STATUS_MASK) 300 #define NQRXC_ERROR(err_stat) __SHIFTOUT(err_stat,NQRXC_ERROR_MASK) 301 302 /* 2:0 is reserved. */ 303 #define NQRXC_ERROR_HB0 __BIT(3) /* Header Buffer Overflow. */ 304 /* 6:4 is reserved. */ 305 /* 8:7 is reserved. */ 306 #define NQRXC_ERROR_L4E __BIT(9) /* L4 error indication. */ 307 #define NQRXC_ERROR_IPE __BIT(10) /* The same as WRX_ER_IPE. */ 308 #define NQRXC_ERROR_RXE __BIT(11) /* The same as WRX_ER_RXE. */ 309 /* XXX Where is WRX_ER_CE, WRX_ER_SE, WRX_ER_SEQ, WRX_ER_CXE error? */ 310 311 #define NQRXC_STATUS_DD __BIT(0) /* The same as WRX_ST_DD. */ 312 #define NQRXC_STATUS_EOP __BIT(1) /* The same as WRX_ST_EOP. */ 313 /* 2 is reserved */ 314 #define NQRXC_STATUS_VP __BIT(3) /* The same as WRX_ST_VP. */ 315 #define NQRXC_STATUS_UDPCS __BIT(4) /* UDP checksum or IP payload checksum. */ 316 /* XXX in I210 spec, this bit is the same as WRX_ST_BPDU(is "???" comment) */ 317 #define NQRXC_STATUS_L4I __BIT(5) /* L4 integrity check was done. */ 318 #define NQRXC_STATUS_IPCS __BIT(6) /* The same as WRX_ST_IPCS. */ 319 #define NQRXC_STATUS_PIF __BIT(7) /* The same as WRX_ST_PIF. */ 320 /* 8 is reserved */ 321 #define NQRXC_STATUS_VEXT __BIT(9) /* First VLAN is found on a bouble VLAN packet. */ 322 #define NQRXC_STATUS_UDPV __BIT(10) /* The packet contains a valid checksum field in a first fragment UDP IPv4 packet. */ 323 #define NQRXC_STATUS_LLINT __BIT(11) /* The packet caused an immediate interrupt. */ 324 #define NQRXC_STATUS_STRIPCRC __BIT(12) /* Ethernet CRC is stripped. */ 325 /* 14:13 is reserved */ 326 #define NQRXC_STATUS_TSIP __BIT(15) /* Timestamp in packet. */ 327 #define NQRXC_STATUS_TS __BIT(16) /* Time stamped packet. */ 328 /* 17 is reserved */ 329 #define NQRXC_STATUS_LB __BIT(18) /* Sent by a local virtual machine (VM to VM switch indication). */ 330 #define NQRXC_STATUS_MC __BIT(19) /* Packet received from Manageability Controller */ 331 /* "MBC" in i350 spec */ 332 333 /* 334 * The Wiseman transmit descriptor. 335 * 336 * The transmit descriptor ring must be aligned to a 4K boundary, 337 * and there must be an even multiple of 8 descriptors in the ring. 338 */ 339 typedef struct wiseman_tx_fields { 340 uint8_t wtxu_status; /* Tx status */ 341 uint8_t wtxu_options; /* options */ 342 uint16_t wtxu_vlan; /* VLAN info */ 343 } __packed wiseman_txfields_t; 344 typedef struct wiseman_txdesc { 345 wiseman_addr_t wtx_addr; /* buffer address */ 346 uint32_t wtx_cmdlen; /* command and length */ 347 wiseman_txfields_t wtx_fields; /* fields; see below */ 348 } __packed wiseman_txdesc_t; 349 350 /* Commands for wtx_cmdlen */ 351 #define WTX_CMD_EOP __BIT(24) /* end of packet */ 352 #define WTX_CMD_IFCS __BIT(25) /* insert FCS */ 353 #define WTX_CMD_RS __BIT(27) /* report status */ 354 #define WTX_CMD_RPS __BIT(28) /* report packet sent */ 355 #define WTX_CMD_DEXT __BIT(29) /* descriptor extension */ 356 #define WTX_CMD_VLE __BIT(30) /* VLAN enable */ 357 #define WTX_CMD_IDE __BIT(31) /* interrupt delay enable */ 358 359 /* Descriptor types (if DEXT is set) */ 360 #define WTX_DTYP_MASK __BIT(20) 361 #define WTX_DTYP_C __SHIFTIN(0, WTX_DTYP_MASK) /* context */ 362 #define WTX_DTYP_D __SHIFTIN(1, WTX_DTYP_MASK) /* data */ 363 364 /* wtx_fields status bits */ 365 #define WTX_ST_DD __BIT(0) /* descriptor done */ 366 #define WTX_ST_EC __BIT(1) /* excessive collisions */ 367 #define WTX_ST_LC __BIT(2) /* late collision */ 368 #define WTX_ST_TU __BIT(3) /* transmit underrun */ 369 370 /* wtx_fields option bits for IP/TCP/UDP checksum offload */ 371 #define WTX_IXSM __BIT(0) /* IP checksum offload */ 372 #define WTX_TXSM __BIT(1) /* TCP/UDP checksum offload */ 373 374 /* Maximum payload per Tx descriptor */ 375 #define WTX_MAX_LEN 4096 376 377 /* 378 * The Livengood TCP/IP context descriptor. 379 */ 380 struct livengood_tcpip_ctxdesc { 381 uint32_t tcpip_ipcs; /* IP checksum context */ 382 uint32_t tcpip_tucs; /* TCP/UDP checksum context */ 383 uint32_t tcpip_cmdlen; 384 uint32_t tcpip_seg; /* TCP segmentation context */ 385 }; 386 387 /* commands for context descriptors */ 388 #define WTX_TCPIP_CMD_TCP __BIT(24) /* 1 = TCP, 0 = UDP */ 389 #define WTX_TCPIP_CMD_IP __BIT(25) /* 1 = IPv4, 0 = IPv6 */ 390 #define WTX_TCPIP_CMD_TSE __BIT(26) /* segmentation context valid */ 391 392 #define WTX_TCPIP_IPCSS(x) ((x) << 0) /* checksum start */ 393 #define WTX_TCPIP_IPCSO(x) ((x) << 8) /* checksum value offset */ 394 #define WTX_TCPIP_IPCSE(x) ((x) << 16) /* checksum end */ 395 396 #define WTX_TCPIP_TUCSS(x) ((x) << 0) /* checksum start */ 397 #define WTX_TCPIP_TUCSO(x) ((x) << 8) /* checksum value offset */ 398 #define WTX_TCPIP_TUCSE(x) ((x) << 16) /* checksum end */ 399 400 #define WTX_TCPIP_SEG_STATUS(x) ((x) << 0) 401 #define WTX_TCPIP_SEG_HDRLEN(x) ((x) << 8) 402 #define WTX_TCPIP_SEG_MSS(x) ((x) << 16) 403 404 /* 405 * PCI config registers used by the Wiseman. 406 */ 407 #define WM_PCI_MMBA PCI_MAPREG_START 408 /* registers for FLASH access on ICH8 */ 409 #define WM_ICH8_FLASH 0x0014 410 411 #define WM_PCI_LTR_CAP_LPT 0xa8 412 413 /* XXX Only for PCH_SPT? */ 414 #define WM_PCI_DESCRING_STATUS 0xe4 415 #define DESCRING_STATUS_FLUSH_REQ __BIT(8) 416 417 /* 418 * Wiseman Control/Status Registers. 419 */ 420 #define WMREG_CTRL 0x0000 /* Device Control Register */ 421 #define CTRL_FD __BIT(0) /* full duplex */ 422 #define CTRL_BEM __BIT(1) /* big-endian mode */ 423 #define CTRL_PRIOR __BIT(2) /* 0 = receive, 1 = fair */ 424 #define CTRL_GIO_M_DIS __BIT(2) /* disabl PCI master access */ 425 #define CTRL_LRST __BIT(3) /* link reset */ 426 #define CTRL_ASDE __BIT(5) /* auto speed detect enable */ 427 #define CTRL_SLU __BIT(6) /* set link up */ 428 #define CTRL_ILOS __BIT(7) /* invert loss of signal */ 429 #define CTRL_SPEED(x) ((x) << 8) /* speed (Livengood) */ 430 #define CTRL_SPEED_10 CTRL_SPEED(0) 431 #define CTRL_SPEED_100 CTRL_SPEED(1) 432 #define CTRL_SPEED_1000 CTRL_SPEED(2) 433 #define CTRL_SPEED_MASK CTRL_SPEED(3) 434 #define CTRL_FRCSPD __BIT(11) /* force speed (Livengood) */ 435 #define CTRL_FRCFDX __BIT(12) /* force full-duplex (Livengood) */ 436 #define CTRL_D_UD_EN __BIT(13) /* Dock/Undock enable */ 437 #define CTRL_D_UD_POL __BIT(14) /* Defined polarity of Dock/Undock indication in SDP[0] */ 438 #define CTRL_F_PHY_R __BIT(15) /* Reset both PHY ports, through PHYRST_N pin */ 439 #define CTRL_EXTLINK_EN __BIT(16) /* enable link status from external LINK_0 and LINK_1 pins */ 440 #define CTRL_LANPHYPC_OVERRIDE __BIT(16) /* SW control of LANPHYPC */ 441 #define CTRL_LANPHYPC_VALUE __BIT(17) /* SW value of LANPHYPC */ 442 #define CTRL_SWDPINS_SHIFT 18 443 #define CTRL_SWDPINS_MASK 0x0f 444 #define CTRL_SWDPIN(x) (1U << (CTRL_SWDPINS_SHIFT + (x))) 445 #define CTRL_SWDPIO_SHIFT 22 446 #define CTRL_SWDPIO_MASK 0x0f 447 #define CTRL_SWDPIO(x) (1U << (CTRL_SWDPIO_SHIFT + (x))) 448 #define CTRL_MEHE __BIT(19) /* Memory Error Handling Enable(I217)*/ 449 #define CTRL_RST __BIT(26) /* device reset */ 450 #define CTRL_RFCE __BIT(27) /* Rx flow control enable */ 451 #define CTRL_TFCE __BIT(28) /* Tx flow control enable */ 452 #define CTRL_VME __BIT(30) /* VLAN Mode Enable */ 453 #define CTRL_PHY_RESET __BIT(31) /* PHY reset (Cordova) */ 454 455 #define WMREG_CTRL_SHADOW 0x0004 /* Device Control Register (shadow) */ 456 457 #define WMREG_STATUS 0x0008 /* Device Status Register */ 458 #define STATUS_FD __BIT(0) /* full duplex */ 459 #define STATUS_LU __BIT(1) /* link up */ 460 #define STATUS_TCKOK __BIT(2) /* Tx clock running */ 461 #define STATUS_RBCOK __BIT(3) /* Rx clock running */ 462 #define STATUS_FUNCID_SHIFT 2 /* 82546 function ID */ 463 #define STATUS_FUNCID_MASK 3 /* ... */ 464 #define STATUS_TXOFF __BIT(4) /* Tx paused */ 465 #define STATUS_TBIMODE __BIT(5) /* fiber mode (Livengood) */ 466 #define STATUS_SPEED __BITS(7, 6) /* speed indication */ 467 #define STATUS_SPEED_10 0 468 #define STATUS_SPEED_100 1 469 #define STATUS_SPEED_1000 2 470 #define STATUS_ASDV(x) ((x) << 8) /* auto speed det. val. (Livengood) */ 471 #define STATUS_LAN_INIT_DONE __BIT(9) /* Lan Init Completion by NVM */ 472 #define STATUS_MTXCKOK __BIT(10) /* MTXD clock running */ 473 #define STATUS_PHYRA __BIT(10) /* PHY Reset Asserted (PCH) */ 474 #define STATUS_PCI66 __BIT(11) /* 66MHz bus (Livengood) */ 475 #define STATUS_BUS64 __BIT(12) /* 64-bit bus (Livengood) */ 476 #define STATUS_2P5_SKU __BIT(12) /* Value of the 2.5GBE SKU strap */ 477 #define STATUS_PCIX_MODE __BIT(13) /* PCIX mode (Cordova) */ 478 #define STATUS_2P5_SKU_OVER __BIT(13) /* Value of the 2.5GBE SKU override */ 479 #define STATUS_PCIXSPD(x) ((x) << 14) /* PCIX speed indication (Cordova) */ 480 #define STATUS_PCIXSPD_50_66 STATUS_PCIXSPD(0) 481 #define STATUS_PCIXSPD_66_100 STATUS_PCIXSPD(1) 482 #define STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2) 483 #define STATUS_PCIXSPD_MASK STATUS_PCIXSPD(3) 484 #define STATUS_GIO_M_ENA __BIT(19) /* GIO master enable */ 485 #define STATUS_DEV_RST_SET __BIT(20) /* Device Reset Set */ 486 487 /* Strapping Option Register (PCH_SPT and newer) */ 488 #define WMREG_STRAP 0x000c 489 #define STRAP_NVMSIZE __BITS(1, 6) 490 #define STRAP_FREQ __BITS(12, 13) 491 #define STRAP_SMBUSADDR __BITS(17, 23) 492 493 #define WMREG_EECD 0x0010 /* EEPROM Control Register */ 494 #define EECD_SK __BIT(0) /* clock */ 495 #define EECD_CS __BIT(1) /* chip select */ 496 #define EECD_DI __BIT(2) /* data in */ 497 #define EECD_DO __BIT(3) /* data out */ 498 #define EECD_FWE(x) ((x) << 4) /* flash write enable control */ 499 #define EECD_FWE_DISABLED EECD_FWE(1) 500 #define EECD_FWE_ENABLED EECD_FWE(2) 501 #define EECD_EE_REQ __BIT(6) /* (shared) EEPROM request */ 502 #define EECD_EE_GNT __BIT(7) /* (shared) EEPROM grant */ 503 #define EECD_EE_PRES __BIT(8) /* EEPROM present */ 504 #define EECD_EE_SIZE __BIT(9) /* EEPROM size 505 (0 = 64 word, 1 = 256 word) */ 506 #define EECD_EE_AUTORD __BIT(9) /* auto read done */ 507 #define EECD_EE_ABITS __BIT(10) /* EEPROM address bits 508 (based on type) */ 509 #define EECD_EE_SIZE_EX_MASK __BITS(14,11) /* EEPROM size for new devices */ 510 #define EECD_EE_TYPE __BIT(13) /* EEPROM type 511 (0 = Microwire, 1 = SPI) */ 512 #define EECD_SEC1VAL __BIT(22) /* Sector One Valid */ 513 #define EECD_SEC1VAL_VALMASK (EECD_EE_AUTORD | EECD_EE_PRES) /* Valid Mask */ 514 515 #define WMREG_FEXTNVM6 0x0010 /* Future Extended NVM 6 */ 516 #define FEXTNVM6_REQ_PLL_CLK __BIT(8) 517 #define FEXTNVM6_ENABLE_K1_ENTRY_CONDITION __BIT(9) 518 #define FEXTNVM6_K1_OFF_ENABLE __BIT(31) 519 520 #define WMREG_EERD 0x0014 /* EEPROM read */ 521 #define EERD_DONE 0x02 /* done bit */ 522 #define EERD_START 0x01 /* First bit for telling part to start operation */ 523 #define EERD_ADDR_SHIFT 2 /* Shift to the address bits */ 524 #define EERD_DATA_SHIFT 16 /* Offset to data in EEPROM read/write registers */ 525 526 #define WMREG_CTRL_EXT 0x0018 /* Extended Device Control Register */ 527 #define CTRL_EXT_NSICR __BIT(0) /* Non Interrupt clear on read */ 528 #define CTRL_EXT_GPI_EN(x) (1U << (x)) /* gpin interrupt enable */ 529 #define CTRL_EXT_NVMVS __BITS(0, 1) /* NVM valid sector */ 530 #define CTRL_EXT_LPCD __BIT(2) /* LCD Power Cycle Done */ 531 #define CTRL_EXT_SWDPINS_SHIFT 4 532 #define CTRL_EXT_SWDPINS_MASK 0x0d 533 /* The bit order of the SW Definable pin is not 6543 but 3654! */ 534 #define CTRL_EXT_SWDPIN(x) (1U << (CTRL_EXT_SWDPINS_SHIFT \ 535 + ((x) == 3 ? 3 : ((x) - 4)))) 536 #define CTRL_EXT_SWDPIO_SHIFT 8 537 #define CTRL_EXT_SWDPIO_MASK 0x0d 538 #define CTRL_EXT_SWDPIO(x) (1U << (CTRL_EXT_SWDPIO_SHIFT \ 539 + ((x) == 3 ? 3 : ((x) - 4)))) 540 #define CTRL_EXT_FORCE_SMBUS __BIT(11) /* Force SMBus mode */ 541 #define CTRL_EXT_ASDCHK __BIT(12) /* ASD check */ 542 #define CTRL_EXT_EE_RST __BIT(13) /* EEPROM reset */ 543 #define CTRL_EXT_IPS __BIT(14) /* invert power state bit 0 */ 544 #define CTRL_EXT_SPD_BYPS __BIT(15) /* speed select bypass */ 545 #define CTRL_EXT_IPS1 __BIT(16) /* invert power state bit 1 */ 546 #define CTRL_EXT_RO_DIS __BIT(17) /* relaxed ordering disabled */ 547 #define CTRL_EXT_SDLPE __BIT(18) /* SerDes Low Power Enable */ 548 #define CTRL_EXT_DMA_DYN_CLK __BIT(19) /* DMA Dynamic Gating Enable */ 549 #define CTRL_EXT_PHYPDEN __BIT(20) 550 #define CTRL_EXT_LINK_MODE_MASK 0x00c00000 551 #define CTRL_EXT_LINK_MODE_GMII 0x00000000 552 #define CTRL_EXT_LINK_MODE_KMRN 0x00000000 553 #define CTRL_EXT_LINK_MODE_1000KX 0x00400000 554 #define CTRL_EXT_LINK_MODE_SGMII 0x00800000 555 #define CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 556 #define CTRL_EXT_LINK_MODE_TBI 0x00c00000 557 #define CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00c00000 558 #define CTRL_EXT_EIAME __BIT(24) /* Extended Interrupt Auto Mask En */ 559 #define CTRL_EXT_I2C_ENA 0x02000000 /* I2C enable */ 560 #define CTRL_EXT_DRV_LOAD 0x10000000 561 #define CTRL_EXT_PBA __BIT(31) /* PBA Support */ 562 563 #define WMREG_MDIC 0x0020 /* MDI Control Register */ 564 #define MDIC_DATA(x) ((x) & 0xffff) 565 #define MDIC_REGADD(x) ((x) << 16) 566 #define MDIC_PHY_SHIFT 21 567 #define MDIC_PHY_MASK __BITS(25, 21) 568 #define MDIC_PHYADD(x) ((x) << 21) 569 570 #define MDIC_OP_RW_MASK __BITS(27, 26) 571 #define MDIC_OP_WRITE __SHIFTIN(1, MDIC_OP_RW_MASK) 572 #define MDIC_OP_READ __SHIFTIN(2, MDIC_OP_RW_MASK) 573 #define MDIC_READY __BIT(28) 574 #define MDIC_I __BIT(29) /* interrupt on MDI complete */ 575 #define MDIC_E __BIT(30) /* MDI error */ 576 #define MDIC_DEST __BIT(31) /* Destination */ 577 578 #define WMREG_SCTL 0x0024 /* SerDes Control - RW */ 579 /* 580 * These 4 macros are also used for other 8bit control registers on the 581 * 82575 582 */ 583 #define SCTL_CTL_READY __BIT(31) 584 #define SCTL_CTL_DATA_MASK 0x000000ff 585 #define SCTL_CTL_ADDR_SHIFT 8 586 #define SCTL_CTL_POLL_TIMEOUT 640 587 #define SCTL_DISABLE_SERDES_LOOPBACK 0x0400 588 589 #define WMREG_FEXTNVM4 0x0024 /* Future Extended NVM 4 - RW */ 590 #define FEXTNVM4_BEACON_DURATION __BITS(2, 0) 591 #define FEXTNVM4_BEACON_DURATION_8US 0x7 592 #define FEXTNVM4_BEACON_DURATION_16US 0x3 593 594 #define WMREG_FCAL 0x0028 /* Flow Control Address Low */ 595 #define FCAL_CONST 0x00c28001 /* Flow Control MAC addr low */ 596 597 #define WMREG_FEXTNVM 0x0028 /* Future Extended NVM register */ 598 #define FEXTNVM_SW_CONFIG __BIT(0) /* SW PHY Config En (ICH8 B0) */ 599 #define FEXTNVM_SW_CONFIG_ICH8M __BIT(27) /* SW PHY Config En (>= ICH8 B1) */ 600 601 #define WMREG_FCAH 0x002c /* Flow Control Address High */ 602 #define FCAH_CONST 0x00000100 /* Flow Control MAC addr high */ 603 604 #define WMREG_FCT 0x0030 /* Flow Control Type */ 605 606 #define WMREG_KUMCTRLSTA 0x0034 /* MAC-PHY interface - RW */ 607 #define KUMCTRLSTA_MASK 0x0000ffff 608 #define KUMCTRLSTA_OFFSET 0x001f0000 609 #define KUMCTRLSTA_OFFSET_SHIFT 16 610 #define KUMCTRLSTA_REN 0x00200000 611 612 #define KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 613 #define KUMCTRLSTA_OFFSET_CTRL 0x00000001 614 #define KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 615 #define KUMCTRLSTA_OFFSET_DIAG 0x00000003 616 #define KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 617 #define KUMCTRLSTA_OFFSET_K1_CONFIG 0x00000007 618 #define KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 619 #define KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 620 #define KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001e 621 #define KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001f 622 623 /* FIFO Control */ 624 #define KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 625 #define KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 626 627 /* In-Band Control */ 628 #define KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT 0x0500 629 #define KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 630 631 /* Diag */ 632 #define KUMCTRLSTA_DIAG_NELPBK 0x1000 633 634 /* K1 Config */ 635 #define KUMCTRLSTA_K1_ENABLE 0x0002 636 637 /* Half-Duplex Control */ 638 #define KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 639 #define KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 640 641 /* M2P Modes */ 642 #define KUMCTRLSTA_OPMODE_MASK 0x000c 643 #define KUMCTRLSTA_OPMODE_INBAND_MDIO 0x0004 644 645 #define WMREG_CONNSW 0x0034 /* Copper/Fiber Switch Control (>= 82575) */ 646 #define CONNSW_AUTOSENSE_EN __BIT(0) /* Auto Sense Enable */ 647 #define CONNSW_AUTOSENSE_CONF __BIT(1) /* Auto Sense Config Mode */ 648 #define CONNSW_ENRGSRC __BIT(2) /* SerDes Energy Detect Src */ 649 #define CONNSW_SERDESD __BIT(9) /* SerDes Signal Detect Ind. */ 650 #define CONNSW_PHYSD __BIT(10) /* PHY Signal Detect Ind. */ 651 #define CONNSW_PHY_PDN __BIT(11) /* Internal PHY in powerdown */ 652 653 #define WMREG_VET 0x0038 /* VLAN Ethertype */ 654 #define WMREG_MDPHYA 0x003c /* PHY address - RW */ 655 656 #define WMREG_FEXTNVM3 0x003c /* Future Extended NVM 3 */ 657 #define FEXTNVM3_PHY_CFG_COUNTER_MASK __BITS(27, 26) 658 #define FEXTNVM3_PHY_CFG_COUNTER_50MS __BIT(27) 659 660 #define WMREG_RAL(x) (0x0040 + ((x) * 8)) /* Receive Address List */ 661 #define WMREG_RAH(x) (WMREG_RAL(x) + 4) 662 #define WMREG_CORDOVA_RAL(x) (((x) <= 15) ? (0x5400 + ((x) * 8)) : \ 663 (0x54e0 + (((x) - 16) * 8))) 664 #define WMREG_CORDOVA_RAH(x) (WMREG_CORDOVA_RAL(x) + 4) 665 #define WMREG_SHRAL(x) (0x5438 + ((x) * 8)) 666 #define WMREG_SHRAH(x) (WMREG_PCH_LPT_SHRAL(x) + 4) 667 #define WMREG_PCH_LPT_SHRAL(x) (0x5408 + ((x) * 8)) 668 #define WMREG_PCH_LPT_SHRAH(x) (WMREG_PCH_LPT_SHRAL(x) + 4) 669 #define WMREG_RAL_LO(b, x) ((b) + ((x) << 3)) 670 #define WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4) 671 /* 672 * Receive Address List: The LO part is the low-order 32-bits 673 * of the MAC address. The HI part is the high-order 16-bits 674 * along with a few control bits. 675 */ 676 #define RAL_AS(x) ((x) << 16) /* address select */ 677 #define RAL_AS_DEST RAL_AS(0) /* (cordova?) */ 678 #define RAL_AS_SOURCE RAL_AS(1) /* (cordova?) */ 679 #define RAL_RDR1 __BIT(30) /* put packet in alt. rx ring */ 680 #define RAL_AV __BIT(31) /* entry is valid */ 681 682 #define WM_RAL_TABSIZE 15 /* RAL size for old devices */ 683 #define WM_RAL_TABSIZE_ICH8 7 /* RAL size for ICH* and PCH* */ 684 #define WM_RAL_TABSIZE_PCH2 5 /* RAL size for PCH2 */ 685 #define WM_RAL_TABSIZE_PCH_LPT 12 /* RAL size for PCH_LPT */ 686 #define WM_RAL_TABSIZE_82575 16 /* RAL size for 82575 */ 687 #define WM_RAL_TABSIZE_82576 24 /* RAL size for 82576 and 82580 */ 688 #define WM_RAL_TABSIZE_I350 32 /* RAL size for I350 */ 689 690 #define WMREG_ICR 0x00c0 /* Interrupt Cause Register */ 691 #define ICR_TXDW __BIT(0) /* Tx desc written back */ 692 #define ICR_TXQE __BIT(1) /* Tx queue empty */ 693 #define ICR_LSC __BIT(2) /* link status change */ 694 #define ICR_RXSEQ __BIT(3) /* receive sequence error */ 695 #define ICR_RXDMT0 __BIT(4) /* Rx ring 0 nearly empty */ 696 #define ICR_RXO __BIT(6) /* Rx overrun */ 697 #define ICR_RXT0 __BIT(7) /* Rx ring 0 timer */ 698 #define ICR_MDAC __BIT(9) /* MDIO access complete */ 699 #define ICR_RXCFG __BIT(10) /* Receiving /C/ */ 700 #define ICR_GPI(x) __BIT(11+(x)) /* general purpose interrupts */ 701 #define ICR_RXQ(x) __BIT(20+(x)) /* 82574: Rx queue x interrupt x=0,1 */ 702 #define ICR_TXQ(x) __BIT(22+(x)) /* 82574: Tx queue x interrupt x=0,1 */ 703 #define ICR_OTHER __BIT(24) /* 82574: Other interrupt */ 704 #define ICR_INT __BIT(31) /* device generated an interrupt */ 705 706 #define WMREG_ITR 0x00c4 /* Interrupt Throttling Register */ 707 #define ITR_IVAL_MASK 0xffff /* Interval mask */ 708 #define ITR_IVAL_SHIFT 0 /* Interval shift */ 709 710 #define WMREG_ICS 0x00c8 /* Interrupt Cause Set Register */ 711 /* See ICR bits. */ 712 713 #define WMREG_IMS 0x00d0 /* Interrupt Mask Set Register */ 714 /* See ICR bits. */ 715 716 #define WMREG_IMC 0x00d8 /* Interrupt Mask Clear Register */ 717 /* See ICR bits. */ 718 719 #define WMREG_EIAC_82574 0x00dc /* Interrupt Auto Clear Register */ 720 #define WMREG_EIAC_82574_MSIX_MASK (ICR_RXQ(0) | ICR_RXQ(1) \ 721 | ICR_TXQ(0) | ICR_TXQ(1) | ICR_OTHER) 722 723 #define WMREG_FEXTNVM7 0x00e4 /* Future Extended NVM 7 */ 724 #define FEXTNVM7_SIDE_CLK_UNGATE __BIT(2) 725 #define FEXTNVM7_DIS_SMB_PERST __BIT(5) 726 #define FEXTNVM7_DIS_PB_READ __BIT(18) 727 728 #define WMREG_IVAR 0x00e4 /* Interrupt Vector Allocation Register */ 729 #define WMREG_IVAR0 0x01700 /* Interrupt Vector Allocation */ 730 #define IVAR_ALLOC_MASK __BITS(0, 6) /* Bit 5 and 6 are reserved */ 731 #define IVAR_VALID __BIT(7) 732 /* IVAR definitions for 82580 and newer */ 733 #define WMREG_IVAR_Q(x) (WMREG_IVAR0 + ((x) / 2) * 4) 734 #define IVAR_TX_MASK_Q(x) (0x000000ffUL << (((x) % 2) == 0 ? 8 : 24)) 735 #define IVAR_RX_MASK_Q(x) (0x000000ffUL << (((x) % 2) == 0 ? 0 : 16)) 736 /* IVAR definitions for 82576 */ 737 #define WMREG_IVAR_Q_82576(x) (WMREG_IVAR0 + ((x) & 0x7) * 4) 738 #define IVAR_TX_MASK_Q_82576(x) (0x000000ffUL << (((x) / 8) == 0 ? 8 : 24)) 739 #define IVAR_RX_MASK_Q_82576(x) (0x000000ffUL << (((x) / 8) == 0 ? 0 : 16)) 740 /* IVAR definitions for 82574 */ 741 #define IVAR_ALLOC_MASK_82574 __BITS(0, 2) 742 #define IVAR_VALID_82574 __BIT(3) 743 #define IVAR_TX_MASK_Q_82574(x) (0x0000000fUL << ((x) == 0 ? 8 : 12)) 744 #define IVAR_RX_MASK_Q_82574(x) (0x0000000fUL << ((x) == 0 ? 0 : 4)) 745 #define IVAR_OTHER_MASK __BITS(16, 19) 746 #define IVAR_INT_ON_ALL_WB __BIT(31) 747 748 #define WMREG_IVAR_MISC 0x01740 /* IVAR for other causes */ 749 #define IVAR_MISC_TCPTIMER __BITS(0, 7) 750 #define IVAR_MISC_OTHER __BITS(8, 15) 751 752 #define WMREG_SVCR 0x00f0 753 #define SVCR_OFF_EN __BIT(0) 754 #define SVCR_OFF_MASKINT __BIT(12) 755 756 #define WMREG_SVT 0x00f4 757 #define SVT_OFF_HWM __BITS(4, 0) 758 759 #define WMREG_LTRV 0x00f8 /* Latency Tolerance Reporting */ 760 #define LTRV_VALUE __BITS(9, 0) 761 #define LTRV_SCALE __BITS(12, 10) 762 #define LTRV_SCALE_MAX 5 763 #define LTRV_SNOOP_REQ __BIT(15) 764 #define LTRV_SEND __BIT(30) 765 #define LTRV_NONSNOOP __BITS(31, 16) 766 #define LTRV_NONSNOOP_REQ __BIT(31) 767 768 #define WMREG_RCTL 0x0100 /* Receive Control */ 769 #define RCTL_EN __BIT(1) /* receiver enable */ 770 #define RCTL_SBP __BIT(2) /* store bad packets */ 771 #define RCTL_UPE __BIT(3) /* unicast promisc. enable */ 772 #define RCTL_MPE __BIT(4) /* multicast promisc. enable */ 773 #define RCTL_LPE __BIT(5) /* large packet enable */ 774 #define RCTL_LBM(x) ((x) << 6) /* loopback mode */ 775 #define RCTL_LBM_NONE RCTL_LBM(0) 776 #define RCTL_LBM_PHY RCTL_LBM(3) 777 #define RCTL_RDMTS(x) ((x) << 8) /* receive desc. min thresh size */ 778 #define RCTL_RDMTS_1_2 RCTL_RDMTS(0) 779 #define RCTL_RDMTS_1_4 RCTL_RDMTS(1) 780 #define RCTL_RDMTS_1_8 RCTL_RDMTS(2) 781 #define RCTL_RDMTS_MASK RCTL_RDMTS(3) 782 #define RCTL_DTYP_MASK __BITS(11,10) /* descriptor type. 82574 only */ 783 #define RCTL_DTYP(x) __SHIFTIN(x,RCTL_DTYP_MASK) 784 #define RCTL_DTYP_ONEBUF RCTL_DTYP(0) /* use one buffer(not split header). */ 785 #define RCTL_DTYP_SPH RCTL_DTYP(1) /* split header buffer. */ 786 /* RCTL_DTYP(2) and RCTL_DTYP(3) are reserved. */ 787 #define RCTL_MO __BITS(13, 12) /* multicast offset */ 788 #define RCTL_BAM __BIT(15) /* broadcast accept mode */ 789 #define RCTL_RDMTS_HEX __BIT(16) 790 #define RCTL_2k (0 << 16) /* 2k Rx buffers */ 791 #define RCTL_1k (1 << 16) /* 1k Rx buffers */ 792 #define RCTL_512 (2 << 16) /* 512 byte Rx buffers */ 793 #define RCTL_256 (3 << 16) /* 256 byte Rx buffers */ 794 #define RCTL_BSEX_16k (1 << 16) /* 16k Rx buffers (BSEX) */ 795 #define RCTL_BSEX_8k (2 << 16) /* 8k Rx buffers (BSEX) */ 796 #define RCTL_BSEX_4k (3 << 16) /* 4k Rx buffers (BSEX) */ 797 #define RCTL_DPF __BIT(22) /* discard pause frames */ 798 #define RCTL_PMCF __BIT(23) /* pass MAC control frames */ 799 #define RCTL_BSEX __BIT(25) /* buffer size extension (Livengood) */ 800 #define RCTL_SECRC __BIT(26) /* strip Ethernet CRC */ 801 802 #define WMREG_OLD_RDTR0 0x0108 /* Receive Delay Timer (ring 0) */ 803 #define WMREG_RDTR 0x2820 804 #define RDTR_FPD __BIT(31) /* flush partial descriptor */ 805 806 #define WMREG_LTRC 0x01a0 /* Latency Tolerance Reportiong Control */ 807 808 #define WMREG_OLD_RDBAL0 0x0110 /* Receive Descriptor Base Low (ring 0) */ 809 #define WMREG_RDBAL(x) \ 810 ((x) < 4 ? (0x02800 + ((x) * 0x100)) : \ 811 (0x0c000 + ((x) * 0x40))) 812 813 #define WMREG_OLD_RDBAH0 0x0114 /* Receive Descriptor Base High (ring 0) */ 814 #define WMREG_RDBAH(x) \ 815 ((x) < 4 ? (0x02804 + ((x) * 0x100)) : \ 816 (0x0c004 + ((x) * 0x40))) 817 818 #define WMREG_OLD_RDLEN0 0x0118 /* Receive Descriptor Length (ring 0) */ 819 #define WMREG_RDLEN(x) \ 820 ((x) < 4 ? (0x02808 + ((x) * 0x100)) : \ 821 (0x0c008 + ((x) * 0x40))) 822 823 #define WMREG_SRRCTL(x) \ 824 ((x) < 4 ? (0x0280c + ((x) * 0x100)) : \ 825 (0x0c00c + ((x) * 0x40))) /* additional recv control used in 82575 ... */ 826 #define SRRCTL_BSIZEPKT_MASK 0x0000007f 827 #define SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 828 #define SRRCTL_BSIZEHDRSIZE_MASK 0x00000f00 829 #define SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 830 #define SRRCTL_DESCTYPE_LEGACY 0x00000000 831 #define SRRCTL_DESCTYPE_ADV_ONEBUF (1U << 25) 832 #define SRRCTL_DESCTYPE_HDR_SPLIT (2U << 25) 833 #define SRRCTL_DESCTYPE_HDR_REPLICATION (3U << 25) 834 #define SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT (4U << 25) 835 #define SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS (5U << 25) /* 82575 only */ 836 #define SRRCTL_DESCTYPE_MASK (7U << 25) 837 #define SRRCTL_DROP_EN 0x80000000 838 839 #define WMREG_OLD_RDH0 0x0120 /* Receive Descriptor Head (ring 0) */ 840 #define WMREG_RDH(x) \ 841 ((x) < 4 ? (0x02810 + ((x) * 0x100)) : \ 842 (0x0c010 + ((x) * 0x40))) 843 844 #define WMREG_OLD_RDT0 0x0128 /* Receive Descriptor Tail (ring 0) */ 845 #define WMREG_RDT(x) \ 846 ((x) < 4 ? (0x02818 + ((x) * 0x100)) : \ 847 (0x0c018 + ((x) * 0x40))) 848 849 #define WMREG_RXDCTL(x) \ 850 ((x) < 4 ? (0x02828 + ((x) * 0x100)) : \ 851 (0x0c028 + ((x) * 0x40))) /* Receive Descriptor Control */ 852 #define RXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ 853 #define RXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ 854 #define RXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ 855 #define RXDCTL_GRAN __BIT(24) /* 0 = cacheline, 1 = descriptor */ 856 /* flags used starting with 82575 ... */ 857 #define RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 858 #define RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */ 859 860 #define WMREG_OLD_RDTR1 0x0130 /* Receive Delay Timer (ring 1) */ 861 #define WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */ 862 #define WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */ 863 #define WMREG_OLD_RDLEN1 0x0140 /* Receive Drscriptor Length (ring 1) */ 864 #define WMREG_OLD_RDH1 0x0148 865 #define WMREG_OLD_RDT1 0x0150 866 #define WMREG_OLD_FCRTH 0x0160 /* Flow Control Rx Threshold Hi (OLD) */ 867 #define WMREG_FCRTH 0x2168 /* Flow Control Rx Threhsold Hi */ 868 #define FCRTH_DFLT 0x00008000 869 870 #define WMREG_OLD_FCRTL 0x0168 /* Flow Control Rx Threshold Lo (OLD) */ 871 #define WMREG_FCRTL 0x2160 /* Flow Control Rx Threshold Lo */ 872 #define FCRTL_DFLT 0x00004000 873 #define FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 874 875 #define WMREG_FCTTV 0x0170 /* Flow Control Transmit Timer Value */ 876 #define FCTTV_DFLT 0x00000600 877 878 #define WMREG_TXCW 0x0178 /* Transmit Configuration Word (TBI mode) */ 879 /* See MII ANAR_X bits. */ 880 #define TXCW_FD __BIT(5) /* Full Duplex */ 881 #define TXCW_HD __BIT(6) /* Half Duplex */ 882 #define TXCW_SYM_PAUSE __BIT(7) /* sym pause request */ 883 #define TXCW_ASYM_PAUSE __BIT(8) /* asym pause request */ 884 #define TXCW_TxConfig __BIT(30) /* Tx Config */ 885 #define TXCW_ANE __BIT(31) /* Autonegotiate */ 886 887 #define WMREG_RXCW 0x0180 /* Receive Configuration Word (TBI mode) */ 888 /* See MII ANLPAR_X bits. */ 889 #define RXCW_NC __BIT(26) /* no carrier */ 890 #define RXCW_IV __BIT(27) /* config invalid */ 891 #define RXCW_CC __BIT(28) /* config change */ 892 #define RXCW_C __BIT(29) /* /C/ reception */ 893 #define RXCW_SYNCH __BIT(30) /* synchronized */ 894 #define RXCW_ANC __BIT(31) /* autonegotiation complete */ 895 896 #define WMREG_MTA 0x0200 /* Multicast Table Array */ 897 #define WMREG_CORDOVA_MTA 0x5200 898 899 #define WMREG_TCTL 0x0400 /* Transmit Control Register */ 900 #define TCTL_EN __BIT(1) /* transmitter enable */ 901 #define TCTL_PSP __BIT(3) /* pad short packets */ 902 #define TCTL_CT(x) (((x) & 0xff) << 4) /* 4:11 - collision threshold */ 903 #define TCTL_COLD(x) (((x) & 0x3ff) << 12) /* 12:21 - collision distance */ 904 #define TCTL_SWXOFF __BIT(22) /* software XOFF */ 905 #define TCTL_RTLC __BIT(24) /* retransmit on late collision */ 906 #define TCTL_NRTU __BIT(25) /* no retransmit on underrun */ 907 #define TCTL_MULR __BIT(28) /* multiple request */ 908 909 #define TX_COLLISION_THRESHOLD 15 910 #define TX_COLLISION_DISTANCE_HDX 512 911 #define TX_COLLISION_DISTANCE_FDX 64 912 913 #define WMREG_TCTL_EXT 0x0404 /* Transmit Control Register */ 914 #define TCTL_EXT_BST_MASK 0x000003ff /* Backoff Slot Time */ 915 #define TCTL_EXT_GCEX_MASK 0x000ffc00 /* Gigabit Carry Extend Padding */ 916 917 #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 918 919 #define WMREG_TIPG 0x0410 /* Transmit IPG Register */ 920 #define TIPG_IPGT_MASK __BITS(0, 9) /* IPG transmit time MASK */ 921 #define TIPG_IPGT(x) __SHIFTIN((x), TIPG_IPGT_MASK) /* IPG transmit time */ 922 #define TIPG_IPGR1(x) ((x) << 10) /* IPG receive time 1 */ 923 #define TIPG_IPGR2(x) ((x) << 20) /* IPG receive time 2 */ 924 #define TIPG_WM_DFLT (TIPG_IPGT(0x0a) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x0a)) 925 #define TIPG_LG_DFLT (TIPG_IPGT(0x06) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) 926 #define TIPG_1000T_DFLT (TIPG_IPGT(0x08) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) 927 #define TIPG_1000T_80003_DFLT \ 928 (TIPG_IPGT(0x08) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) 929 #define TIPG_10_100_80003_DFLT \ 930 (TIPG_IPGT(0x09) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) 931 932 #define WMREG_TQC 0x0418 933 934 #define WMREG_OLD_TDBAL 0x0420 /* Transmit Descriptor Base Lo */ 935 #define WMREG_TDBAL(x) \ 936 ((x) < 4 ? (0x03800 + ((x) * 0x100)) : \ 937 (0x0e000 + ((x) * 0x40))) 938 939 #define WMREG_OLD_TDBAH 0x0424 /* Transmit Descriptor Base Hi */ 940 #define WMREG_TDBAH(x)\ 941 ((x) < 4 ? (0x03804 + ((x) * 0x100)) : \ 942 (0x0e004 + ((x) * 0x40))) 943 944 #define WMREG_OLD_TDLEN 0x0428 /* Transmit Descriptor Length */ 945 #define WMREG_TDLEN(x) \ 946 ((x) < 4 ? (0x03808 + ((x) * 0x100)) : \ 947 (0x0e008 + ((x) * 0x40))) 948 949 #define WMREG_OLD_TDH 0x0430 /* Transmit Descriptor Head */ 950 #define WMREG_TDH(x) \ 951 ((x) < 4 ? (0x03810 + ((x) * 0x100)) : \ 952 (0x0e010 + ((x) * 0x40))) 953 954 #define WMREG_OLD_TDT 0x0438 /* Transmit Descriptor Tail */ 955 #define WMREG_TDT(x) \ 956 ((x) < 4 ? (0x03818 + ((x) * 0x100)) : \ 957 (0x0e018 + ((x) * 0x40))) 958 959 #define WMREG_OLD_TIDV 0x0440 /* Transmit Delay Interrupt Value */ 960 #define WMREG_TIDV 0x3820 961 962 #define WMREG_AIT 0x0458 /* Adaptive IFS Throttle */ 963 #define WMREG_VFTA 0x0600 964 965 #define WMREG_LEDCTL 0x0e00 /* LED Control - RW */ 966 967 #define WMREG_MDICNFG 0x0e04 /* MDC/MDIO Configuration Register */ 968 #define MDICNFG_PHY_SHIFT 21 969 #define MDICNFG_PHY_MASK __BITS(25, 21) 970 #define MDICNFG_COM_MDIO __BIT(30) 971 #define MDICNFG_DEST __BIT(31) 972 973 #define WM_MC_TABSIZE 128 974 #define WM_ICH8_MC_TABSIZE 32 975 #define WM_VLAN_TABSIZE 128 976 977 #define WMREG_PHPM 0x0e14 /* PHY Power Management */ 978 #define PHPM_SPD_EN __BIT(0) /* Smart Power Down */ 979 #define PHPM_D0A_LPLU __BIT(1) /* D0 Low Power Link Up */ 980 #define PHPM_NOND0A_LPLU __BIT(2) /* Non-D0a LPLU */ 981 #define PHPM_NOND0A_GBE_DIS __BIT(3) /* Disable 1G in non-D0a */ 982 #define PHPM_GO_LINK_D __BIT(5) /* Go Link Disconnect */ 983 984 #define WMREG_EEER 0x0e30 /* Energy Efficiency Ethernet "EEE" */ 985 #define EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ 986 #define EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ 987 #define EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ 988 #define EEER_EEER_NEG 0x20000000 /* EEER capability nego */ 989 #define EEER_EEER_RX_LPI_STATUS 0x40000000 /* EEER Rx in LPI state */ 990 #define EEER_EEER_TX_LPI_STATUS 0x80000000 /* EEER Tx in LPI state */ 991 #define WMREG_EEE_SU 0x0e34 /* EEE Setup */ 992 #define WMREG_IPCNFG 0x0e38 /* Internal PHY Configuration */ 993 #define IPCNFG_10BASE_TE 0x00000002 /* IPCNFG 10BASE-Te low power op. */ 994 #define IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ 995 #define IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ 996 997 #define WMREG_EXTCNFCTR 0x0f00 /* Extended Configuration Control */ 998 #define EXTCNFCTR_PCIE_WRITE_ENABLE 0x00000001 999 #define EXTCNFCTR_OEM_WRITE_ENABLE 0x00000008 1000 #define EXTCNFCTR_MDIO_SW_OWNERSHIP 0x00000020 1001 #define EXTCNFCTR_MDIO_HW_OWNERSHIP 0x00000040 1002 #define EXTCNFCTR_GATE_PHY_CFG 0x00000080 1003 #define EXTCNFCTR_EXT_CNF_POINTER 0x0fff0000 1004 1005 #define WMREG_EXTCNFSIZE 0x0f08 /* Extended Configuration Size */ 1006 #define EXTCNFSIZE_LENGTH __BITS(23, 16) 1007 1008 #define WMREG_PHY_CTRL 0x0f10 /* PHY control */ 1009 #define PHY_CTRL_SPD_EN (1 << 0) 1010 #define PHY_CTRL_D0A_LPLU (1 << 1) 1011 #define PHY_CTRL_NOND0A_LPLU (1 << 2) 1012 #define PHY_CTRL_NOND0A_GBE_DIS (1 << 3) 1013 #define PHY_CTRL_GBE_DIS (1 << 6) 1014 1015 #define WMREG_PCIEANACFG 0x0f18 /* PCIE Analog Config */ 1016 1017 #define WMREG_IOSFPC 0x0f28 /* Tx corrupted data */ 1018 1019 #define WMREG_PBA 0x1000 /* Packet Buffer Allocation */ 1020 #define PBA_BYTE_SHIFT 10 /* KB -> bytes */ 1021 #define PBA_ADDR_SHIFT 7 /* KB -> quadwords */ 1022 #define PBA_8K 0x0008 1023 #define PBA_10K 0x000a 1024 #define PBA_12K 0x000c 1025 #define PBA_14K 0x000e 1026 #define PBA_16K 0x0010 /* 16K, default Tx allocation */ 1027 #define PBA_20K 0x0014 1028 #define PBA_22K 0x0016 1029 #define PBA_24K 0x0018 1030 #define PBA_26K 0x001a 1031 #define PBA_30K 0x001e 1032 #define PBA_32K 0x0020 1033 #define PBA_34K 0x0022 1034 #define PBA_35K 0x0023 1035 #define PBA_40K 0x0028 1036 #define PBA_48K 0x0030 /* 48K, default Rx allocation */ 1037 #define PBA_64K 0x0040 1038 #define PBA_RXA_MASK __BITS(15, 0) 1039 1040 #define WMREG_PBS 0x1008 /* Packet Buffer Size (ICH) */ 1041 1042 #define WMREG_PBECCSTS 0x100c /* Packet Buffer ECC Status (PCH_LPT) */ 1043 #define PBECCSTS_CORR_ERR_CNT_MASK 0x000000ff 1044 #define PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000ff00 1045 #define PBECCSTS_UNCORR_ECC_ENABLE 0x00010000 1046 1047 #define WMREG_EEMNGCTL 0x1010 /* MNG EEprom Control */ 1048 #define EEMNGCTL_CFGDONE_0 0x040000 /* MNG config cycle done */ 1049 #define EEMNGCTL_CFGDONE_1 0x080000 /* 2nd port */ 1050 1051 #define WMREG_I2CCMD 0x1028 /* SFPI2C Command Register - RW */ 1052 #define I2CCMD_REG_ADDR_SHIFT 16 1053 #define I2CCMD_REG_ADDR 0x00ff0000 1054 #define I2CCMD_PHY_ADDR_SHIFT 24 1055 #define I2CCMD_PHY_ADDR 0x07000000 1056 #define I2CCMD_OPCODE_READ 0x08000000 1057 #define I2CCMD_OPCODE_WRITE 0x00000000 1058 #define I2CCMD_RESET 0x10000000 1059 #define I2CCMD_READY 0x20000000 1060 #define I2CCMD_INTERRUPT_ENA 0x40000000 1061 #define I2CCMD_ERROR 0x80000000 1062 #define MAX_SGMII_PHY_REG_ADDR 255 1063 #define I2CCMD_PHY_TIMEOUT 200 1064 1065 #define WMREG_EEWR 0x102c /* EEPROM write */ 1066 1067 #define WMREG_PBA_ECC 0x01100 /* PBA ECC */ 1068 #define PBA_ECC_COUNTER_MASK 0xfff00000 /* ECC counter mask */ 1069 #define PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 1070 #define PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ 1071 #define PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 1072 #define PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ 1073 1074 #define WMREG_GPIE 0x01514 /* General Purpose Interrupt Enable */ 1075 #define GPIE_NSICR __BIT(0) /* Non Selective Interrupt Clear */ 1076 #define GPIE_MULTI_MSIX __BIT(4) /* Multiple MSIX */ 1077 #define GPIE_EIAME __BIT(30) /* Extended Interrupt Auto Mask Ena. */ 1078 #define GPIE_PBA __BIT(31) /* PBA support */ 1079 1080 #define WMREG_EICS 0x01520 /* Ext. Interrupt Cause Set - WO */ 1081 #define WMREG_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 1082 #define WMREG_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 1083 #define WMREG_EIAC 0x0152c /* Ext. Interrupt Auto Clear - RW */ 1084 #define WMREG_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 1085 1086 #define WMREG_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 1087 1088 #define WMREG_MSIXBM(x) (0x1600 + (x) * 4) /* MSI-X Allocation */ 1089 1090 #define EITR_RX_QUEUE(x) __BIT(0+(x)) /* Rx Queue x Interrupt x=[0-3] */ 1091 #define EITR_TX_QUEUE(x) __BIT(8+(x)) /* Tx Queue x Interrupt x=[0-3] */ 1092 #define EITR_TCP_TIMER 0x40000000 /* TCP Timer */ 1093 #define EITR_OTHER 0x80000000 /* Interrupt Cause Active */ 1094 1095 #define WMREG_EITR(x) (0x01680 + (0x4 * (x))) 1096 #define EITR_ITR_INT_MASK __BITS(14,2) 1097 #define EITR_COUNTER_MASK_82575 __BITS(31,16) 1098 #define EITR_CNT_INGR __BIT(31) /* does not overwrite counter */ 1099 1100 #define WMREG_EITR_82574(x) (0x000e8 + (0x4 * (x))) 1101 #define EITR_ITR_INT_MASK_82574 __BITS(15, 0) 1102 1103 #define WMREG_RXPBS 0x2404 /* Rx Packet Buffer Size */ 1104 #define RXPBS_SIZE_MASK_82576 0x0000007f 1105 1106 #define WMREG_RDFH 0x2410 /* Receive Data FIFO Head */ 1107 #define WMREG_RDFT 0x2418 /* Receive Data FIFO Tail */ 1108 #define WMREG_RDFHS 0x2420 /* Receive Data FIFO Head Saved */ 1109 #define WMREG_RDFTS 0x2428 /* Receive Data FIFO Tail Saved */ 1110 #define WMREG_RADV 0x282c /* Receive Interrupt Absolute Delay Timer */ 1111 1112 #define WMREG_TXDMAC 0x3000 /* Transfer DMA Control */ 1113 #define TXDMAC_DPP __BIT(0) /* disable packet prefetch */ 1114 1115 #define WMREG_KABGTXD 0x3004 /* AFE and Gap Transmit Ref Data */ 1116 #define KABGTXD_BGSQLBIAS 0x00050000 1117 1118 #define WMREG_TDFH 0x3410 /* Transmit Data FIFO Head */ 1119 #define WMREG_TDFT 0x3418 /* Transmit Data FIFO Tail */ 1120 #define WMREG_TDFHS 0x3420 /* Transmit Data FIFO Head Saved */ 1121 #define WMREG_TDFTS 0x3428 /* Transmit Data FIFO Tail Saved */ 1122 #define WMREG_TDFPC 0x3430 /* Transmit Data FIFO Packet Count */ 1123 1124 #define WMREG_TXDCTL(n) /* Trandmit Descriptor Control */ \ 1125 (((n) < 4) ? (0x3828 + ((n) * 0x100)) : (0xe028 + ((n) * 0x40))) 1126 #define TXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ 1127 #define TXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ 1128 #define TXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ 1129 /* flags used starting with 82575 ... */ 1130 #define TXDCTL_COUNT_DESC __BIT(22) /* Enable the counting of desc. 1131 still to be processed. */ 1132 #define TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 1133 #define TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ 1134 #define TXDCTL_PRIORITY 0x08000000 1135 1136 #define WMREG_TADV 0x382c /* Transmit Absolute Interrupt Delay Timer */ 1137 #define WMREG_TSPMT 0x3830 /* TCP Segmentation Pad and Minimum 1138 Threshold (Cordova) */ 1139 #define TSPMT_TSMT(x) (x) /* TCP seg min transfer */ 1140 #define TSPMT_TSPBP(x) ((x) << 16) /* TCP seg pkt buf padding */ 1141 1142 #define WMREG_TARC0 0x3840 /* Tx arbitration count (0) */ 1143 #define WMREG_TARC1 0x3940 /* Tx arbitration count (1) */ 1144 1145 #define WMREG_CRCERRS 0x4000 /* CRC Error Count */ 1146 #define WMREG_ALGNERRC 0x4004 /* Alignment Error Count */ 1147 #define WMREG_SYMERRC 0x4008 /* Symbol Error Count */ 1148 #define WMREG_RXERRC 0x400c /* Receive error Count - R/clr */ 1149 #define WMREG_MPC 0x4010 /* Missed Packets Count - R/clr */ 1150 #define WMREG_SCC 0x4014 /* Single Collision Count - R/clr */ 1151 #define WMREG_ECOL 0x4018 /* Excessive Collisions Count - R/clr */ 1152 #define WMREG_MCC 0x401c /* Multiple Collision Count - R/clr */ 1153 #define WMREG_LATECOL 0x4020 /* Late Collisions Count - R/clr */ 1154 #define WMREG_COLC 0x4028 /* Collision Count - R/clr */ 1155 #define WMREG_CBTMPC 0x402c /* Circuit Breaker Tx Manageability Packet */ 1156 #define WMREG_DC 0x4030 /* Defer Count - R/clr */ 1157 #define WMREG_TNCRS 0x4034 /* Tx with No CRS - R/clr */ 1158 #define WMREG_SEC 0x4038 /* Sequence Error Count */ 1159 1160 /* Old */ 1161 #define WMREG_CEXTERR 0x403c /* Carrier Extension Error Count */ 1162 /* New */ 1163 #define WMREG_HTDPMC 0x403c /* Host Tx Discarded Packets by MAC Count */ 1164 1165 #define WMREG_RLEC 0x4040 /* Receive Length Error Count */ 1166 #define WMREG_CBRDPC 0x4044 /* Circuit Breaker Rx Dropped Packet Count */ 1167 #define WMREG_XONRXC 0x4048 /* XON Rx Count - R/clr */ 1168 #define WMREG_XONTXC 0x404c /* XON Tx Count - R/clr */ 1169 #define WMREG_XOFFRXC 0x4050 /* XOFF Rx Count - R/clr */ 1170 #define WMREG_XOFFTXC 0x4054 /* XOFF Tx Count - R/clr */ 1171 #define WMREG_FCRUC 0x4058 /* Flow Control Rx Unsupported Count - R/clr */ 1172 #define WMREG_PRC64 0x405c /* Packets Rx (64 bytes) - R/clr */ 1173 #define WMREG_PRC127 0x4060 /* Packets Rx (65-127 bytes) - R/clr */ 1174 #define WMREG_PRC255 0x4064 /* Packets Rx (128-255 bytes) - R/clr */ 1175 #define WMREG_PRC511 0x4068 /* Packets Rx (255-511 bytes) - R/clr */ 1176 #define WMREG_PRC1023 0x406c /* Packets Rx (512-1023 bytes) - R/clr */ 1177 #define WMREG_PRC1522 0x4070 /* Packets Rx (1024-1522 bytes) - R/clr */ 1178 #define WMREG_GPRC 0x4074 /* Good Packets Rx Count - R/clr */ 1179 #define WMREG_BPRC 0x4078 /* Broadcast Packets Rx Count - R/clr */ 1180 #define WMREG_MPRC 0x407c /* Multicast Packets Rx Count - R/clr */ 1181 #define WMREG_GPTC 0x4080 /* Good Packets Tx Count - R/clr */ 1182 #define WMREG_GORCL 0x4088 /* Good Octets Rx Count Low - R/clr */ 1183 #define WMREG_GORCH 0x408c /* Good Octets Rx Count High - R/clr */ 1184 #define WMREG_GOTCL 0x4090 /* Good Octets Tx Count Low - R/clr */ 1185 #define WMREG_GOTCH 0x4094 /* Good Octets Tx Count High - R/clr */ 1186 #define WMREG_RNBC 0x40a0 /* Receive No Buffers Count */ 1187 #define WMREG_RUC 0x40a4 /* Rx Undersize Count - R/clr */ 1188 #define WMREG_RFC 0x40a8 /* Rx Fragment Count - R/clr */ 1189 #define WMREG_ROC 0x40ac /* Rx Oversize Count - R/clr */ 1190 #define WMREG_RJC 0x40b0 /* Rx Jabber Count - R/clr */ 1191 #define WMREG_MGTPRC 0x40b4 /* Management Packets RX Count - R/clr */ 1192 #define WMREG_MGTPDC 0x40b8 /* Management Packets Dropped Count - R/clr */ 1193 #define WMREG_MGTPTC 0x40bc /* Management Packets TX Count - R/clr */ 1194 #define WMREG_TORL 0x40c0 /* Total Octets Rx Low - R/clr */ 1195 #define WMREG_TORH 0x40c4 /* Total Octets Rx High - R/clr */ 1196 #define WMREG_TOTL 0x40c8 /* Total Octets Tx Low - R/clr */ 1197 #define WMREG_TOTH 0x40cc /* Total Octets Tx High - R/clr */ 1198 #define WMREG_TPR 0x40d0 /* Total Packets Rx - R/clr */ 1199 #define WMREG_TPT 0x40d4 /* Total Packets Tx - R/clr */ 1200 #define WMREG_PTC64 0x40d8 /* Packets Tx (64 bytes) - R/clr */ 1201 #define WMREG_PTC127 0x40dc /* Packets Tx (65-127 bytes) - R/clr */ 1202 #define WMREG_PTC255 0x40e0 /* Packets Tx (128-255 bytes) - R/clr */ 1203 #define WMREG_PTC511 0x40e4 /* Packets Tx (256-511 bytes) - R/clr */ 1204 #define WMREG_PTC1023 0x40e8 /* Packets Tx (512-1023 bytes) - R/clr */ 1205 #define WMREG_PTC1522 0x40ec /* Packets Tx (1024-1522 Bytes) - R/clr */ 1206 #define WMREG_MPTC 0x40f0 /* Multicast Packets Tx Count - R/clr */ 1207 #define WMREG_BPTC 0x40f4 /* Broadcast Packets Tx Count */ 1208 #define WMREG_TSCTC 0x40f8 /* TCP Segmentation Context Tx */ 1209 1210 /* Old */ 1211 #define WMREG_TSCTFC 0x40fc /* TCP Segmentation Context Tx Fail */ 1212 /* New */ 1213 #define WMREG_CBRMPC 0x40fc /* Circuit Breaker Rx Manageability Packet */ 1214 1215 #define WMREG_IAC 0x4100 /* Interrupt Assertion Count */ 1216 1217 /* Old */ 1218 #define WMREG_ICRXPTC 0x4104 /* Interrupt Cause Rx Pkt Timer Expire Count */ 1219 #define WMREG_ICRXATC 0x4108 /* Interrupt Cause Rx Abs Timer Expire Count */ 1220 #define WMREG_ICTXPTC 0x410c /* Interrupt Cause Tx Pkt Timer Expire Count */ 1221 #define WMREG_ICTXATC 0x4110 /* Interrupt Cause Tx Abs Timer Expire Count */ 1222 #define WMREG_ICTXQEC 0x4118 /* Interrupt Cause Tx Queue Empty Count */ 1223 #define WMREG_ICTXQMTC 0x411c /* Interrupt Cause Tx Queue Min Thresh Count */ 1224 #define WMREG_ICRXDMTC 0x4120 /* Interrupt Cause Rx Desc Min Thresh Count */ 1225 #define WMREG_ICRXOC 0x4124 /* Interrupt Cause Receiver Overrun Count */ 1226 /* New */ 1227 #define WMREG_RPTHC 0x4104 /* Rx Pkt To Host Count */ 1228 #define WMREG_DEBUG1 0x4108 /* Debug Counter 1 */ 1229 #define WMREG_DEBUG2 0x410c /* Debug Counter 2 */ 1230 #define WMREG_DEBUG3 0x4110 /* Debug Counter 3 */ 1231 #define WMREG_HGPTC 0x4118 /* Host Good Packets Tx Count (>=82576?) */ 1232 #define WMREG_DEBUG4 0x411c /* Debug Counter 4 */ 1233 #define WMREG_RXDMTC 0x4120 /* Rx Desc Min Thresh Count */ 1234 #define WMREG_HTCBDPC 0x4124 /* Host Tx Circuit Breaker Dropped Pkt. Cnt. */ 1235 #define WMREG_HGORCL 0x4128 /* Host Good Octets Rx Count Low (>=82576?) */ 1236 #define WMREG_HGORCH 0x412c /* Host Good Octets Rx Count High (>=82576?) */ 1237 #define WMREG_HGOTCL 0x4130 /* Host Good Octets Tx Count Low (>=82576?) */ 1238 #define WMREG_HGOTCH 0x4134 /* Host Good Octets Tx Count High (>=82576?) */ 1239 #define WMREG_LENERRS 0x4138 /* Length Errors Count (>=82576?) */ 1240 1241 #define WMREG_TLPIC 0x4148 /* EEE Tx LPI Count */ 1242 #define WMREG_RLPIC 0x414c /* EEE Rx LPI Count */ 1243 #define WMREG_B2OGPRC 0x4158 /* BMC2OS packets received by host */ 1244 #define WMREG_O2BSPC 0x415c /* OS2BMC packets transmitted by host */ 1245 1246 #define WMREG_PCS_CFG 0x4200 /* PCS Configuration */ 1247 #define PCS_CFG_PCS_EN __BIT(3) 1248 1249 #define WMREG_PCS_LCTL 0x4208 /* PCS Link Control */ 1250 #define PCS_LCTL_FLV_LINK_UP __BIT(0) /* Forced Link Value */ 1251 #define PCS_LCTL_FSV_MASK __BITS(2, 1) /* Forced Speed Value */ 1252 #define PCS_LCTL_FSV_10 0 /* 10Mbps */ 1253 #define PCS_LCTL_FSV_100 __BIT(1) /* 100Mbps */ 1254 #define PCS_LCTL_FSV_1000 __BIT(2) /* 1Gpbs */ 1255 #define PCS_LCTL_FDV_FULL __BIT(3) /* Force Duplex Value */ 1256 #define PCS_LCTL_FSD __BIT(4) /* Force Speed and Duplex */ 1257 #define PCS_LCTL_FORCE_LINK __BIT(5) /* Force Link */ 1258 #define PCS_LCTL_LINK_LATCH_LOW __BIT(6) /* Link Latch Low */ 1259 #define PCS_LCTL_FORCE_FC __BIT(7) /* Force Flow Control */ 1260 #define PCS_LCTL_AN_ENABLE __BIT(16) /* AN enable */ 1261 #define PCS_LCTL_AN_RESTART __BIT(17) /* AN restart */ 1262 #define PCS_LCTL_AN_TIMEOUT __BIT(18) /* AN Timeout Enable */ 1263 #define PCS_LCTL_AN_SGMII_BYP __BIT(19) /* AN SGMII Bypass */ 1264 #define PCS_LCTL_AN_SGMII_TRIG __BIT(20) /* AN SGMII Trigger */ 1265 #define PCS_LCTL_FAST_LINKTIMER __BIT(24) /* Fast Link Timer */ 1266 #define PCS_LCTL_LINK_OK_FIX_EN __BIT(25) /* Link OK Fix Enable */ 1267 1268 #define WMREG_PCS_LSTS 0x420c /* PCS Link Status */ 1269 #define PCS_LSTS_LINKOK __BIT(0) 1270 #define PCS_LSTS_SPEED __BITS(2, 1) 1271 #define PCS_LSTS_SPEED_10 0 1272 #define PCS_LSTS_SPEED_100 1 1273 #define PCS_LSTS_SPEED_1000 2 1274 #define PCS_LSTS_FDX __BIT(3) 1275 #define PCS_LSTS_AN_COMP __BIT(16) 1276 1277 #define WMREG_PCS_ANADV 0x4218 /* AN Advertsement */ 1278 #define WMREG_PCS_LPAB 0x421c /* Link Partnet Ability */ 1279 #define WMREG_PCS_NPTX 0x4220 /* Next Page Transmit */ 1280 #define WMREG_SCVPC 0x4228 /* SerDes/SGMII Code Violation Packet Count */ 1281 1282 #define WMREG_RXCSUM 0x5000 /* Receive Checksum register */ 1283 #define RXCSUM_PCSS 0x000000ff /* Packet Checksum Start */ 1284 #define RXCSUM_IPOFL __BIT(8) /* IP checksum offload */ 1285 #define RXCSUM_TUOFL __BIT(9) /* TCP/UDP checksum offload */ 1286 #define RXCSUM_IPV6OFL __BIT(10) /* IPv6 checksum offload */ 1287 #define RXCSUM_CRCOFL __BIT(11) /* SCTP CRC32 checksum offload */ 1288 #define RXCSUM_IPPCSE __BIT(12) /* IP payload checksum enable */ 1289 #define RXCSUM_PCSD __BIT(13) /* packet checksum disabled */ 1290 1291 #define WMREG_RLPML 0x5004 /* Rx Long Packet Max Length */ 1292 1293 #define WMREG_RFCTL 0x5008 /* Receive Filter Control */ 1294 #define WMREG_RFCTL_NFSWDIS __BIT(6) /* NFS Write Disable */ 1295 #define WMREG_RFCTL_NFSRDIS __BIT(7) /* NFS Read Disable */ 1296 #define WMREG_RFCTL_ACKDIS __BIT(12) /* ACK Accelerate Disable */ 1297 #define WMREG_RFCTL_ACKD_DIS __BIT(13) /* ACK data Disable */ 1298 #define WMREG_RFCTL_EXSTEN __BIT(15) /* Extended status Enable. 82574 only. */ 1299 #define WMREG_RFCTL_IPV6EXDIS __BIT(16) /* IPv6 Extension Header Disable */ 1300 #define WMREG_RFCTL_NEWIPV6EXDIS __BIT(17) /* New IPv6 Extension Header */ 1301 1302 #define WMREG_WUC 0x5800 /* Wakeup Control */ 1303 #define WUC_APME 0x00000001 /* APM Enable */ 1304 #define WUC_PME_EN 0x00000002 /* PME Enable */ 1305 #define WUC_PME_STATUS 0x00000004 /* PME Status */ 1306 #define WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 1307 #define WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 1308 1309 #define WMREG_WUFC 0x5808 /* Wakeup Filter Control */ 1310 #define WUFC_LNKC __BIT(0) /* Link Status Change Wakeup Enable */ 1311 #define WUFC_MAG __BIT(1) /* Magic Packet Wakeup Enable */ 1312 #define WUFC_EX __BIT(2) /* Directed Exact Wakeup Enable */ 1313 #define WUFC_MC __BIT(3) /* Directed Multicast Wakeup En */ 1314 #define WUFC_BC __BIT(4) /* Broadcast Wakeup Enable */ 1315 #define WUFC_ARPDIR __BIT(5) /* ARP Request Packet Wakeup En */ 1316 #define WUFC_IPV4 __BIT(6) /* Directed IPv4 Packet Wakeup En */ 1317 #define WUFC_IPV6 __BIT(7) /* Directed IPv6 Packet Wakeup En */ 1318 #define WUFC_NS __BIT(9) /* NS Wakeup En */ 1319 #define WUFC_NSDIR __BIT(10) /* NS Directed En */ 1320 #define WUFC_ARP __BIT(11) /* ARP request En */ 1321 #define WUFC_FLEX_HQ __BIT(14) /* Flex Filters Host Queueing En */ 1322 #define WUFC_NOTCO __BIT(15) /* ? */ 1323 #define WUFC_FLX __BITS(23, 16) /* Flexible Filter [0-7] En */ 1324 #define WUFC_FLXACT __BITS(27, 24) /* Flexible Filter [0-3] Action */ 1325 #define WUFC_FW_RST_WK __BIT(31) /* Wake on Firmware Reset Assert En */ 1326 1327 #define WMREG_WUS 0x5810 /* Wakeup Status (R/W1C) */ 1328 /* Bit 30-24 and 15-12 are reserved */ 1329 #define WUS_MNG __BIT(8) /* Manageability event */ 1330 #define WUS_FLAGS "\20" \ 1331 "\1LINKC" "\2MAG" "\3EX" "\4MC" \ 1332 "\5BC" "\6ARPDIR" "\7IPV4" "\10IPV6" \ 1333 "\11MNG" "\12NS" "\13NSDIR" "\14ARP" \ 1334 "\21FLX0" "\22FLX1" "\23FLX2" "\24FLX3" \ 1335 "\25FLX4" "\26FLX5" "\27FLX6" "\30FLX7" \ 1336 "\40FW_RST_WK" 1337 1338 #define WMREG_MRQC 0x5818 /* Multiple Receive Queues Command */ 1339 #define MRQC_DISABLE_RSS 0x00000000 1340 #define MRQC_ENABLE_RSS_MQ_82574 __BIT(0) /* enable RSS for 82574 */ 1341 #define MRQC_ENABLE_RSS_MQ __BIT(1) /* enable hardware max RSS without VMDq */ 1342 #define MRQC_ENABLE_RSS_VMDQ __BITS(1, 0) /* enable RSS with VMDq */ 1343 #define MRQC_DEFQ_MASK __BITS(5, 3) 1344 /* 1345 * Defines the default queue in non VMDq 1346 * mode according to value of the Multiple Receive 1347 * Queues Enable field. 1348 */ 1349 #define MRQC_DEFQ_NOT_RSS_FLT __SHFTIN(__BIT(1), MRQC_DEFQ_MASK) 1350 /* 1351 * the destination of all packets 1352 * not forwarded by RSS or filters 1353 */ 1354 #define MRQC_DEFQ_NOT_MAC_ETH __SHFTIN(__BITS(1, 0), MRQC_DEFQ_MASK) 1355 /* 1356 * Def_Q field is ignored. Queueing 1357 * decision of all packets not forwarded 1358 * by MAC address and Ether-type filters 1359 * is according to VT_CTL.DEF_PL field. 1360 */ 1361 #define MRQC_DEFQ_IGNORED1 __SHFTIN(__BIT(2), MRQC_DEFQ_MASK) 1362 /* Def_Q field is ignored */ 1363 #define MRQC_DEFQ_IGNORED2 __SHFTIN(__BIT(2)|__BIT(0), MRQC_DEFQ_MASK) 1364 /* Def_Q field is ignored */ 1365 #define MRQC_DEFQ_VMDQ __SHFTIN(__BITS(2, 1), MRQC_DEFQ_MASK) 1366 /* for VMDq mode */ 1367 #define MRQC_RSS_FIELD_IPV4_TCP __BIT(16) 1368 #define MRQC_RSS_FIELD_IPV4 __BIT(17) 1369 #define MRQC_RSS_FIELD_IPV6_TCP_EX __BIT(18) 1370 #define MRQC_RSS_FIELD_IPV6_EX __BIT(19) 1371 #define MRQC_RSS_FIELD_IPV6 __BIT(20) 1372 #define MRQC_RSS_FIELD_IPV6_TCP __BIT(21) 1373 #define MRQC_RSS_FIELD_IPV4_UDP __BIT(22) 1374 #define MRQC_RSS_FIELD_IPV6_UDP __BIT(23) 1375 #define MRQC_RSS_FIELD_IPV6_UDP_EX __BIT(24) 1376 1377 #define WMREG_RETA_Q(x) (0x5c00 + ((x) >> 2) * 4) /* Redirection Table */ 1378 #define RETA_NUM_ENTRIES 128 1379 #define RETA_ENTRY_MASK_Q(x) (0x000000ffUL << (((x) % 4) * 8)) /* Redirection Table */ 1380 #define RETA_ENT_QINDEX_MASK __BITS(3,0) /*queue index for 82580 and newer */ 1381 #define RETA_ENT_QINDEX0_MASK_82575 __BITS(3,2) /*queue index for pool0 */ 1382 #define RETA_ENT_QINDEX1_MASK_82575 __BITS(7,6) /*queue index for pool1 and regular RSS */ 1383 #define RETA_ENT_QINDEX_MASK_82574 __BIT(7) /*queue index for 82574 */ 1384 1385 #define WMREG_RSSRK(x) (0x5c80 + (x) * 4) /* RSS Random Key Register */ 1386 #define RSSRK_NUM_REGS 10 1387 1388 #define WMREG_MANC 0x5820 /* Management Control */ 1389 #define MANC_SMBUS_EN __BIT(0) 1390 #define MANC_ASF_EN __BIT(1) 1391 #define MANC_ARP_EN __BIT(13) 1392 #define MANC_RECV_TCO_RESET __BIT(16) 1393 #define MANC_RECV_TCO_EN __BIT(17) 1394 #define MANC_BLK_PHY_RST_ON_IDE __BIT(18) 1395 #define MANC_RECV_ALL __BIT(19) 1396 #define MANC_EN_MAC_ADDR_FILTER __BIT(20) 1397 #define MANC_EN_MNG2HOST __BIT(21) 1398 #define MANC_EN_BMC2OS __BIT(28) 1399 1400 #define WMREG_MANC2H 0x5860 /* Management Control To Host - RW */ 1401 #define MANC2H_PORT_623 (1 << 5) 1402 #define MANC2H_PORT_624 (1 << 6) 1403 1404 #define WMREG_GCR 0x5b00 /* PCIe Control */ 1405 #define GCR_RXD_NO_SNOOP 0x00000001 1406 #define GCR_RXDSCW_NO_SNOOP 0x00000002 1407 #define GCR_RXDSCR_NO_SNOOP 0x00000004 1408 #define GCR_TXD_NO_SNOOP 0x00000008 1409 #define GCR_TXDSCW_NO_SNOOP 0x00000010 1410 #define GCR_TXDSCR_NO_SNOOP 0x00000020 1411 #define GCR_CMPL_TMOUT_MASK 0x0000f000 1412 #define GCR_CMPL_TMOUT_10MS 0x00001000 1413 #define GCR_CMPL_TMOUT_RESEND 0x00010000 1414 #define GCR_CAP_VER2 0x00040000 1415 #define GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 1416 #define GCR_NO_SNOOP_ALL (GCR_RXD_NO_SNOOP | \ 1417 GCR_RXDSCW_NO_SNOOP | \ 1418 GCR_RXDSCR_NO_SNOOP | \ 1419 GCR_TXD_NO_SNOOP | \ 1420 GCR_TXDSCW_NO_SNOOP | \ 1421 GCR_TXDSCR_NO_SNOOP) 1422 1423 #define WMREG_FACTPS 0x5b30 /* Function Active and Power State to MNG */ 1424 #define FACTPS_MNGCG 0x20000000 1425 #define FACTPS_LFS 0x40000000 /* LAN Function Select */ 1426 1427 #define WMREG_GIOCTL 0x5b44 /* GIO Analog Control Register */ 1428 #define WMREG_CCMCTL 0x5b48 /* CCM Control Register */ 1429 #define WMREG_SCCTL 0x5b4c /* PCIc PLL Configuration Register */ 1430 1431 #define WMREG_SWSM 0x5b50 /* SW Semaphore */ 1432 #define SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 1433 #define SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 1434 #define SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 1435 #define SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 1436 /* Intel driver defines H2ME register at 0x5b50 */ 1437 #define WMREG_H2ME 0x5b50 /* SW Semaphore */ 1438 #define H2ME_ULP __BIT(11) 1439 #define H2ME_ENFORCE_SETTINGS __BIT(12) 1440 1441 #define WMREG_FWSM 0x5b54 /* FW Semaphore */ 1442 #define FWSM_MODE __BITS(1, 3) 1443 #define MNG_ICH_IAMT_MODE 0x2 /* PT mode? */ 1444 #define MNG_IAMT_MODE 0x3 1445 #define FWSM_RSPCIPHY __BIT(6) /* Reset PHY on PCI reset */ 1446 #define FWSM_WLOCK_MAC __BITS(7, 9) 1447 #define FWSM_ULP_CFG_DONE __BIT(10) 1448 #define FWSM_FW_VALID __BIT(15) /* FW established a valid mode */ 1449 1450 #define WMREG_SWSM2 0x5b58 /* SW Semaphore 2 */ 1451 #define SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 1452 1453 #define WMREG_SW_FW_SYNC 0x5b5c /* software-firmware semaphore */ 1454 #define SWFW_EEP_SM 0x0001 /* eeprom access */ 1455 #define SWFW_PHY0_SM 0x0002 /* first ctrl phy access */ 1456 #define SWFW_PHY1_SM 0x0004 /* second ctrl phy access */ 1457 #define SWFW_MAC_CSR_SM 0x0008 1458 #define SWFW_PHY2_SM 0x0020 /* first ctrl phy access */ 1459 #define SWFW_PHY3_SM 0x0040 /* first ctrl phy access */ 1460 #define SWFW_SOFT_SHIFT 0 /* software semaphores */ 1461 #define SWFW_FIRM_SHIFT 16 /* firmware semaphores */ 1462 1463 #define WMREG_GCR2 0x5b64 /* 3GPIO Control Register 2 */ 1464 #define WMREG_FEXTNVM9 0x5bb4 /* Future Extended NVM 9 */ 1465 #define FEXTNVM9_IOSFSB_CLKGATE_DIS __BIT(11) 1466 #define FEXTNVM9_IOSFSB_CLKREQ_DIS __BIT(12) 1467 #define WMREG_FEXTNVM11 0x5bbc /* Future Extended NVM 11 */ 1468 #define FEXTNVM11_DIS_MULRFIX __BIT(13) /* Disable MULR fix */ 1469 1470 #define WMREG_FFLT_DBG 0x05F04 /* Debug Register */ 1471 1472 #define WMREG_CRC_OFFSET 0x5f50 1473 #define WMREG_PCH_RAICC(x) (WMREG_CRC_OFFSET + (x) * 4) 1474 1475 #define WMREG_B2OSPC 0x8fe0 /* BMC2OS packets sent by BMC */ 1476 #define WMREG_O2BGPTC 0x8fe4 /* OS2BMC packets received by BMC */ 1477 1478 #define WMREG_HRMPC 0xa018 /* Header Redirection Missed Packet Count */ 1479 1480 #define WMREG_EEC 0x12010 1481 #define EEC_FLASH_DETECTED __BIT(19) /* FLASH */ 1482 #define EEC_FLUPD __BIT(23) /* Update FLASH */ 1483 1484 #define WMREG_EEARBC_I210 0x12024 1485 1486 /* 1487 * NVM related values. 1488 * Microwire, SPI, and flash 1489 */ 1490 #define UWIRE_OPC_ERASE 0x04 /* MicroWire "erase" opcode */ 1491 #define UWIRE_OPC_WRITE 0x05 /* MicroWire "write" opcode */ 1492 #define UWIRE_OPC_READ 0x06 /* MicroWire "read" opcode */ 1493 1494 #define SPI_OPC_WRITE 0x02 /* SPI "write" opcode */ 1495 #define SPI_OPC_READ 0x03 /* SPI "read" opcode */ 1496 #define SPI_OPC_A8 0x08 /* opcode bit 3 == address bit 8 */ 1497 #define SPI_OPC_WREN 0x06 /* SPI "set write enable" opcode */ 1498 #define SPI_OPC_WRDI 0x04 /* SPI "clear write enable" opcode */ 1499 #define SPI_OPC_RDSR 0x05 /* SPI "read status" opcode */ 1500 #define SPI_OPC_WRSR 0x01 /* SPI "write status" opcode */ 1501 #define SPI_MAX_RETRIES 5000 /* max wait of 5ms for RDY signal */ 1502 1503 #define SPI_SR_RDY 0x01 1504 #define SPI_SR_WEN 0x02 1505 #define SPI_SR_BP0 0x04 1506 #define SPI_SR_BP1 0x08 1507 #define SPI_SR_WPEN 0x80 1508 1509 #define NVM_CHECKSUM 0xBABA 1510 #define NVM_SIZE 0x0040 1511 #define NVM_WORD_SIZE_BASE_SHIFT 6 1512 1513 #define NVM_OFF_MACADDR 0x0000 /* MAC address offset 0 */ 1514 #define NVM_OFF_MACADDR1 0x0001 /* MAC address offset 1 */ 1515 #define NVM_OFF_MACADDR2 0x0002 /* MAC address offset 2 */ 1516 #define NVM_OFF_COMPAT 0x0003 1517 #define NVM_OFF_ID_LED_SETTINGS 0x0004 1518 #define NVM_OFF_VERSION 0x0005 1519 #define NVM_OFF_CFG1 0x000a /* config word 1 */ 1520 #define NVM_OFF_CFG2 0x000f /* config word 2 */ 1521 #define NVM_OFF_EEPROM_SIZE 0x0012 /* NVM SIZE */ 1522 #define NVM_OFF_CFG4 0x0013 /* config word 4 */ 1523 #define NVM_OFF_CFG3_PORTB 0x0014 /* config word 3 */ 1524 #define NVM_OFF_FUTURE_INIT_WORD1 0x0019 1525 #define NVM_OFF_INIT_3GIO_3 0x001a /* PCIe Initial Configuration Word 3 */ 1526 #define NVM_OFF_K1_CONFIG 0x001b /* NVM K1 Config */ 1527 #define NVM_OFF_LED_1_CFG 0x001c 1528 #define NVM_OFF_LED_0_2_CFG 0x001f 1529 #define NVM_OFF_SWDPIN 0x0020 /* SWD Pins (Cordova) */ 1530 #define NVM_OFF_CFG3_PORTA 0x0024 /* config word 3 */ 1531 #define NVM_OFF_ALT_MAC_ADDR_PTR 0x0037 /* to the alternative MAC addresses */ 1532 #define NVM_OFF_COMB_VER_PTR 0x003d 1533 #define NVM_OFF_IMAGE_UID0 0x0042 1534 #define NVM_OFF_IMAGE_UID1 0x0043 1535 1536 #define NVM_COMPAT_VALID_CHECKSUM 0x0001 1537 1538 #define NVM_CFG1_LVDID __BIT(0) 1539 #define NVM_CFG1_LSSID __BIT(1) 1540 #define NVM_CFG1_PME_CLOCK __BIT(2) 1541 #define NVM_CFG1_PM __BIT(3) 1542 #define NVM_CFG1_ILOS __BIT(4) /* Invert loss of signal */ 1543 #define NVM_CFG1_SWDPIO_SHIFT 5 1544 #define NVM_CFG1_SWDPIO_MASK (0xf << NVM_CFG1_SWDPIO_SHIFT) 1545 #define NVM_CFG1_IPS1 __BIT(8) 1546 #define NVM_CFG1_LRST __BIT(9) 1547 #define NVM_CFG1_FD __BIT(10) 1548 #define NVM_CFG1_FRCSPD __BIT(11) 1549 #define NVM_CFG1_IPS0 __BIT(12) 1550 #define NVM_CFG1_64_32_BAR __BIT(13) 1551 1552 #define NVM_CFG2_CSR_RD_SPLIT __BIT(1) 1553 #define NVM_CFG2_82544_APM_EN __BIT(2) 1554 #define NVM_CFG2_64_BIT __BIT(3) 1555 #define NVM_CFG2_MAX_READ __BIT(4) 1556 #define NVM_CFG2_DMCR_MAP __BIT(5) 1557 #define NVM_CFG2_133_CAP __BIT(6) 1558 #define NVM_CFG2_MSI_DIS __BIT(7) 1559 #define NVM_CFG2_FLASH_DIS __BIT(8) 1560 #define NVM_CFG2_FLASH_SIZE(x) (((x) & 3) >> 9) 1561 #define NVM_CFG2_APM_EN __BIT(10) 1562 #define NVM_CFG2_ANE __BIT(11) 1563 #define NVM_CFG2_PAUSE(x) (((x) & 3) >> 12) 1564 #define NVM_CFG2_ASDE __BIT(14) 1565 #define NVM_CFG2_APM_PME __BIT(15) 1566 #define NVM_CFG2_SWDPIO_SHIFT 4 1567 #define NVM_CFG2_SWDPIO_MASK (0xf << NVM_CFG2_SWDPIO_SHIFT) 1568 #define NVM_CFG2_MNGM_SHIFT 13 /* Manageability Operation mode */ 1569 #define NVM_CFG2_MNGM_MASK (3U << NVM_CFG2_MNGM_SHIFT) 1570 #define NVM_CFG2_MNGM_DIS 0 1571 #define NVM_CFG2_MNGM_NCSI 1 1572 #define NVM_CFG2_MNGM_PT 2 1573 1574 #define NVM_COMPAT_MAS_EN(x) __BIT(x) /* Media Auto Sense Enable */ 1575 #define NVM_COMPAT_SERDES_FORCE_MODE __BIT(14) /* Don't use autonego */ 1576 1577 #define NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM 0x0040 1578 1579 #define NVM_K1_CONFIG_ENABLE 0x01 1580 1581 #define NVM_SWDPIN_MASK 0xdf 1582 #define NVM_SWDPIN_SWDPIN_SHIFT 0 1583 #define NVM_SWDPIN_SWDPIO_SHIFT 8 1584 1585 #define NVM_3GIO_3_ASPM_MASK (0x3 << 2) /* Active State PM Support */ 1586 1587 #define NVM_CFG3_PORTA_EXT_MDIO __BIT(2) /* External MDIO Interface */ 1588 #define NVM_CFG3_PORTA_COM_MDIO __BIT(3) /* MDIO Interface is shared */ 1589 #define NVM_CFG3_APME __BIT(10) /* APM Enable */ 1590 #define NVM_CFG3_ILOS __BIT(13) /* Invert loss of signal */ 1591 1592 #define NVM_OFF_MACADDR_82571(x) (3 * (x)) 1593 1594 /* 1595 * EEPROM Partitioning. See Table 6-1, "EEPROM Top Level Partitioning" 1596 * in 82580's datasheet. 1597 */ 1598 #define NVM_OFF_LAN_FUNC_82580(x) ((x) ? (0x40 + (0x40 * (x))) : 0) 1599 1600 #define NVM_COMBO_VER_OFF 0x0083 1601 1602 #define NVM_MAJOR_MASK 0xf000 1603 #define NVM_MAJOR_SHIFT 12 1604 #define NVM_MINOR_MASK 0x0ff0 1605 #define NVM_MINOR_SHIFT 4 1606 #define NVM_BUILD_MASK 0x000f 1607 #define NVM_UID_VALID 0x8000 1608 1609 /* iNVM Registers for i21[01] */ 1610 #define WM_INVM_DATA_REG(reg) (0x12120 + 4*(reg)) 1611 #define INVM_SIZE 64 /* Number of INVM Data Registers */ 1612 1613 /* iNVM default value */ 1614 #define NVM_INIT_CTRL_2_DEFAULT_I211 0x7243 1615 #define NVM_INIT_CTRL_4_DEFAULT_I211 0x00c1 1616 #define NVM_LED_1_CFG_DEFAULT_I211 0x0184 1617 #define NVM_LED_0_2_CFG_DEFAULT_I211 0x200c 1618 #define NVM_RESERVED_WORD 0xffff 1619 1620 #define INVM_DWORD_TO_RECORD_TYPE(dword) ((dword) & 0x7) 1621 #define INVM_DWORD_TO_WORD_ADDRESS(dword) (((dword) & 0x0000FE00) >> 9) 1622 #define INVM_DWORD_TO_WORD_DATA(dword) (((dword) & 0xFFFF0000) >> 16) 1623 1624 #define INVM_UNINITIALIZED_STRUCTURE 0x0 1625 #define INVM_WORD_AUTOLOAD_STRUCTURE 0x1 1626 #define INVM_CSR_AUTOLOAD_STRUCTURE 0x2 1627 #define INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE 0x3 1628 #define INVM_RSA_KEY_SHA256_STRUCTURE 0x4 1629 #define INVM_INVALIDATED_STRUCTURE 0xf 1630 1631 #define INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8 1632 #define INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1 1633 1634 #define INVM_DEFAULT_AL 0x202f 1635 #define INVM_AUTOLOAD 0x0a 1636 #define INVM_PLL_WO_VAL 0x0010 1637 1638 /* Version and Image Type field */ 1639 #define INVM_VER_1 __BITS(12,3) 1640 #define INVM_VER_2 __BITS(22,13) 1641 #define INVM_IMGTYPE __BITS(28,23) 1642 #define INVM_MINOR __BITS(3,0) 1643 #define INVM_MAJOR __BITS(9,4) 1644 1645 /* Word definitions for ID LED Settings */ 1646 #define ID_LED_RESERVED_FFFF 0xffff 1647 1648 /* ich8 flash control */ 1649 #define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ 1650 #define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ 1651 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ 1652 #define ICH_FLASH_SEG_SIZE_256 256 1653 #define ICH_FLASH_SEG_SIZE_4K 4096 1654 #define ICH_FLASH_SEG_SIZE_64K 65536 1655 1656 #define ICH_CYCLE_READ 0x0 1657 #define ICH_CYCLE_RESERVED 0x1 1658 #define ICH_CYCLE_WRITE 0x2 1659 #define ICH_CYCLE_ERASE 0x3 1660 1661 #define ICH_FLASH_GFPREG 0x0000 1662 #define ICH_FLASH_HSFSTS 0x0004 /* Flash Status Register */ 1663 #define HSFSTS_DONE 0x0001 /* Flash Cycle Done */ 1664 #define HSFSTS_ERR 0x0002 /* Flash Cycle Error */ 1665 #define HSFSTS_DAEL 0x0004 /* Direct Access error Log */ 1666 #define HSFSTS_ERSZ_MASK 0x0018 /* Block/Sector Erase Size */ 1667 #define HSFSTS_ERSZ_SHIFT 3 1668 #define HSFSTS_FLINPRO 0x0020 /* flash SPI cycle in Progress */ 1669 #define HSFSTS_FLDVAL 0x4000 /* Flash Descriptor Valid */ 1670 #define HSFSTS_FLLK 0x8000 /* Flash Configuration Lock-Down */ 1671 #define ICH_FLASH_HSFCTL 0x0006 /* Flash control Register */ 1672 #define HSFCTL_GO 0x0001 /* Flash Cycle Go */ 1673 #define HSFCTL_CYCLE_MASK 0x0006 /* Flash Cycle */ 1674 #define HSFCTL_CYCLE_SHIFT 1 1675 #define HSFCTL_BCOUNT_MASK 0x0300 /* Data Byte Count */ 1676 #define HSFCTL_BCOUNT_SHIFT 8 1677 #define ICH_FLASH_FADDR 0x0008 1678 #define ICH_FLASH_FDATA0 0x0010 1679 #define ICH_FLASH_FRACC 0x0050 1680 #define ICH_FLASH_FREG0 0x0054 1681 #define ICH_FLASH_FREG1 0x0058 1682 #define ICH_FLASH_FREG2 0x005c 1683 #define ICH_FLASH_FREG3 0x0060 1684 #define ICH_FLASH_FPR0 0x0074 1685 #define ICH_FLASH_FPR1 0x0078 1686 #define ICH_FLASH_SSFSTS 0x0090 1687 #define ICH_FLASH_SSFCTL 0x0092 1688 #define ICH_FLASH_PREOP 0x0094 1689 #define ICH_FLASH_OPTYPE 0x0096 1690 #define ICH_FLASH_OPMENU 0x0098 1691 1692 #define ICH_FLASH_REG_MAPSIZE 0x00a0 1693 #define ICH_FLASH_SECTOR_SIZE 4096 1694 #define ICH_GFPREG_BASE_MASK 0x1fff 1695 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00ffffff 1696 1697 #define ICH_NVM_SIG_WORD 0x13 1698 #define ICH_NVM_SIG_MASK 0xc000 1699 #define ICH_NVM_VALID_SIG_MASK 0xc0 1700 #define ICH_NVM_SIG_VALUE 0x80 1701 1702 #define NVM_SIZE_MULTIPLIER 4096 /* multiplier for NVMS field */ 1703 #define WM_PCH_SPT_FLASHOFFSET 0xe000 /* offset of NVM access regs(PCH_SPT)*/ 1704 1705 /* for PCI express Capability registers */ 1706 #define WM_PCIE_DCSR2_16MS 0x00000005 1707 1708 /* SFF SFP ROM data */ 1709 #define SFF_SFP_ID_OFF 0x00 1710 #define SFF_SFP_ID_UNKNOWN 0x00 /* Unknown */ 1711 #define SFF_SFP_ID_SFF 0x02 /* Module soldered to motherboard */ 1712 #define SFF_SFP_ID_SFP 0x03 /* SFP transceiver */ 1713 1714 #define SFF_SFP_ETH_FLAGS_OFF 0x06 1715 #define SFF_SFP_ETH_FLAGS_1000SX 0x01 1716 #define SFF_SFP_ETH_FLAGS_1000LX 0x02 1717 #define SFF_SFP_ETH_FLAGS_1000CX 0x04 1718 #define SFF_SFP_ETH_FLAGS_1000T 0x08 1719 #define SFF_SFP_ETH_FLAGS_100LX 0x10 1720 #define SFF_SFP_ETH_FLAGS_100FX 0x20 1721 1722 /* I21[01] PHY related definitions */ 1723 #define GS40G_PAGE_SELECT 0x16 1724 #define GS40G_PAGE_SHIFT 16 1725 #define GS40G_OFFSET_MASK 0xffff 1726 #define GS40G_PHY_PLL_FREQ_PAGE 0xfc0000 1727 #define GS40G_PHY_PLL_FREQ_REG 0x000e 1728 #define GS40G_PHY_PLL_UNCONF 0xff 1729 1730 /* advanced TX descriptor for 82575 and newer */ 1731 typedef union nq_txdesc { 1732 struct { 1733 uint64_t nqtxd_addr; 1734 uint32_t nqtxd_cmdlen; 1735 uint32_t nqtxd_fields; 1736 } nqtx_data; 1737 struct { 1738 uint32_t nqtxc_vl_len; 1739 uint32_t nqtxc_sn; 1740 uint32_t nqtxc_cmd; 1741 uint32_t nqtxc_mssidx; 1742 } nqtx_ctx; 1743 } __packed nq_txdesc_t; 1744 1745 1746 /* Commands for nqtxd_cmdlen and nqtxc_cmd */ 1747 #define NQTX_CMD_EOP __BIT(24) /* end of packet */ 1748 #define NQTX_CMD_IFCS __BIT(25) /* insert FCS */ 1749 #define NQTX_CMD_RS __BIT(27) /* report status */ 1750 #define NQTX_CMD_DEXT __BIT(29) /* descriptor extension */ 1751 #define NQTX_CMD_VLE __BIT(30) /* VLAN enable */ 1752 #define NQTX_CMD_TSE __BIT(31) /* TCP segmentation enable */ 1753 1754 /* Descriptor types (if DEXT is set) */ 1755 #define NQTX_DTYP_C (2U << 20) /* context */ 1756 #define NQTX_DTYP_D (3U << 20) /* data */ 1757 1758 #define NQTXD_FIELDS_IDX_SHIFT 4 /* context index shift */ 1759 #define NQTXD_FIELDS_IDX_MASK 0xf 1760 #define NQTXD_FIELDS_PAYLEN_SHIFT 14 /* payload len shift */ 1761 #define NQTXD_FIELDS_PAYLEN_MASK 0x3ffff 1762 1763 #define NQTXD_FIELDS_IXSM __BIT(8) /* do IP checksum */ 1764 #define NQTXD_FIELDS_TUXSM __BIT(9) /* do TCP/UDP checksum */ 1765 1766 #define NQTXC_VLLEN_IPLEN_SHIFT 0 /* IP header len */ 1767 #define NQTXC_VLLEN_IPLEN_MASK 0x1ff 1768 #define NQTXC_VLLEN_MACLEN_SHIFT 9 /* MAC header len */ 1769 #define NQTXC_VLLEN_MACLEN_MASK 0x7f 1770 #define NQTXC_VLLEN_VLAN_SHIFT 16 /* vlan number */ 1771 #define NQTXC_VLLEN_VLAN_MASK 0xffff 1772 1773 #define NQTXC_CMD_MKRLOC_SHIFT 0 /* IP checksum offset */ 1774 #define NQTXC_CMD_MKRLOC_MASK 0x1ff 1775 #define NQTXC_CMD_SNAP __BIT(9) 1776 #define NQTXC_CMD_IPV_MASK __BIT(10) 1777 #define NQTXC_CMD_IP4 __SHIFTIN(1, NQTXC_CMD_IPV_MASK) 1778 #define NQTXC_CMD_IP6 __SHIFTIN(0, NQTXC_CMD_IPV_MASK) 1779 #define NQTXC_CMD_TP_MASK __BIT(11) 1780 #define NQTXC_CMD_TCP __SHIFTIN(1, NQTXC_CMD_TP_MASK) 1781 #define NQTXC_CMD_UDP __SHIFTIN(0, NQTXC_CMD_TP_MASK) 1782 #define NQTXC_MSSIDX_IDX_SHIFT 4 /* context index shift */ 1783 #define NQTXC_MSSIDX_IDX_MASK 0xf 1784 #define NQTXC_MSSIDX_L4LEN_SHIFT 8 /* L4 header len shift */ 1785 #define NQTXC_MSSIDX_L4LEN_MASK 0xff 1786 #define NQTXC_MSSIDX_MSS_SHIFT 16 /* MSS */ 1787 #define NQTXC_MSSIDX_MSS_MASK 0xffff 1788