1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/pc.h"
28 #include "hw/char/serial.h"
29 #include "hw/char/parallel.h"
30 #include "hw/hyperv/hv-balloon.h"
31 #include "hw/i386/fw_cfg.h"
32 #include "hw/i386/vmport.h"
33 #include "sysemu/cpus.h"
34 #include "hw/ide/ide-bus.h"
35 #include "hw/timer/hpet.h"
36 #include "hw/loader.h"
37 #include "hw/rtc/mc146818rtc.h"
38 #include "hw/intc/i8259.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/input/i8042.h"
41 #include "hw/audio/pcspk.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/xen.h"
44 #include "sysemu/reset.h"
45 #include "kvm/kvm_i386.h"
46 #include "hw/xen/xen.h"
47 #include "qapi/qmp/qlist.h"
48 #include "qemu/error-report.h"
49 #include "hw/acpi/cpu_hotplug.h"
50 #include "acpi-build.h"
51 #include "hw/mem/nvdimm.h"
52 #include "hw/cxl/cxl_host.h"
53 #include "hw/usb.h"
54 #include "hw/i386/intel_iommu.h"
55 #include "hw/net/ne2000-isa.h"
56 #include "hw/virtio/virtio-iommu.h"
57 #include "hw/virtio/virtio-md-pci.h"
58 #include "hw/i386/kvm/xen_overlay.h"
59 #include "hw/i386/kvm/xen_evtchn.h"
60 #include "hw/i386/kvm/xen_gnttab.h"
61 #include "hw/i386/kvm/xen_xenstore.h"
62 #include "hw/mem/memory-device.h"
63 #include "e820_memory_layout.h"
64 #include "trace.h"
65 #include CONFIG_DEVICES
66
67 #ifdef CONFIG_XEN_EMU
68 #include "hw/xen/xen-legacy-backend.h"
69 #include "hw/xen/xen-bus.h"
70 #endif
71
72 /*
73 * Helper for setting model-id for CPU models that changed model-id
74 * depending on QEMU versions up to QEMU 2.4.
75 */
76 #define PC_CPU_MODEL_IDS(v) \
77 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
78 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
79 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
80
81 GlobalProperty pc_compat_9_0[] = {
82 { TYPE_X86_CPU, "guest-phys-bits", "0" },
83 { "sev-guest", "legacy-vm-type", "true" },
84 { TYPE_X86_CPU, "legacy-multi-node", "on" },
85 };
86 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0);
87
88 GlobalProperty pc_compat_8_2[] = {};
89 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2);
90
91 GlobalProperty pc_compat_8_1[] = {};
92 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1);
93
94 GlobalProperty pc_compat_8_0[] = {
95 { "virtio-mem", "unplugged-inaccessible", "auto" },
96 };
97 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0);
98
99 GlobalProperty pc_compat_7_2[] = {
100 { "ICH9-LPC", "noreboot", "true" },
101 };
102 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2);
103
104 GlobalProperty pc_compat_7_1[] = {};
105 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
106
107 GlobalProperty pc_compat_7_0[] = {};
108 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
109
110 GlobalProperty pc_compat_6_2[] = {
111 { "virtio-mem", "unplugged-inaccessible", "off" },
112 };
113 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
114
115 GlobalProperty pc_compat_6_1[] = {
116 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
117 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
118 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
119 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
120 };
121 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
122
123 GlobalProperty pc_compat_6_0[] = {
124 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
125 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
126 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
127 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
128 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
129 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
130 };
131 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
132
133 GlobalProperty pc_compat_5_2[] = {
134 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
135 };
136 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
137
138 GlobalProperty pc_compat_5_1[] = {
139 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
140 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
141 };
142 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
143
144 GlobalProperty pc_compat_5_0[] = {
145 };
146 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
147
148 GlobalProperty pc_compat_4_2[] = {
149 { "mch", "smbase-smram", "off" },
150 };
151 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
152
153 GlobalProperty pc_compat_4_1[] = {};
154 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
155
156 GlobalProperty pc_compat_4_0[] = {};
157 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
158
159 GlobalProperty pc_compat_3_1[] = {
160 { "intel-iommu", "dma-drain", "off" },
161 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
162 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
163 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
164 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
165 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
166 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
167 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
168 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
169 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
170 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
171 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
172 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
173 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
174 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
175 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
176 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
177 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
178 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
179 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
180 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
181 };
182 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
183
184 GlobalProperty pc_compat_3_0[] = {
185 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
186 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
187 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
188 };
189 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
190
191 GlobalProperty pc_compat_2_12[] = {
192 { TYPE_X86_CPU, "legacy-cache", "on" },
193 { TYPE_X86_CPU, "topoext", "off" },
194 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
195 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
196 };
197 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
198
199 GlobalProperty pc_compat_2_11[] = {
200 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
201 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
202 };
203 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
204
205 GlobalProperty pc_compat_2_10[] = {
206 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
207 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
208 { "q35-pcihost", "x-pci-hole64-fix", "off" },
209 };
210 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
211
212 GlobalProperty pc_compat_2_9[] = {
213 { "mch", "extended-tseg-mbytes", "0" },
214 };
215 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
216
217 GlobalProperty pc_compat_2_8[] = {
218 { TYPE_X86_CPU, "tcg-cpuid", "off" },
219 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
220 { "ICH9-LPC", "x-smi-broadcast", "off" },
221 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
222 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
223 };
224 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
225
226 GlobalProperty pc_compat_2_7[] = {
227 { TYPE_X86_CPU, "l3-cache", "off" },
228 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
229 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
230 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
231 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
232 { "isa-pcspk", "migrate", "off" },
233 };
234 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
235
236 GlobalProperty pc_compat_2_6[] = {
237 { TYPE_X86_CPU, "cpuid-0xb", "off" },
238 { "vmxnet3", "romfile", "" },
239 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
240 { "apic-common", "legacy-instance-id", "on", }
241 };
242 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
243
244 GlobalProperty pc_compat_2_5[] = {};
245 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
246
247 GlobalProperty pc_compat_2_4[] = {
248 PC_CPU_MODEL_IDS("2.4.0")
249 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
250 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
251 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
252 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
253 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
254 { TYPE_X86_CPU, "check", "off" },
255 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
256 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
257 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
258 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
259 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
260 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
261 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
262 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
263 };
264 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
265
266 GlobalProperty pc_compat_2_3[] = {
267 PC_CPU_MODEL_IDS("2.3.0")
268 { TYPE_X86_CPU, "arat", "off" },
269 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
270 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
271 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
272 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
273 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
274 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
275 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
276 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
277 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
278 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
279 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
280 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
281 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
282 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
283 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
284 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
285 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
286 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
287 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
288 };
289 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
290
291 GlobalProperty pc_compat_2_2[] = {
292 PC_CPU_MODEL_IDS("2.2.0")
293 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
294 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
295 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
296 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
297 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
298 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
299 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
300 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
301 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
302 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
303 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
304 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
305 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
306 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
307 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
308 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
309 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
310 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
311 };
312 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
313
314 GlobalProperty pc_compat_2_1[] = {
315 PC_CPU_MODEL_IDS("2.1.0")
316 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
317 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
318 };
319 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
320
321 GlobalProperty pc_compat_2_0[] = {
322 PC_CPU_MODEL_IDS("2.0.0")
323 { "virtio-scsi-pci", "any_layout", "off" },
324 { "PIIX4_PM", "memory-hotplug-support", "off" },
325 { "apic", "version", "0x11" },
326 { "nec-usb-xhci", "superspeed-ports-first", "off" },
327 { "nec-usb-xhci", "force-pcie-endcap", "on" },
328 { "pci-serial", "prog_if", "0" },
329 { "pci-serial-2x", "prog_if", "0" },
330 { "pci-serial-4x", "prog_if", "0" },
331 { "virtio-net-pci", "guest_announce", "off" },
332 { "ICH9-LPC", "memory-hotplug-support", "off" },
333 };
334 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
335
pc_gsi_create(qemu_irq ** irqs,bool pci_enabled)336 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
337 {
338 GSIState *s;
339
340 s = g_new0(GSIState, 1);
341 if (kvm_ioapic_in_kernel()) {
342 kvm_pc_setup_irq_routing(pci_enabled);
343 }
344 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
345
346 return s;
347 }
348
ioport80_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)349 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
350 unsigned size)
351 {
352 }
353
ioport80_read(void * opaque,hwaddr addr,unsigned size)354 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
355 {
356 return 0xffffffffffffffffULL;
357 }
358
359 /* MS-DOS compatibility mode FPU exception support */
ioportF0_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)360 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
361 unsigned size)
362 {
363 if (tcg_enabled()) {
364 cpu_set_ignne();
365 }
366 }
367
ioportF0_read(void * opaque,hwaddr addr,unsigned size)368 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
369 {
370 return 0xffffffffffffffffULL;
371 }
372
373 /* PC cmos mappings */
374
375 #define REG_EQUIPMENT_BYTE 0x14
376
cmos_init_hd(MC146818RtcState * s,int type_ofs,int info_ofs,int16_t cylinders,int8_t heads,int8_t sectors)377 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs,
378 int16_t cylinders, int8_t heads, int8_t sectors)
379 {
380 mc146818rtc_set_cmos_data(s, type_ofs, 47);
381 mc146818rtc_set_cmos_data(s, info_ofs, cylinders);
382 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8);
383 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads);
384 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff);
385 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff);
386 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
387 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders);
388 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8);
389 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors);
390 }
391
392 /* convert boot_device letter to something recognizable by the bios */
boot_device2nibble(char boot_device)393 static int boot_device2nibble(char boot_device)
394 {
395 switch(boot_device) {
396 case 'a':
397 case 'b':
398 return 0x01; /* floppy boot */
399 case 'c':
400 return 0x02; /* hard drive boot */
401 case 'd':
402 return 0x03; /* CD-ROM boot */
403 case 'n':
404 return 0x04; /* Network boot */
405 }
406 return 0;
407 }
408
set_boot_dev(PCMachineState * pcms,MC146818RtcState * s,const char * boot_device,Error ** errp)409 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s,
410 const char *boot_device, Error **errp)
411 {
412 #define PC_MAX_BOOT_DEVICES 3
413 int nbds, bds[3] = { 0, };
414 int i;
415
416 nbds = strlen(boot_device);
417 if (nbds > PC_MAX_BOOT_DEVICES) {
418 error_setg(errp, "Too many boot devices for PC");
419 return;
420 }
421 for (i = 0; i < nbds; i++) {
422 bds[i] = boot_device2nibble(boot_device[i]);
423 if (bds[i] == 0) {
424 error_setg(errp, "Invalid boot device for PC: '%c'",
425 boot_device[i]);
426 return;
427 }
428 }
429 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]);
430 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk);
431 }
432
pc_boot_set(void * opaque,const char * boot_device,Error ** errp)433 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
434 {
435 PCMachineState *pcms = opaque;
436 X86MachineState *x86ms = X86_MACHINE(pcms);
437
438 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp);
439 }
440
pc_cmos_init_floppy(MC146818RtcState * rtc_state,ISADevice * floppy)441 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy)
442 {
443 int val, nb;
444 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
445 FLOPPY_DRIVE_TYPE_NONE };
446
447 #ifdef CONFIG_FDC_ISA
448 /* floppy type */
449 if (floppy) {
450 for (int i = 0; i < 2; i++) {
451 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
452 }
453 }
454 #endif
455
456 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
457 cmos_get_fd_drive_type(fd_type[1]);
458 mc146818rtc_set_cmos_data(rtc_state, 0x10, val);
459
460 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE);
461 nb = 0;
462 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
463 nb++;
464 }
465 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
466 nb++;
467 }
468 switch (nb) {
469 case 0:
470 break;
471 case 1:
472 val |= 0x01; /* 1 drive, ready for boot */
473 break;
474 case 2:
475 val |= 0x41; /* 2 drives, ready for boot */
476 break;
477 }
478 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val);
479 }
480
481 typedef struct check_fdc_state {
482 ISADevice *floppy;
483 bool multiple;
484 } CheckFdcState;
485
check_fdc(Object * obj,void * opaque)486 static int check_fdc(Object *obj, void *opaque)
487 {
488 CheckFdcState *state = opaque;
489 Object *fdc;
490 uint32_t iobase;
491 Error *local_err = NULL;
492
493 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
494 if (!fdc) {
495 return 0;
496 }
497
498 iobase = object_property_get_uint(obj, "iobase", &local_err);
499 if (local_err || iobase != 0x3f0) {
500 error_free(local_err);
501 return 0;
502 }
503
504 if (state->floppy) {
505 state->multiple = true;
506 } else {
507 state->floppy = ISA_DEVICE(obj);
508 }
509 return 0;
510 }
511
512 static const char * const fdc_container_path[] = {
513 "/unattached", "/peripheral", "/peripheral-anon"
514 };
515
516 /*
517 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
518 * and ACPI objects.
519 */
pc_find_fdc0(void)520 static ISADevice *pc_find_fdc0(void)
521 {
522 int i;
523 Object *container;
524 CheckFdcState state = { 0 };
525
526 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
527 container = container_get(qdev_get_machine(), fdc_container_path[i]);
528 object_child_foreach(container, check_fdc, &state);
529 }
530
531 if (state.multiple) {
532 warn_report("multiple floppy disk controllers with "
533 "iobase=0x3f0 have been found");
534 error_printf("the one being picked for CMOS setup might not reflect "
535 "your intent");
536 }
537
538 return state.floppy;
539 }
540
pc_cmos_init_late(PCMachineState * pcms)541 static void pc_cmos_init_late(PCMachineState *pcms)
542 {
543 X86MachineState *x86ms = X86_MACHINE(pcms);
544 MC146818RtcState *s = MC146818_RTC(x86ms->rtc);
545 int16_t cylinders;
546 int8_t heads, sectors;
547 int val;
548 int i, trans;
549
550 val = 0;
551 if (pcms->idebus[0] &&
552 ide_get_geometry(pcms->idebus[0], 0,
553 &cylinders, &heads, §ors) >= 0) {
554 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
555 val |= 0xf0;
556 }
557 if (pcms->idebus[0] &&
558 ide_get_geometry(pcms->idebus[0], 1,
559 &cylinders, &heads, §ors) >= 0) {
560 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
561 val |= 0x0f;
562 }
563 mc146818rtc_set_cmos_data(s, 0x12, val);
564
565 val = 0;
566 for (i = 0; i < 4; i++) {
567 /* NOTE: ide_get_geometry() returns the physical
568 geometry. It is always such that: 1 <= sects <= 63, 1
569 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
570 geometry can be different if a translation is done. */
571 BusState *idebus = pcms->idebus[i / 2];
572 if (idebus &&
573 ide_get_geometry(idebus, i % 2,
574 &cylinders, &heads, §ors) >= 0) {
575 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1;
576 assert((trans & ~3) == 0);
577 val |= trans << (i * 2);
578 }
579 }
580 mc146818rtc_set_cmos_data(s, 0x39, val);
581
582 pc_cmos_init_floppy(s, pc_find_fdc0());
583
584 /* various important CMOS locations needed by PC/Bochs bios */
585
586 /* memory size */
587 /* base memory (first MiB) */
588 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
589 mc146818rtc_set_cmos_data(s, 0x15, val);
590 mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
591 /* extended memory (next 64MiB) */
592 if (x86ms->below_4g_mem_size > 1 * MiB) {
593 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
594 } else {
595 val = 0;
596 }
597 if (val > 65535)
598 val = 65535;
599 mc146818rtc_set_cmos_data(s, 0x17, val);
600 mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
601 mc146818rtc_set_cmos_data(s, 0x30, val);
602 mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
603 /* memory between 16MiB and 4GiB */
604 if (x86ms->below_4g_mem_size > 16 * MiB) {
605 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
606 } else {
607 val = 0;
608 }
609 if (val > 65535)
610 val = 65535;
611 mc146818rtc_set_cmos_data(s, 0x34, val);
612 mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
613 /* memory above 4GiB */
614 val = x86ms->above_4g_mem_size / 65536;
615 mc146818rtc_set_cmos_data(s, 0x5b, val);
616 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
617 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
618
619 val = 0;
620 val |= 0x02; /* FPU is there */
621 val |= 0x04; /* PS/2 mouse installed */
622 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val);
623 }
624
handle_a20_line_change(void * opaque,int irq,int level)625 static void handle_a20_line_change(void *opaque, int irq, int level)
626 {
627 X86CPU *cpu = opaque;
628
629 /* XXX: send to all CPUs ? */
630 /* XXX: add logic to handle multiple A20 line sources */
631 x86_cpu_set_a20(cpu, level);
632 }
633
634 #define NE2000_NB_MAX 6
635
636 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
637 0x280, 0x380 };
638 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
639
pc_init_ne2k_isa(ISABus * bus,NICInfo * nd,Error ** errp)640 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp)
641 {
642 static int nb_ne2k = 0;
643
644 if (nb_ne2k == NE2000_NB_MAX) {
645 error_setg(errp,
646 "maximum number of ISA NE2000 devices exceeded");
647 return false;
648 }
649 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
650 ne2000_irq[nb_ne2k], nd);
651 nb_ne2k++;
652 return true;
653 }
654
pc_acpi_smi_interrupt(void * opaque,int irq,int level)655 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
656 {
657 X86CPU *cpu = opaque;
658
659 if (level) {
660 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
661 }
662 }
663
664 static
pc_machine_done(Notifier * notifier,void * data)665 void pc_machine_done(Notifier *notifier, void *data)
666 {
667 PCMachineState *pcms = container_of(notifier,
668 PCMachineState, machine_done);
669 X86MachineState *x86ms = X86_MACHINE(pcms);
670
671 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state,
672 &error_fatal);
673
674 if (pcms->cxl_devices_state.is_enabled) {
675 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
676 }
677
678 /* set the number of CPUs */
679 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
680
681 fw_cfg_add_extra_pci_roots(pcms->pcibus, x86ms->fw_cfg);
682
683 acpi_setup();
684 if (x86ms->fw_cfg) {
685 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type);
686 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
687 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
688 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
689 }
690
691 pc_cmos_init_late(pcms);
692 }
693
694 /* setup pci memory address space mapping into system address space */
pc_pci_as_mapping_init(MemoryRegion * system_memory,MemoryRegion * pci_address_space)695 void pc_pci_as_mapping_init(MemoryRegion *system_memory,
696 MemoryRegion *pci_address_space)
697 {
698 /* Set to lower priority than RAM */
699 memory_region_add_subregion_overlap(system_memory, 0x0,
700 pci_address_space, -1);
701 }
702
xen_load_linux(PCMachineState * pcms)703 void xen_load_linux(PCMachineState *pcms)
704 {
705 int i;
706 FWCfgState *fw_cfg;
707 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
708 X86MachineState *x86ms = X86_MACHINE(pcms);
709
710 assert(MACHINE(pcms)->kernel_filename != NULL);
711
712 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
713 &address_space_memory);
714 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
715 rom_set_fw(fw_cfg);
716
717 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
718 pcmc->pvh_enabled);
719 for (i = 0; i < nb_option_roms; i++) {
720 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
721 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
722 !strcmp(option_rom[i].name, "pvh.bin") ||
723 !strcmp(option_rom[i].name, "multiboot.bin") ||
724 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
725 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
726 }
727 x86ms->fw_cfg = fw_cfg;
728 }
729
730 #define PC_ROM_MIN_VGA 0xc0000
731 #define PC_ROM_MIN_OPTION 0xc8000
732 #define PC_ROM_MAX 0xe0000
733 #define PC_ROM_ALIGN 0x800
734 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
735
pc_above_4g_end(PCMachineState * pcms)736 static hwaddr pc_above_4g_end(PCMachineState *pcms)
737 {
738 X86MachineState *x86ms = X86_MACHINE(pcms);
739
740 if (pcms->sgx_epc.size != 0) {
741 return sgx_epc_above_4g_end(&pcms->sgx_epc);
742 }
743
744 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
745 }
746
pc_get_device_memory_range(PCMachineState * pcms,hwaddr * base,ram_addr_t * device_mem_size)747 static void pc_get_device_memory_range(PCMachineState *pcms,
748 hwaddr *base,
749 ram_addr_t *device_mem_size)
750 {
751 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
752 MachineState *machine = MACHINE(pcms);
753 ram_addr_t size;
754 hwaddr addr;
755
756 size = machine->maxram_size - machine->ram_size;
757 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
758
759 if (pcmc->enforce_aligned_dimm) {
760 /* size device region assuming 1G page max alignment per slot */
761 size += (1 * GiB) * machine->ram_slots;
762 }
763
764 *base = addr;
765 *device_mem_size = size;
766 }
767
pc_get_cxl_range_start(PCMachineState * pcms)768 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
769 {
770 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
771 MachineState *ms = MACHINE(pcms);
772 hwaddr cxl_base;
773 ram_addr_t size;
774
775 if (pcmc->has_reserved_memory &&
776 (ms->ram_size < ms->maxram_size)) {
777 pc_get_device_memory_range(pcms, &cxl_base, &size);
778 cxl_base += size;
779 } else {
780 cxl_base = pc_above_4g_end(pcms);
781 }
782
783 return cxl_base;
784 }
785
pc_get_cxl_range_end(PCMachineState * pcms)786 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
787 {
788 uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
789
790 if (pcms->cxl_devices_state.fixed_windows) {
791 GList *it;
792
793 start = ROUND_UP(start, 256 * MiB);
794 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
795 CXLFixedWindow *fw = it->data;
796 start += fw->size;
797 }
798 }
799
800 return start;
801 }
802
pc_max_used_gpa(PCMachineState * pcms,uint64_t pci_hole64_size)803 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
804 {
805 X86CPU *cpu = X86_CPU(first_cpu);
806 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
807 MachineState *ms = MACHINE(pcms);
808
809 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
810 /* 64-bit systems */
811 return pc_pci_hole64_start() + pci_hole64_size - 1;
812 }
813
814 /* 32-bit systems */
815 if (pcmc->broken_32bit_mem_addr_check) {
816 /* old value for compatibility reasons */
817 return ((hwaddr)1 << cpu->phys_bits) - 1;
818 }
819
820 /*
821 * 32-bit systems don't have hole64 but they might have a region for
822 * memory devices. Even if additional hotplugged memory devices might
823 * not be usable by most guest OSes, we need to still consider them for
824 * calculating the highest possible GPA so that we can properly report
825 * if someone configures them on a CPU that cannot possibly address them.
826 */
827 if (pcmc->has_reserved_memory &&
828 (ms->ram_size < ms->maxram_size)) {
829 hwaddr devmem_start;
830 ram_addr_t devmem_size;
831
832 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size);
833 devmem_start += devmem_size;
834 return devmem_start - 1;
835 }
836
837 /* configuration without any memory hotplug */
838 return pc_above_4g_end(pcms) - 1;
839 }
840
841 /*
842 * AMD systems with an IOMMU have an additional hole close to the
843 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
844 * on kernel version, VFIO may or may not let you DMA map those ranges.
845 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
846 * with certain memory sizes. It's also wrong to use those IOVA ranges
847 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
848 * The ranges reserved for Hyper-Transport are:
849 *
850 * FD_0000_0000h - FF_FFFF_FFFFh
851 *
852 * The ranges represent the following:
853 *
854 * Base Address Top Address Use
855 *
856 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
857 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
858 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
859 * FD_F910_0000h FD_F91F_FFFFh System Management
860 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
861 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
862 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
863 * FD_FE00_0000h FD_FFFF_FFFFh Configuration
864 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
865 * FE_2000_0000h FF_FFFF_FFFFh Reserved
866 *
867 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
868 * Table 3: Special Address Controls (GPA) for more information.
869 */
870 #define AMD_HT_START 0xfd00000000UL
871 #define AMD_HT_END 0xffffffffffUL
872 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
873 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
874
pc_memory_init(PCMachineState * pcms,MemoryRegion * system_memory,MemoryRegion * rom_memory,uint64_t pci_hole64_size)875 void pc_memory_init(PCMachineState *pcms,
876 MemoryRegion *system_memory,
877 MemoryRegion *rom_memory,
878 uint64_t pci_hole64_size)
879 {
880 int linux_boot, i;
881 MemoryRegion *option_rom_mr;
882 MemoryRegion *ram_below_4g, *ram_above_4g;
883 FWCfgState *fw_cfg;
884 MachineState *machine = MACHINE(pcms);
885 MachineClass *mc = MACHINE_GET_CLASS(machine);
886 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
887 X86MachineState *x86ms = X86_MACHINE(pcms);
888 hwaddr maxphysaddr, maxusedaddr;
889 hwaddr cxl_base, cxl_resv_end = 0;
890 X86CPU *cpu = X86_CPU(first_cpu);
891
892 assert(machine->ram_size == x86ms->below_4g_mem_size +
893 x86ms->above_4g_mem_size);
894
895 linux_boot = (machine->kernel_filename != NULL);
896
897 /*
898 * The HyperTransport range close to the 1T boundary is unique to AMD
899 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
900 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
901 * older machine types (<= 7.0) for compatibility purposes.
902 */
903 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
904 /* Bail out if max possible address does not cross HT range */
905 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
906 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
907 }
908
909 /*
910 * Advertise the HT region if address space covers the reserved
911 * region or if we relocate.
912 */
913 if (cpu->phys_bits >= 40) {
914 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
915 }
916 }
917
918 /*
919 * phys-bits is required to be appropriately configured
920 * to make sure max used GPA is reachable.
921 */
922 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
923 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
924 if (maxphysaddr < maxusedaddr) {
925 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
926 " phys-bits too low (%u)",
927 maxphysaddr, maxusedaddr, cpu->phys_bits);
928 exit(EXIT_FAILURE);
929 }
930
931 /*
932 * Split single memory region and use aliases to address portions of it,
933 * done for backwards compatibility with older qemus.
934 */
935 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
936 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
937 0, x86ms->below_4g_mem_size);
938 memory_region_add_subregion(system_memory, 0, ram_below_4g);
939 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
940 if (x86ms->above_4g_mem_size > 0) {
941 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
942 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
943 machine->ram,
944 x86ms->below_4g_mem_size,
945 x86ms->above_4g_mem_size);
946 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
947 ram_above_4g);
948 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
949 E820_RAM);
950 }
951
952 if (pcms->sgx_epc.size != 0) {
953 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
954 }
955
956 if (!pcmc->has_reserved_memory &&
957 (machine->ram_slots ||
958 (machine->maxram_size > machine->ram_size))) {
959
960 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
961 mc->name);
962 exit(EXIT_FAILURE);
963 }
964
965 /* initialize device memory address space */
966 if (pcmc->has_reserved_memory &&
967 (machine->ram_size < machine->maxram_size)) {
968 ram_addr_t device_mem_size;
969 hwaddr device_mem_base;
970
971 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
972 error_report("unsupported amount of memory slots: %"PRIu64,
973 machine->ram_slots);
974 exit(EXIT_FAILURE);
975 }
976
977 if (QEMU_ALIGN_UP(machine->maxram_size,
978 TARGET_PAGE_SIZE) != machine->maxram_size) {
979 error_report("maximum memory size must by aligned to multiple of "
980 "%d bytes", TARGET_PAGE_SIZE);
981 exit(EXIT_FAILURE);
982 }
983
984 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size);
985
986 if (device_mem_base + device_mem_size < device_mem_size) {
987 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
988 machine->maxram_size);
989 exit(EXIT_FAILURE);
990 }
991 machine_memory_devices_init(machine, device_mem_base, device_mem_size);
992 }
993
994 if (pcms->cxl_devices_state.is_enabled) {
995 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
996 hwaddr cxl_size = MiB;
997
998 cxl_base = pc_get_cxl_range_start(pcms);
999 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
1000 memory_region_add_subregion(system_memory, cxl_base, mr);
1001 cxl_resv_end = cxl_base + cxl_size;
1002 if (pcms->cxl_devices_state.fixed_windows) {
1003 hwaddr cxl_fmw_base;
1004 GList *it;
1005
1006 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
1007 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
1008 CXLFixedWindow *fw = it->data;
1009
1010 fw->base = cxl_fmw_base;
1011 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
1012 "cxl-fixed-memory-region", fw->size);
1013 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
1014 cxl_fmw_base += fw->size;
1015 cxl_resv_end = cxl_fmw_base;
1016 }
1017 }
1018 }
1019
1020 /* Initialize PC system firmware */
1021 pc_system_firmware_init(pcms, rom_memory);
1022
1023 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1024 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1025 &error_fatal);
1026 if (pcmc->pci_enabled) {
1027 memory_region_set_readonly(option_rom_mr, true);
1028 }
1029 memory_region_add_subregion_overlap(rom_memory,
1030 PC_ROM_MIN_VGA,
1031 option_rom_mr,
1032 1);
1033
1034 fw_cfg = fw_cfg_arch_create(machine,
1035 x86ms->boot_cpus, x86ms->apic_id_limit);
1036
1037 rom_set_fw(fw_cfg);
1038
1039 if (machine->device_memory) {
1040 uint64_t *val = g_malloc(sizeof(*val));
1041 uint64_t res_mem_end = machine->device_memory->base;
1042
1043 if (!pcmc->broken_reserved_end) {
1044 res_mem_end += memory_region_size(&machine->device_memory->mr);
1045 }
1046
1047 if (pcms->cxl_devices_state.is_enabled) {
1048 res_mem_end = cxl_resv_end;
1049 }
1050 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1051 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1052 }
1053
1054 if (linux_boot) {
1055 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1056 pcmc->pvh_enabled);
1057 }
1058
1059 for (i = 0; i < nb_option_roms; i++) {
1060 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1061 }
1062 x86ms->fw_cfg = fw_cfg;
1063
1064 /* Init default IOAPIC address space */
1065 x86ms->ioapic_as = &address_space_memory;
1066
1067 /* Init ACPI memory hotplug IO base address */
1068 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1069 }
1070
1071 /*
1072 * The 64bit pci hole starts after "above 4G RAM" and
1073 * potentially the space reserved for memory hotplug.
1074 */
pc_pci_hole64_start(void)1075 uint64_t pc_pci_hole64_start(void)
1076 {
1077 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1078 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1079 MachineState *ms = MACHINE(pcms);
1080 uint64_t hole64_start = 0;
1081 ram_addr_t size = 0;
1082
1083 if (pcms->cxl_devices_state.is_enabled) {
1084 hole64_start = pc_get_cxl_range_end(pcms);
1085 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1086 pc_get_device_memory_range(pcms, &hole64_start, &size);
1087 if (!pcmc->broken_reserved_end) {
1088 hole64_start += size;
1089 }
1090 } else {
1091 hole64_start = pc_above_4g_end(pcms);
1092 }
1093
1094 return ROUND_UP(hole64_start, 1 * GiB);
1095 }
1096
pc_vga_init(ISABus * isa_bus,PCIBus * pci_bus)1097 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1098 {
1099 DeviceState *dev = NULL;
1100
1101 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1102 if (pci_bus) {
1103 PCIDevice *pcidev = pci_vga_init(pci_bus);
1104 dev = pcidev ? &pcidev->qdev : NULL;
1105 } else if (isa_bus) {
1106 ISADevice *isadev = isa_vga_init(isa_bus);
1107 dev = isadev ? DEVICE(isadev) : NULL;
1108 }
1109 rom_reset_order_override();
1110 return dev;
1111 }
1112
1113 static const MemoryRegionOps ioport80_io_ops = {
1114 .write = ioport80_write,
1115 .read = ioport80_read,
1116 .endianness = DEVICE_NATIVE_ENDIAN,
1117 .impl = {
1118 .min_access_size = 1,
1119 .max_access_size = 1,
1120 },
1121 };
1122
1123 static const MemoryRegionOps ioportF0_io_ops = {
1124 .write = ioportF0_write,
1125 .read = ioportF0_read,
1126 .endianness = DEVICE_NATIVE_ENDIAN,
1127 .impl = {
1128 .min_access_size = 1,
1129 .max_access_size = 1,
1130 },
1131 };
1132
pc_superio_init(ISABus * isa_bus,bool create_fdctrl,bool create_i8042,bool no_vmport)1133 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1134 bool create_i8042, bool no_vmport)
1135 {
1136 int i;
1137 DriveInfo *fd[MAX_FD];
1138 qemu_irq *a20_line;
1139 ISADevice *i8042, *port92, *vmmouse;
1140
1141 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1142 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1143
1144 for (i = 0; i < MAX_FD; i++) {
1145 fd[i] = drive_get(IF_FLOPPY, 0, i);
1146 create_fdctrl |= !!fd[i];
1147 }
1148 if (create_fdctrl) {
1149 #ifdef CONFIG_FDC_ISA
1150 ISADevice *fdc = isa_new(TYPE_ISA_FDC);
1151 if (fdc) {
1152 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1153 isa_fdc_init_drives(fdc, fd);
1154 }
1155 #endif
1156 }
1157
1158 if (!create_i8042) {
1159 return;
1160 }
1161
1162 i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1163 if (!no_vmport) {
1164 isa_create_simple(isa_bus, TYPE_VMPORT);
1165 vmmouse = isa_try_new("vmmouse");
1166 } else {
1167 vmmouse = NULL;
1168 }
1169 if (vmmouse) {
1170 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1171 &error_abort);
1172 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1173 }
1174 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1175
1176 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1177 qdev_connect_gpio_out_named(DEVICE(i8042),
1178 I8042_A20_LINE, 0, a20_line[0]);
1179 qdev_connect_gpio_out_named(DEVICE(port92),
1180 PORT92_A20_LINE, 0, a20_line[1]);
1181 g_free(a20_line);
1182 }
1183
pc_basic_device_init(struct PCMachineState * pcms,ISABus * isa_bus,qemu_irq * gsi,ISADevice * rtc_state,bool create_fdctrl,uint32_t hpet_irqs)1184 void pc_basic_device_init(struct PCMachineState *pcms,
1185 ISABus *isa_bus, qemu_irq *gsi,
1186 ISADevice *rtc_state,
1187 bool create_fdctrl,
1188 uint32_t hpet_irqs)
1189 {
1190 int i;
1191 DeviceState *hpet = NULL;
1192 int pit_isa_irq = 0;
1193 qemu_irq pit_alt_irq = NULL;
1194 ISADevice *pit = NULL;
1195 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1196 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1197 X86MachineState *x86ms = X86_MACHINE(pcms);
1198
1199 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1200 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1201
1202 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1203 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1204
1205 /*
1206 * Check if an HPET shall be created.
1207 */
1208 if (pcms->hpet_enabled) {
1209 qemu_irq rtc_irq;
1210
1211 hpet = qdev_try_new(TYPE_HPET);
1212 if (!hpet) {
1213 error_report("couldn't create HPET device");
1214 exit(1);
1215 }
1216 /*
1217 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*,
1218 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set
1219 * the property, use whatever mask they specified.
1220 */
1221 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1222 HPET_INTCAP, NULL);
1223 if (!compat) {
1224 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1225 }
1226 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1227 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1228
1229 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1230 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1231 }
1232 pit_isa_irq = -1;
1233 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1234 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1235
1236 /* overwrite connection created by south bridge */
1237 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq);
1238 }
1239
1240 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state),
1241 "date");
1242
1243 #ifdef CONFIG_XEN_EMU
1244 if (xen_mode == XEN_EMULATE) {
1245 xen_overlay_create();
1246 xen_evtchn_create(IOAPIC_NUM_PINS, gsi);
1247 xen_gnttab_create();
1248 xen_xenstore_create();
1249 if (pcms->pcibus) {
1250 pci_create_simple(pcms->pcibus, -1, "xen-platform");
1251 }
1252 xen_bus_init();
1253 }
1254 #endif
1255
1256 qemu_register_boot_set(pc_boot_set, pcms);
1257 set_boot_dev(pcms, MC146818_RTC(rtc_state),
1258 MACHINE(pcms)->boot_config.order, &error_fatal);
1259
1260 if (!xen_enabled() &&
1261 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1262 if (kvm_pit_in_kernel()) {
1263 pit = kvm_pit_init(isa_bus, 0x40);
1264 } else {
1265 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1266 }
1267 if (hpet) {
1268 /* connect PIT to output control line of the HPET */
1269 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1270 }
1271 object_property_set_link(OBJECT(pcms->pcspk), "pit",
1272 OBJECT(pit), &error_fatal);
1273 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal);
1274 }
1275
1276 /* Super I/O */
1277 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1278 pcms->vmport != ON_OFF_AUTO_ON);
1279 }
1280
pc_nic_init(PCMachineClass * pcmc,ISABus * isa_bus,PCIBus * pci_bus)1281 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1282 {
1283 MachineClass *mc = MACHINE_CLASS(pcmc);
1284 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000);
1285 NICInfo *nd;
1286
1287 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1288
1289 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) {
1290 pc_init_ne2k_isa(isa_bus, nd, &error_fatal);
1291 }
1292
1293 /* Anything remaining should be a PCI NIC */
1294 pci_init_nic_devices(pci_bus, mc->default_nic);
1295
1296 rom_reset_order_override();
1297 }
1298
pc_i8259_create(ISABus * isa_bus,qemu_irq * i8259_irqs)1299 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1300 {
1301 qemu_irq *i8259;
1302
1303 if (kvm_pic_in_kernel()) {
1304 i8259 = kvm_i8259_init(isa_bus);
1305 } else if (xen_enabled()) {
1306 i8259 = xen_interrupt_controller_init();
1307 } else {
1308 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1309 }
1310
1311 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1312 i8259_irqs[i] = i8259[i];
1313 }
1314
1315 g_free(i8259);
1316 }
1317
pc_memory_pre_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1318 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1319 Error **errp)
1320 {
1321 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1322 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1323 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1324 const MachineState *ms = MACHINE(hotplug_dev);
1325 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1326 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1327 Error *local_err = NULL;
1328
1329 /*
1330 * When "acpi=off" is used with the Q35 machine type, no ACPI is built,
1331 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1332 * addition to cover this case.
1333 */
1334 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1335 error_setg(errp,
1336 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1337 return;
1338 }
1339
1340 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1341 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1342 return;
1343 }
1344
1345 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1346 if (local_err) {
1347 error_propagate(errp, local_err);
1348 return;
1349 }
1350
1351 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1352 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1353 }
1354
pc_memory_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1355 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1356 DeviceState *dev, Error **errp)
1357 {
1358 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1359 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1360 MachineState *ms = MACHINE(hotplug_dev);
1361 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1362
1363 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1364
1365 if (is_nvdimm) {
1366 nvdimm_plug(ms->nvdimms_state);
1367 }
1368
1369 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1370 }
1371
pc_memory_unplug_request(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1372 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1373 DeviceState *dev, Error **errp)
1374 {
1375 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1376
1377 /*
1378 * When "acpi=off" is used with the Q35 machine type, no ACPI is built,
1379 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1380 * addition to cover this case.
1381 */
1382 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1383 error_setg(errp,
1384 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1385 return;
1386 }
1387
1388 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1389 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1390 return;
1391 }
1392
1393 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1394 errp);
1395 }
1396
pc_memory_unplug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1397 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1398 DeviceState *dev, Error **errp)
1399 {
1400 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1401 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1402 Error *local_err = NULL;
1403
1404 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1405 if (local_err) {
1406 goto out;
1407 }
1408
1409 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1410 qdev_unrealize(dev);
1411 out:
1412 error_propagate(errp, local_err);
1413 }
1414
pc_hv_balloon_pre_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1415 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev,
1416 DeviceState *dev, Error **errp)
1417 {
1418 /* The vmbus handler has no hotplug handler; we should never end up here. */
1419 g_assert(!dev->hotplugged);
1420 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1421 errp);
1422 }
1423
pc_hv_balloon_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1424 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev,
1425 DeviceState *dev, Error **errp)
1426 {
1427 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1428 }
1429
pc_machine_device_pre_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1430 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1431 DeviceState *dev, Error **errp)
1432 {
1433 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1434 pc_memory_pre_plug(hotplug_dev, dev, errp);
1435 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1436 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1437 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1438 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1439 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1440 /* Declare the APIC range as the reserved MSI region */
1441 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1442 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1443 QList *reserved_regions = qlist_new();
1444
1445 qlist_append_str(reserved_regions, resv_prop_str);
1446 qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
1447
1448 g_free(resv_prop_str);
1449 }
1450
1451 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1452 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1453 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1454
1455 if (pcms->iommu) {
1456 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1457 "for x86 yet.");
1458 return;
1459 }
1460 pcms->iommu = dev;
1461 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1462 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp);
1463 }
1464 }
1465
pc_machine_device_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1466 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1467 DeviceState *dev, Error **errp)
1468 {
1469 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1470 pc_memory_plug(hotplug_dev, dev, errp);
1471 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1472 x86_cpu_plug(hotplug_dev, dev, errp);
1473 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1474 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1475 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1476 pc_hv_balloon_plug(hotplug_dev, dev, errp);
1477 }
1478 }
1479
pc_machine_device_unplug_request_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1480 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1481 DeviceState *dev, Error **errp)
1482 {
1483 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1484 pc_memory_unplug_request(hotplug_dev, dev, errp);
1485 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1486 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1487 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1488 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
1489 errp);
1490 } else {
1491 error_setg(errp, "acpi: device unplug request for not supported device"
1492 " type: %s", object_get_typename(OBJECT(dev)));
1493 }
1494 }
1495
pc_machine_device_unplug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1496 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1497 DeviceState *dev, Error **errp)
1498 {
1499 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1500 pc_memory_unplug(hotplug_dev, dev, errp);
1501 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1502 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1503 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1504 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1505 } else {
1506 error_setg(errp, "acpi: device unplug for not supported device"
1507 " type: %s", object_get_typename(OBJECT(dev)));
1508 }
1509 }
1510
pc_get_hotplug_handler(MachineState * machine,DeviceState * dev)1511 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1512 DeviceState *dev)
1513 {
1514 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1515 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1516 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
1517 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1518 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) ||
1519 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1520 return HOTPLUG_HANDLER(machine);
1521 }
1522
1523 return NULL;
1524 }
1525
pc_machine_get_vmport(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1526 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1527 void *opaque, Error **errp)
1528 {
1529 PCMachineState *pcms = PC_MACHINE(obj);
1530 OnOffAuto vmport = pcms->vmport;
1531
1532 visit_type_OnOffAuto(v, name, &vmport, errp);
1533 }
1534
pc_machine_set_vmport(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1535 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1536 void *opaque, Error **errp)
1537 {
1538 PCMachineState *pcms = PC_MACHINE(obj);
1539
1540 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1541 }
1542
pc_machine_get_fd_bootchk(Object * obj,Error ** errp)1543 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp)
1544 {
1545 PCMachineState *pcms = PC_MACHINE(obj);
1546
1547 return pcms->fd_bootchk;
1548 }
1549
pc_machine_set_fd_bootchk(Object * obj,bool value,Error ** errp)1550 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp)
1551 {
1552 PCMachineState *pcms = PC_MACHINE(obj);
1553
1554 pcms->fd_bootchk = value;
1555 }
1556
pc_machine_get_smbus(Object * obj,Error ** errp)1557 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1558 {
1559 PCMachineState *pcms = PC_MACHINE(obj);
1560
1561 return pcms->smbus_enabled;
1562 }
1563
pc_machine_set_smbus(Object * obj,bool value,Error ** errp)1564 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1565 {
1566 PCMachineState *pcms = PC_MACHINE(obj);
1567
1568 pcms->smbus_enabled = value;
1569 }
1570
pc_machine_get_sata(Object * obj,Error ** errp)1571 static bool pc_machine_get_sata(Object *obj, Error **errp)
1572 {
1573 PCMachineState *pcms = PC_MACHINE(obj);
1574
1575 return pcms->sata_enabled;
1576 }
1577
pc_machine_set_sata(Object * obj,bool value,Error ** errp)1578 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1579 {
1580 PCMachineState *pcms = PC_MACHINE(obj);
1581
1582 pcms->sata_enabled = value;
1583 }
1584
pc_machine_get_hpet(Object * obj,Error ** errp)1585 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1586 {
1587 PCMachineState *pcms = PC_MACHINE(obj);
1588
1589 return pcms->hpet_enabled;
1590 }
1591
pc_machine_set_hpet(Object * obj,bool value,Error ** errp)1592 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1593 {
1594 PCMachineState *pcms = PC_MACHINE(obj);
1595
1596 pcms->hpet_enabled = value;
1597 }
1598
pc_machine_get_i8042(Object * obj,Error ** errp)1599 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1600 {
1601 PCMachineState *pcms = PC_MACHINE(obj);
1602
1603 return pcms->i8042_enabled;
1604 }
1605
pc_machine_set_i8042(Object * obj,bool value,Error ** errp)1606 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1607 {
1608 PCMachineState *pcms = PC_MACHINE(obj);
1609
1610 pcms->i8042_enabled = value;
1611 }
1612
pc_machine_get_default_bus_bypass_iommu(Object * obj,Error ** errp)1613 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1614 {
1615 PCMachineState *pcms = PC_MACHINE(obj);
1616
1617 return pcms->default_bus_bypass_iommu;
1618 }
1619
pc_machine_set_default_bus_bypass_iommu(Object * obj,bool value,Error ** errp)1620 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1621 Error **errp)
1622 {
1623 PCMachineState *pcms = PC_MACHINE(obj);
1624
1625 pcms->default_bus_bypass_iommu = value;
1626 }
1627
pc_machine_get_smbios_ep(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1628 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1629 void *opaque, Error **errp)
1630 {
1631 PCMachineState *pcms = PC_MACHINE(obj);
1632 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1633
1634 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1635 }
1636
pc_machine_set_smbios_ep(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1637 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1638 void *opaque, Error **errp)
1639 {
1640 PCMachineState *pcms = PC_MACHINE(obj);
1641
1642 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1643 }
1644
pc_machine_get_max_ram_below_4g(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1645 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1646 const char *name, void *opaque,
1647 Error **errp)
1648 {
1649 PCMachineState *pcms = PC_MACHINE(obj);
1650 uint64_t value = pcms->max_ram_below_4g;
1651
1652 visit_type_size(v, name, &value, errp);
1653 }
1654
pc_machine_set_max_ram_below_4g(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1655 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1656 const char *name, void *opaque,
1657 Error **errp)
1658 {
1659 PCMachineState *pcms = PC_MACHINE(obj);
1660 uint64_t value;
1661
1662 if (!visit_type_size(v, name, &value, errp)) {
1663 return;
1664 }
1665 if (value > 4 * GiB) {
1666 error_setg(errp,
1667 "Machine option 'max-ram-below-4g=%"PRIu64
1668 "' expects size less than or equal to 4G", value);
1669 return;
1670 }
1671
1672 if (value < 1 * MiB) {
1673 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1674 "BIOS may not work with less than 1MiB", value);
1675 }
1676
1677 pcms->max_ram_below_4g = value;
1678 }
1679
pc_machine_get_max_fw_size(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1680 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1681 const char *name, void *opaque,
1682 Error **errp)
1683 {
1684 PCMachineState *pcms = PC_MACHINE(obj);
1685 uint64_t value = pcms->max_fw_size;
1686
1687 visit_type_size(v, name, &value, errp);
1688 }
1689
pc_machine_set_max_fw_size(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1690 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1691 const char *name, void *opaque,
1692 Error **errp)
1693 {
1694 PCMachineState *pcms = PC_MACHINE(obj);
1695 uint64_t value;
1696
1697 if (!visit_type_size(v, name, &value, errp)) {
1698 return;
1699 }
1700
1701 /*
1702 * We don't have a theoretically justifiable exact lower bound on the base
1703 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1704 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1705 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to
1706 * 16MiB in size.
1707 */
1708 if (value > 16 * MiB) {
1709 error_setg(errp,
1710 "User specified max allowed firmware size %" PRIu64 " is "
1711 "greater than 16MiB. If combined firmware size exceeds "
1712 "16MiB the system may not boot, or experience intermittent"
1713 "stability issues.",
1714 value);
1715 return;
1716 }
1717
1718 pcms->max_fw_size = value;
1719 }
1720
1721
pc_machine_initfn(Object * obj)1722 static void pc_machine_initfn(Object *obj)
1723 {
1724 PCMachineState *pcms = PC_MACHINE(obj);
1725 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1726
1727 #ifdef CONFIG_VMPORT
1728 pcms->vmport = ON_OFF_AUTO_AUTO;
1729 #else
1730 pcms->vmport = ON_OFF_AUTO_OFF;
1731 #endif /* CONFIG_VMPORT */
1732 pcms->max_ram_below_4g = 0; /* use default */
1733 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
1734 pcms->south_bridge = pcmc->default_south_bridge;
1735
1736 /* acpi build is enabled by default if machine supports it */
1737 pcms->acpi_build_enabled = pcmc->has_acpi_build;
1738 pcms->smbus_enabled = true;
1739 pcms->sata_enabled = true;
1740 pcms->i8042_enabled = true;
1741 pcms->max_fw_size = 8 * MiB;
1742 #ifdef CONFIG_HPET
1743 pcms->hpet_enabled = true;
1744 #endif
1745 pcms->fd_bootchk = true;
1746 pcms->default_bus_bypass_iommu = false;
1747
1748 pc_system_flash_create(pcms);
1749 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1750 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1751 OBJECT(pcms->pcspk), "audiodev");
1752 if (pcmc->pci_enabled) {
1753 cxl_machine_init(obj, &pcms->cxl_devices_state);
1754 }
1755
1756 pcms->machine_done.notify = pc_machine_done;
1757 qemu_add_machine_init_done_notifier(&pcms->machine_done);
1758 }
1759
pc_machine_reset(MachineState * machine,ShutdownCause reason)1760 static void pc_machine_reset(MachineState *machine, ShutdownCause reason)
1761 {
1762 CPUState *cs;
1763 X86CPU *cpu;
1764
1765 qemu_devices_reset(reason);
1766
1767 /* Reset APIC after devices have been reset to cancel
1768 * any changes that qemu_devices_reset() might have done.
1769 */
1770 CPU_FOREACH(cs) {
1771 cpu = X86_CPU(cs);
1772
1773 x86_cpu_after_reset(cpu);
1774 }
1775 }
1776
pc_machine_wakeup(MachineState * machine)1777 static void pc_machine_wakeup(MachineState *machine)
1778 {
1779 cpu_synchronize_all_states();
1780 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE);
1781 cpu_synchronize_all_post_reset();
1782 }
1783
pc_hotplug_allowed(MachineState * ms,DeviceState * dev,Error ** errp)1784 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1785 {
1786 X86IOMMUState *iommu = x86_iommu_get_default();
1787 IntelIOMMUState *intel_iommu;
1788
1789 if (iommu &&
1790 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1791 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1792 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1793 if (!intel_iommu->caching_mode) {
1794 error_setg(errp, "Device assignment is not allowed without "
1795 "enabling caching-mode=on for Intel IOMMU.");
1796 return false;
1797 }
1798 }
1799
1800 return true;
1801 }
1802
pc_machine_class_init(ObjectClass * oc,void * data)1803 static void pc_machine_class_init(ObjectClass *oc, void *data)
1804 {
1805 MachineClass *mc = MACHINE_CLASS(oc);
1806 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc);
1807 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1808 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1809
1810 pcmc->pci_enabled = true;
1811 pcmc->has_acpi_build = true;
1812 pcmc->rsdp_in_ram = true;
1813 pcmc->smbios_defaults = true;
1814 pcmc->smbios_uuid_encoded = true;
1815 pcmc->gigabyte_align = true;
1816 pcmc->has_reserved_memory = true;
1817 pcmc->enforce_aligned_dimm = true;
1818 pcmc->enforce_amd_1tb_hole = true;
1819 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1820 * to be used at the moment, 32K should be enough for a while. */
1821 pcmc->acpi_data_size = 0x20000 + 0x8000;
1822 pcmc->pvh_enabled = true;
1823 pcmc->kvmclock_create_always = true;
1824 pcmc->resizable_acpi_blob = true;
1825 x86mc->apic_xrupt_override = true;
1826 assert(!mc->get_hotplug_handler);
1827 mc->get_hotplug_handler = pc_get_hotplug_handler;
1828 mc->hotplug_allowed = pc_hotplug_allowed;
1829 mc->auto_enable_numa_with_memhp = true;
1830 mc->auto_enable_numa_with_memdev = true;
1831 mc->has_hotpluggable_cpus = true;
1832 mc->default_boot_order = "cad";
1833 mc->block_default_type = IF_IDE;
1834 mc->max_cpus = 255;
1835 mc->reset = pc_machine_reset;
1836 mc->wakeup = pc_machine_wakeup;
1837 hc->pre_plug = pc_machine_device_pre_plug_cb;
1838 hc->plug = pc_machine_device_plug_cb;
1839 hc->unplug_request = pc_machine_device_unplug_request_cb;
1840 hc->unplug = pc_machine_device_unplug_cb;
1841 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1842 mc->nvdimm_supported = true;
1843 mc->smp_props.dies_supported = true;
1844 mc->default_ram_id = "pc.ram";
1845 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO;
1846
1847 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1848 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1849 NULL, NULL);
1850 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1851 "Maximum ram below the 4G boundary (32bit boundary)");
1852
1853 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1854 pc_machine_get_vmport, pc_machine_set_vmport,
1855 NULL, NULL);
1856 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1857 "Enable vmport (pc & q35)");
1858
1859 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1860 pc_machine_get_smbus, pc_machine_set_smbus);
1861 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1862 "Enable/disable system management bus");
1863
1864 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1865 pc_machine_get_sata, pc_machine_set_sata);
1866 object_class_property_set_description(oc, PC_MACHINE_SATA,
1867 "Enable/disable Serial ATA bus");
1868
1869 object_class_property_add_bool(oc, "hpet",
1870 pc_machine_get_hpet, pc_machine_set_hpet);
1871 object_class_property_set_description(oc, "hpet",
1872 "Enable/disable high precision event timer emulation");
1873
1874 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1875 pc_machine_get_i8042, pc_machine_set_i8042);
1876
1877 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1878 pc_machine_get_default_bus_bypass_iommu,
1879 pc_machine_set_default_bus_bypass_iommu);
1880
1881 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1882 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1883 NULL, NULL);
1884 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1885 "Maximum combined firmware size");
1886
1887 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1888 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1889 NULL, NULL);
1890 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1891 "SMBIOS Entry Point type [32, 64]");
1892
1893 object_class_property_add_bool(oc, "fd-bootchk",
1894 pc_machine_get_fd_bootchk,
1895 pc_machine_set_fd_bootchk);
1896 }
1897
1898 static const TypeInfo pc_machine_info = {
1899 .name = TYPE_PC_MACHINE,
1900 .parent = TYPE_X86_MACHINE,
1901 .abstract = true,
1902 .instance_size = sizeof(PCMachineState),
1903 .instance_init = pc_machine_initfn,
1904 .class_size = sizeof(PCMachineClass),
1905 .class_init = pc_machine_class_init,
1906 .interfaces = (InterfaceInfo[]) {
1907 { TYPE_HOTPLUG_HANDLER },
1908 { }
1909 },
1910 };
1911
pc_machine_register_types(void)1912 static void pc_machine_register_types(void)
1913 {
1914 type_register_static(&pc_machine_info);
1915 }
1916
1917 type_init(pc_machine_register_types)
1918