1 #ifndef _G_CHIPSET_NVOC_H_
2 #define _G_CHIPSET_NVOC_H_
3 #include "nvoc/runtime.h"
4
5 #ifdef __cplusplus
6 extern "C" {
7 #endif
8
9 /*
10 * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
11 * SPDX-License-Identifier: MIT
12 *
13 * Permission is hereby granted, free of charge, to any person obtaining a
14 * copy of this software and associated documentation files (the "Software"),
15 * to deal in the Software without restriction, including without limitation
16 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
17 * and/or sell copies of the Software, and to permit persons to whom the
18 * Software is furnished to do so, subject to the following conditions:
19 *
20 * The above copyright notice and this permission notice shall be included in
21 * all copies or substantial portions of the Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
28 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
29 * DEALINGS IN THE SOFTWARE.
30 */
31
32 #include "g_chipset_nvoc.h"
33
34 #ifndef CHIPSET_H
35 #define CHIPSET_H
36
37 /**************** Resource Manager Defines and Structures ******************\
38 * *
39 * Defines and structures used for the Core Logic Object. *
40 * *
41 \***************************************************************************/
42
43 #include "platform/hwbc.h"
44
45 // forward declare PcieAerCapability struct
46 struct PcieAerCapability;
47
48 // forward declaration of PexL1SubstateCapability
49 struct PexL1SubstateCapability;
50
51 // PCIe Enhanced Configuration space structure
52 typedef struct PCIECONFIGSPACEBASE PCIECONFIGSPACEBASE;
53 typedef struct PCIECONFIGSPACEBASE *PPCIECONFIGSPACEBASE;
54 struct PCIECONFIGSPACEBASE
55 {
56 RmPhysAddr baseAddress;
57 NvU32 domain;
58 NvU8 startBusNumber;
59 NvU8 endBusNumber;
60 PPCIECONFIGSPACEBASE next;
61 };
62
63 // Seen in both nvagp.c and elsewhere
64 #define PCI_MAX_DOMAINS 65536
65 #define PCI_MAX_BUSES 256
66 #define PCI_MAX_DEVICES 32
67 #define PCI_CLASS_DISPLAY_DEV 0x03
68 #define PCI_COMMAND 0x04
69 #define PCI_BASE_ADDRESS_0 0x10 /* Aperture Base */
70
71 #define PCI_VENDOR_ID_AMD 0x1022
72 #define PCI_VENDOR_ID_ALI 0x10B9
73 #define PCI_VENDOR_ID_NVIDIA 0x10DE
74
75 #define CL_MAX_LINK_WIDTH(p) ((p & 0x3f0) >> 4) // Max Link width is 9:4
76 // CL_IS_ROOT_PORT() returns NV_TRUE if root port of PCI-E Root Complex
77 // Device/Port type is 23:20
78 // Root port is 0100b
79 #define CL_IS_ROOT_PORT(p) (((p & 0xf00000) >> 20) == 0x4)
80 #define CL_IS_UPSTREAM_PORT(p) (((p & 0xf00000) >> 20) == 0x5)
81 #define CL_IS_DOWNSTREAM_PORT(p) (((p & 0xf00000) >> 20) == 0x6)
82 #define CL_AVG_LINK_WIDTH 8
83 #define CL_DAGWOOD_LINK_WIDTH 8
84 #define CL_SINGLE_DW_LINK_WIDTH 8
85
86 //
87 // Offset arguments to Pcie[Read|WriteRoot]PortConfigReg
88 //
89
90 // PCI Express capability
91 #define CL_PCIE_BEGIN 0x0100
92 #define CL_PCIE_CAP (CL_PCIE_BEGIN + 0x00)
93 #define CL_PCIE_DEV_CAP (CL_PCIE_BEGIN + 0x04)
94 #define CL_PCIE_DEV_CTRL_STATUS (CL_PCIE_BEGIN + 0x08)
95 #define CL_PCIE_LINK_CAP (CL_PCIE_BEGIN + 0x0C)
96 #define CL_PCIE_LINK_CTRL_STATUS (CL_PCIE_BEGIN + 0x10)
97 #define CL_PCIE_SLOT_CAP (CL_PCIE_BEGIN + 0x14)
98 #define CL_PCIE_SLOT_CTRL_STATUS (CL_PCIE_BEGIN + 0x18)
99 #define CL_PCIE_ROOT_CTRL_RSVDP (CL_PCIE_BEGIN + 0x1C)
100 #define CL_PCIE_ROOT_STATUS (CL_PCIE_BEGIN + 0x20)
101 #define CL_PCIE_DEV_CAP_2 (CL_PCIE_BEGIN + 0x24)
102 #define CL_PCIE_DEV_CTRL_2 (CL_PCIE_BEGIN + 0x28)
103 #define CL_PCIE_END (CL_PCIE_BEGIN + 0x2C)
104
105 // PCI Express Capabilities
106 #define CL_PCIE_CAP_SLOT NVBIT(24)
107
108 // PCI Express Link Control ASPM Control Bits
109 #define CL_PCIE_LINK_CTRL_STATUS_ASPM_L0S_BIT NVBIT(0)
110 #define CL_PCIE_LINK_CTRL_STATUS_ASPM_L1_BIT NVBIT(1)
111 #define CL_PCIE_LINK_CTRL_STATUS_ASPM_MASK \
112 (CL_PCIE_LINK_CTRL_STATUS_ASPM_L0S_BIT|CL_PCIE_LINK_CTRL_STATUS_ASPM_L1_BIT)
113
114 // PCI Express Link control ASPM capability Bits
115 #define CL_PCIE_LINK_CAP_ASPM_L0S_BIT NVBIT(10)
116 #define CL_PCIE_LINK_CAP_ASPM_L1_BIT NVBIT(11)
117 #define CL_PCIE_LINK_CAP_CLOCK_PM_BIT NVBIT(18)
118
119 // PCI Express Slot Capabilities
120 #define CL_PCIE_SLOT_CAP_HOTPLUG_SURPRISE NVBIT(5)
121 #define CL_PCIE_SLOT_CAP_HOTPLUG_CAPABLE NVBIT(6)
122
123 //
124 // CL_DEVICE_CONTROL_STATUS bits for hal
125 //
126 // From PCI-E manual
127 #define CL_PCIE_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED NVBIT(16)
128 #define CL_PCIE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED NVBIT(17)
129 #define CL_PCIE_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED NVBIT(18)
130 #define CL_PCIE_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED NVBIT(19)
131
132 // PCI Express Latency Tolerance Reporting Capability Bit
133 #define CL_PCIE_DEV_CAP_2_LTR_SUPPORTED_BIT NVBIT(11)
134 #define CL_PCIE_DEV_CTRL_2_LTR_ENABLED_BIT NVBIT(10)
135
136 // Advanced Error Reporting capability
137 #define CL_AER_BEGIN 0x0200
138 #define CL_AER_CAP (CL_AER_BEGIN + 0x00)
139 #define CL_AER_UNCORRECTABLE_STATUS (CL_AER_BEGIN + 0x04)
140 #define CL_AER_UNCORRECTABLE_MASK (CL_AER_BEGIN + 0x08)
141 #define CL_AER_UNCORRECTABLE_SEVERITY (CL_AER_BEGIN + 0x0C)
142 #define CL_AER_CORRECTABLE_STATUS (CL_AER_BEGIN + 0x10)
143 #define CL_AER_CORRECTABLE_MASK (CL_AER_BEGIN + 0x14)
144 #define CL_AER_ADVANCED_CAP_CONTROL (CL_AER_BEGIN + 0x18)
145 #define CL_AER_HEADER_LOG (CL_AER_BEGIN + 0x1C)
146 #define CL_AER_ROOT_ERROR_COMMAND (CL_AER_BEGIN + 0x2C)
147 #define CL_AER_ROOT_ERROR_STATUS (CL_AER_BEGIN + 0x30)
148 #define CL_AER_ERROR_SOURCE (CL_AER_BEGIN + 0x34)
149 #define CL_AER_END (CL_AER_BEGIN + 0x34)
150
151 // PCI Express Device Capabilities 2
152 #define CL_PCIE_DEV_CAP_2_ATOMICS_SUPPORTED_BIT NVBIT(6)
153 #define CL_PCIE_DEV_CAP_2_ATOMIC_32BIT NVBIT(7)
154 #define CL_PCIE_DEV_CAP_2_ATOMIC_64BIT NVBIT(8)
155 #define CL_PCIE_DEV_CAP_2_ATOMIC_128BIT NVBIT(9)
156
157 // PCI Express Device Control & Status 2
158 #define CL_PCIE_DEV_CTRL_2_ATOMICS_EGRESS_BLOCK_BIT NVBIT(7)
159
160 // Defines for Atomic Mask
161 #define CL_ATOMIC_32BIT NVBIT(0)
162 #define CL_ATOMIC_64BIT NVBIT(1)
163 #define CL_ATOMIC_128BIT NVBIT(2)
164
165 #define CL_IS_L0_SUPPORTED(p) (((p) & CL_PCIE_LINK_CAP_ASPM_L0S_BIT))
166 #define CL_IS_L1_SUPPORTED(p) (((p) & CL_PCIE_LINK_CAP_ASPM_L1_BIT))
167
168 #define CL_IS_LTR_PORT_SUPPORTED(p) (((p) & CL_PCIE_DEV_CAP_2_LTR_SUPPORTED_BIT))
169 #define CL_IS_LTR_PORT_ENABLED(p) (((p) & CL_PCIE_DEV_CTRL_2_LTR_ENABLED_BIT))
170
171 #define CL_IS_ATOMICS_SUPPORTED(p) (((p) & CL_PCIE_DEV_CAP_2_ATOMICS_SUPPORTED_BIT))
172 #define CL_IS_ATOMICS_EGRESS_BLOCKED(p) (((p) & CL_PCIE_DEV_CTRL_2_ATOMICS_EGRESS_BLOCK_BIT))
173
174 #define CL_IS_32BIT_ATOMICS_SUPPORTED(p) (((p) & CL_PCIE_DEV_CAP_2_ATOMIC_32BIT))
175 #define CL_IS_64BIT_ATOMICS_SUPPORTED(p) (((p) & CL_PCIE_DEV_CAP_2_ATOMIC_64BIT))
176 #define CL_IS_128BIT_ATOMICS_SUPPORTED(p) (((p) & CL_PCIE_DEV_CAP_2_ATOMIC_128BIT))
177
178 //
179 // This defines PCI-E Advanced Error Reporting Capability structure per PCI-E manual
180 // (refer to section 7.10 of PCI Express Base Specification, v1.1)
181 //
182 typedef struct PcieAerCapability
183 {
184 NvU32 PexEnhCapHeader; // (+0x00) PCI-E Enhanced Capability Header
185 NvU32 UncorrErrStatusReg; // (+0x04) Uncorrectable Error Status Register
186 NvU32 UncorrErrMaskReg; // (+0x08) Uncorrectable Error Mask Register
187 NvU32 UncorrErrSeverityReg; // (+0x0C) Uncorrectable Error Severity Register
188 NvU32 CorrErrStatusReg; // (+0x10) Correctable Error Status Register
189 NvU32 CorrErrMaskReg; // (+0x14) Correctable Error Mask Register
190 NvU32 AEcapCrtlReg; // (+0x18) Advanced Error Capability and Control Register
191 struct { // (+0x1C) Header Log Register
192 NvU32 Header[4]; // (+0x1C-0x2B)
193 } HeaderLogReg;
194 NvU32 RootErrCmd; // (+0x2C) Root Error Command
195 NvU32 RooErrStatus; // (+0x30) Root Error Status
196 NvU32 ErrSrcReg; // (+0x34) Error Source Register (Correctable Err Src Id + Err Src Id)
197 } PcieAerCapability, *PPcieAerCapability;
198
199 // Virtual Channel Capability
200 #define CL_VC_BEGIN 0x0300
201 #define CL_VC_RESOURCE_CTRL_0 (CL_VC_BEGIN + 0x14)
202 #define CL_VC_END (CL_VC_BEGIN + 0x1C)
203
204 typedef struct
205 {
206 NvU16 deviceID; // deviceID
207 NvU16 vendorID; // vendorID
208 NvU16 subdeviceID; // subsystem deviceID
209 NvU16 subvendorID; // subsystem vendorID
210 NvU8 revisionID; // revision ID
211 } BUSINFO;
212
213 // L1 PM substates Capability
214 #define CL_L1_SS_BEGIN 0x0400
215 #define CL_L1_SS_CAP_HDR (CL_L1_SS_BEGIN + 0x00)
216 #define CL_L1_SS_CAP_REG (CL_L1_SS_BEGIN + 0x04)
217 #define CL_L1_SS_CTRL1_REG (CL_L1_SS_BEGIN + 0x08)
218 #define CL_L1_SS_CTRL2_REG (CL_L1_SS_BEGIN + 0x0C)
219 #define CL_L1_SS_END CL_L1_SS_CTRL2_REG
220
221 //
222 // This defines PCI-E L1 PM Substates Extended Capability structure per PCI-E manual
223 // (refer to section 7.xx of ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf
224 //
225 typedef struct PexL1SubstateCapability
226 {
227 NvU32 PexEnhCapHeader; // (+0x00) PCI-E Enhanced Capability Header
228 NvU32 Capabilities; // (+0x04) L1 PM Substates capabilities Register
229 NvU32 Control1Reg; // (+0x08) L1 PM Substates Control1 Register
230 NvU32 Control2Reg; // (+0x0C) L1 PM Substates Control2 Register
231 } PexL1SubstateCapability, *PPexL1SubstateCapability;
232
233 typedef struct BUSTOPOLOGYINFO BUSTOPOLOGYINFO;
234 typedef struct BUSTOPOLOGYINFO *PBUSTOPOLOGYINFO;
235 struct BUSTOPOLOGYINFO
236 {
237 PBUSTOPOLOGYINFO next;
238 void *handle;
239 BUSINFO busInfo;
240 NvU32 domain;
241 NvU8 bus, device, func, secBus;
242 NvU16 pciSubBaseClass;
243 NvBool bVgaAdapter;
244 };
245
246 typedef struct GspSystemInfo GspSystemInfo;
247
248
249 // Private field names are wrapped in PRIVATE_FIELD, which does nothing for
250 // the matching C source file, but causes diagnostics to be issued if another
251 // source file references the field.
252 #ifdef NVOC_CHIPSET_H_PRIVATE_ACCESS_ALLOWED
253 #define PRIVATE_FIELD(x) x
254 #else
255 #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x)
256 #endif
257
258 struct OBJCL {
259 const struct NVOC_RTTI *__nvoc_rtti;
260 struct Object __nvoc_base_Object;
261 struct Object *__nvoc_pbase_Object;
262 struct OBJCL *__nvoc_pbase_OBJCL;
263 NvBool PDB_PROP_CL_PCIE_CONFIG_ACCESSIBLE;
264 NvBool PDB_PROP_CL_DISABLE_BR03_FLOW_CONTROL;
265 NvBool PDB_PROP_CL_ASLM_SUPPORTS_NV_LINK_UPGRADE;
266 NvBool PDB_PROP_CL_ASLM_SUPPORTS_FAST_LINK_UPGRADE;
267 NvBool PDB_PROP_CL_ASLM_SUPPORTS_HOT_RESET;
268 NvBool PDB_PROP_CL_ASLM_SUPPORTS_GEN2_LINK_UPGRADE;
269 NvBool PDB_PROP_CL_FORCE_SNOOP_READS_AND_WRITES_WAR_BUG_410390;
270 NvBool PDB_PROP_CL_IS_CHIPSET_IN_ASPM_POR_LIST;
271 NvBool PDB_PROP_CL_ASPM_L0S_CHIPSET_DISABLED;
272 NvBool PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED;
273 NvBool PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY;
274 NvBool PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY;
275 NvBool PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED;
276 NvBool PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED;
277 NvBool PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_GEFORCE;
278 NvBool PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE;
279 NvBool PDB_PROP_CL_NOSNOOP_NOT_CAPABLE;
280 NvBool PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE;
281 NvBool PDB_PROP_CL_PCIE_FORCE_GEN2_ENABLE;
282 NvBool PDB_PROP_CL_PCIE_GEN2_AT_LESS_THAN_X16_DISABLED;
283 NvBool PDB_PROP_CL_ROOTPORT_NEEDS_NOSNOOP_WAR;
284 NvBool PDB_PROP_CL_INTEL_CPU_ROOTPORT1_NEEDS_H57_WAR;
285 NvBool PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ;
286 NvBool PDB_PROP_CL_ON_PCIE_GEN3_PATSBURG;
287 NvBool PDB_PROP_CL_IS_EXTERNAL_GPU;
288 NvBool PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU;
289 NvBool PDB_PROP_CL_BUG_999673_P2P_ARBITRARY_SPLIT_WAR;
290 NvBool PDB_PROP_CL_UPSTREAM_LTR_SUPPORTED;
291 NvBool PDB_PROP_CL_BUG_1340801_DISABLE_GEN3_ON_GIGABYTE_SNIPER_3;
292 NvBool PDB_PROP_CL_BUG_1681803_WAR_DISABLE_MSCG;
293 NvBool PDB_PROP_CL_PCIE_NON_COHERENT_USE_TC0_ONLY;
294 NvBool PDB_PROP_CL_UNSUPPORTED_CHIPSET;
295 NvBool PDB_PROP_CL_IS_CHIPSET_IO_COHERENT;
296 NvBool PDB_PROP_CL_DISABLE_IOMAP_WC;
297 NvBool PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE;
298 NvBool PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR;
299 NvBool PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS;
300 NBADDR NBAddr;
301 NvBool EnteredRecoverySinceErrorsLastChecked;
302 struct OBJHWBC *pHWBC;
303 NvU32 br04HwbcCount;
304 NBADDR FHBAddr;
305 BUSINFO FHBBusInfo;
306 NvU32 Chipset;
307 NvU32 ChipsetSliBondType;
308 NvBool ChipsetInitialized;
309 PPCIECONFIGSPACEBASE pPcieConfigSpaceBase;
310 NBADDR chipsetIDBusAddr;
311 BUSINFO chipsetIDInfo;
312 PBUSTOPOLOGYINFO pBusTopologyInfo;
313 };
314
315 #ifndef __NVOC_CLASS_OBJCL_TYPEDEF__
316 #define __NVOC_CLASS_OBJCL_TYPEDEF__
317 typedef struct OBJCL OBJCL;
318 #endif /* __NVOC_CLASS_OBJCL_TYPEDEF__ */
319
320 #ifndef __nvoc_class_id_OBJCL
321 #define __nvoc_class_id_OBJCL 0x547dbb
322 #endif /* __nvoc_class_id_OBJCL */
323
324 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJCL;
325
326 #define __staticCast_OBJCL(pThis) \
327 ((pThis)->__nvoc_pbase_OBJCL)
328
329 #ifdef __nvoc_chipset_h_disabled
330 #define __dynamicCast_OBJCL(pThis) ((OBJCL*)NULL)
331 #else //__nvoc_chipset_h_disabled
332 #define __dynamicCast_OBJCL(pThis) \
333 ((OBJCL*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(OBJCL)))
334 #endif //__nvoc_chipset_h_disabled
335
336 #define PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ_BASE_CAST
337 #define PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ_BASE_NAME PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ
338 #define PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE_BASE_CAST
339 #define PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE_BASE_NAME PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE
340 #define PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_GEFORCE_BASE_CAST
341 #define PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_GEFORCE_BASE_NAME PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_GEFORCE
342 #define PDB_PROP_CL_UPSTREAM_LTR_SUPPORTED_BASE_CAST
343 #define PDB_PROP_CL_UPSTREAM_LTR_SUPPORTED_BASE_NAME PDB_PROP_CL_UPSTREAM_LTR_SUPPORTED
344 #define PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS_BASE_CAST
345 #define PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS_BASE_NAME PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS
346 #define PDB_PROP_CL_BUG_1681803_WAR_DISABLE_MSCG_BASE_CAST
347 #define PDB_PROP_CL_BUG_1681803_WAR_DISABLE_MSCG_BASE_NAME PDB_PROP_CL_BUG_1681803_WAR_DISABLE_MSCG
348 #define PDB_PROP_CL_ON_PCIE_GEN3_PATSBURG_BASE_CAST
349 #define PDB_PROP_CL_ON_PCIE_GEN3_PATSBURG_BASE_NAME PDB_PROP_CL_ON_PCIE_GEN3_PATSBURG
350 #define PDB_PROP_CL_ASLM_SUPPORTS_NV_LINK_UPGRADE_BASE_CAST
351 #define PDB_PROP_CL_ASLM_SUPPORTS_NV_LINK_UPGRADE_BASE_NAME PDB_PROP_CL_ASLM_SUPPORTS_NV_LINK_UPGRADE
352 #define PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED_BASE_CAST
353 #define PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED_BASE_NAME PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED
354 #define PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE_BASE_CAST
355 #define PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE_BASE_NAME PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE
356 #define PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED_BASE_CAST
357 #define PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED_BASE_NAME PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED
358 #define PDB_PROP_CL_PCIE_GEN2_AT_LESS_THAN_X16_DISABLED_BASE_CAST
359 #define PDB_PROP_CL_PCIE_GEN2_AT_LESS_THAN_X16_DISABLED_BASE_NAME PDB_PROP_CL_PCIE_GEN2_AT_LESS_THAN_X16_DISABLED
360 #define PDB_PROP_CL_UNSUPPORTED_CHIPSET_BASE_CAST
361 #define PDB_PROP_CL_UNSUPPORTED_CHIPSET_BASE_NAME PDB_PROP_CL_UNSUPPORTED_CHIPSET
362 #define PDB_PROP_CL_ASLM_SUPPORTS_GEN2_LINK_UPGRADE_BASE_CAST
363 #define PDB_PROP_CL_ASLM_SUPPORTS_GEN2_LINK_UPGRADE_BASE_NAME PDB_PROP_CL_ASLM_SUPPORTS_GEN2_LINK_UPGRADE
364 #define PDB_PROP_CL_IS_CHIPSET_IN_ASPM_POR_LIST_BASE_CAST
365 #define PDB_PROP_CL_IS_CHIPSET_IN_ASPM_POR_LIST_BASE_NAME PDB_PROP_CL_IS_CHIPSET_IN_ASPM_POR_LIST
366 #define PDB_PROP_CL_BUG_999673_P2P_ARBITRARY_SPLIT_WAR_BASE_CAST
367 #define PDB_PROP_CL_BUG_999673_P2P_ARBITRARY_SPLIT_WAR_BASE_NAME PDB_PROP_CL_BUG_999673_P2P_ARBITRARY_SPLIT_WAR
368 #define PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY_BASE_CAST
369 #define PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY_BASE_NAME PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY
370 #define PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU_BASE_CAST
371 #define PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU_BASE_NAME PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU
372 #define PDB_PROP_CL_PCIE_FORCE_GEN2_ENABLE_BASE_CAST
373 #define PDB_PROP_CL_PCIE_FORCE_GEN2_ENABLE_BASE_NAME PDB_PROP_CL_PCIE_FORCE_GEN2_ENABLE
374 #define PDB_PROP_CL_DISABLE_BR03_FLOW_CONTROL_BASE_CAST
375 #define PDB_PROP_CL_DISABLE_BR03_FLOW_CONTROL_BASE_NAME PDB_PROP_CL_DISABLE_BR03_FLOW_CONTROL
376 #define PDB_PROP_CL_DISABLE_IOMAP_WC_BASE_CAST
377 #define PDB_PROP_CL_DISABLE_IOMAP_WC_BASE_NAME PDB_PROP_CL_DISABLE_IOMAP_WC
378 #define PDB_PROP_CL_PCIE_CONFIG_ACCESSIBLE_BASE_CAST
379 #define PDB_PROP_CL_PCIE_CONFIG_ACCESSIBLE_BASE_NAME PDB_PROP_CL_PCIE_CONFIG_ACCESSIBLE
380 #define PDB_PROP_CL_NOSNOOP_NOT_CAPABLE_BASE_CAST
381 #define PDB_PROP_CL_NOSNOOP_NOT_CAPABLE_BASE_NAME PDB_PROP_CL_NOSNOOP_NOT_CAPABLE
382 #define PDB_PROP_CL_ASPM_L0S_CHIPSET_DISABLED_BASE_CAST
383 #define PDB_PROP_CL_ASPM_L0S_CHIPSET_DISABLED_BASE_NAME PDB_PROP_CL_ASPM_L0S_CHIPSET_DISABLED
384 #define PDB_PROP_CL_INTEL_CPU_ROOTPORT1_NEEDS_H57_WAR_BASE_CAST
385 #define PDB_PROP_CL_INTEL_CPU_ROOTPORT1_NEEDS_H57_WAR_BASE_NAME PDB_PROP_CL_INTEL_CPU_ROOTPORT1_NEEDS_H57_WAR
386 #define PDB_PROP_CL_BUG_1340801_DISABLE_GEN3_ON_GIGABYTE_SNIPER_3_BASE_CAST
387 #define PDB_PROP_CL_BUG_1340801_DISABLE_GEN3_ON_GIGABYTE_SNIPER_3_BASE_NAME PDB_PROP_CL_BUG_1340801_DISABLE_GEN3_ON_GIGABYTE_SNIPER_3
388 #define PDB_PROP_CL_ASLM_SUPPORTS_HOT_RESET_BASE_CAST
389 #define PDB_PROP_CL_ASLM_SUPPORTS_HOT_RESET_BASE_NAME PDB_PROP_CL_ASLM_SUPPORTS_HOT_RESET
390 #define PDB_PROP_CL_IS_EXTERNAL_GPU_BASE_CAST
391 #define PDB_PROP_CL_IS_EXTERNAL_GPU_BASE_NAME PDB_PROP_CL_IS_EXTERNAL_GPU
392 #define PDB_PROP_CL_ROOTPORT_NEEDS_NOSNOOP_WAR_BASE_CAST
393 #define PDB_PROP_CL_ROOTPORT_NEEDS_NOSNOOP_WAR_BASE_NAME PDB_PROP_CL_ROOTPORT_NEEDS_NOSNOOP_WAR
394 #define PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_BASE_CAST
395 #define PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_BASE_NAME PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED
396 #define PDB_PROP_CL_FORCE_SNOOP_READS_AND_WRITES_WAR_BUG_410390_BASE_CAST
397 #define PDB_PROP_CL_FORCE_SNOOP_READS_AND_WRITES_WAR_BUG_410390_BASE_NAME PDB_PROP_CL_FORCE_SNOOP_READS_AND_WRITES_WAR_BUG_410390
398 #define PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY_BASE_CAST
399 #define PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY_BASE_NAME PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY
400 #define PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR_BASE_CAST
401 #define PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR_BASE_NAME PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR
402 #define PDB_PROP_CL_PCIE_NON_COHERENT_USE_TC0_ONLY_BASE_CAST
403 #define PDB_PROP_CL_PCIE_NON_COHERENT_USE_TC0_ONLY_BASE_NAME PDB_PROP_CL_PCIE_NON_COHERENT_USE_TC0_ONLY
404 #define PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE_BASE_CAST
405 #define PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE_BASE_NAME PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE
406 #define PDB_PROP_CL_IS_CHIPSET_IO_COHERENT_BASE_CAST
407 #define PDB_PROP_CL_IS_CHIPSET_IO_COHERENT_BASE_NAME PDB_PROP_CL_IS_CHIPSET_IO_COHERENT
408 #define PDB_PROP_CL_ASLM_SUPPORTS_FAST_LINK_UPGRADE_BASE_CAST
409 #define PDB_PROP_CL_ASLM_SUPPORTS_FAST_LINK_UPGRADE_BASE_NAME PDB_PROP_CL_ASLM_SUPPORTS_FAST_LINK_UPGRADE
410
411 NV_STATUS __nvoc_objCreateDynamic_OBJCL(OBJCL**, Dynamic*, NvU32, va_list);
412
413 NV_STATUS __nvoc_objCreate_OBJCL(OBJCL**, Dynamic*, NvU32);
414 #define __objCreate_OBJCL(ppNewObj, pParent, createFlags) \
415 __nvoc_objCreate_OBJCL((ppNewObj), staticCast((pParent), Dynamic), (createFlags))
416
417 NV_STATUS clInit_IMPL(struct OBJGPU *arg0, struct OBJCL *pCl);
418
419
420 #ifdef __nvoc_chipset_h_disabled
clInit(struct OBJGPU * arg0,struct OBJCL * pCl)421 static inline NV_STATUS clInit(struct OBJGPU *arg0, struct OBJCL *pCl) {
422 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
423 return NV_ERR_NOT_SUPPORTED;
424 }
425 #else //__nvoc_chipset_h_disabled
426 #define clInit(arg0, pCl) clInit_IMPL(arg0, pCl)
427 #endif //__nvoc_chipset_h_disabled
428
429 #define clInit_HAL(arg0, pCl) clInit(arg0, pCl)
430
431 void clUpdateConfig_IMPL(struct OBJGPU *arg0, struct OBJCL *pCl);
432
433
434 #ifdef __nvoc_chipset_h_disabled
clUpdateConfig(struct OBJGPU * arg0,struct OBJCL * pCl)435 static inline void clUpdateConfig(struct OBJGPU *arg0, struct OBJCL *pCl) {
436 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
437 }
438 #else //__nvoc_chipset_h_disabled
439 #define clUpdateConfig(arg0, pCl) clUpdateConfig_IMPL(arg0, pCl)
440 #endif //__nvoc_chipset_h_disabled
441
442 #define clUpdateConfig_HAL(arg0, pCl) clUpdateConfig(arg0, pCl)
443
444 NV_STATUS clTeardown_IMPL(struct OBJGPU *arg0, struct OBJCL *pCl);
445
446
447 #ifdef __nvoc_chipset_h_disabled
clTeardown(struct OBJGPU * arg0,struct OBJCL * pCl)448 static inline NV_STATUS clTeardown(struct OBJGPU *arg0, struct OBJCL *pCl) {
449 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
450 return NV_ERR_NOT_SUPPORTED;
451 }
452 #else //__nvoc_chipset_h_disabled
453 #define clTeardown(arg0, pCl) clTeardown_IMPL(arg0, pCl)
454 #endif //__nvoc_chipset_h_disabled
455
456 #define clTeardown_HAL(arg0, pCl) clTeardown(arg0, pCl)
457
458 void clInitPropertiesFromRegistry_IMPL(struct OBJGPU *arg0, struct OBJCL *pCl);
459
460
461 #ifdef __nvoc_chipset_h_disabled
clInitPropertiesFromRegistry(struct OBJGPU * arg0,struct OBJCL * pCl)462 static inline void clInitPropertiesFromRegistry(struct OBJGPU *arg0, struct OBJCL *pCl) {
463 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
464 }
465 #else //__nvoc_chipset_h_disabled
466 #define clInitPropertiesFromRegistry(arg0, pCl) clInitPropertiesFromRegistry_IMPL(arg0, pCl)
467 #endif //__nvoc_chipset_h_disabled
468
469 #define clInitPropertiesFromRegistry_HAL(arg0, pCl) clInitPropertiesFromRegistry(arg0, pCl)
470
471 NvU32 clInitMappingPciBusDevice_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1);
472
473
474 #ifdef __nvoc_chipset_h_disabled
clInitMappingPciBusDevice(struct OBJGPU * arg0,struct OBJCL * arg1)475 static inline NvU32 clInitMappingPciBusDevice(struct OBJGPU *arg0, struct OBJCL *arg1) {
476 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
477 return 0;
478 }
479 #else //__nvoc_chipset_h_disabled
480 #define clInitMappingPciBusDevice(arg0, arg1) clInitMappingPciBusDevice_IMPL(arg0, arg1)
481 #endif //__nvoc_chipset_h_disabled
482
483 #define clInitMappingPciBusDevice_HAL(arg0, arg1) clInitMappingPciBusDevice(arg0, arg1)
484
485 NV_STATUS clFindFHBAndGetChipsetInfoIndex_IMPL(struct OBJCL *arg0, NvU16 *arg1);
486
487
488 #ifdef __nvoc_chipset_h_disabled
clFindFHBAndGetChipsetInfoIndex(struct OBJCL * arg0,NvU16 * arg1)489 static inline NV_STATUS clFindFHBAndGetChipsetInfoIndex(struct OBJCL *arg0, NvU16 *arg1) {
490 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
491 return NV_ERR_NOT_SUPPORTED;
492 }
493 #else //__nvoc_chipset_h_disabled
494 #define clFindFHBAndGetChipsetInfoIndex(arg0, arg1) clFindFHBAndGetChipsetInfoIndex_IMPL(arg0, arg1)
495 #endif //__nvoc_chipset_h_disabled
496
497 #define clFindFHBAndGetChipsetInfoIndex_HAL(arg0, arg1) clFindFHBAndGetChipsetInfoIndex(arg0, arg1)
498
499 NV_STATUS clInitPcie_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1);
500
501
502 #ifdef __nvoc_chipset_h_disabled
clInitPcie(struct OBJGPU * arg0,struct OBJCL * arg1)503 static inline NV_STATUS clInitPcie(struct OBJGPU *arg0, struct OBJCL *arg1) {
504 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
505 return NV_ERR_NOT_SUPPORTED;
506 }
507 #else //__nvoc_chipset_h_disabled
508 #define clInitPcie(arg0, arg1) clInitPcie_IMPL(arg0, arg1)
509 #endif //__nvoc_chipset_h_disabled
510
511 #define clInitPcie_HAL(arg0, arg1) clInitPcie(arg0, arg1)
512
513 void clUpdatePcieConfig_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1);
514
515
516 #ifdef __nvoc_chipset_h_disabled
clUpdatePcieConfig(struct OBJGPU * arg0,struct OBJCL * arg1)517 static inline void clUpdatePcieConfig(struct OBJGPU *arg0, struct OBJCL *arg1) {
518 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
519 }
520 #else //__nvoc_chipset_h_disabled
521 #define clUpdatePcieConfig(arg0, arg1) clUpdatePcieConfig_IMPL(arg0, arg1)
522 #endif //__nvoc_chipset_h_disabled
523
524 #define clUpdatePcieConfig_HAL(arg0, arg1) clUpdatePcieConfig(arg0, arg1)
525
526 NV_STATUS clTeardownPcie_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1);
527
528
529 #ifdef __nvoc_chipset_h_disabled
clTeardownPcie(struct OBJGPU * arg0,struct OBJCL * arg1)530 static inline NV_STATUS clTeardownPcie(struct OBJGPU *arg0, struct OBJCL *arg1) {
531 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
532 return NV_ERR_NOT_SUPPORTED;
533 }
534 #else //__nvoc_chipset_h_disabled
535 #define clTeardownPcie(arg0, arg1) clTeardownPcie_IMPL(arg0, arg1)
536 #endif //__nvoc_chipset_h_disabled
537
538 #define clTeardownPcie_HAL(arg0, arg1) clTeardownPcie(arg0, arg1)
539
540 NV_STATUS clPcieReadPortConfigReg_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, PORTDATA *arg2, NvU32 arg3, NvU32 *arg4);
541
542
543 #ifdef __nvoc_chipset_h_disabled
clPcieReadPortConfigReg(struct OBJGPU * arg0,struct OBJCL * arg1,PORTDATA * arg2,NvU32 arg3,NvU32 * arg4)544 static inline NV_STATUS clPcieReadPortConfigReg(struct OBJGPU *arg0, struct OBJCL *arg1, PORTDATA *arg2, NvU32 arg3, NvU32 *arg4) {
545 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
546 return NV_ERR_NOT_SUPPORTED;
547 }
548 #else //__nvoc_chipset_h_disabled
549 #define clPcieReadPortConfigReg(arg0, arg1, arg2, arg3, arg4) clPcieReadPortConfigReg_IMPL(arg0, arg1, arg2, arg3, arg4)
550 #endif //__nvoc_chipset_h_disabled
551
552 #define clPcieReadPortConfigReg_HAL(arg0, arg1, arg2, arg3, arg4) clPcieReadPortConfigReg(arg0, arg1, arg2, arg3, arg4)
553
554 NV_STATUS clPcieWriteRootPortConfigReg_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 arg2, NvU32 arg3);
555
556
557 #ifdef __nvoc_chipset_h_disabled
clPcieWriteRootPortConfigReg(struct OBJGPU * arg0,struct OBJCL * arg1,NvU32 arg2,NvU32 arg3)558 static inline NV_STATUS clPcieWriteRootPortConfigReg(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 arg2, NvU32 arg3) {
559 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
560 return NV_ERR_NOT_SUPPORTED;
561 }
562 #else //__nvoc_chipset_h_disabled
563 #define clPcieWriteRootPortConfigReg(arg0, arg1, arg2, arg3) clPcieWriteRootPortConfigReg_IMPL(arg0, arg1, arg2, arg3)
564 #endif //__nvoc_chipset_h_disabled
565
566 #define clPcieWriteRootPortConfigReg_HAL(arg0, arg1, arg2, arg3) clPcieWriteRootPortConfigReg(arg0, arg1, arg2, arg3)
567
568 NV_STATUS clPcieReadAerCapability_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, struct PcieAerCapability *arg2);
569
570
571 #ifdef __nvoc_chipset_h_disabled
clPcieReadAerCapability(struct OBJGPU * arg0,struct OBJCL * arg1,struct PcieAerCapability * arg2)572 static inline NV_STATUS clPcieReadAerCapability(struct OBJGPU *arg0, struct OBJCL *arg1, struct PcieAerCapability *arg2) {
573 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
574 return NV_ERR_NOT_SUPPORTED;
575 }
576 #else //__nvoc_chipset_h_disabled
577 #define clPcieReadAerCapability(arg0, arg1, arg2) clPcieReadAerCapability_IMPL(arg0, arg1, arg2)
578 #endif //__nvoc_chipset_h_disabled
579
580 #define clPcieReadAerCapability_HAL(arg0, arg1, arg2) clPcieReadAerCapability(arg0, arg1, arg2)
581
582 NV_STATUS clPcieReadL1SsCapability_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, struct PexL1SubstateCapability *arg2);
583
584
585 #ifdef __nvoc_chipset_h_disabled
clPcieReadL1SsCapability(struct OBJGPU * arg0,struct OBJCL * arg1,struct PexL1SubstateCapability * arg2)586 static inline NV_STATUS clPcieReadL1SsCapability(struct OBJGPU *arg0, struct OBJCL *arg1, struct PexL1SubstateCapability *arg2) {
587 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
588 return NV_ERR_NOT_SUPPORTED;
589 }
590 #else //__nvoc_chipset_h_disabled
591 #define clPcieReadL1SsCapability(arg0, arg1, arg2) clPcieReadL1SsCapability_IMPL(arg0, arg1, arg2)
592 #endif //__nvoc_chipset_h_disabled
593
594 #define clPcieReadL1SsCapability_HAL(arg0, arg1, arg2) clPcieReadL1SsCapability(arg0, arg1, arg2)
595
596 NV_STATUS clPcieReadDevCtrlStatus_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 *arg2, NvU32 *arg3);
597
598
599 #ifdef __nvoc_chipset_h_disabled
clPcieReadDevCtrlStatus(struct OBJGPU * arg0,struct OBJCL * arg1,NvU32 * arg2,NvU32 * arg3)600 static inline NV_STATUS clPcieReadDevCtrlStatus(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 *arg2, NvU32 *arg3) {
601 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
602 return NV_ERR_NOT_SUPPORTED;
603 }
604 #else //__nvoc_chipset_h_disabled
605 #define clPcieReadDevCtrlStatus(arg0, arg1, arg2, arg3) clPcieReadDevCtrlStatus_IMPL(arg0, arg1, arg2, arg3)
606 #endif //__nvoc_chipset_h_disabled
607
608 #define clPcieReadDevCtrlStatus_HAL(arg0, arg1, arg2, arg3) clPcieReadDevCtrlStatus(arg0, arg1, arg2, arg3)
609
610 NV_STATUS clPcieClearDevCtrlStatus_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 *arg2);
611
612
613 #ifdef __nvoc_chipset_h_disabled
clPcieClearDevCtrlStatus(struct OBJGPU * arg0,struct OBJCL * arg1,NvU32 * arg2)614 static inline NV_STATUS clPcieClearDevCtrlStatus(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 *arg2) {
615 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
616 return NV_ERR_NOT_SUPPORTED;
617 }
618 #else //__nvoc_chipset_h_disabled
619 #define clPcieClearDevCtrlStatus(arg0, arg1, arg2) clPcieClearDevCtrlStatus_IMPL(arg0, arg1, arg2)
620 #endif //__nvoc_chipset_h_disabled
621
622 #define clPcieClearDevCtrlStatus_HAL(arg0, arg1, arg2) clPcieClearDevCtrlStatus(arg0, arg1, arg2)
623
624 NvU16 clPcieReadWord_IMPL(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5);
625
626
627 #ifdef __nvoc_chipset_h_disabled
clPcieReadWord(struct OBJCL * arg0,NvU32 arg1,NvU8 arg2,NvU8 arg3,NvU8 arg4,NvU32 arg5)628 static inline NvU16 clPcieReadWord(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5) {
629 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
630 return 0;
631 }
632 #else //__nvoc_chipset_h_disabled
633 #define clPcieReadWord(arg0, arg1, arg2, arg3, arg4, arg5) clPcieReadWord_IMPL(arg0, arg1, arg2, arg3, arg4, arg5)
634 #endif //__nvoc_chipset_h_disabled
635
636 #define clPcieReadWord_HAL(arg0, arg1, arg2, arg3, arg4, arg5) clPcieReadWord(arg0, arg1, arg2, arg3, arg4, arg5)
637
638 NvU32 clPcieReadDword_IMPL(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5);
639
640
641 #ifdef __nvoc_chipset_h_disabled
clPcieReadDword(struct OBJCL * arg0,NvU32 arg1,NvU8 arg2,NvU8 arg3,NvU8 arg4,NvU32 arg5)642 static inline NvU32 clPcieReadDword(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5) {
643 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
644 return 0;
645 }
646 #else //__nvoc_chipset_h_disabled
647 #define clPcieReadDword(arg0, arg1, arg2, arg3, arg4, arg5) clPcieReadDword_IMPL(arg0, arg1, arg2, arg3, arg4, arg5)
648 #endif //__nvoc_chipset_h_disabled
649
650 #define clPcieReadDword_HAL(arg0, arg1, arg2, arg3, arg4, arg5) clPcieReadDword(arg0, arg1, arg2, arg3, arg4, arg5)
651
652 void clPcieWriteWord_IMPL(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5, NvU16 arg6);
653
654
655 #ifdef __nvoc_chipset_h_disabled
clPcieWriteWord(struct OBJCL * arg0,NvU32 arg1,NvU8 arg2,NvU8 arg3,NvU8 arg4,NvU32 arg5,NvU16 arg6)656 static inline void clPcieWriteWord(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5, NvU16 arg6) {
657 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
658 }
659 #else //__nvoc_chipset_h_disabled
660 #define clPcieWriteWord(arg0, arg1, arg2, arg3, arg4, arg5, arg6) clPcieWriteWord_IMPL(arg0, arg1, arg2, arg3, arg4, arg5, arg6)
661 #endif //__nvoc_chipset_h_disabled
662
663 #define clPcieWriteWord_HAL(arg0, arg1, arg2, arg3, arg4, arg5, arg6) clPcieWriteWord(arg0, arg1, arg2, arg3, arg4, arg5, arg6)
664
665 void clPcieWriteDword_IMPL(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5, NvU32 arg6);
666
667
668 #ifdef __nvoc_chipset_h_disabled
clPcieWriteDword(struct OBJCL * arg0,NvU32 arg1,NvU8 arg2,NvU8 arg3,NvU8 arg4,NvU32 arg5,NvU32 arg6)669 static inline void clPcieWriteDword(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5, NvU32 arg6) {
670 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
671 }
672 #else //__nvoc_chipset_h_disabled
673 #define clPcieWriteDword(arg0, arg1, arg2, arg3, arg4, arg5, arg6) clPcieWriteDword_IMPL(arg0, arg1, arg2, arg3, arg4, arg5, arg6)
674 #endif //__nvoc_chipset_h_disabled
675
676 #define clPcieWriteDword_HAL(arg0, arg1, arg2, arg3, arg4, arg5, arg6) clPcieWriteDword(arg0, arg1, arg2, arg3, arg4, arg5, arg6)
677
678 NvBool clFindBR04_IMPL(POBJGPU *pGpus, NvU32 NumGpus, NvBool flat, NvU32 devId, struct OBJCL *pCl);
679
680
681 #ifdef __nvoc_chipset_h_disabled
clFindBR04(POBJGPU * pGpus,NvU32 NumGpus,NvBool flat,NvU32 devId,struct OBJCL * pCl)682 static inline NvBool clFindBR04(POBJGPU *pGpus, NvU32 NumGpus, NvBool flat, NvU32 devId, struct OBJCL *pCl) {
683 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
684 return NV_FALSE;
685 }
686 #else //__nvoc_chipset_h_disabled
687 #define clFindBR04(pGpus, NumGpus, flat, devId, pCl) clFindBR04_IMPL(pGpus, NumGpus, flat, devId, pCl)
688 #endif //__nvoc_chipset_h_disabled
689
690 #define clFindBR04_HAL(pGpus, NumGpus, flat, devId, pCl) clFindBR04(pGpus, NumGpus, flat, devId, pCl)
691
692 NV_STATUS clResumeBridge_IMPL(struct OBJCL *pCl);
693
694
695 #ifdef __nvoc_chipset_h_disabled
clResumeBridge(struct OBJCL * pCl)696 static inline NV_STATUS clResumeBridge(struct OBJCL *pCl) {
697 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
698 return NV_ERR_NOT_SUPPORTED;
699 }
700 #else //__nvoc_chipset_h_disabled
701 #define clResumeBridge(pCl) clResumeBridge_IMPL(pCl)
702 #endif //__nvoc_chipset_h_disabled
703
704 #define clResumeBridge_HAL(pCl) clResumeBridge(pCl)
705
706 NV_STATUS clChangeUpstreamBusSpeed_IMPL(NvU8 primaryBus, struct OBJCL *pCl, NvU32 cmd);
707
708
709 #ifdef __nvoc_chipset_h_disabled
clChangeUpstreamBusSpeed(NvU8 primaryBus,struct OBJCL * pCl,NvU32 cmd)710 static inline NV_STATUS clChangeUpstreamBusSpeed(NvU8 primaryBus, struct OBJCL *pCl, NvU32 cmd) {
711 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
712 return NV_ERR_NOT_SUPPORTED;
713 }
714 #else //__nvoc_chipset_h_disabled
715 #define clChangeUpstreamBusSpeed(primaryBus, pCl, cmd) clChangeUpstreamBusSpeed_IMPL(primaryBus, pCl, cmd)
716 #endif //__nvoc_chipset_h_disabled
717
718 #define clChangeUpstreamBusSpeed_HAL(primaryBus, pCl, cmd) clChangeUpstreamBusSpeed(primaryBus, pCl, cmd)
719
720 NV_STATUS clGetUpstreamBusSpeed_IMPL(NvU8 primaryBus, struct OBJCL *pCl, NvU32 *speed);
721
722
723 #ifdef __nvoc_chipset_h_disabled
clGetUpstreamBusSpeed(NvU8 primaryBus,struct OBJCL * pCl,NvU32 * speed)724 static inline NV_STATUS clGetUpstreamBusSpeed(NvU8 primaryBus, struct OBJCL *pCl, NvU32 *speed) {
725 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
726 return NV_ERR_NOT_SUPPORTED;
727 }
728 #else //__nvoc_chipset_h_disabled
729 #define clGetUpstreamBusSpeed(primaryBus, pCl, speed) clGetUpstreamBusSpeed_IMPL(primaryBus, pCl, speed)
730 #endif //__nvoc_chipset_h_disabled
731
732 #define clGetUpstreamBusSpeed_HAL(primaryBus, pCl, speed) clGetUpstreamBusSpeed(primaryBus, pCl, speed)
733
734 NV_STATUS clHWBCGetUpstreamBAR0_IMPL(NvU8 primaryBus, struct OBJCL *pCl, RmPhysAddr *pBAR0);
735
736
737 #ifdef __nvoc_chipset_h_disabled
clHWBCGetUpstreamBAR0(NvU8 primaryBus,struct OBJCL * pCl,RmPhysAddr * pBAR0)738 static inline NV_STATUS clHWBCGetUpstreamBAR0(NvU8 primaryBus, struct OBJCL *pCl, RmPhysAddr *pBAR0) {
739 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
740 return NV_ERR_NOT_SUPPORTED;
741 }
742 #else //__nvoc_chipset_h_disabled
743 #define clHWBCGetUpstreamBAR0(primaryBus, pCl, pBAR0) clHWBCGetUpstreamBAR0_IMPL(primaryBus, pCl, pBAR0)
744 #endif //__nvoc_chipset_h_disabled
745
746 #define clHWBCGetUpstreamBAR0_HAL(primaryBus, pCl, pBAR0) clHWBCGetUpstreamBAR0(primaryBus, pCl, pBAR0)
747
748 void *clFindP2PBrdg_IMPL(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 *arg3, NvU8 *arg4, NvU8 *arg5, NvU16 *arg6, NvU16 *arg7);
749
750
751 #ifdef __nvoc_chipset_h_disabled
clFindP2PBrdg(struct OBJCL * arg0,NvU32 arg1,NvU8 arg2,NvU8 * arg3,NvU8 * arg4,NvU8 * arg5,NvU16 * arg6,NvU16 * arg7)752 static inline void *clFindP2PBrdg(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 *arg3, NvU8 *arg4, NvU8 *arg5, NvU16 *arg6, NvU16 *arg7) {
753 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
754 return NULL;
755 }
756 #else //__nvoc_chipset_h_disabled
757 #define clFindP2PBrdg(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7) clFindP2PBrdg_IMPL(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
758 #endif //__nvoc_chipset_h_disabled
759
760 #define clFindP2PBrdg_HAL(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7) clFindP2PBrdg(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
761
762 void *clFindBrdgUpstreamPort_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvBool arg2, NvU8 *arg3, NvU8 *arg4, NvU8 *arg5, NvU16 *arg6, NvU16 *arg7, NvU8 *arg8);
763
764
765 #ifdef __nvoc_chipset_h_disabled
clFindBrdgUpstreamPort(struct OBJGPU * arg0,struct OBJCL * arg1,NvBool arg2,NvU8 * arg3,NvU8 * arg4,NvU8 * arg5,NvU16 * arg6,NvU16 * arg7,NvU8 * arg8)766 static inline void *clFindBrdgUpstreamPort(struct OBJGPU *arg0, struct OBJCL *arg1, NvBool arg2, NvU8 *arg3, NvU8 *arg4, NvU8 *arg5, NvU16 *arg6, NvU16 *arg7, NvU8 *arg8) {
767 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
768 return NULL;
769 }
770 #else //__nvoc_chipset_h_disabled
771 #define clFindBrdgUpstreamPort(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) clFindBrdgUpstreamPort_IMPL(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8)
772 #endif //__nvoc_chipset_h_disabled
773
774 #define clFindBrdgUpstreamPort_HAL(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) clFindBrdgUpstreamPort(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8)
775
776 NV_STATUS clSetPortPcieCapOffset_IMPL(struct OBJCL *arg0, void *arg1, NvU32 *arg2);
777
778
779 #ifdef __nvoc_chipset_h_disabled
clSetPortPcieCapOffset(struct OBJCL * arg0,void * arg1,NvU32 * arg2)780 static inline NV_STATUS clSetPortPcieCapOffset(struct OBJCL *arg0, void *arg1, NvU32 *arg2) {
781 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
782 return NV_ERR_NOT_SUPPORTED;
783 }
784 #else //__nvoc_chipset_h_disabled
785 #define clSetPortPcieCapOffset(arg0, arg1, arg2) clSetPortPcieCapOffset_IMPL(arg0, arg1, arg2)
786 #endif //__nvoc_chipset_h_disabled
787
788 #define clSetPortPcieCapOffset_HAL(arg0, arg1, arg2) clSetPortPcieCapOffset(arg0, arg1, arg2)
789
790 NV_STATUS clStorePcieConfigSpaceBaseFromMcfg_IMPL(struct OBJCL *pCl);
791
792
793 #ifdef __nvoc_chipset_h_disabled
clStorePcieConfigSpaceBaseFromMcfg(struct OBJCL * pCl)794 static inline NV_STATUS clStorePcieConfigSpaceBaseFromMcfg(struct OBJCL *pCl) {
795 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
796 return NV_ERR_NOT_SUPPORTED;
797 }
798 #else //__nvoc_chipset_h_disabled
799 #define clStorePcieConfigSpaceBaseFromMcfg(pCl) clStorePcieConfigSpaceBaseFromMcfg_IMPL(pCl)
800 #endif //__nvoc_chipset_h_disabled
801
802 #define clStorePcieConfigSpaceBaseFromMcfg_HAL(pCl) clStorePcieConfigSpaceBaseFromMcfg(pCl)
803
804 NV_STATUS clInsertPcieConfigSpaceBase_IMPL(struct OBJCL *arg0, RmPhysAddr arg1, NvU32 arg2, NvU8 arg3, NvU8 arg4);
805
806
807 #ifdef __nvoc_chipset_h_disabled
clInsertPcieConfigSpaceBase(struct OBJCL * arg0,RmPhysAddr arg1,NvU32 arg2,NvU8 arg3,NvU8 arg4)808 static inline NV_STATUS clInsertPcieConfigSpaceBase(struct OBJCL *arg0, RmPhysAddr arg1, NvU32 arg2, NvU8 arg3, NvU8 arg4) {
809 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
810 return NV_ERR_NOT_SUPPORTED;
811 }
812 #else //__nvoc_chipset_h_disabled
813 #define clInsertPcieConfigSpaceBase(arg0, arg1, arg2, arg3, arg4) clInsertPcieConfigSpaceBase_IMPL(arg0, arg1, arg2, arg3, arg4)
814 #endif //__nvoc_chipset_h_disabled
815
816 #define clInsertPcieConfigSpaceBase_HAL(arg0, arg1, arg2, arg3, arg4) clInsertPcieConfigSpaceBase(arg0, arg1, arg2, arg3, arg4)
817
818 RmPhysAddr clFindPcieConfigSpaceBase_IMPL(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2);
819
820
821 #ifdef __nvoc_chipset_h_disabled
clFindPcieConfigSpaceBase(struct OBJCL * arg0,NvU32 arg1,NvU8 arg2)822 static inline RmPhysAddr clFindPcieConfigSpaceBase(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2) {
823 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
824 RmPhysAddr ret;
825 portMemSet(&ret, 0, sizeof(RmPhysAddr));
826 return ret;
827 }
828 #else //__nvoc_chipset_h_disabled
829 #define clFindPcieConfigSpaceBase(arg0, arg1, arg2) clFindPcieConfigSpaceBase_IMPL(arg0, arg1, arg2)
830 #endif //__nvoc_chipset_h_disabled
831
832 #define clFindPcieConfigSpaceBase_HAL(arg0, arg1, arg2) clFindPcieConfigSpaceBase(arg0, arg1, arg2)
833
834 void clFreePcieConfigSpaceBase_IMPL(struct OBJCL *pCl);
835
836
837 #ifdef __nvoc_chipset_h_disabled
clFreePcieConfigSpaceBase(struct OBJCL * pCl)838 static inline void clFreePcieConfigSpaceBase(struct OBJCL *pCl) {
839 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
840 }
841 #else //__nvoc_chipset_h_disabled
842 #define clFreePcieConfigSpaceBase(pCl) clFreePcieConfigSpaceBase_IMPL(pCl)
843 #endif //__nvoc_chipset_h_disabled
844
845 #define clFreePcieConfigSpaceBase_HAL(pCl) clFreePcieConfigSpaceBase(pCl)
846
847 NV_STATUS clInitDeviceInfo_IMPL(struct OBJCL *arg0, struct OBJGPU *arg1);
848
849
850 #ifdef __nvoc_chipset_h_disabled
clInitDeviceInfo(struct OBJCL * arg0,struct OBJGPU * arg1)851 static inline NV_STATUS clInitDeviceInfo(struct OBJCL *arg0, struct OBJGPU *arg1) {
852 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
853 return NV_ERR_NOT_SUPPORTED;
854 }
855 #else //__nvoc_chipset_h_disabled
856 #define clInitDeviceInfo(arg0, arg1) clInitDeviceInfo_IMPL(arg0, arg1)
857 #endif //__nvoc_chipset_h_disabled
858
859 #define clInitDeviceInfo_HAL(arg0, arg1) clInitDeviceInfo(arg0, arg1)
860
861 void clCountBR_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2);
862
863
864 #ifdef __nvoc_chipset_h_disabled
clCountBR(struct OBJGPU * arg0,struct OBJCL * arg1,NvU8 * arg2)865 static inline void clCountBR(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2) {
866 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
867 }
868 #else //__nvoc_chipset_h_disabled
869 #define clCountBR(arg0, arg1, arg2) clCountBR_IMPL(arg0, arg1, arg2)
870 #endif //__nvoc_chipset_h_disabled
871
872 #define clCountBR_HAL(arg0, arg1, arg2) clCountBR(arg0, arg1, arg2)
873
874 void clFindCommonBR_IMPL(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pBR04Bus, NvBool bScanAll);
875
876
877 #ifdef __nvoc_chipset_h_disabled
clFindCommonBR(struct OBJGPU * pGpu1,struct OBJGPU * pGpu2,struct OBJCL * pCl,NvU8 * pBR04Bus,NvBool bScanAll)878 static inline void clFindCommonBR(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pBR04Bus, NvBool bScanAll) {
879 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
880 }
881 #else //__nvoc_chipset_h_disabled
882 #define clFindCommonBR(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll) clFindCommonBR_IMPL(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll)
883 #endif //__nvoc_chipset_h_disabled
884
885 #define clFindCommonBR_HAL(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll) clFindCommonBR(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll)
886
887 void clFindCommonDownstreamBR_IMPL(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pPciSwitchBus);
888
889
890 #ifdef __nvoc_chipset_h_disabled
clFindCommonDownstreamBR(struct OBJGPU * pGpu1,struct OBJGPU * pGpu2,struct OBJCL * pCl,NvU8 * pPciSwitchBus)891 static inline void clFindCommonDownstreamBR(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pPciSwitchBus) {
892 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
893 }
894 #else //__nvoc_chipset_h_disabled
895 #define clFindCommonDownstreamBR(pGpu1, pGpu2, pCl, pPciSwitchBus) clFindCommonDownstreamBR_IMPL(pGpu1, pGpu2, pCl, pPciSwitchBus)
896 #endif //__nvoc_chipset_h_disabled
897
898 #define clFindCommonDownstreamBR_HAL(pGpu1, pGpu2, pCl, pPciSwitchBus) clFindCommonDownstreamBR(pGpu1, pGpu2, pCl, pPciSwitchBus)
899
900 void clFindBR_IMPL(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvBool *pBRNotBR04A03, NvBool *pNoUnsupportedBRFound, NvBool *pNoOnboardBR04);
901
902
903 #ifdef __nvoc_chipset_h_disabled
clFindBR(struct OBJGPU * pGpu,struct OBJCL * pCl,NvU8 * pBR03Bus,NvU8 * pBR04Bus,NvBool * pBRNotBR04A03,NvBool * pNoUnsupportedBRFound,NvBool * pNoOnboardBR04)904 static inline void clFindBR(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvBool *pBRNotBR04A03, NvBool *pNoUnsupportedBRFound, NvBool *pNoOnboardBR04) {
905 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
906 }
907 #else //__nvoc_chipset_h_disabled
908 #define clFindBR(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04) clFindBR_IMPL(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04)
909 #endif //__nvoc_chipset_h_disabled
910
911 #define clFindBR_HAL(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04) clFindBR(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04)
912
913 void clSearchBR04_IMPL(struct OBJCL *pCl, NvU8 *pBR04BusArray, NvU8 *pBR04RevArray, NvU8 *pBR04Count);
914
915
916 #ifdef __nvoc_chipset_h_disabled
clSearchBR04(struct OBJCL * pCl,NvU8 * pBR04BusArray,NvU8 * pBR04RevArray,NvU8 * pBR04Count)917 static inline void clSearchBR04(struct OBJCL *pCl, NvU8 *pBR04BusArray, NvU8 *pBR04RevArray, NvU8 *pBR04Count) {
918 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
919 }
920 #else //__nvoc_chipset_h_disabled
921 #define clSearchBR04(pCl, pBR04BusArray, pBR04RevArray, pBR04Count) clSearchBR04_IMPL(pCl, pBR04BusArray, pBR04RevArray, pBR04Count)
922 #endif //__nvoc_chipset_h_disabled
923
924 #define clSearchBR04_HAL(pCl, pBR04BusArray, pBR04RevArray, pBR04Count) clSearchBR04(pCl, pBR04BusArray, pBR04RevArray, pBR04Count)
925
926 NV_STATUS clPcieGetMaxCapableLinkWidth_IMPL(struct OBJCL *pCl, struct OBJGPU *pGpu, NvU32 *maxCapableLinkWidth);
927
928
929 #ifdef __nvoc_chipset_h_disabled
clPcieGetMaxCapableLinkWidth(struct OBJCL * pCl,struct OBJGPU * pGpu,NvU32 * maxCapableLinkWidth)930 static inline NV_STATUS clPcieGetMaxCapableLinkWidth(struct OBJCL *pCl, struct OBJGPU *pGpu, NvU32 *maxCapableLinkWidth) {
931 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
932 return NV_ERR_NOT_SUPPORTED;
933 }
934 #else //__nvoc_chipset_h_disabled
935 #define clPcieGetMaxCapableLinkWidth(pCl, pGpu, maxCapableLinkWidth) clPcieGetMaxCapableLinkWidth_IMPL(pCl, pGpu, maxCapableLinkWidth)
936 #endif //__nvoc_chipset_h_disabled
937
938 #define clPcieGetMaxCapableLinkWidth_HAL(pCl, pGpu, maxCapableLinkWidth) clPcieGetMaxCapableLinkWidth(pCl, pGpu, maxCapableLinkWidth)
939
940 NV_STATUS clPcieIsRelaxedOrderingSafe_IMPL(struct OBJCL *pCl, struct OBJGPU *pGpu, NvBool *result);
941
942
943 #ifdef __nvoc_chipset_h_disabled
clPcieIsRelaxedOrderingSafe(struct OBJCL * pCl,struct OBJGPU * pGpu,NvBool * result)944 static inline NV_STATUS clPcieIsRelaxedOrderingSafe(struct OBJCL *pCl, struct OBJGPU *pGpu, NvBool *result) {
945 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
946 return NV_ERR_NOT_SUPPORTED;
947 }
948 #else //__nvoc_chipset_h_disabled
949 #define clPcieIsRelaxedOrderingSafe(pCl, pGpu, result) clPcieIsRelaxedOrderingSafe_IMPL(pCl, pGpu, result)
950 #endif //__nvoc_chipset_h_disabled
951
952 #define clPcieIsRelaxedOrderingSafe_HAL(pCl, pGpu, result) clPcieIsRelaxedOrderingSafe(pCl, pGpu, result)
953
954 NV_STATUS clStoreBusTopologyCache_IMPL(struct OBJCL *pCl, NvU32 secDomain, NvU16 secBus);
955
956
957 #ifdef __nvoc_chipset_h_disabled
clStoreBusTopologyCache(struct OBJCL * pCl,NvU32 secDomain,NvU16 secBus)958 static inline NV_STATUS clStoreBusTopologyCache(struct OBJCL *pCl, NvU32 secDomain, NvU16 secBus) {
959 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
960 return NV_ERR_NOT_SUPPORTED;
961 }
962 #else //__nvoc_chipset_h_disabled
963 #define clStoreBusTopologyCache(pCl, secDomain, secBus) clStoreBusTopologyCache_IMPL(pCl, secDomain, secBus)
964 #endif //__nvoc_chipset_h_disabled
965
966 #define clStoreBusTopologyCache_HAL(pCl, secDomain, secBus) clStoreBusTopologyCache(pCl, secDomain, secBus)
967
968 void clFreeBusTopologyCache_IMPL(struct OBJCL *pCl);
969
970
971 #ifdef __nvoc_chipset_h_disabled
clFreeBusTopologyCache(struct OBJCL * pCl)972 static inline void clFreeBusTopologyCache(struct OBJCL *pCl) {
973 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
974 }
975 #else //__nvoc_chipset_h_disabled
976 #define clFreeBusTopologyCache(pCl) clFreeBusTopologyCache_IMPL(pCl)
977 #endif //__nvoc_chipset_h_disabled
978
979 #define clFreeBusTopologyCache_HAL(pCl) clFreeBusTopologyCache(pCl)
980
981 NvBool clIsL1MaskEnabledForUpstreamPort_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1);
982
983
984 #ifdef __nvoc_chipset_h_disabled
clIsL1MaskEnabledForUpstreamPort(struct OBJGPU * arg0,struct OBJCL * arg1)985 static inline NvBool clIsL1MaskEnabledForUpstreamPort(struct OBJGPU *arg0, struct OBJCL *arg1) {
986 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
987 return NV_FALSE;
988 }
989 #else //__nvoc_chipset_h_disabled
990 #define clIsL1MaskEnabledForUpstreamPort(arg0, arg1) clIsL1MaskEnabledForUpstreamPort_IMPL(arg0, arg1)
991 #endif //__nvoc_chipset_h_disabled
992
993 #define clIsL1MaskEnabledForUpstreamPort_HAL(arg0, arg1) clIsL1MaskEnabledForUpstreamPort(arg0, arg1)
994
995 NvBool clIsL0sMaskEnabledForUpstreamPort_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1);
996
997
998 #ifdef __nvoc_chipset_h_disabled
clIsL0sMaskEnabledForUpstreamPort(struct OBJGPU * arg0,struct OBJCL * arg1)999 static inline NvBool clIsL0sMaskEnabledForUpstreamPort(struct OBJGPU *arg0, struct OBJCL *arg1) {
1000 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1001 return NV_FALSE;
1002 }
1003 #else //__nvoc_chipset_h_disabled
1004 #define clIsL0sMaskEnabledForUpstreamPort(arg0, arg1) clIsL0sMaskEnabledForUpstreamPort_IMPL(arg0, arg1)
1005 #endif //__nvoc_chipset_h_disabled
1006
1007 #define clIsL0sMaskEnabledForUpstreamPort_HAL(arg0, arg1) clIsL0sMaskEnabledForUpstreamPort(arg0, arg1)
1008
1009 NV_STATUS clControlL0sL1LinkControlUpstreamPort_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvBool arg2);
1010
1011
1012 #ifdef __nvoc_chipset_h_disabled
clControlL0sL1LinkControlUpstreamPort(struct OBJGPU * arg0,struct OBJCL * arg1,NvBool arg2)1013 static inline NV_STATUS clControlL0sL1LinkControlUpstreamPort(struct OBJGPU *arg0, struct OBJCL *arg1, NvBool arg2) {
1014 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1015 return NV_ERR_NOT_SUPPORTED;
1016 }
1017 #else //__nvoc_chipset_h_disabled
1018 #define clControlL0sL1LinkControlUpstreamPort(arg0, arg1, arg2) clControlL0sL1LinkControlUpstreamPort_IMPL(arg0, arg1, arg2)
1019 #endif //__nvoc_chipset_h_disabled
1020
1021 #define clControlL0sL1LinkControlUpstreamPort_HAL(arg0, arg1, arg2) clControlL0sL1LinkControlUpstreamPort(arg0, arg1, arg2)
1022
1023 NV_STATUS clChipsetAspmPublicControl_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 arg2);
1024
1025
1026 #ifdef __nvoc_chipset_h_disabled
clChipsetAspmPublicControl(struct OBJGPU * arg0,struct OBJCL * arg1,NvU32 arg2)1027 static inline NV_STATUS clChipsetAspmPublicControl(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 arg2) {
1028 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1029 return NV_ERR_NOT_SUPPORTED;
1030 }
1031 #else //__nvoc_chipset_h_disabled
1032 #define clChipsetAspmPublicControl(arg0, arg1, arg2) clChipsetAspmPublicControl_IMPL(arg0, arg1, arg2)
1033 #endif //__nvoc_chipset_h_disabled
1034
1035 #define clChipsetAspmPublicControl_HAL(arg0, arg1, arg2) clChipsetAspmPublicControl(arg0, arg1, arg2)
1036
1037 NvBool clRootportNeedsNosnoopWAR_FWCLIENT(struct OBJGPU *arg0, struct OBJCL *arg1);
1038
1039
1040 #ifdef __nvoc_chipset_h_disabled
clRootportNeedsNosnoopWAR(struct OBJGPU * arg0,struct OBJCL * arg1)1041 static inline NvBool clRootportNeedsNosnoopWAR(struct OBJGPU *arg0, struct OBJCL *arg1) {
1042 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1043 return NV_FALSE;
1044 }
1045 #else //__nvoc_chipset_h_disabled
1046 #define clRootportNeedsNosnoopWAR(arg0, arg1) clRootportNeedsNosnoopWAR_FWCLIENT(arg0, arg1)
1047 #endif //__nvoc_chipset_h_disabled
1048
1049 #define clRootportNeedsNosnoopWAR_HAL(arg0, arg1) clRootportNeedsNosnoopWAR(arg0, arg1)
1050
1051 NvU16 clPcieGetGpuLostDiagnosticData_IMPL(struct OBJGPU *pGpu, struct OBJCL *arg0, NvU8 *pBuffer, NvU32 size);
1052
1053
1054 #ifdef __nvoc_chipset_h_disabled
clPcieGetGpuLostDiagnosticData(struct OBJGPU * pGpu,struct OBJCL * arg0,NvU8 * pBuffer,NvU32 size)1055 static inline NvU16 clPcieGetGpuLostDiagnosticData(struct OBJGPU *pGpu, struct OBJCL *arg0, NvU8 *pBuffer, NvU32 size) {
1056 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1057 return 0;
1058 }
1059 #else //__nvoc_chipset_h_disabled
1060 #define clPcieGetGpuLostDiagnosticData(pGpu, arg0, pBuffer, size) clPcieGetGpuLostDiagnosticData_IMPL(pGpu, arg0, pBuffer, size)
1061 #endif //__nvoc_chipset_h_disabled
1062
1063 #define clPcieGetGpuLostDiagnosticData_HAL(pGpu, arg0, pBuffer, size) clPcieGetGpuLostDiagnosticData(pGpu, arg0, pBuffer, size)
1064
1065 NvU32 clGetChipsetL1ClockPMSupport_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1);
1066
1067
1068 #ifdef __nvoc_chipset_h_disabled
clGetChipsetL1ClockPMSupport(struct OBJGPU * arg0,struct OBJCL * arg1)1069 static inline NvU32 clGetChipsetL1ClockPMSupport(struct OBJGPU *arg0, struct OBJCL *arg1) {
1070 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1071 return 0;
1072 }
1073 #else //__nvoc_chipset_h_disabled
1074 #define clGetChipsetL1ClockPMSupport(arg0, arg1) clGetChipsetL1ClockPMSupport_IMPL(arg0, arg1)
1075 #endif //__nvoc_chipset_h_disabled
1076
1077 #define clGetChipsetL1ClockPMSupport_HAL(arg0, arg1) clGetChipsetL1ClockPMSupport(arg0, arg1)
1078
1079 NV_STATUS clConstruct_IMPL(struct OBJCL *arg_pCl);
1080
1081 #define __nvoc_clConstruct(arg_pCl) clConstruct_IMPL(arg_pCl)
1082 void clDestruct_IMPL(struct OBJCL *pCl);
1083
1084 #define __nvoc_clDestruct(pCl) clDestruct_IMPL(pCl)
1085 NvBool clUpstreamVgaDecodeEnabled_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1);
1086
1087 #ifdef __nvoc_chipset_h_disabled
clUpstreamVgaDecodeEnabled(struct OBJGPU * arg0,struct OBJCL * arg1)1088 static inline NvBool clUpstreamVgaDecodeEnabled(struct OBJGPU *arg0, struct OBJCL *arg1) {
1089 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1090 return NV_FALSE;
1091 }
1092 #else //__nvoc_chipset_h_disabled
1093 #define clUpstreamVgaDecodeEnabled(arg0, arg1) clUpstreamVgaDecodeEnabled_IMPL(arg0, arg1)
1094 #endif //__nvoc_chipset_h_disabled
1095
1096 NV_STATUS clPcieGetRootGenSpeed_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2);
1097
1098 #ifdef __nvoc_chipset_h_disabled
clPcieGetRootGenSpeed(struct OBJGPU * arg0,struct OBJCL * arg1,NvU8 * arg2)1099 static inline NV_STATUS clPcieGetRootGenSpeed(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2) {
1100 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1101 return NV_ERR_NOT_SUPPORTED;
1102 }
1103 #else //__nvoc_chipset_h_disabled
1104 #define clPcieGetRootGenSpeed(arg0, arg1, arg2) clPcieGetRootGenSpeed_IMPL(arg0, arg1, arg2)
1105 #endif //__nvoc_chipset_h_disabled
1106
1107 NV_STATUS clPcieGetDownstreamPortLinkCap2_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 *arg2);
1108
1109 #ifdef __nvoc_chipset_h_disabled
clPcieGetDownstreamPortLinkCap2(struct OBJGPU * arg0,struct OBJCL * arg1,NvU32 * arg2)1110 static inline NV_STATUS clPcieGetDownstreamPortLinkCap2(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 *arg2) {
1111 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1112 return NV_ERR_NOT_SUPPORTED;
1113 }
1114 #else //__nvoc_chipset_h_disabled
1115 #define clPcieGetDownstreamPortLinkCap2(arg0, arg1, arg2) clPcieGetDownstreamPortLinkCap2_IMPL(arg0, arg1, arg2)
1116 #endif //__nvoc_chipset_h_disabled
1117
1118 NV_STATUS clCheckUpstreamLtrSupport_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvBool *arg2);
1119
1120 #ifdef __nvoc_chipset_h_disabled
clCheckUpstreamLtrSupport(struct OBJGPU * arg0,struct OBJCL * arg1,NvBool * arg2)1121 static inline NV_STATUS clCheckUpstreamLtrSupport(struct OBJGPU *arg0, struct OBJCL *arg1, NvBool *arg2) {
1122 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1123 return NV_ERR_NOT_SUPPORTED;
1124 }
1125 #else //__nvoc_chipset_h_disabled
1126 #define clCheckUpstreamLtrSupport(arg0, arg1, arg2) clCheckUpstreamLtrSupport_IMPL(arg0, arg1, arg2)
1127 #endif //__nvoc_chipset_h_disabled
1128
1129 NV_STATUS clGetAtomicTypesSupported_IMPL(NvU32 arg0, NvU8 arg1, struct OBJCL *arg2, NvU32 *arg3);
1130
1131 #ifdef __nvoc_chipset_h_disabled
clGetAtomicTypesSupported(NvU32 arg0,NvU8 arg1,struct OBJCL * arg2,NvU32 * arg3)1132 static inline NV_STATUS clGetAtomicTypesSupported(NvU32 arg0, NvU8 arg1, struct OBJCL *arg2, NvU32 *arg3) {
1133 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1134 return NV_ERR_NOT_SUPPORTED;
1135 }
1136 #else //__nvoc_chipset_h_disabled
1137 #define clGetAtomicTypesSupported(arg0, arg1, arg2, arg3) clGetAtomicTypesSupported_IMPL(arg0, arg1, arg2, arg3)
1138 #endif //__nvoc_chipset_h_disabled
1139
1140 void clSyncWithGsp_IMPL(struct OBJCL *arg0, GspSystemInfo *arg1);
1141
1142 #ifdef __nvoc_chipset_h_disabled
clSyncWithGsp(struct OBJCL * arg0,GspSystemInfo * arg1)1143 static inline void clSyncWithGsp(struct OBJCL *arg0, GspSystemInfo *arg1) {
1144 NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
1145 }
1146 #else //__nvoc_chipset_h_disabled
1147 #define clSyncWithGsp(arg0, arg1) clSyncWithGsp_IMPL(arg0, arg1)
1148 #endif //__nvoc_chipset_h_disabled
1149
1150 #undef PRIVATE_FIELD
1151
1152
1153 #endif // CHIPSET_H
1154
1155 #ifdef __cplusplus
1156 } // extern "C"
1157 #endif
1158
1159 #endif // _G_CHIPSET_NVOC_H_
1160