1 /* $NetBSD: pdqreg.h,v 1.19 2008/06/24 10:12:06 gmcgarry Exp $ */ 2 3 /*- 4 * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Id: pdqreg.h,v 1.11 1997/03/21 21:16:04 thomas Exp 27 * 28 */ 29 30 /* 31 * DEC PDQ FDDI Controller; PDQ port driver definitions 32 * 33 */ 34 35 #ifndef _PDQREG_H 36 #define _PDQREG_H 37 38 #if !defined(KERNEL) && !defined(_KERNEL) 39 #include <stddef.h> 40 #elif !defined(offsetof) 41 #define offsetof(t, m) ((char *) (&((t *)0L)->m) - (char *) 0L) 42 #endif 43 #if defined(PDQTEST) && !defined(PDQ_NDEBUG) 44 #include <assert.h> 45 #define PDQ_ASSERT assert 46 #else 47 #define PDQ_ASSERT(x) do { } while(0) 48 #endif 49 50 #define PDQ_RING_SIZE(array) ((sizeof(array) / sizeof(array[0]))) 51 #define PDQ_ARRAY_SIZE(array) ((sizeof(array) / sizeof(array[0]))) 52 #define PDQ_RING_MASK(array) (PDQ_RING_SIZE(array) - 1) 53 #define PDQ_BITMASK(n) (1L << (pdq_uint32_t) (n)) 54 55 #define PDQ_FDDI_MAX 4495 56 #define PDQ_FDDI_LLC_MIN 20 57 #define PDQ_FDDI_SMT_MIN 37 58 59 #define PDQ_FDDI_SMT 0x40 60 #define PDQ_FDDI_LLC_ASYNC 0x50 61 #define PDQ_FDDI_LLC_SYNC 0xD0 62 #define PDQ_FDDI_IMP_ASYNC 0x60 63 #define PDQ_FDDI_IMP_SYNC 0xE0 64 65 #define PDQ_FDDIFC_C 0x80 66 #define PDQ_FDDIFC_L 0x40 67 #define PDQ_FDDIFC_F 0x30 68 #define PDQ_FDDIFC_Z 0x0F 69 70 #define PDQ_FDDI_PH0 0x20 71 #define PDQ_FDDI_PH1 0x38 72 #define PDQ_FDDI_PH2 0x00 73 74 typedef pdq_uint32_t pdq_physaddr_t; 75 76 struct _pdq_lanaddr_t { 77 pdq_uint8_t lanaddr_bytes[8]; 78 }; 79 80 typedef struct { 81 pdq_uint8_t fwrev_bytes[4]; 82 } pdq_fwrev_t; 83 84 struct _pdq_csrs_t { 85 pdq_bus_memoffset_t csr_port_reset; /* 0x00 [RW] */ 86 pdq_bus_memoffset_t csr_host_data; /* 0x04 [R] */ 87 pdq_bus_memoffset_t csr_port_control; /* 0x08 [RW] */ 88 pdq_bus_memoffset_t csr_port_data_a; /* 0x0C [RW] */ 89 pdq_bus_memoffset_t csr_port_data_b; /* 0x10 [RW] */ 90 pdq_bus_memoffset_t csr_port_status; /* 0x14 [R] */ 91 pdq_bus_memoffset_t csr_host_int_type_0; /* 0x18 [RW] */ 92 pdq_bus_memoffset_t csr_host_int_enable; /* 0x1C [RW] */ 93 pdq_bus_memoffset_t csr_type_2_producer; /* 0x20 [RW] */ 94 pdq_bus_memoffset_t csr_cmd_response_producer; /* 0x28 [RW] */ 95 pdq_bus_memoffset_t csr_cmd_request_producer; /* 0x2C [RW] */ 96 pdq_bus_memoffset_t csr_host_smt_producer; /* 0x30 [RW] */ 97 pdq_bus_memoffset_t csr_unsolicited_producer; /* 0x34 [RW] */ 98 pdq_bus_t csr_bus; 99 pdq_bus_memaddr_t csr_base; 100 }; 101 102 struct _pdq_pci_csrs_t { 103 pdq_bus_memoffset_t csr_pfi_mode_control; /* 0x40 [RW] */ 104 pdq_bus_memoffset_t csr_pfi_status; /* 0x44 [RW] */ 105 pdq_bus_memoffset_t csr_fifo_write; /* 0x48 [RW] */ 106 pdq_bus_memoffset_t csr_fifo_read; /* 0x4C [RW] */ 107 pdq_bus_t csr_bus; 108 pdq_bus_memaddr_t csr_base; 109 }; 110 111 #define PDQ_PFI_MODE_DMA_ENABLE 0x01 /* DMA Enable */ 112 #define PDQ_PFI_MODE_PFI_PCI_INTR 0x02 /* PFI-to-PCI Int Enable */ 113 #define PDQ_PFI_MODE_PDQ_PCI_INTR 0x04 /* PDQ-to-PCI Int Enable */ 114 115 #define PDQ_PFI_STATUS_PDQ_INTR 0x10 /* PDQ Int received */ 116 #define PDQ_PFI_STATUS_DMA_ABORT 0x08 /* PDQ DMA Abort asserted */ 117 118 #define PDQ_EISA_BURST_HOLDOFF 0x0040 119 #define PDQ_EISA_SLOT_ID 0x0C80 120 #define PDQ_EISA_SLOT_CTRL 0x0C84 121 #define PDQ_EISA_MEM_ADD_CMP_0 0x0C85 122 #define PDQ_EISA_MEM_ADD_CMP_1 0x0C86 123 #define PDQ_EISA_MEM_ADD_CMP_2 0x0C87 124 #define PDQ_EISA_MEM_ADD_HI_CMP_0 0x0C88 125 #define PDQ_EISA_MEM_ADD_HI_CMP_1 0x0C89 126 #define PDQ_EISA_MEM_ADD_HI_CMP_2 0x0C8A 127 #define PDQ_EISA_MEM_ADD_MASK_0 0x0C8B 128 #define PDQ_EISA_MEM_ADD_MASK_1 0x0C8C 129 #define PDQ_EISA_MEM_ADD_MASK_2 0x0C8D 130 #define PDQ_EISA_MEM_ADD_LO_CMP_0 0x0C8E 131 #define PDQ_EISA_MEM_ADD_LO_CMP_1 0x0C8F 132 #define PDQ_EISA_MEM_ADD_LO_CMP_2 0x0C90 133 #define PDQ_EISA_IO_CMP_0_0 0x0C91 134 #define PDQ_EISA_IO_CMP_0_1 0x0C92 135 #define PDQ_EISA_IO_CMP_1_0 0x0C93 136 #define PDQ_EISA_IO_CMP_1_1 0x0C94 137 #define PDQ_EISA_IO_CMP_2_0 0x0C95 138 #define PDQ_EISA_IO_CMP_2_1 0x0C96 139 #define PDQ_EISA_IO_CMP_3_0 0x0C97 140 #define PDQ_EISA_IO_CMP_3_1 0x0C98 141 #define PDQ_EISA_IO_ADD_MASK_0_0 0x0C99 142 #define PDQ_EISA_IO_ADD_MASK_0_1 0x0C9A 143 #define PDQ_EISA_IO_ADD_MASK_1_0 0x0C9B 144 #define PDQ_EISA_IO_ADD_MASK_1_1 0x0C9C 145 #define PDQ_EISA_IO_ADD_MASK_2_0 0x0C9D 146 #define PDQ_EISA_IO_ADD_MASK_2_1 0x0C9E 147 #define PDQ_EISA_IO_ADD_MASK_3_0 0x0C9F 148 #define PDQ_EISA_IO_ADD_MASK_3_1 0x0CA0 149 #define PDQ_EISA_MOD_CONFIG_1 0x0CA1 150 #define PDQ_EISA_MOD_CONFIG_2 0x0CA2 151 #define PDQ_EISA_MOD_CONFIG_3 0x0CA3 152 #define PDQ_EISA_MOD_CONFIG_4 0x0CA4 153 #define PDQ_EISA_MOD_CONFIG_5 0x0CA5 154 #define PDQ_EISA_MOD_CONFIG_6 0x0CA6 155 #define PDQ_EISA_MOD_CONFIG_7 0x0CA7 156 #define PDQ_EISA_DIP_SWITCH 0x0CA8 157 #define PDQ_EISA_IO_CONFIG_STAT_0 0x0CA9 158 #define PDQ_EISA_IO_CONFIG_STAT_1 0x0CAA 159 #define PDQ_EISA_DMA_CONFIG 0x0CAB 160 #define PDQ_EISA_INPUT_PORT 0x0CAC 161 #define PDQ_EISA_OUTPUT_PORT 0x0CAD 162 #define PDQ_EISA_FUNCTION_CTRL 0x0CAE 163 164 #define PDQ_TC_CSR_OFFSET 0x00100000 165 #define PDQ_TC_CSR_SPACE 0x0040 166 #define PDQ_FBUS_CSR_OFFSET 0x00200000 167 #define PDQ_FBUS_CSR_SPACE 0x0080 168 169 /* 170 * Port Reset Data A Definitions 171 */ 172 #define PDQ_PRESET_SKIP_SELFTEST 0x0004 173 #define PDQ_PRESET_SOFT_RESET 0x0002 174 #define PDQ_PRESET_UPGRADE 0x0001 175 /* 176 * Port Control Register Definitions 177 */ 178 #define PDQ_PCTL_CMD_ERROR 0x8000 179 #define PDQ_PCTL_FLASH_BLAST 0x4000 180 #define PDQ_PCTL_HALT 0x2000 181 #define PDQ_PCTL_COPY_DATA 0x1000 182 #define PDQ_PCTL_ERROR_LOG_START 0x0800 183 #define PDQ_PCTL_ERROR_LOG_READ 0x0400 184 #define PDQ_PCTL_XMT_DATA_FLUSH_DONE 0x0200 185 #define PDQ_PCTL_DMA_INIT 0x0100 186 #define PDQ_DMA_INIT_LW_BSWAP_DATA 0x02 187 #define PDQ_DMA_INIT_LW_BSWAP_LITERAL 0x01 188 #define PDQ_PCTL_INIT_START 0x0080 189 #define PDQ_PCTL_CONSUMER_BLOCK 0x0040 190 #define PDQ_PCTL_DMA_UNINIT 0x0020 191 #define PDQ_PCTL_RING_MEMBER 0x0010 192 #define PDQ_PCTL_MLA_READ 0x0008 193 #define PDQ_PCTL_FW_REV_READ 0x0004 194 #define PDQ_PCTL_DEVICE_SPECIFIC 0x0002 195 #define PDQ_PCTL_SUB_CMD 0x0001 196 197 typedef enum { 198 PDQ_SUB_CMD_LINK_UNINIT=1, 199 PDQ_SUB_CMD_DMA_BURST_SIZE_SET=2, 200 PDQ_SUB_CMD_PDQ_REV_GET=4 201 } pdq_sub_cmd_t; 202 203 typedef enum { 204 PDQ_DMA_BURST_4LW=0, 205 PDQ_DMA_BURST_8LW=1, 206 PDQ_DMA_BURST_16LW=2, 207 PDQ_DMA_BURST_32LW=3 208 } pdq_dma_burst_size_t; 209 210 typedef enum { 211 PDQ_CHIP_REV_A_B_OR_C=0, 212 PDQ_CHIP_REV_D=2, 213 PDQ_CHIP_REV_E=4 214 } pdq_chip_rev_t; 215 /* 216 * Port Status Register Definitions 217 */ 218 #define PDQ_PSTS_RCV_DATA_PENDING 0x80000000ul 219 #define PDQ_PSTS_XMT_DATA_PENDING 0x40000000ul 220 #define PDQ_PSTS_HOST_SMT_PENDING 0x20000000ul 221 #define PDQ_PSTS_UNSOL_PENDING 0x10000000ul 222 #define PDQ_PSTS_CMD_RSP_PENDING 0x08000000ul 223 #define PDQ_PSTS_CMD_REQ_PENDING 0x04000000ul 224 #define PDQ_PSTS_TYPE_0_PENDING 0x02000000ul 225 #define PDQ_PSTS_INTR_PENDING 0xFE000000ul 226 #define PDQ_PSTS_ADAPTER_STATE(sts) ((pdq_state_t) (((sts) >> 8) & 0x07)) 227 #define PDQ_PSTS_HALT_ID(sts) ((pdq_halt_code_t) ((sts) & 0xFF)) 228 /* 229 * Host Interrupt Register Definitions 230 */ 231 #define PDQ_HOST_INT_TX_ENABLE 0x80000000ul 232 #define PDQ_HOST_INT_RX_ENABLE 0x40000000ul 233 #define PDQ_HOST_INT_UNSOL_ENABLE 0x20000000ul 234 #define PDQ_HOST_INT_HOST_SMT_ENABLE 0x10000000ul 235 #define PDQ_HOST_INT_CMD_RSP_ENABLE 0x08000000ul 236 #define PDQ_HOST_INT_CMD_RQST_ENABLE 0x04000000ul 237 238 #define PDQ_HOST_INT_1MS 0x80 239 #define PDQ_HOST_INT_20MS 0x40 240 #define PDQ_HOST_INT_CSR_CMD_DONE 0x20 241 #define PDQ_HOST_INT_STATE_CHANGE 0x10 242 #define PDQ_HOST_INT_XMT_DATA_FLUSH 0x08 243 #define PDQ_HOST_INT_NXM 0x04 244 #define PDQ_HOST_INT_PM_PARITY_ERROR 0x02 245 #define PDQ_HOST_INT_HOST_BUS_PARITY_ERROR 0x01 246 #define PDQ_HOST_INT_FATAL_ERROR 0x07 247 248 typedef enum { 249 PDQH_SELFTEST_TIMEOUT=0, 250 PDQH_HOST_BUS_PARITY_ERROR=1, 251 PDQH_HOST_DIRECTED_HALT=2, 252 PDQH_SOFTWARE_FAULT=3, 253 PDQH_HARDWARE_FAULT=4, 254 PDQH_PC_TRACE_PATH_TEST=5, 255 PDQH_DMA_ERROR=6, 256 PDQH_IMAGE_CRC_ERROR=7, 257 PDQH_ADAPTER_PROCESSOR_ERROR=8, 258 PDQH_MAX=9 259 } pdq_halt_code_t; 260 261 typedef struct { 262 pdq_uint16_t pdqcb_receives; 263 pdq_uint16_t pdqcb_transmits; 264 pdq_uint32_t pdqcb__filler1; 265 pdq_uint32_t pdqcb_host_smt; 266 pdq_uint32_t pdqcb__filler2; 267 pdq_uint32_t pdqcb_unsolicited_event; 268 pdq_uint32_t pdqcb__filler3; 269 pdq_uint32_t pdqcb_command_response; 270 pdq_uint32_t pdqcb__filler4; 271 pdq_uint32_t pdqcb_command_request; 272 pdq_uint32_t pdqcb__filler5[7]; 273 } pdq_consumer_block_t; 274 275 typedef struct { 276 pdq_uint32_t rxd_pa_hi; 277 #define PDQ_RXDESC_PA_HI(x) (((x) & 0xffff) << 0) /* : 16 */ 278 #define PDQ_RXDESC_SEG_CNT(x) (((x) & 0x000f) << 16) /* : 4 */ 279 #define PDQ_RXDESC_SEG_LEN(x) ((((x) & 0xc) << 27) | (((x) & 0x1ff0) << 16)) 280 #define PDQ_RXDESC_SOP 0x80000000 /* : 1 */ 281 pdq_uint32_t rxd_pa_lo; 282 } pdq_rxdesc_t; 283 284 #define PDQ_RXS_LEN(x) (((x) >> 0) & 0x1fff) /* : 13 */ 285 #define PDQ_RXS_RCC_SS(x) (((x) >> 13) & 0x0003) /* : 2 */ 286 #define PDQ_RXS_RCC_DD(x) (((x) >> 15) & 0x0003) /* : 2 */ 287 #define PDQ_RXS_RCC_REASON(x) (((x) >> 17) & 0x0007) /* : 3 */ 288 #define PDQ_RXS_RCC_BADCRC(x) (((x) >> 20) & 0x0001) /* : 1 */ 289 #define PDQ_RXS_RCC_BADPDU(x) (((x) >> 21) & 0x0001) /* : 1 */ 290 #define PDQ_RXS_FSB__RSVD(x) (((x) >> 22) & 0x0003) /* : 2 */ 291 #define PDQ_RXS_FSB_C(x) (((x) >> 24) & 0x0001) /* : 1 */ 292 #define PDQ_RXS_FSB_A(x) (((x) >> 25) & 0x0001) /* : 1 */ 293 #define PDQ_RXS_FSB_E(x) (((x) >> 26) & 0x0001) /* : 1 */ 294 #define PDQ_RXS_FSC(x) (((x) >> 27) & 0x0007) /* : 3 */ 295 #define PDQ_RXS__RSVD(x) (((x) >> 30) & 0x0003) /* : 2 */ 296 297 #define PDQ_RXS_RCC_DD_NO_MATCH 0x00 298 #define PDQ_RXS_RCC_DD_PROMISC_MATCH 0x01 299 #define PDQ_RXS_RCC_DD_CAM_MATCH 0x02 300 #define PDQ_RXS_RCC_DD_MLA_MATCH 0x03 301 302 typedef struct { 303 pdq_uint32_t txd_pa_hi; 304 #define PDQ_TXDESC_PA_HI(x) (((x) & 0xffff) << 0) 305 #define PDQ_TXDESC_SEG_LEN(x) (((x) & 0x1fff) << 16) 306 #define PDQ_TXDESC_MBZ 0x20000000 307 #define PDQ_TXDESC_EOP 0x40000000 308 #define PDQ_TXDESC_SOP 0x80000000 309 pdq_uint32_t txd_pa_lo; 310 } pdq_txdesc_t; 311 312 typedef struct { 313 pdq_rxdesc_t pdqdb_receives[256]; /* 2048; 0x0000..0x07FF */ 314 pdq_txdesc_t pdqdb_transmits[256]; /* 2048; 0x0800..0x0FFF */ 315 pdq_rxdesc_t pdqdb_host_smt[64]; /* 512; 0x1000..0x11FF */ 316 pdq_rxdesc_t pdqdb_unsolicited_events[16]; /* 128; 0x1200..0x127F */ 317 pdq_rxdesc_t pdqdb_command_responses[16]; /* 128; 0x1280..0x12FF */ 318 pdq_txdesc_t pdqdb_command_requests[16]; /* 128; 0x1300..0x137F */ 319 /* 320 * The rest of the descriptor block is unused. 321 * As such we could use it for other things. 322 */ 323 pdq_uint32_t pdqdb__filler1[16]; /* 64; 0x1380..0x13BF */ 324 pdq_consumer_block_t pdqdb_consumer; /* 64; 0x13C0..0x13FF */ 325 /* 326 * The maximum command size is 512 so as long as thes 327 * command is at least that long all will be fine. 328 */ 329 pdq_uint32_t pdqdb__filler2[64]; /* 256; 0x1400..0x14FF */ 330 pdq_uint8_t pdqdb_cmd_request_buf[1024]; /* 1024; 0x1500..0x18FF */ 331 pdq_uint8_t pdqdb_cmd_response_buf[1024]; /* 1024; 0x1900..0x1CFF */ 332 pdq_uint32_t pdqdb__filler3[128]; /* 512; 0x1D00..0x1EFF */ 333 pdq_uint8_t pdqdb_tx_hdr[4]; /* 4; 0x1F00..0x1F03 */ 334 pdq_uint32_t pdqdb__filler4[63]; /* 252; 0x1F04..0x1FFF */ 335 } pdq_descriptor_block_t; 336 337 #define PDQ_SIZE_COMMAND_RESPONSE 512 338 339 typedef enum { 340 PDQC_START=0, 341 PDQC_FILTER_SET=1, 342 PDQC_FILTER_GET=2, 343 PDQC_CHARS_SET=3, 344 PDQC_STATUS_CHARS_GET=4, 345 PDQC_COUNTERS_GET=5, 346 PDQC_COUNTERS_SET=6, 347 PDQC_ADDR_FILTER_SET=7, 348 PDQC_ADDR_FILTER_GET=8, 349 PDQC_ERROR_LOG_CLEAR=9, 350 PDQC_ERROR_LOG_GET=10, 351 PDQC_FDDI_MIB_GET=11, 352 PDQC_DEC_EXT_MIB_GET=12, 353 PDQC_DEV_SPECIFIC_GET=13, 354 PDQC_SNMP_SET=14, 355 PDQC_SMT_MIB_GET=16, 356 PDQC_SMT_MIB_SET=17, 357 PDQC_BOGUS_CMD=18 358 } pdq_cmd_code_t; 359 360 typedef struct { 361 /* 362 * These value manage the available space in command/response 363 * buffer area. 364 */ 365 pdq_physaddr_t ci_pa_request_bufstart; 366 pdq_uint8_t *ci_request_bufstart; 367 pdq_physaddr_t ci_pa_response_bufstart; 368 pdq_uint8_t *ci_response_bufstart; 369 /* 370 * Bitmask of commands to sent to the PDQ 371 */ 372 pdq_uint32_t ci_pending_commands; 373 /* 374 * Variables to maintain the PDQ queues. 375 */ 376 pdq_uint32_t ci_command_active; 377 pdq_uint32_t ci_request_producer; 378 pdq_uint32_t ci_response_producer; 379 pdq_uint32_t ci_request_completion; 380 pdq_uint32_t ci_response_completion; 381 /* 382 * 383 */ 384 pdq_physaddr_t ci_pa_request_descriptors; 385 pdq_physaddr_t ci_pa_response_descriptors; 386 387 pdq_cmd_code_t ci_queued_commands[16]; 388 } pdq_command_info_t; 389 390 #define PDQ_SIZE_UNSOLICITED_EVENT 512 391 #define PDQ_NUM_UNSOLICITED_EVENTS (PDQ_OS_PAGESIZE / PDQ_SIZE_UNSOLICITED_EVENT) 392 393 typedef struct _pdq_unsolicited_event_t pdq_unsolicited_event_t; 394 395 typedef struct { 396 pdq_physaddr_t ui_pa_bufstart; 397 pdq_physaddr_t ui_pa_descriptors; 398 pdq_unsolicited_event_t *ui_events; 399 400 pdq_uint32_t ui_free; 401 pdq_uint32_t ui_producer; 402 pdq_uint32_t ui_completion; 403 } pdq_unsolicited_info_t; 404 405 #define PDQ_RX_FC_OFFSET (sizeof(pdq_uint32_t) + 3) 406 #define PDQ_RX_SEGCNT ((PDQ_FDDI_MAX + PDQ_OS_DATABUF_SIZE - 1) / PDQ_OS_DATABUF_SIZE) 407 #define PDQ_DO_TYPE2_PRODUCER(pdq) \ 408 PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_type_2_producer, \ 409 ((pdq)->pdq_rx_info.rx_producer << 0) \ 410 | ((pdq)->pdq_tx_info.tx_producer << 8) \ 411 | ((pdq)->pdq_rx_info.rx_completion << 16) \ 412 | ((pdq)->pdq_tx_info.tx_completion << 24)) 413 414 #define PDQ_DO_HOST_SMT_PRODUCER(pdq) \ 415 PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_host_smt_producer, \ 416 ((pdq)->pdq_host_smt_info.rx_producer << 0) \ 417 | ((pdq)->pdq_host_smt_info.rx_completion << 8))\ 418 419 #define PDQ_ADVANCE(n, a, m) ((n) = ((n) + (a)) & (m)) 420 421 typedef struct { 422 void *q_head; 423 void *q_tail; 424 } pdq_databuf_queue_t; 425 426 typedef struct { 427 void *rx_buffers; 428 pdq_physaddr_t rx_pa_descriptors; 429 430 pdq_uint32_t rx_target; 431 pdq_uint32_t rx_free; 432 pdq_uint32_t rx_producer; 433 pdq_uint32_t rx_completion; 434 } pdq_rx_info_t; 435 436 typedef struct { 437 pdq_databuf_queue_t tx_txq; 438 pdq_txdesc_t tx_hdrdesc; 439 pdq_uint8_t tx_descriptor_count[256]; 440 pdq_physaddr_t tx_pa_descriptors; 441 442 pdq_uint32_t tx_free; 443 pdq_uint32_t tx_producer; 444 pdq_uint32_t tx_completion; 445 } pdq_tx_info_t; 446 447 typedef struct _pdq_os_ctx_t pdq_os_ctx_t; 448 struct _pdq_t { 449 pdq_csrs_t pdq_csrs; 450 pdq_pci_csrs_t pdq_pci_csrs; 451 pdq_type_t pdq_type; 452 pdq_chip_rev_t pdq_chip_rev; 453 pdq_lanaddr_t pdq_hwaddr; 454 pdq_fwrev_t pdq_fwrev; 455 pdq_descriptor_block_t *pdq_dbp; 456 pdq_consumer_block_t *pdq_cbp; 457 pdq_uint32_t pdq_intrmask; 458 pdq_uint32_t pdq_flags; 459 #define PDQ_PROMISC 0x0001 460 #define PDQ_ALLMULTI 0x0002 461 #define PDQ_PASS_SMT 0x0004 462 #define PDQ_RUNNING 0x0008 463 #define PDQ_PRINTCHARS 0x0010 464 #define PDQ_TXOK 0x0020 465 #define PDQ_WANT_FDX 0x0040 466 #define PDQ_IS_FDX 0x0080 467 #define PDQ_IS_ONRING 0x0100 468 const char *pdq_os_name; 469 pdq_os_ctx_t *pdq_os_ctx; 470 pdq_uint32_t pdq_unit; 471 pdq_command_info_t pdq_command_info; 472 pdq_unsolicited_info_t pdq_unsolicited_info; 473 pdq_tx_info_t pdq_tx_info; 474 pdq_rx_info_t pdq_rx_info; 475 pdq_rx_info_t pdq_host_smt_info; 476 void *pdq_receive_buffers[256]; 477 void *pdq_host_smt_buffers[64]; 478 pdq_physaddr_t pdq_pa_consumer_block; 479 pdq_physaddr_t pdq_pa_descriptor_block; 480 }; 481 482 #define PDQ_DB_BUSPA(pdq, m) \ 483 ((pdq)->pdq_pa_descriptor_block + \ 484 ((u_int8_t *) (m) - (u_int8_t *) (pdq)->pdq_dbp)) 485 486 487 typedef enum { 488 PDQR_SUCCESS=0, 489 PDQR_FAILURE=1, 490 PDQR_WARNING=2, 491 PDQR_LOOP_MODE_BAD=3, 492 PDQR_ITEM_CODE_BAD=4, 493 PDQR_TVX_BAD=5, 494 PDQR_TREQ_BAD=6, 495 PDQR_RESTRICTED_TOKEN_BAD=7, 496 PDQR_NO_EOL=12, 497 PDQR_FILTER_STATE_BAD=13, 498 PDQR_CMD_TYPE_BAD=14, 499 PDQR_ADAPTER_STATE_BAD=15, 500 PDQR_RING_PURGER_BAD=16, 501 PDQR_LEM_THRESHOLD_BAD=17, 502 PDQR_LOOP_NOT_SUPPORTED=18, 503 PDQR_FLUSH_TIME_BAD=19, 504 PDQR_NOT_YET_IMPLEMENTED=20, 505 PDQR_CONFIG_POLICY_BAD=21, 506 PDQR_STATION_ACTION_BAD=22, 507 PDQR_MAC_ACTION_BAD=23, 508 PDQR_CON_POLICIES_BAD=24, 509 PDQR_MAC_LOOP_TIME_BAD=25, 510 PDQR_TB_MAX_BAD=26, 511 PDQR_LER_CUTOFF_BAD=27, 512 PDQR_LER_ALARM_BAD=28, 513 PDQR_MAC_PATHS_REQ_BAD=29, 514 PDQR_MAC_T_REQ_BAD=30, 515 PDQR_EMAC_RING_PURGER_BAD=31, 516 PDQR_EMAC_RTOKEN_TIMOUT_AD=32, 517 PDQR_NO_SUCH_ENTRY=33, 518 PDQR_T_NOTIFY_BAD=34, 519 PDQR_TR_MAX_EXP_BAD=35, 520 PDQR_FRAME_ERR_THRESHOLD_BAD=36, 521 PDQR_MAX_TREQ_BAD=37, 522 PDQR_FULL_DUPLEX_ENABLE_BAD=38, 523 PDQR_ITEM_INDEX_BAD=39 524 } pdq_response_code_t; 525 526 typedef enum { 527 PDQI_EOL=0, 528 PDQI_T_REQ=1, 529 PDQI_TVX=2, 530 PDQI_RESTRICTED_TOKEN=3, 531 PDQI_LEM_THRESHOLD=4, 532 PDQI_RING_PURGER=5, 533 PDQI_COUNTER_INTERVAL=6, 534 PDQI_IND_GROUP_PROM=7, 535 PDQI_GROUP_PROM=8, 536 PDQI_BROADCAST=9, 537 PDQI_SMT_PROM=10, 538 PDQI_SMT_USER=11, 539 PDQI_RESERVED=12, 540 PDQI_IMPLEMENTOR=13, 541 PDQI_LOOPBACK_MODE=14, 542 PDQI_SMT_CONFIG_POLICY=16, 543 PDQI_SMT_CONNECTION_POLICY=17, 544 PDQI_SMT_T_NOTIFY=18, 545 PDQI_SMT_STATION_ACTION=19, 546 PDQI_MAC_PATHS_REQUESTED=21, 547 PDQI_MAC_ACTION=23, 548 PDQI_PORT_CONNECTION_POLICIES=24, 549 PDQI_PORT_PATHS_REQUESTED=25, 550 PDQI_PORT_MAC_LOOP_TIME=26, 551 PDQI_PORT_TB_MAX=27, 552 PDQI_PORT_LER_CUTOFF=28, 553 PDQI_PORT_LER_ALARM=29, 554 PDQI_PORT_ACTION=30, 555 PDQI_FLUSH_TIME=32, 556 PDQI_SMT_USER_DATA=33, 557 PDQI_SMT_STATUS_REPORT_POLICY=34, 558 PDQI_SMT_TRACE_MAX_EXPIRATION=35, 559 PDQI_MAC_FRAME_ERR_THRESHOLD=36, 560 PDQI_MAC_UNIT_DATA_ENABLE=37, 561 PDQI_PATH_TVX_LOWER_BOUND=38, 562 PDQI_PATH_TMAX_LOWER_BOUND=39, 563 PDQI_PATH_MAX_TREQ=40, 564 PDQI_MAC_TREQ=41, 565 PDQI_EMAC_RING_PURGER=42, 566 PDQI_EMAC_RTOKEN_TIMEOUT=43, 567 PDQI_FULL_DUPLEX_ENABLE=44 568 } pdq_item_code_t; 569 570 typedef enum { 571 PDQSNMP_EOL=0, 572 PDQSNMP_FULL_DUPLEX_ENABLE=0x2F11 573 } pdq_snmp_item_code_t; 574 575 typedef enum { 576 PDQ_FILTER_BLOCK=0, 577 PDQ_FILTER_PASS=1 578 } pdq_filter_state_t; 579 580 typedef enum { 581 PDQ_STATION_TYPE_SAS=0, 582 PDQ_STATION_TYPE_DAC=1, 583 PDQ_STATION_TYPE_SAC=2, 584 PDQ_STATION_TYPE_NAC=3, 585 PDQ_STATION_TYPE_DAS=4 586 } pdq_station_type_t; 587 588 typedef enum { 589 PDQ_STATION_STATE_OFF=0, 590 PDQ_STATION_STATE_ON=1, 591 PDQ_STATION_STATE_LOOPBACK=2 592 } pdq_station_state_t; 593 594 typedef enum { 595 PDQ_LINK_STATE_OFF_READY=1, 596 PDQ_LINK_STATE_OFF_FAULT_RECOVERY=2, 597 PDQ_LINK_STATE_ON_RING_INIT=3, 598 PDQ_LINK_STATE_ON_RING_RUN=4, 599 PDQ_LINK_STATE_BROKEN=5 600 } pdq_link_state_t; 601 602 typedef enum { 603 PDQ_DA_TEST_STATE_UNKNOWN=0, 604 PDQ_DA_TEST_STATE_SUCCESS=1, 605 PDQ_DA_TEST_STATE_DUPLICATE=2 606 } pdq_da_test_state_t; 607 608 typedef enum { 609 PDQ_RING_PURGER_STATE_OFF=0, 610 PDQ_RING_PURGER_STATE_CANDIDATE=1, 611 PDQ_RING_PURGER_STATE_NON_PURGER=2, 612 PDQ_RING_PURGER_STATE_PURGER=3 613 } pdq_ring_purger_state_t; 614 615 typedef enum { 616 PDQ_FRAME_STRING_MODE_SA_MATCH=0, 617 PDQ_FRAME_STRING_MODE_FCI_STRIP=1 618 } pdq_frame_strip_mode_t; 619 620 typedef enum { 621 PDQ_RING_ERROR_REASON_NO_ERROR=0, 622 PDQ_RING_ERROR_REASON_RING_INIT_INITIATED=5, 623 PDQ_RING_ERROR_REASON_RING_INIT_RECEIVED=6, 624 PDQ_RING_ERROR_REASON_RING_BEACONING_INITIATED=7, 625 PDQ_RING_ERROR_REASON_DUPLICATE_ADDRESS_DETECTED=8, 626 PDQ_RING_ERROR_REASON_DUPLICATE_TOKEN_DETECTED=9, 627 PDQ_RING_ERROR_REASON_RING_PURGER_ERROR=10, 628 PDQ_RING_ERROR_REASON_FCI_STRIP_ERROR=11, 629 PDQ_RING_ERROR_REASON_RING_OP_OSCILLATION=12, 630 PDQ_RING_ERROR_REASON_DIRECTED_BEACON_RECEVIED=13, 631 PDQ_RING_ERROR_REASON_PC_TRACE_INITIATED=14, 632 PDQ_RING_ERROR_REASON_PC_TRACE_RECEVIED=15 633 } pdq_ring_error_reason_t; 634 635 typedef enum { 636 PDQ_STATION_MODE_NORMAL=0, 637 PDQ_STATION_MODE_INTERNAL_LOOPBACK=1 638 } pdq_station_mode_t; 639 640 typedef enum { 641 PDQ_PHY_TYPE_A=0, 642 PDQ_PHY_TYPE_B=1, 643 PDQ_PHY_TYPE_S=2, 644 PDQ_PHY_TYPE_M=3, 645 PDQ_PHY_TYPE_UNKNOWN=4 646 } pdq_phy_type_t; 647 648 typedef enum { 649 PDQ_PMD_TYPE_ANSI_MUTLI_MODE=0, 650 PDQ_PMD_TYPE_ANSI_SINGLE_MODE_TYPE_1=1, 651 PDQ_PMD_TYPE_ANSI_SIGNLE_MODE_TYPE_2=2, 652 PDQ_PMD_TYPE_ANSI_SONET=3, 653 PDQ_PMD_TYPE_LOW_POWER=100, 654 PDQ_PMD_TYPE_THINWIRE=101, 655 PDQ_PMD_TYPE_SHIELDED_TWISTED_PAIR=102, 656 PDQ_PMD_TYPE_UNSHIELDED_TWISTED_PAIR=103 657 } pdq_pmd_type_t; 658 659 typedef enum { 660 PDQ_PMD_CLASS_ANSI_MULTI_MODE=0, 661 PDQ_PMD_CLASS_SINGLE_MODE_TYPE_1=1, 662 PDQ_PMD_CLASS_SINGLE_MODE_TYPE_2=2, 663 PDQ_PMD_CLASS_SONET=3, 664 PDQ_PMD_CLASS_LOW_COST_POWER_FIBER=4, 665 PDQ_PMD_CLASS_TWISTED_PAIR=5, 666 PDQ_PMD_CLASS_UNKNOWN=6, 667 PDQ_PMD_CLASS_UNSPECIFIED=7 668 } pdq_pmd_class_t; 669 670 typedef enum { 671 PDQ_PHY_STATE_INTERNAL_LOOPBACK=0, 672 PDQ_PHY_STATE_BROKEN=1, 673 PDQ_PHY_STATE_OFF_READY=2, 674 PDQ_PHY_STATE_WAITING=3, 675 PDQ_PHY_STATE_STARTING=4, 676 PDQ_PHY_STATE_FAILED=5, 677 PDQ_PHY_STATE_WATCH=6, 678 PDQ_PHY_STATE_INUSE=7 679 } pdq_phy_state_t; 680 681 typedef enum { 682 PDQ_REJECT_REASON_NONE=0, 683 PDQ_REJECT_REASON_LOCAL_LCT=1, 684 PDQ_REJECT_REASON_REMOTE_LCT=2, 685 PDQ_REJECT_REASON_LCT_BOTH_SIDES=3, 686 PDQ_REJECT_REASON_LEM_REJECT=4, 687 PDQ_REJECT_REASON_TOPOLOGY_ERROR=5, 688 PDQ_REJECT_REASON_NOISE_REJECT=6, 689 PDQ_REJECT_REASON_REMOTE_REJECT=7, 690 PDQ_REJECT_REASON_TRACE_IN_PROGRESS=8, 691 PDQ_REJECT_REASON_TRACE_RECEIVED_DISABLED=9, 692 PDQ_REJECT_REASON_STANDBY=10, 693 PDQ_REJECT_REASON_LCT_PROTOCOL_ERROR=11 694 } pdq_reject_reason_t; 695 696 typedef enum { 697 PDQ_BROKEN_REASON_NONE=0 698 } pdq_broken_reason_t; 699 700 typedef enum { 701 PDQ_RI_REASON_TVX_EXPIRED=0, 702 PDQ_RI_REASON_TRT_EXPIRED=1, 703 PDQ_RI_REASON_RING_PURGER_ELECTION_ATTEMPT_LIMIT_EXCEEDED=2, 704 PDQ_RI_REASON_PURGE_ERROR_LIMIT_EXCEEDED=3, 705 PDQ_RI_REASON_RESTRICTED_TOKEN_TIMEOUT=4 706 } pdq_ri_reason_t; 707 708 typedef enum { 709 PDQ_LCT_DIRECTION_LOCAL_LCT=0, 710 PDQ_LCT_DIRECTION_REMOTE_LCT=1, 711 PDQ_LCT_DIRECTION_LCT_BOTH_SIDES=2 712 } pdq_lct_direction_t; 713 714 typedef enum { 715 PDQ_PORT_A=0, 716 PDQ_PORT_B=1 717 } pdq_port_type_t; 718 719 typedef struct { 720 pdq_uint8_t station_id_bytes[8]; 721 } pdq_station_id_t; 722 723 typedef pdq_uint32_t pdq_fdditimer_t; 724 /* 725 * Command format for Start, Filter_Get, ... commands 726 */ 727 typedef struct { 728 pdq_cmd_code_t generic_op; 729 } pdq_cmd_generic_t; 730 731 /* 732 * Response format for Start, Filter_Set, ... commands 733 */ 734 typedef struct { 735 pdq_uint32_t generic_reserved; 736 pdq_cmd_code_t generic_op; 737 pdq_response_code_t generic_status; 738 } pdq_response_generic_t; 739 740 /* 741 * Command format for Filter_Set command 742 */ 743 typedef struct { 744 pdq_cmd_code_t filter_set_op; 745 struct { 746 pdq_item_code_t item_code; 747 pdq_filter_state_t filter_state; 748 } filter_set_items[7]; 749 pdq_item_code_t filter_set_eol_item_code; 750 } pdq_cmd_filter_set_t; 751 752 /* 753 * Response format for Filter_Get command. 754 */ 755 typedef struct { 756 pdq_uint32_t filter_get_reserved; 757 pdq_cmd_code_t filter_get_op; 758 pdq_response_code_t filter_get_status; 759 pdq_filter_state_t filter_get_ind_group_prom; 760 pdq_filter_state_t filter_get_group_prom; 761 pdq_filter_state_t filter_get_broadcast_all; 762 pdq_filter_state_t filter_get_smt_prom; 763 pdq_filter_state_t filter_get_smt_user; 764 pdq_filter_state_t filter_get_reserved_all; 765 pdq_filter_state_t filter_get_implementor_all; 766 } pdq_response_filter_get_t; 767 768 #define PDQ_SIZE_RESPONSE_FILTER_GET 0x28 769 770 typedef struct { 771 pdq_cmd_code_t chars_set_op; 772 struct { 773 pdq_item_code_t item_code; 774 pdq_uint32_t item_value; 775 pdq_port_type_t item_port; 776 } chars_set_items[1]; 777 pdq_item_code_t chars_set_eol_item_code; 778 } pdq_cmd_chars_set_t; 779 780 typedef struct { 781 pdq_cmd_code_t addr_filter_set_op; 782 pdq_lanaddr_t addr_filter_set_addresses[62]; 783 } pdq_cmd_addr_filter_set_t; 784 785 #define PDQ_SIZE_CMD_ADDR_FILTER_SET 0x1F4 786 787 typedef struct { 788 pdq_uint32_t addr_filter_get_reserved; 789 pdq_cmd_code_t addr_filter_get_op; 790 pdq_response_code_t addr_filter_get_status; 791 pdq_lanaddr_t addr_filter_get_addresses[62]; 792 } pdq_response_addr_filter_get_t; 793 794 #define PDQ_SIZE_RESPONSE_ADDR_FILTER_GET 0x1FC 795 796 typedef struct { 797 pdq_uint32_t status_chars_get_reserved; 798 pdq_cmd_code_t status_chars_get_op; 799 pdq_response_code_t status_chars_get_status; 800 struct { 801 /* Station Characteristic Attributes */ 802 pdq_station_id_t station_id; 803 pdq_station_type_t station_type; 804 pdq_uint32_t smt_version_id; 805 pdq_uint32_t smt_max_version_id; 806 pdq_uint32_t smt_min_version_id; 807 /* Station Status Attributes */ 808 pdq_station_state_t station_state; 809 /* Link Characteristic Attributes */ 810 pdq_lanaddr_t link_address; 811 pdq_fdditimer_t t_req; 812 pdq_fdditimer_t tvx; 813 pdq_fdditimer_t restricted_token_timeout; 814 pdq_boolean_t ring_purger_enable; 815 pdq_link_state_t link_state; 816 pdq_fdditimer_t negotiated_trt; 817 pdq_da_test_state_t dup_addr_flag; 818 /* Link Status Attributes */ 819 pdq_lanaddr_t upstream_neighbor; 820 pdq_lanaddr_t old_upstream_neighbor; 821 pdq_boolean_t upstream_neighbor_dup_addr_flag; 822 pdq_lanaddr_t downstream_neighbor; 823 pdq_lanaddr_t old_downstream_neighbor; 824 pdq_ring_purger_state_t ring_purger_state; 825 pdq_frame_strip_mode_t frame_strip_mode; 826 pdq_ring_error_reason_t ring_error_reason; 827 pdq_boolean_t loopback; 828 pdq_fdditimer_t ring_latency; 829 pdq_lanaddr_t last_dir_beacon_sa; 830 pdq_lanaddr_t last_dir_beacon_una; 831 /* Phy Characteristic Attributes */ 832 pdq_phy_type_t phy_type[2]; 833 pdq_pmd_type_t pmd_type[2]; 834 pdq_uint32_t lem_threshold[2]; 835 /* Phy Status Attributes */ 836 pdq_phy_state_t phy_state[2]; 837 pdq_phy_type_t neighbor_phy_type[2]; 838 pdq_uint32_t link_error_estimate[2]; 839 pdq_broken_reason_t broken_reason[2]; 840 pdq_reject_reason_t reject_reason[2]; 841 /* Miscellaneous */ 842 pdq_uint32_t counter_interval; 843 pdq_fwrev_t module_rev; 844 pdq_fwrev_t firmware_rev; 845 pdq_uint32_t mop_device_type; 846 pdq_uint32_t fddi_led[2]; 847 pdq_uint32_t flush; 848 } status_chars_get; 849 } pdq_response_status_chars_get_t; 850 851 #define PDQ_SIZE_RESPONSE_STATUS_CHARS_GET 0xF0 852 853 typedef struct { 854 pdq_uint32_t fddi_mib_get_reserved; 855 pdq_cmd_code_t fddi_mib_get_op; 856 pdq_response_code_t fddi_mib_get_status; 857 struct { 858 /* SMT Objects */ 859 pdq_station_id_t smt_station_id; 860 pdq_uint32_t smt_op_version_id; 861 pdq_uint32_t smt_hi_version_id; 862 pdq_uint32_t smt_lo_version_id; 863 pdq_uint32_t smt_mac_ct; 864 pdq_uint32_t smt_non_master_ct; 865 pdq_uint32_t smt_master_ct; 866 pdq_uint32_t smt_paths_available; 867 pdq_uint32_t smt_config_capabilities; 868 pdq_uint32_t smt_config_policy; 869 pdq_uint32_t smt_connection_policy; 870 pdq_uint32_t smt_t_notify; 871 pdq_uint32_t smt_status_reporting; 872 pdq_uint32_t smt_ecm_state; 873 pdq_uint32_t smt_cf_state; 874 pdq_uint32_t smt_hold_state; 875 pdq_uint32_t smt_remote_disconnect_flag; 876 pdq_uint32_t smt_station_action; 877 /* MAC Objects */ 878 pdq_uint32_t mac_frame_status_capabilities; 879 pdq_uint32_t mac_t_max_greatest_lower_bound; 880 pdq_uint32_t mac_tvx_greatest_lower_bound; 881 pdq_uint32_t mac_paths_available; 882 pdq_uint32_t mac_current_path; 883 pdq_lanaddr_t mac_upstream_neighbor; 884 pdq_lanaddr_t mac_old_upstream_neighbor; 885 pdq_uint32_t mac_dup_addr_test; 886 pdq_uint32_t mac_paths_requested; 887 pdq_uint32_t mac_downstream_port_type; 888 pdq_lanaddr_t mac_smt_address; 889 pdq_uint32_t mac_t_req; 890 pdq_uint32_t mac_t_neg; 891 pdq_uint32_t mac_t_max; 892 pdq_uint32_t mac_tvx_value; 893 pdq_uint32_t mac_t_min; 894 pdq_uint32_t mac_current_frame_status; 895 pdq_uint32_t mac_frame_error_threshold; 896 pdq_uint32_t mac_frame_error_ratio; 897 pdq_uint32_t mac_rmt_state; 898 pdq_uint32_t mac_da_flag; 899 pdq_uint32_t mac_una_da_flag; 900 pdq_uint32_t mac_frame_condition; 901 pdq_uint32_t mac_chip_set; 902 pdq_uint32_t mac_action; 903 /* Port Objects */ 904 pdq_uint32_t port_pc_type[2]; 905 pdq_uint32_t port_pc_neighbor[2]; 906 pdq_uint32_t port_connection_policies[2]; 907 pdq_uint32_t port_remote_mac_indicated[2]; 908 pdq_uint32_t port_ce_state[2]; 909 pdq_uint32_t port_paths_requested[2]; 910 pdq_uint32_t port_mac_placement[2]; 911 pdq_uint32_t port_available_paths[2]; 912 pdq_uint32_t port_mac_loop_time[2]; 913 pdq_uint32_t port_tb_max[2]; 914 pdq_uint32_t port_bs_flag[2]; 915 pdq_uint32_t port_ler_estimate[2]; 916 pdq_uint32_t port_ler_cutoff[2]; 917 pdq_uint32_t port_ler_alarm[2]; 918 pdq_uint32_t port_connect_state[2]; 919 pdq_uint32_t port_pcm_state[2]; 920 pdq_uint32_t port_pc_withhold[2]; 921 pdq_uint32_t port_ler_condition[2]; 922 pdq_uint32_t port_chip_set[2]; 923 pdq_uint32_t port_action[2]; 924 /* Attachment Objects */ 925 pdq_uint32_t attachment_class; 926 pdq_uint32_t attachment_optical_bypass_present; 927 pdq_uint32_t attachment_imax_expiration; 928 pdq_uint32_t attachment_inserted_status; 929 pdq_uint32_t attachment_insert_policy; 930 } fddi_mib_get; 931 } pdq_response_fddi_mib_get_t; 932 933 #define PDQ_SIZE_RESPONSE_FDDI_MIB_GET 0x17C 934 935 typedef enum { 936 PDQ_FDX_STATE_IDLE=0, 937 PDQ_FDX_STATE_REQUEST=1, 938 PDQ_FDX_STATE_CONFIRM=2, 939 PDQ_FDX_STATE_OPERATION=3 940 } pdq_fdx_state_t; 941 942 typedef struct { 943 pdq_uint32_t dec_ext_mib_get_reserved; 944 pdq_cmd_code_t dec_ext_mib_get_op; 945 pdq_response_code_t dec_ext_mib_get_response; 946 struct { 947 /* SMT Objects */ 948 pdq_uint32_t esmt_station_type; 949 /* MAC Objects */ 950 pdq_uint32_t emac_link_state; 951 pdq_uint32_t emac_ring_purger_state; 952 pdq_uint32_t emac_ring_purger_enable; 953 pdq_uint32_t emac_frame_strip_mode; 954 pdq_uint32_t emac_ring_error_reason; 955 pdq_uint32_t emac_upstream_nbr_dupl_address_flag; 956 pdq_uint32_t emac_restricted_token_timeout; 957 /* Port Objects */ 958 pdq_uint32_t eport_pmd_type[2]; 959 pdq_uint32_t eport_phy_state[2]; 960 pdq_uint32_t eport_reject_reason[2]; 961 /* Full Duplex Objects */ 962 pdq_boolean_t fdx_enable; 963 pdq_boolean_t fdx_operational; 964 pdq_fdx_state_t fdx_state; 965 } dec_ext_mib_get; 966 } pdq_response_dec_ext_mib_get_t; 967 968 #define PDQ_SIZE_RESPONSE_DEC_EXT_MIB_GET 0x50 969 970 typedef struct { 971 pdq_cmd_code_t snmp_set_op; 972 struct { 973 pdq_item_code_t item_code; 974 pdq_uint32_t item_value; 975 pdq_port_type_t item_port; 976 } snmp_set_items[7]; 977 pdq_item_code_t snmp_set_eol_item_code; 978 } pdq_cmd_snmp_set_t; 979 980 typedef enum { 981 PDQ_CALLER_ID_NONE=0, 982 PDQ_CALLER_ID_SELFTEST=1, 983 PDQ_CALLER_ID_MFG=2, 984 PDQ_CALLER_ID_FIRMWARE=5, 985 PDQ_CALLER_ID_CONSOLE=8 986 } pdq_caller_id_t; 987 988 typedef struct { 989 pdq_uint32_t error_log_get__reserved; 990 pdq_cmd_code_t error_log_get_op; 991 pdq_response_code_t error_log_get_status; 992 /* Error Header */ 993 pdq_uint32_t error_log_get_event_status; 994 /* Event Information Block */ 995 pdq_caller_id_t error_log_get_caller_id; 996 pdq_uint32_t error_log_get_timestamp[2]; 997 pdq_uint32_t error_log_get_write_count; 998 /* Diagnostic Information */ 999 pdq_uint32_t error_log_get_fru_implication_mask; 1000 pdq_uint32_t error_log_get_test_id; 1001 pdq_uint32_t error_log_get_diag_reserved[6]; 1002 /* Firmware Information */ 1003 pdq_uint32_t error_log_get_fw_reserved[112]; 1004 } pdq_response_error_log_get_t; 1005 1006 1007 /* 1008 * Definitions for the Unsolicited Event Queue. 1009 */ 1010 typedef enum { 1011 PDQ_UNSOLICITED_EVENT=0, 1012 PDQ_UNSOLICITED_COUNTERS=1 1013 } pdq_event_t; 1014 1015 typedef enum { 1016 PDQ_ENTITY_STATION=0, 1017 PDQ_ENTITY_LINK=1, 1018 PDQ_ENTITY_PHY_PORT=2, 1019 PDQ_ENTITY_MAX=3 1020 } pdq_entity_t; 1021 1022 typedef enum { 1023 PDQ_STATION_EVENT_TRACE_RECEIVED=1, 1024 PDQ_STATION_EVENT_MAX=2 1025 } pdq_station_event_t; 1026 1027 typedef enum { 1028 PDQ_STATION_EVENT_ARGUMENT_REASON=0, /* pdq_uint32_t */ 1029 PDQ_STATION_EVENT_ARGUMENT_EOL=0xFF 1030 } pdq_station_event_argument_t; 1031 1032 typedef enum { 1033 PDQ_LINK_EVENT_TRANSMIT_UNDERRUN=0, 1034 PDQ_LINK_EVENT_TRANSMIT_FAILED=1, 1035 PDQ_LINK_EVENT_BLOCK_CHECK_ERROR=2, 1036 PDQ_LINK_EVENT_FRAME_STATUS_ERROR=3, 1037 PDQ_LINK_EVENT_PDU_LENGTH_ERROR=4, 1038 PDQ_LINK_EVENT_RECEIVE_DATA_OVERRUN=7, 1039 PDQ_LINK_EVENT_NO_USER_BUFFER=9, 1040 PDQ_LINK_EVENT_RING_INITIALIZATION_INITIATED=10, 1041 PDQ_LINK_EVENT_RING_INITIALIZATION_RECEIVED=11, 1042 PDQ_LINK_EVENT_RING_BEACON_INITIATED=12, 1043 PDQ_LINK_EVENT_DUPLICATE_ADDRESS_FAILURE=13, 1044 PDQ_LINK_EVENT_DUPLICATE_TOKEN_DETECTED=14, 1045 PDQ_LINK_EVENT_RING_PURGE_ERROR=15, 1046 PDQ_LINK_EVENT_FCI_STRIP_ERROR=16, 1047 PDQ_LINK_EVENT_TRACE_INITIATED=17, 1048 PDQ_LINK_EVENT_DIRECTED_BEACON_RECEIVED=18, 1049 PDQ_LINK_EVENT_MAX=19 1050 } pdq_link_event_t; 1051 1052 typedef enum { 1053 PDQ_LINK_EVENT_ARGUMENT_REASON=0, /* pdq_rireason_t */ 1054 PDQ_LINK_EVENT_ARGUMENT_DATA_LINK_HEADER=1, /* pdq_dlhdr_t */ 1055 PDQ_LINK_EVENT_ARGUMENT_SOURCE=2, /* pdq_lanaddr_t */ 1056 PDQ_LINK_EVENT_ARGUMENT_UPSTREAM_NEIGHBOR=3,/* pdq_lanaddr_t */ 1057 PDQ_LINK_EVENT_ARGUMENT_EOL=0xFF 1058 } pdq_link_event_argument_t; 1059 1060 typedef enum { 1061 PDQ_PHY_EVENT_LEM_ERROR_MONITOR_REJECT=0, 1062 PDQ_PHY_EVENT_ELASTICITY_BUFFER_ERROR=1, 1063 PDQ_PHY_EVENT_LINK_CONFIDENCE_TEST_REJECT=2, 1064 PDQ_PHY_EVENT_MAX=3 1065 } pdq_phy_event_t; 1066 1067 typedef enum { 1068 PDQ_PHY_EVENT_ARGUMENT_DIRECTION=0, /* pdq_lct_direction_t */ 1069 PDQ_PHY_EVENT_ARGUMENT_EOL=0xFF 1070 } pdq_phy_event_arguments; 1071 1072 struct _pdq_unsolicited_event_t { 1073 pdq_uint32_t rvent_reserved; 1074 pdq_event_t event_type; 1075 pdq_entity_t event_entity; 1076 pdq_uint32_t event_index; 1077 union { 1078 pdq_station_event_t station_event; 1079 pdq_link_event_t link_event; 1080 pdq_phy_event_t phy_event; 1081 pdq_uint32_t value; 1082 } event_code; 1083 /* 1084 * The remainder of this event is an argument list. 1085 */ 1086 pdq_uint32_t event__filler[123]; 1087 }; 1088 1089 #endif /* _PDQREG_H */ 1090