1 /////////////////////////////////////////////////////////////////////////
2 // $Id: 3dnow.cc 13466 2018-02-16 07:57:32Z sshwarts $
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // Copyright (c) 2002-2018 Stanislav Shwartsman
6 // Written by Stanislav Shwartsman [sshwarts at sourceforge net]
7 //
8 // This library is free software; you can redistribute it and/or
9 // modify it under the terms of the GNU Lesser General Public
10 // License as published by the Free Software Foundation; either
11 // version 2 of the License, or (at your option) any later version.
12 //
13 // This library is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 // Lesser General Public License for more details.
17 //
18 // You should have received a copy of the GNU Lesser General Public
19 // License along with this library; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
21 //
22 /////////////////////////////////////////////////////////////////////////
23
24 #define NEED_CPU_REG_SHORTCUTS 1
25 #include "bochs.h"
26 #include "cpu.h"
27 #define LOG_THIS BX_CPU_THIS_PTR
28
29 #if BX_SUPPORT_3DNOW
30
prepare_softfloat_status_word(float_status_t & status,int rounding_mode)31 BX_CPP_INLINE void prepare_softfloat_status_word(float_status_t &status, int rounding_mode)
32 {
33 status.float_exception_flags = 0; // clear exceptions before execution
34 status.float_nan_handling_mode = float_first_operand_nan;
35 status.float_rounding_mode = rounding_mode;
36 status.flush_underflow_to_zero = 0;
37 }
38
PFPNACC_PqQq(bxInstruction_c * i)39 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFPNACC_PqQq(bxInstruction_c *i)
40 {
41 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
42
43 BX_NEXT_INSTR(i);
44 }
45
46 /* 0F 0F /r 0C */
PI2FW_PqQq(bxInstruction_c * i)47 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PI2FW_PqQq(bxInstruction_c *i)
48 {
49 #if BX_CPU_LEVEL >= 5
50 BxPackedMmxRegister result, op;
51
52 BX_CPU_THIS_PTR prepareMMX();
53
54 /* op is a register or memory reference */
55 if (i->modC0()) {
56 op = BX_READ_MMX_REG(i->src());
57 }
58 else {
59 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
60 /* pointer, segment address pair */
61 op = read_virtual_qword(i->seg(), eaddr);
62 }
63
64 BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
65
66 float_status_t status_word;
67 prepare_softfloat_status_word(status_word, float_round_to_zero);
68
69 MMXUD0(result) =
70 int32_to_float32((Bit32s)(MMXSW0(op)), status_word);
71 MMXUD1(result) =
72 int32_to_float32((Bit32s)(MMXSW2(op)), status_word);
73
74 /* now write result back to destination */
75 BX_WRITE_MMX_REG(i->dst(), result);
76
77 BX_NEXT_INSTR(i);
78 #endif
79 }
80
81 /* 0F 0F /r 0D */
PI2FD_PqQq(bxInstruction_c * i)82 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PI2FD_PqQq(bxInstruction_c *i)
83 {
84 #if BX_CPU_LEVEL >= 5
85 BxPackedMmxRegister result, op;
86
87 BX_CPU_THIS_PTR prepareMMX();
88
89 /* op is a register or memory reference */
90 if (i->modC0()) {
91 op = BX_READ_MMX_REG(i->src());
92 }
93 else {
94 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
95 /* pointer, segment address pair */
96 op = read_virtual_qword(i->seg(), eaddr);
97 }
98
99 BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
100
101 float_status_t status_word;
102 prepare_softfloat_status_word(status_word, float_round_to_zero);
103
104 MMXUD0(result) =
105 int32_to_float32(MMXSD0(op), status_word);
106 MMXUD1(result) =
107 int32_to_float32(MMXSD1(op), status_word);
108
109 /* now write result back to destination */
110 BX_WRITE_MMX_REG(i->dst(), result);
111
112 BX_NEXT_INSTR(i);
113 #endif
114 }
115
PF2IW_PqQq(bxInstruction_c * i)116 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PF2IW_PqQq(bxInstruction_c *i)
117 {
118 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
119
120 BX_NEXT_INSTR(i);
121 }
122
123 /* 0F 0F /r 1D */
PF2ID_PqQq(bxInstruction_c * i)124 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PF2ID_PqQq(bxInstruction_c *i)
125 {
126 #if BX_CPU_LEVEL >= 5
127 BxPackedMmxRegister result, op;
128
129 BX_CPU_THIS_PTR prepareMMX();
130
131 /* op is a register or memory reference */
132 if (i->modC0()) {
133 op = BX_READ_MMX_REG(i->src());
134 }
135 else {
136 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
137 /* pointer, segment address pair */
138 op = read_virtual_qword(i->seg(), eaddr);
139 }
140
141 BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
142
143 float_status_t status_word;
144 prepare_softfloat_status_word(status_word, float_round_to_zero);
145
146 MMXSD0(result) =
147 float32_to_int32_round_to_zero(MMXUD0(op), status_word);
148 MMXSD1(result) =
149 float32_to_int32_round_to_zero(MMXUD1(op), status_word);
150
151 /* now write result back to destination */
152 BX_WRITE_MMX_REG(i->dst(), result);
153
154 BX_NEXT_INSTR(i);
155 #endif
156 }
157
PFNACC_PqQq(bxInstruction_c * i)158 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFNACC_PqQq(bxInstruction_c *i)
159 {
160 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
161
162 BX_NEXT_INSTR(i);
163 }
164
PFCMPGE_PqQq(bxInstruction_c * i)165 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFCMPGE_PqQq(bxInstruction_c *i)
166 {
167 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
168
169 BX_NEXT_INSTR(i);
170 }
171
PFMIN_PqQq(bxInstruction_c * i)172 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFMIN_PqQq(bxInstruction_c *i)
173 {
174 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
175
176 BX_NEXT_INSTR(i);
177 }
178
PFRCP_PqQq(bxInstruction_c * i)179 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFRCP_PqQq(bxInstruction_c *i)
180 {
181 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
182
183 BX_NEXT_INSTR(i);
184 }
185
PFRSQRT_PqQq(bxInstruction_c * i)186 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFRSQRT_PqQq(bxInstruction_c *i)
187 {
188 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
189
190 BX_NEXT_INSTR(i);
191 }
192
PFSUB_PqQq(bxInstruction_c * i)193 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFSUB_PqQq(bxInstruction_c *i)
194 {
195 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
196
197 BX_NEXT_INSTR(i);
198 }
199
PFADD_PqQq(bxInstruction_c * i)200 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFADD_PqQq(bxInstruction_c *i)
201 {
202 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
203
204 BX_NEXT_INSTR(i);
205 }
206
PFCMPGT_PqQq(bxInstruction_c * i)207 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFCMPGT_PqQq(bxInstruction_c *i)
208 {
209 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
210
211 BX_NEXT_INSTR(i);
212 }
213
PFMAX_PqQq(bxInstruction_c * i)214 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFMAX_PqQq(bxInstruction_c *i)
215 {
216 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
217
218 BX_NEXT_INSTR(i);
219 }
220
PFRCPIT1_PqQq(bxInstruction_c * i)221 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFRCPIT1_PqQq(bxInstruction_c *i)
222 {
223 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
224
225 BX_NEXT_INSTR(i);
226 }
227
PFRSQIT1_PqQq(bxInstruction_c * i)228 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFRSQIT1_PqQq(bxInstruction_c *i)
229 {
230 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
231
232 BX_NEXT_INSTR(i);
233 }
234
PFSUBR_PqQq(bxInstruction_c * i)235 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFSUBR_PqQq(bxInstruction_c *i)
236 {
237 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
238
239 BX_NEXT_INSTR(i);
240 }
241
PFACC_PqQq(bxInstruction_c * i)242 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFACC_PqQq(bxInstruction_c *i)
243 {
244 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
245
246 BX_NEXT_INSTR(i);
247 }
248
PFCMPEQ_PqQq(bxInstruction_c * i)249 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFCMPEQ_PqQq(bxInstruction_c *i)
250 {
251 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
252
253 BX_NEXT_INSTR(i);
254 }
255
PFMUL_PqQq(bxInstruction_c * i)256 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFMUL_PqQq(bxInstruction_c *i)
257 {
258 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
259
260 BX_NEXT_INSTR(i);
261 }
262
PFRCPIT2_PqQq(bxInstruction_c * i)263 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PFRCPIT2_PqQq(bxInstruction_c *i)
264 {
265 BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeNameShort()));
266
267 BX_NEXT_INSTR(i);
268 }
269
270 /* 0F 0F /r B7 */
PMULHRW_PqQq(bxInstruction_c * i)271 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHRW_PqQq(bxInstruction_c *i)
272 {
273 #if BX_CPU_LEVEL >= 5
274 BX_CPU_THIS_PTR prepareMMX();
275
276 BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->dst()), op2, result;
277
278 /* op2 is a register or memory reference */
279 if (i->modC0()) {
280 op2 = BX_READ_MMX_REG(i->src());
281 }
282 else {
283 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
284 /* pointer, segment address pair */
285 op2 = read_virtual_qword(i->seg(), eaddr);
286 }
287
288 BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
289
290 Bit32s product1 = Bit32s(MMXSW0(op1)) * Bit32s(MMXSW0(op2)) + 0x8000;
291 Bit32s product2 = Bit32s(MMXSW1(op1)) * Bit32s(MMXSW1(op2)) + 0x8000;
292 Bit32s product3 = Bit32s(MMXSW2(op1)) * Bit32s(MMXSW2(op2)) + 0x8000;
293 Bit32s product4 = Bit32s(MMXSW3(op1)) * Bit32s(MMXSW3(op2)) + 0x8000;
294
295 MMXUW0(result) = Bit16u(product1 >> 16);
296 MMXUW1(result) = Bit16u(product2 >> 16);
297 MMXUW2(result) = Bit16u(product3 >> 16);
298 MMXUW3(result) = Bit16u(product4 >> 16);
299
300 /* now write result back to destination */
301 BX_WRITE_MMX_REG(i->dst(), result);
302
303 BX_NEXT_INSTR(i);
304 #endif
305 }
306
307 /* 0F 0F /r BB */
PSWAPD_PqQq(bxInstruction_c * i)308 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSWAPD_PqQq(bxInstruction_c *i)
309 {
310 #if BX_CPU_LEVEL >= 5
311 BX_CPU_THIS_PTR prepareMMX();
312
313 BxPackedMmxRegister result, op;
314
315 /* op is a register or memory reference */
316 if (i->modC0()) {
317 op = BX_READ_MMX_REG(i->src());
318 }
319 else {
320 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
321 /* pointer, segment address pair */
322 op = read_virtual_qword(i->seg(), eaddr);
323 }
324
325 BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
326
327 MMXUD0(result) = MMXUD1(op);
328 MMXUD1(result) = MMXUD0(op);
329
330 /* now write result back to destination */
331 BX_WRITE_MMX_REG(i->dst(), result);
332
333 BX_NEXT_INSTR(i);
334 #endif
335 }
336
337 #endif
338