1 /* 2 * UniPhier DDR PHY registers 3 * 4 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef ARCH_DDRPHY_REGS_H 10 #define ARCH_DDRPHY_REGS_H 11 12 #include <linux/compiler.h> 13 14 #ifndef __ASSEMBLY__ 15 16 struct ddrphy { 17 u32 ridr; /* Revision Identification Register */ 18 u32 pir; /* PHY Initialixation Register */ 19 u32 pgcr[2]; /* PHY General Configuration Register */ 20 u32 pgsr[2]; /* PHY General Status Register */ 21 u32 pllcr; /* PLL Control Register */ 22 u32 ptr[5]; /* PHY Timing Register */ 23 u32 acmdlr; /* AC Master Delay Line Register */ 24 u32 acbdlr; /* AC Bit Delay Line Register */ 25 u32 aciocr; /* AC I/O Configuration Register */ 26 u32 dxccr; /* DATX8 Common Configuration Register */ 27 u32 dsgcr; /* DDR System General Configuration Register */ 28 u32 dcr; /* DRAM Configuration Register */ 29 u32 dtpr[3]; /* DRAM Timing Parameters Register */ 30 u32 mr0; /* Mode Register 0 */ 31 u32 mr1; /* Mode Register 1 */ 32 u32 mr2; /* Mode Register 2 */ 33 u32 mr3; /* Mode Register 3 */ 34 u32 odtcr; /* ODT Configuration Register */ 35 u32 dtcr; /* Data Training Configuration Register */ 36 u32 dtar[4]; /* Data Training Address Register */ 37 u32 dtdr[2]; /* Data Training Data Register */ 38 u32 dtedr[2]; /* Data Training Eye Data Register */ 39 u32 pgcr2; /* PHY General Configuration Register 2 */ 40 u32 rsv0[8]; /* Reserved */ 41 u32 rdimmgcr[2]; /* RDIMM General Configuration Register */ 42 u32 rdimmcr0[2]; /* RDIMM Control Register */ 43 u32 dcuar; /* DCU Address Register */ 44 u32 dcudr; /* DCU Data Register */ 45 u32 dcurr; /* DCU Run Register */ 46 u32 dculr; /* DCU Loop Register */ 47 u32 dcugcr; /* DCU General Configuration Register */ 48 u32 dcutpr; /* DCU Timing Parameters Register */ 49 u32 dcusr[2]; /* DCU Status Register */ 50 u32 rsv1[8]; /* Reserved */ 51 u32 bistrr; /* BIST Run Register */ 52 u32 bistwcr; /* BIST Word Count Register */ 53 u32 bistmskr[3]; /* BIST Mask Register */ 54 u32 bistlsr; /* BIST LFSR Sed Register */ 55 u32 bistar[3]; /* BIST Address Register */ 56 u32 bistudpr; /* BIST User Data Pattern Register */ 57 u32 bistgsr; /* BIST General Status Register */ 58 u32 bistwer; /* BIST Word Error Register */ 59 u32 bistber[4]; /* BIST Bit Error Register */ 60 u32 bistwcsr; /* BIST Word Count Status Register */ 61 u32 bistfwr[3]; /* BIST Fail Word Register */ 62 u32 rsv2[10]; /* Reserved */ 63 u32 gpr[2]; /* General Purpose Register */ 64 struct ddrphy_zq { /* ZQ */ 65 u32 cr[2]; /* Impedance Control Register */ 66 u32 sr[2]; /* Impedance Status Register */ 67 } zq[4]; 68 struct ddrphy_datx8 { /* DATX8 */ 69 u32 gcr; /* General Configuration Register */ 70 u32 gsr[2]; /* General Status Register */ 71 u32 bdlr[5]; /* Bit Delay Line Register */ 72 u32 lcdlr[3]; /* Local Calibrated Delay Line Register */ 73 u32 mdlr; /* Master Delay Line Register */ 74 u32 gtr; /* General Timing Register */ 75 u32 gsr2; /* General Status Register 2 */ 76 u32 rsv[2]; /* Reserved */ 77 } dx[9]; 78 }; 79 80 #endif /* __ASSEMBLY__ */ 81 82 #define PIR_INIT (1 << 0) /* Initialization Trigger */ 83 #define PIR_ZCAL (1 << 1) /* Impedance Calibration */ 84 #define PIR_PLLINIT (1 << 4) /* PLL Initialization */ 85 #define PIR_DCAL (1 << 5) /* DDL Calibration */ 86 #define PIR_PHYRST (1 << 6) /* PHY Reset */ 87 #define PIR_DRAMRST (1 << 7) /* DRAM Reset */ 88 #define PIR_DRAMINIT (1 << 8) /* DRAM Initialization */ 89 #define PIR_WL (1 << 9) /* Write Leveling */ 90 #define PIR_QSGATE (1 << 10) /* Read DQS Gate Training */ 91 #define PIR_WLADJ (1 << 11) /* Write Leveling Adjust */ 92 #define PIR_RDDSKW (1 << 12) /* Read Data Bit Deskew */ 93 #define PIR_WRDSKW (1 << 13) /* Write Data Bit Deskew */ 94 #define PIR_RDEYE (1 << 14) /* Read Data Eye Training */ 95 #define PIR_WREYE (1 << 15) /* Write Data Eye Training */ 96 #define PIR_LOCKBYP (1 << 28) /* PLL Lock Bypass */ 97 #define PIR_DCALBYP (1 << 29) /* DDL Calibration Bypass */ 98 #define PIR_ZCALBYP (1 << 30) /* Impedance Calib Bypass */ 99 #define PIR_INITBYP (1 << 31) /* Initialization Bypass */ 100 101 #define PGSR0_IDONE (1 << 0) /* Initialization Done */ 102 #define PGSR0_PLDONE (1 << 1) /* PLL Lock Done */ 103 #define PGSR0_DCDONE (1 << 2) /* DDL Calibration Done */ 104 #define PGSR0_ZCDONE (1 << 3) /* Impedance Calibration Done */ 105 #define PGSR0_DIDONE (1 << 4) /* DRAM Initialization Done */ 106 #define PGSR0_WLDONE (1 << 5) /* Write Leveling Done */ 107 #define PGSR0_QSGDONE (1 << 6) /* DQS Gate Training Done */ 108 #define PGSR0_WLADONE (1 << 7) /* Write Leveling Adjust Done */ 109 #define PGSR0_RDDONE (1 << 8) /* Read Bit Deskew Done */ 110 #define PGSR0_WDDONE (1 << 9) /* Write Bit Deskew Done */ 111 #define PGSR0_REDONE (1 << 10) /* Read Eye Training Done */ 112 #define PGSR0_WEDONE (1 << 11) /* Write Eye Training Done */ 113 #define PGSR0_IERR (1 << 16) /* Initialization Error */ 114 #define PGSR0_PLERR (1 << 17) /* PLL Lock Error */ 115 #define PGSR0_DCERR (1 << 18) /* DDL Calibration Error */ 116 #define PGSR0_ZCERR (1 << 19) /* Impedance Calib Error */ 117 #define PGSR0_DIERR (1 << 20) /* DRAM Initialization Error */ 118 #define PGSR0_WLERR (1 << 21) /* Write Leveling Error */ 119 #define PGSR0_QSGERR (1 << 22) /* DQS Gate Training Error */ 120 #define PGSR0_WLAERR (1 << 23) /* Write Leveling Adj Error */ 121 #define PGSR0_RDERR (1 << 24) /* Read Bit Deskew Error */ 122 #define PGSR0_WDERR (1 << 25) /* Write Bit Deskew Error */ 123 #define PGSR0_REERR (1 << 26) /* Read Eye Training Error */ 124 #define PGSR0_WEERR (1 << 27) /* Write Eye Training Error */ 125 #define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/ 126 #define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT)) 127 #define PGSR0_APLOCK (1 << 31) /* AC PLL Lock */ 128 129 #define DXCCR_DQSRES_OPEN (0 << 5) 130 #define DXCCR_DQSRES_688_OHM (1 << 5) 131 #define DXCCR_DQSRES_611_OHM (2 << 5) 132 #define DXCCR_DQSRES_550_OHM (3 << 5) 133 #define DXCCR_DQSRES_500_OHM (4 << 5) 134 #define DXCCR_DQSRES_458_OHM (5 << 5) 135 #define DXCCR_DQSRES_393_OHM (6 << 5) 136 #define DXCCR_DQSRES_344_OHM (7 << 5) 137 138 #define DXCCR_DQSNRES_OPEN (0 << 9) 139 #define DXCCR_DQSNRES_688_OHM (1 << 9) 140 #define DXCCR_DQSNRES_611_OHM (2 << 9) 141 #define DXCCR_DQSNRES_550_OHM (3 << 9) 142 #define DXCCR_DQSNRES_500_OHM (4 << 9) 143 #define DXCCR_DQSNRES_458_OHM (5 << 9) 144 #define DXCCR_DQSNRES_393_OHM (6 << 9) 145 #define DXCCR_DQSNRES_344_OHM (7 << 9) 146 147 #define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */ 148 #define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT)) 149 #define DTCR_DTMPR (1 << 6) /* Data Training using MPR */ 150 #define DTCR_RNKEN_SHIFT 24 /* Rank Enable */ 151 #define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT)) 152 153 #define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ 154 #define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT)) 155 156 /* SoC-specific parameters */ 157 #define NR_DATX8_PER_DDRPHY 2 158 159 #if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) 160 #define NR_DDRPHY_PER_CH 1 161 #else 162 #define NR_DDRPHY_PER_CH 2 163 #endif 164 165 #define NR_DDRCH 2 166 167 #define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy)) 168 169 #ifndef __ASSEMBLY__ 170 void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); 171 void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank); 172 int ddrphy_training(struct ddrphy __iomem *phy); 173 #endif 174 175 #endif /* ARCH_DDRPHY_REGS_H */ 176