1 /* $NetBSD: display_mode_vba.h,v 1.2 2021/12/18 23:45:04 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 29 #ifndef __DML2_DISPLAY_MODE_VBA_H__ 30 #define __DML2_DISPLAY_MODE_VBA_H__ 31 32 #include "dml_common_defs.h" 33 34 struct display_mode_lib; 35 36 void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib); 37 38 #define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes) 39 40 dml_get_attr_decl(clk_dcf_deepsleep); 41 dml_get_attr_decl(wm_urgent); 42 dml_get_attr_decl(wm_memory_trip); 43 dml_get_attr_decl(wm_writeback_urgent); 44 dml_get_attr_decl(wm_stutter_exit); 45 dml_get_attr_decl(wm_stutter_enter_exit); 46 dml_get_attr_decl(wm_dram_clock_change); 47 dml_get_attr_decl(wm_writeback_dram_clock_change); 48 dml_get_attr_decl(wm_xfc_underflow); 49 dml_get_attr_decl(stutter_efficiency_no_vblank); 50 dml_get_attr_decl(stutter_efficiency); 51 dml_get_attr_decl(urgent_latency); 52 dml_get_attr_decl(urgent_extra_latency); 53 dml_get_attr_decl(nonurgent_latency); 54 dml_get_attr_decl(dram_clock_change_latency); 55 dml_get_attr_decl(dispclk_calculated); 56 dml_get_attr_decl(total_data_read_bw); 57 dml_get_attr_decl(return_bw); 58 dml_get_attr_decl(tcalc); 59 dml_get_attr_decl(fraction_of_urgent_bandwidth); 60 dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip); 61 62 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe) 63 64 dml_get_pipe_attr_decl(dsc_delay); 65 dml_get_pipe_attr_decl(dppclk_calculated); 66 dml_get_pipe_attr_decl(dscclk_calculated); 67 dml_get_pipe_attr_decl(min_ttu_vblank); 68 dml_get_pipe_attr_decl(vratio_prefetch_l); 69 dml_get_pipe_attr_decl(vratio_prefetch_c); 70 dml_get_pipe_attr_decl(dst_x_after_scaler); 71 dml_get_pipe_attr_decl(dst_y_after_scaler); 72 dml_get_pipe_attr_decl(dst_y_per_vm_vblank); 73 dml_get_pipe_attr_decl(dst_y_per_row_vblank); 74 dml_get_pipe_attr_decl(dst_y_prefetch); 75 dml_get_pipe_attr_decl(dst_y_per_vm_flip); 76 dml_get_pipe_attr_decl(dst_y_per_row_flip); 77 dml_get_pipe_attr_decl(xfc_transfer_delay); 78 dml_get_pipe_attr_decl(xfc_precharge_delay); 79 dml_get_pipe_attr_decl(xfc_remote_surface_flip_latency); 80 dml_get_pipe_attr_decl(xfc_prefetch_margin); 81 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank); 82 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip); 83 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank); 84 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip); 85 86 unsigned int get_vstartup_calculated( 87 struct display_mode_lib *mode_lib, 88 const display_e2e_pipe_params_st *pipes, 89 unsigned int num_pipes, 90 unsigned int which_pipe); 91 92 double get_total_immediate_flip_bytes( 93 struct display_mode_lib *mode_lib, 94 const display_e2e_pipe_params_st *pipes, 95 unsigned int num_pipes); 96 double get_total_immediate_flip_bw( 97 struct display_mode_lib *mode_lib, 98 const display_e2e_pipe_params_st *pipes, 99 unsigned int num_pipes); 100 double get_total_prefetch_bw( 101 struct display_mode_lib *mode_lib, 102 const display_e2e_pipe_params_st *pipes, 103 unsigned int num_pipes); 104 unsigned int dml_get_voltage_level( 105 struct display_mode_lib *mode_lib, 106 const display_e2e_pipe_params_st *pipes, 107 unsigned int num_pipes); 108 109 void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib); 110 111 bool Calculate256BBlockSizes( 112 enum source_format_class SourcePixelFormat, 113 enum dm_swizzle_mode SurfaceTiling, 114 unsigned int BytePerPixelY, 115 unsigned int BytePerPixelC, 116 unsigned int *BlockHeight256BytesY, 117 unsigned int *BlockHeight256BytesC, 118 unsigned int *BlockWidth256BytesY, 119 unsigned int *BlockWidth256BytesC); 120 121 struct vba_vars_st { 122 ip_params_st ip; 123 soc_bounding_box_st soc; 124 125 int maxMpcComb; 126 bool UseMaximumVStartup; 127 128 double WritebackDISPCLK; 129 double DPPCLKUsingSingleDPPLuma; 130 double DPPCLKUsingSingleDPPChroma; 131 double DISPCLKWithRamping; 132 double DISPCLKWithoutRamping; 133 double GlobalDPPCLK; 134 double DISPCLKWithRampingRoundedToDFSGranularity; 135 double DISPCLKWithoutRampingRoundedToDFSGranularity; 136 double MaxDispclkRoundedToDFSGranularity; 137 bool DCCEnabledAnyPlane; 138 double ReturnBandwidthToDCN; 139 unsigned int TotalActiveDPP; 140 unsigned int TotalDCCActiveDPP; 141 double UrgentRoundTripAndOutOfOrderLatency; 142 double StutterPeriod; 143 double FrameTimeForMinFullDETBufferingTime; 144 double AverageReadBandwidth; 145 double TotalRowReadBandwidth; 146 double PartOfBurstThatFitsInROB; 147 double StutterBurstTime; 148 unsigned int NextPrefetchMode; 149 double NextMaxVStartup; 150 double VBlankTime; 151 double SmallestVBlank; 152 double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX]; 153 double EffectiveDETPlusLBLinesLuma; 154 double EffectiveDETPlusLBLinesChroma; 155 double UrgentLatencySupportUsLuma; 156 double UrgentLatencySupportUsChroma; 157 unsigned int DSCFormatFactor; 158 159 bool DummyPStateCheck; 160 bool DRAMClockChangeSupportsVActive; 161 bool PrefetchModeSupported; 162 bool PrefetchAndImmediateFlipSupported; 163 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only 164 double XFCRemoteSurfaceFlipDelay; 165 double TInitXFill; 166 double TslvChk; 167 double SrcActiveDrainRate; 168 bool ImmediateFlipSupported; 169 enum mpc_combine_affinity WhenToDoMPCCombine; // Mode Support only 170 171 bool PrefetchERROR; 172 173 unsigned int VStartupLines; 174 unsigned int ActiveDPPs; 175 unsigned int LBLatencyHidingSourceLinesY; 176 unsigned int LBLatencyHidingSourceLinesC; 177 double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; 178 double MinActiveDRAMClockChangeMargin; 179 double InitFillLevel; 180 double FinalFillMargin; 181 double FinalFillLevel; 182 double RemainingFillLevel; 183 double TFinalxFill; 184 185 // 186 // SOC Bounding Box Parameters 187 // 188 double SRExitTime; 189 double SREnterPlusExitTime; 190 double UrgentLatencyPixelDataOnly; 191 double UrgentLatencyPixelMixedWithVMData; 192 double UrgentLatencyVMDataOnly; 193 double UrgentLatency; // max of the above three 194 double WritebackLatency; 195 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support 196 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support 197 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; // Mode Support 198 double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; // Mode Support 199 double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation; // Mode Support 200 double NumberOfChannels; 201 double DRAMChannelWidth; 202 double FabricDatapathToDCNDataReturn; 203 double ReturnBusWidth; 204 double Downspreading; 205 double DISPCLKDPPCLKDSCCLKDownSpreading; 206 double DISPCLKDPPCLKVCOSpeed; 207 double RoundTripPingLatencyCycles; 208 double UrgentOutOfOrderReturnPerChannel; 209 double UrgentOutOfOrderReturnPerChannelPixelDataOnly; 210 double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData; 211 double UrgentOutOfOrderReturnPerChannelVMDataOnly; 212 unsigned int VMMPageSize; 213 double DRAMClockChangeLatency; 214 double XFCBusTransportTime; 215 bool UseUrgentBurstBandwidth; 216 double XFCXBUFLatencyTolerance; 217 218 // 219 // IP Parameters 220 // 221 unsigned int ROBBufferSizeInKByte; 222 double DETBufferSizeInKByte; 223 double DETBufferSizeInTime; 224 unsigned int DPPOutputBufferPixels; 225 unsigned int OPPOutputBufferLines; 226 unsigned int PixelChunkSizeInKByte; 227 double ReturnBW; 228 bool GPUVMEnable; 229 bool HostVMEnable; 230 unsigned int GPUVMMaxPageTableLevels; 231 unsigned int HostVMMaxPageTableLevels; 232 unsigned int HostVMCachedPageTableLevels; 233 unsigned int OverrideGPUVMPageTableLevels; 234 unsigned int OverrideHostVMPageTableLevels; 235 unsigned int MetaChunkSize; 236 double MinPixelChunkSizeBytes; 237 double MinMetaChunkSizeBytes; 238 unsigned int WritebackChunkSize; 239 bool ODMCapability; 240 unsigned int NumberOfDSC; 241 unsigned int LineBufferSize; 242 unsigned int MaxLineBufferLines; 243 unsigned int WritebackInterfaceLumaBufferSize; 244 unsigned int WritebackInterfaceChromaBufferSize; 245 unsigned int WritebackChromaLineBufferWidth; 246 enum writeback_config WritebackConfiguration; 247 double MaxDCHUBToPSCLThroughput; 248 double MaxPSCLToLBThroughput; 249 unsigned int PTEBufferSizeInRequestsLuma; 250 unsigned int PTEBufferSizeInRequestsChroma; 251 double DISPCLKRampingMargin; 252 unsigned int MaxInterDCNTileRepeaters; 253 bool XFCSupported; 254 double XFCSlvChunkSize; 255 double XFCFillBWOverhead; 256 double XFCFillConstant; 257 double XFCTSlvVupdateOffset; 258 double XFCTSlvVupdateWidth; 259 double XFCTSlvVreadyOffset; 260 double DPPCLKDelaySubtotal; 261 double DPPCLKDelaySCL; 262 double DPPCLKDelaySCLLBOnly; 263 double DPPCLKDelayCNVCFormater; 264 double DPPCLKDelayCNVCCursor; 265 double DISPCLKDelaySubtotal; 266 bool ProgressiveToInterlaceUnitInOPP; 267 // Pipe/Plane Parameters 268 int VoltageLevel; 269 double FabricClock; 270 double DRAMSpeed; 271 double DISPCLK; 272 double SOCCLK; 273 double DCFCLK; 274 275 unsigned int NumberOfActivePlanes; 276 unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX]; 277 unsigned int ViewportWidth[DC__NUM_DPP__MAX]; 278 unsigned int ViewportHeight[DC__NUM_DPP__MAX]; 279 unsigned int ViewportYStartY[DC__NUM_DPP__MAX]; 280 unsigned int ViewportYStartC[DC__NUM_DPP__MAX]; 281 unsigned int PitchY[DC__NUM_DPP__MAX]; 282 unsigned int PitchC[DC__NUM_DPP__MAX]; 283 double HRatio[DC__NUM_DPP__MAX]; 284 double VRatio[DC__NUM_DPP__MAX]; 285 unsigned int htaps[DC__NUM_DPP__MAX]; 286 unsigned int vtaps[DC__NUM_DPP__MAX]; 287 unsigned int HTAPsChroma[DC__NUM_DPP__MAX]; 288 unsigned int VTAPsChroma[DC__NUM_DPP__MAX]; 289 unsigned int HTotal[DC__NUM_DPP__MAX]; 290 unsigned int VTotal[DC__NUM_DPP__MAX]; 291 unsigned int VTotal_Max[DC__NUM_DPP__MAX]; 292 unsigned int VTotal_Min[DC__NUM_DPP__MAX]; 293 int DPPPerPlane[DC__NUM_DPP__MAX]; 294 double PixelClock[DC__NUM_DPP__MAX]; 295 double PixelClockBackEnd[DC__NUM_DPP__MAX]; 296 bool DCCEnable[DC__NUM_DPP__MAX]; 297 bool FECEnable[DC__NUM_DPP__MAX]; 298 unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX]; 299 unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX]; 300 enum scan_direction_class SourceScan[DC__NUM_DPP__MAX]; 301 enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX]; 302 bool WritebackEnable[DC__NUM_DPP__MAX]; 303 unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX]; 304 double WritebackDestinationWidth[DC__NUM_DPP__MAX]; 305 double WritebackDestinationHeight[DC__NUM_DPP__MAX]; 306 double WritebackSourceHeight[DC__NUM_DPP__MAX]; 307 enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX]; 308 unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX]; 309 unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX]; 310 unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX]; 311 unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX]; 312 double WritebackHRatio[DC__NUM_DPP__MAX]; 313 double WritebackVRatio[DC__NUM_DPP__MAX]; 314 unsigned int HActive[DC__NUM_DPP__MAX]; 315 unsigned int VActive[DC__NUM_DPP__MAX]; 316 bool Interlace[DC__NUM_DPP__MAX]; 317 enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX]; 318 unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX]; 319 bool DynamicMetadataEnable[DC__NUM_DPP__MAX]; 320 int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX]; 321 unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX]; 322 double DCCRate[DC__NUM_DPP__MAX]; 323 double AverageDCCCompressionRate; 324 enum odm_combine_mode ODMCombineEnabled[DC__NUM_DPP__MAX]; 325 double OutputBpp[DC__NUM_DPP__MAX]; 326 bool DSCEnabled[DC__NUM_DPP__MAX]; 327 unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX]; 328 enum output_format_class OutputFormat[DC__NUM_DPP__MAX]; 329 enum output_encoder_class Output[DC__NUM_DPP__MAX]; 330 unsigned int BlendingAndTiming[DC__NUM_DPP__MAX]; 331 bool SynchronizedVBlank; 332 unsigned int NumberOfCursors[DC__NUM_DPP__MAX]; 333 unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX]; 334 unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX]; 335 bool XFCEnabled[DC__NUM_DPP__MAX]; 336 bool ScalerEnabled[DC__NUM_DPP__MAX]; 337 338 // Intermediates/Informational 339 bool ImmediateFlipSupport; 340 double DETBufferSizeY[DC__NUM_DPP__MAX]; 341 double DETBufferSizeC[DC__NUM_DPP__MAX]; 342 unsigned int SwathHeightY[DC__NUM_DPP__MAX]; 343 unsigned int SwathHeightC[DC__NUM_DPP__MAX]; 344 unsigned int LBBitPerPixel[DC__NUM_DPP__MAX]; 345 double LastPixelOfLineExtraWatermark; 346 double TotalDataReadBandwidth; 347 unsigned int TotalActiveWriteback; 348 unsigned int EffectiveLBLatencyHidingSourceLinesLuma; 349 unsigned int EffectiveLBLatencyHidingSourceLinesChroma; 350 double BandwidthAvailableForImmediateFlip; 351 unsigned int PrefetchMode[DC__VOLTAGE_STATES + 1][2]; 352 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES + 1][2]; 353 unsigned int MinPrefetchMode; 354 unsigned int MaxPrefetchMode; 355 bool AnyLinesForVMOrRowTooLarge; 356 double MaxVStartup; 357 bool IgnoreViewportPositioning; 358 bool ErrorResult[DC__NUM_DPP__MAX]; 359 // 360 // Calculated dml_ml->vba.Outputs 361 // 362 double DCFCLKDeepSleep; 363 double UrgentWatermark; 364 double UrgentExtraLatency; 365 double WritebackUrgentWatermark; 366 double StutterExitWatermark; 367 double StutterEnterPlusExitWatermark; 368 double DRAMClockChangeWatermark; 369 double WritebackDRAMClockChangeWatermark; 370 double StutterEfficiency; 371 double StutterEfficiencyNotIncludingVBlank; 372 double NonUrgentLatencyTolerance; 373 double MinActiveDRAMClockChangeLatencySupported; 374 375 // These are the clocks calcuated by the library but they are not actually 376 // used explicitly. They are fetched by tests and then possibly used. The 377 // ultimate values to use are the ones specified by the parameters to DML 378 double DISPCLK_calculated; 379 double DPPCLK_calculated[DC__NUM_DPP__MAX]; 380 381 unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX]; 382 double VUpdateWidthPix[DC__NUM_DPP__MAX]; 383 double VReadyOffsetPix[DC__NUM_DPP__MAX]; 384 385 unsigned int TotImmediateFlipBytes; 386 double TCalc; 387 388 display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX]; 389 unsigned int cache_num_pipes; 390 unsigned int pipe_plane[DC__NUM_DPP__MAX]; 391 392 /* vba mode support */ 393 /*inputs*/ 394 bool EmbeddedPanel[DC__NUM_DPP__MAX]; 395 bool SupportGFX7CompatibleTilingIn32bppAnd64bpp; 396 double MaxHSCLRatio; 397 double MaxVSCLRatio; 398 unsigned int MaxNumWriteback; 399 bool WritebackLumaAndChromaScalingSupported; 400 bool Cursor64BppSupport; 401 double DCFCLKPerState[DC__VOLTAGE_STATES + 1]; 402 double DCFCLKState[DC__VOLTAGE_STATES + 1][2]; 403 double FabricClockPerState[DC__VOLTAGE_STATES + 1]; 404 double SOCCLKPerState[DC__VOLTAGE_STATES + 1]; 405 double PHYCLKPerState[DC__VOLTAGE_STATES + 1]; 406 double DTBCLKPerState[DC__VOLTAGE_STATES + 1]; 407 double MaxDppclk[DC__VOLTAGE_STATES + 1]; 408 double MaxDSCCLK[DC__VOLTAGE_STATES + 1]; 409 double DRAMSpeedPerState[DC__VOLTAGE_STATES + 1]; 410 double MaxDispclk[DC__VOLTAGE_STATES + 1]; 411 int VoltageOverrideLevel; 412 413 /*outputs*/ 414 bool ScaleRatioAndTapsSupport; 415 bool SourceFormatPixelAndScanSupport; 416 double TotalBandwidthConsumedGBytePerSecond; 417 bool DCCEnabledInAnyPlane; 418 bool WritebackLatencySupport; 419 bool WritebackModeSupport; 420 bool Writeback10bpc420Supported; 421 bool BandwidthSupport[DC__VOLTAGE_STATES + 1]; 422 unsigned int TotalNumberOfActiveWriteback; 423 double CriticalPoint; 424 double ReturnBWToDCNPerState; 425 bool IsErrorResult[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 426 bool prefetch_vm_bw_valid; 427 bool prefetch_row_bw_valid; 428 bool NumberOfOTGSupport; 429 bool NonsupportedDSCInputBPC; 430 bool WritebackScaleRatioAndTapsSupport; 431 bool CursorSupport; 432 bool PitchSupport; 433 enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES + 1]; 434 435 double WritebackLineBufferLumaBufferSize; 436 double WritebackLineBufferChromaBufferSize; 437 double WritebackMinHSCLRatio; 438 double WritebackMinVSCLRatio; 439 double WritebackMaxHSCLRatio; 440 double WritebackMaxVSCLRatio; 441 double WritebackMaxHSCLTaps; 442 double WritebackMaxVSCLTaps; 443 unsigned int MaxNumDPP; 444 unsigned int MaxNumOTG; 445 double CursorBufferSize; 446 double CursorChunkSize; 447 unsigned int Mode; 448 double OutputLinkDPLanes[DC__NUM_DPP__MAX]; 449 double ForcedOutputLinkBPP[DC__NUM_DPP__MAX]; // Mode Support only 450 double ImmediateFlipBW[DC__NUM_DPP__MAX]; 451 double MaxMaxVStartup[DC__VOLTAGE_STATES + 1][2]; 452 453 double WritebackLumaVExtra; 454 double WritebackChromaVExtra; 455 double WritebackRequiredDISPCLK; 456 double MaximumSwathWidthSupport; 457 double MaximumSwathWidthInDETBuffer; 458 double MaximumSwathWidthInLineBuffer; 459 double MaxDispclkRoundedDownToDFSGranularity; 460 double MaxDppclkRoundedDownToDFSGranularity; 461 double PlaneRequiredDISPCLKWithoutODMCombine; 462 double PlaneRequiredDISPCLKWithODMCombine; 463 double PlaneRequiredDISPCLK; 464 double TotalNumberOfActiveOTG; 465 double FECOverhead; 466 double EffectiveFECOverhead; 467 double Outbpp; 468 unsigned int OutbppDSC; 469 double TotalDSCUnitsRequired; 470 double bpp; 471 unsigned int slices; 472 double SwathWidthGranularityY; 473 double RoundedUpMaxSwathSizeBytesY; 474 double SwathWidthGranularityC; 475 double RoundedUpMaxSwathSizeBytesC; 476 double EffectiveDETLBLinesLuma; 477 double EffectiveDETLBLinesChroma; 478 double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES + 1][2]; 479 double PDEAndMetaPTEBytesPerFrameY; 480 double PDEAndMetaPTEBytesPerFrameC; 481 unsigned int MetaRowBytesY; 482 unsigned int MetaRowBytesC; 483 unsigned int DPTEBytesPerRowC; 484 unsigned int DPTEBytesPerRowY; 485 double ExtraLatency; 486 double TimeCalc; 487 double TWait; 488 double MaximumReadBandwidthWithPrefetch; 489 double MaximumReadBandwidthWithoutPrefetch; 490 double total_dcn_read_bw_with_flip; 491 double total_dcn_read_bw_with_flip_no_urgent_burst; 492 double FractionOfUrgentBandwidth; 493 double FractionOfUrgentBandwidthImmediateFlip; // Mode Support debugging output 494 495 /* ms locals */ 496 double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES + 1][2]; 497 unsigned int NoOfDPP[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 498 int NoOfDPPThisState[DC__NUM_DPP__MAX]; 499 enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX]; 500 double SwathWidthYThisState[DC__NUM_DPP__MAX]; 501 unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 502 unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX]; 503 unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX]; 504 double VRatioPreY[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 505 double VRatioPreC[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 506 double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 507 double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 508 double RequiredDPPCLK[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 509 double RequiredDPPCLKThisState[DC__NUM_DPP__MAX]; 510 bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 511 bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 512 bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES + 1][2]; 513 bool PrefetchSupported[DC__VOLTAGE_STATES + 1][2]; 514 bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES + 1][2]; 515 double RequiredDISPCLK[DC__VOLTAGE_STATES + 1][2]; 516 bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES + 1][2]; 517 bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES + 1][2]; 518 unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES + 1][2]; 519 unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES + 1][2]; 520 bool ModeSupport[DC__VOLTAGE_STATES + 1][2]; 521 double ReturnBWPerState[DC__VOLTAGE_STATES + 1][2]; 522 bool DIOSupport[DC__VOLTAGE_STATES + 1]; 523 bool NotEnoughDSCUnits[DC__VOLTAGE_STATES + 1]; 524 bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1]; 525 bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1]; 526 double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES + 1]; 527 bool ROBSupport[DC__VOLTAGE_STATES + 1][2]; 528 bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES + 1][2]; 529 bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES + 1][2]; 530 double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES + 1][2]; 531 double PrefetchBW[DC__NUM_DPP__MAX]; 532 double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 533 double MetaRowBytes[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 534 double DPTEBytesPerRow[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 535 double PrefetchLinesY[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 536 double PrefetchLinesC[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 537 unsigned int MaxNumSwY[DC__NUM_DPP__MAX]; 538 unsigned int MaxNumSwC[DC__NUM_DPP__MAX]; 539 double PrefillY[DC__NUM_DPP__MAX]; 540 double PrefillC[DC__NUM_DPP__MAX]; 541 double LineTimesForPrefetch[DC__NUM_DPP__MAX]; 542 double LinesForMetaPTE[DC__NUM_DPP__MAX]; 543 double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX]; 544 double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX]; 545 double SwathWidthYSingleDPP[DC__NUM_DPP__MAX]; 546 double BytePerPixelInDETY[DC__NUM_DPP__MAX]; 547 double BytePerPixelInDETC[DC__NUM_DPP__MAX]; 548 bool RequiresDSC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX]; 549 unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX]; 550 double RequiresFEC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX]; 551 double OutputBppPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX]; 552 double DSCDelayPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX]; 553 bool ViewportSizeSupport[DC__VOLTAGE_STATES + 1][2]; 554 unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX]; 555 unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX]; 556 unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX]; 557 unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX]; 558 double MaxSwathHeightY[DC__NUM_DPP__MAX]; 559 double MaxSwathHeightC[DC__NUM_DPP__MAX]; 560 double MinSwathHeightY[DC__NUM_DPP__MAX]; 561 double MinSwathHeightC[DC__NUM_DPP__MAX]; 562 double ReadBandwidthLuma[DC__NUM_DPP__MAX]; 563 double ReadBandwidthChroma[DC__NUM_DPP__MAX]; 564 double ReadBandwidth[DC__NUM_DPP__MAX]; 565 double WriteBandwidth[DC__NUM_DPP__MAX]; 566 double PSCL_FACTOR[DC__NUM_DPP__MAX]; 567 double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX]; 568 double MaximumVStartup[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 569 unsigned int MacroTileWidthY[DC__NUM_DPP__MAX]; 570 unsigned int MacroTileWidthC[DC__NUM_DPP__MAX]; 571 double AlignedDCCMetaPitch[DC__NUM_DPP__MAX]; 572 double AlignedYPitch[DC__NUM_DPP__MAX]; 573 double AlignedCPitch[DC__NUM_DPP__MAX]; 574 double MaximumSwathWidth[DC__NUM_DPP__MAX]; 575 double cursor_bw[DC__NUM_DPP__MAX]; 576 double cursor_bw_pre[DC__NUM_DPP__MAX]; 577 double Tno_bw[DC__NUM_DPP__MAX]; 578 double prefetch_vmrow_bw[DC__NUM_DPP__MAX]; 579 double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX]; 580 double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX]; 581 double final_flip_bw[DC__NUM_DPP__MAX]; 582 bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES + 1][2]; 583 double WritebackDelay[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX]; 584 unsigned int vm_group_bytes[DC__NUM_DPP__MAX]; 585 unsigned int dpte_group_bytes[DC__NUM_DPP__MAX]; 586 unsigned int dpte_row_height[DC__NUM_DPP__MAX]; 587 unsigned int meta_req_height[DC__NUM_DPP__MAX]; 588 unsigned int meta_req_width[DC__NUM_DPP__MAX]; 589 unsigned int meta_row_height[DC__NUM_DPP__MAX]; 590 unsigned int meta_row_width[DC__NUM_DPP__MAX]; 591 unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX]; 592 unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX]; 593 unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX]; 594 unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX]; 595 unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX]; 596 bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX]; 597 double meta_row_bw[DC__NUM_DPP__MAX]; 598 double dpte_row_bw[DC__NUM_DPP__MAX]; 599 double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX]; // WM 600 double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX]; // WM 601 double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX]; 602 double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX]; 603 enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES + 1][2]; 604 double UrgentBurstFactorCursor[DC__NUM_DPP__MAX]; 605 double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX]; 606 double UrgentBurstFactorLuma[DC__NUM_DPP__MAX]; 607 double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX]; 608 double UrgentBurstFactorChroma[DC__NUM_DPP__MAX]; 609 double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX]; 610 611 612 bool MPCCombine[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 613 double SwathWidthCSingleDPP[DC__NUM_DPP__MAX]; 614 double MaximumSwathWidthInLineBufferLuma; 615 double MaximumSwathWidthInLineBufferChroma; 616 double MaximumSwathWidthLuma[DC__NUM_DPP__MAX]; 617 double MaximumSwathWidthChroma[DC__NUM_DPP__MAX]; 618 enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX]; 619 double dummy1[DC__NUM_DPP__MAX]; 620 double dummy2[DC__NUM_DPP__MAX]; 621 double dummy3[DC__NUM_DPP__MAX]; 622 double dummy4[DC__NUM_DPP__MAX]; 623 double dummy5; 624 double dummy6; 625 double dummy7[DC__NUM_DPP__MAX]; 626 double dummy8[DC__NUM_DPP__MAX]; 627 unsigned int dummyinteger1ms[DC__NUM_DPP__MAX]; 628 double dummyinteger2ms[DC__NUM_DPP__MAX]; 629 unsigned int dummyinteger3[DC__NUM_DPP__MAX]; 630 unsigned int dummyinteger4[DC__NUM_DPP__MAX]; 631 unsigned int dummyinteger5; 632 unsigned int dummyinteger6; 633 unsigned int dummyinteger7; 634 unsigned int dummyinteger8; 635 unsigned int dummyinteger9; 636 unsigned int dummyinteger10; 637 unsigned int dummyinteger11; 638 unsigned int dummyinteger12; 639 unsigned int dummyintegerarr1[DC__NUM_DPP__MAX]; 640 unsigned int dummyintegerarr2[DC__NUM_DPP__MAX]; 641 unsigned int dummyintegerarr3[DC__NUM_DPP__MAX]; 642 unsigned int dummyintegerarr4[DC__NUM_DPP__MAX]; 643 bool dummysinglestring; 644 bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX]; 645 double PlaneRequiredDISPCLKWithODMCombine2To1; 646 double PlaneRequiredDISPCLKWithODMCombine4To1; 647 unsigned int TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES + 1][2]; 648 bool LinkDSCEnable; 649 bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES + 1]; 650 enum odm_combine_mode ODMCombineEnableThisState[DC__NUM_DPP__MAX]; 651 double SwathWidthCThisState[DC__NUM_DPP__MAX]; 652 bool ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX]; 653 double AlignedDCCMetaPitchY[DC__NUM_DPP__MAX]; 654 double AlignedDCCMetaPitchC[DC__NUM_DPP__MAX]; 655 656 unsigned int NotEnoughUrgentLatencyHiding; 657 unsigned int NotEnoughUrgentLatencyHidingPre; 658 int PTEBufferSizeInRequestsForLuma; 659 int PTEBufferSizeInRequestsForChroma; 660 661 // Missing from VBA 662 int dpte_group_bytes_chroma; 663 unsigned int vm_group_bytes_chroma; 664 double dst_x_after_scaler; 665 double dst_y_after_scaler; 666 unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata; 667 668 /* perf locals*/ 669 double PrefetchBandwidth[DC__NUM_DPP__MAX]; 670 double VInitPreFillY[DC__NUM_DPP__MAX]; 671 double VInitPreFillC[DC__NUM_DPP__MAX]; 672 unsigned int MaxNumSwathY[DC__NUM_DPP__MAX]; 673 unsigned int MaxNumSwathC[DC__NUM_DPP__MAX]; 674 unsigned int VStartup[DC__NUM_DPP__MAX]; 675 double DSTYAfterScaler[DC__NUM_DPP__MAX]; 676 double DSTXAfterScaler[DC__NUM_DPP__MAX]; 677 bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX]; 678 bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX]; 679 double VRatioPrefetchY[DC__NUM_DPP__MAX]; 680 double VRatioPrefetchC[DC__NUM_DPP__MAX]; 681 double DestinationLinesForPrefetch[DC__NUM_DPP__MAX]; 682 double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX]; 683 double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX]; 684 double MinTTUVBlank[DC__NUM_DPP__MAX]; 685 double BytePerPixelDETY[DC__NUM_DPP__MAX]; 686 double BytePerPixelDETC[DC__NUM_DPP__MAX]; 687 double SwathWidthY[DC__NUM_DPP__MAX]; 688 double SwathWidthSingleDPPY[DC__NUM_DPP__MAX]; 689 double CursorRequestDeliveryTime[DC__NUM_DPP__MAX]; 690 double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX]; 691 double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX]; 692 double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX]; 693 double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX]; 694 double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX]; 695 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX]; 696 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX]; 697 double PixelPTEBytesPerRow[DC__NUM_DPP__MAX]; 698 double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX]; 699 double MetaRowByte[DC__NUM_DPP__MAX]; 700 double PrefetchSourceLinesY[DC__NUM_DPP__MAX]; 701 double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX]; 702 double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX]; 703 double PrefetchSourceLinesC[DC__NUM_DPP__MAX]; 704 double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX]; 705 double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX]; 706 double DSCCLK_calculated[DC__NUM_DPP__MAX]; 707 unsigned int DSCDelay[DC__NUM_DPP__MAX]; 708 unsigned int MaxVStartupLines[DC__NUM_DPP__MAX]; 709 double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX]; 710 double DPPCLK[DC__NUM_DPP__MAX]; 711 unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX]; 712 unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX]; 713 unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX]; 714 double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX]; 715 unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX]; 716 unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX]; 717 unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX]; 718 unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX]; 719 double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX]; 720 double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX]; 721 double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX]; 722 double XFCTransferDelay[DC__NUM_DPP__MAX]; 723 double XFCPrechargeDelay[DC__NUM_DPP__MAX]; 724 double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX]; 725 double XFCPrefetchMargin[DC__NUM_DPP__MAX]; 726 unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX]; 727 unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX]; 728 double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; // WM 729 double FullDETBufferingTimeC[DC__NUM_DPP__MAX]; // WM 730 double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX]; 731 double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX]; 732 double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX]; 733 double TimePerMetaChunkNominal[DC__NUM_DPP__MAX]; 734 double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX]; 735 double TimePerMetaChunkFlip[DC__NUM_DPP__MAX]; 736 unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX]; 737 unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX]; 738 unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX]; 739 unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX]; 740 unsigned int PTERequestSizeY[DC__NUM_DPP__MAX]; 741 unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX]; 742 unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX]; 743 unsigned int PTERequestSizeC[DC__NUM_DPP__MAX]; 744 double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX]; 745 double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX]; 746 double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX]; 747 double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX]; 748 double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX]; 749 double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX]; 750 double TimePerVMGroupVBlank[DC__NUM_DPP__MAX]; 751 double TimePerVMGroupFlip[DC__NUM_DPP__MAX]; 752 double TimePerVMRequestVBlank[DC__NUM_DPP__MAX]; 753 double TimePerVMRequestFlip[DC__NUM_DPP__MAX]; 754 unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX]; 755 unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX]; 756 unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX]; 757 unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX]; 758 double LinesToFinishSwathTransferStutterCriticalPlane; 759 unsigned int BytePerPixelYCriticalPlane; 760 double SwathWidthYCriticalPlane; 761 double LinesInDETY[DC__NUM_DPP__MAX]; 762 double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX]; 763 764 double SwathWidthSingleDPPC[DC__NUM_DPP__MAX]; 765 double SwathWidthC[DC__NUM_DPP__MAX]; 766 unsigned int BytePerPixelY[DC__NUM_DPP__MAX]; 767 unsigned int BytePerPixelC[DC__NUM_DPP__MAX]; 768 unsigned int dummyinteger1; 769 unsigned int dummyinteger2; 770 double FinalDRAMClockChangeLatency; 771 double Tdmdl_vm[DC__NUM_DPP__MAX]; 772 double Tdmdl[DC__NUM_DPP__MAX]; 773 unsigned int ThisVStartup; 774 bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX]; 775 double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX]; 776 double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX]; 777 double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX]; 778 double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX]; 779 unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX]; 780 unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX]; 781 unsigned int DCCCIndependent64ByteBlock[DC__NUM_DPP__MAX]; 782 double VStartupMargin; 783 bool NotEnoughTimeForDynamicMetadata; 784 785 /* Missing from VBA */ 786 unsigned int MaximumMaxVStartupLines; 787 double FabricAndDRAMBandwidth; 788 double LinesInDETLuma; 789 double LinesInDETChroma; 790 unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX]; 791 unsigned int LinesInDETC[DC__NUM_DPP__MAX]; 792 unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX]; 793 double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 794 double UrgentLatencySupportUs[DC__NUM_DPP__MAX]; 795 double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES + 1]; 796 bool UrgentLatencySupport[DC__VOLTAGE_STATES + 1][2]; 797 unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 798 unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 799 double qual_row_bw[DC__NUM_DPP__MAX]; 800 double prefetch_row_bw[DC__NUM_DPP__MAX]; 801 double prefetch_vm_bw[DC__NUM_DPP__MAX]; 802 803 double PTEGroupSize; 804 unsigned int PDEProcessingBufIn64KBReqs; 805 806 double MaxTotalVActiveRDBandwidth; 807 bool DoUrgentLatencyAdjustment; 808 double UrgentLatencyAdjustmentFabricClockComponent; 809 double UrgentLatencyAdjustmentFabricClockReference; 810 double MinUrgentLatencySupportUs; 811 double MinFullDETBufferingTime; 812 double AverageReadBandwidthGBytePerSecond; 813 bool FirstMainPlane; 814 815 unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX]; 816 unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX]; 817 double HRatioChroma[DC__NUM_DPP__MAX]; 818 double VRatioChroma[DC__NUM_DPP__MAX]; 819 int WritebackSourceWidth[DC__NUM_DPP__MAX]; 820 821 bool ModeIsSupported; 822 bool ODMCombine4To1Supported; 823 824 unsigned int SurfaceWidthY[DC__NUM_DPP__MAX]; 825 unsigned int SurfaceWidthC[DC__NUM_DPP__MAX]; 826 unsigned int SurfaceHeightY[DC__NUM_DPP__MAX]; 827 unsigned int SurfaceHeightC[DC__NUM_DPP__MAX]; 828 unsigned int WritebackHTaps[DC__NUM_DPP__MAX]; 829 unsigned int WritebackVTaps[DC__NUM_DPP__MAX]; 830 bool DSCEnable[DC__NUM_DPP__MAX]; 831 832 double DRAMClockChangeLatencyOverride; 833 834 double GPUVMMinPageSize; 835 double HostVMMinPageSize; 836 837 bool MPCCombineEnable[DC__NUM_DPP__MAX]; 838 unsigned int HostVMMaxNonCachedPageTableLevels; 839 bool DynamicMetadataVMEnabled; 840 double WritebackInterfaceBufferSize; 841 double WritebackLineBufferSize; 842 843 double DCCRateLuma[DC__NUM_DPP__MAX]; 844 double DCCRateChroma[DC__NUM_DPP__MAX]; 845 846 double PHYCLKD18PerState[DC__VOLTAGE_STATES + 1]; 847 int MinVoltageLevel; 848 int MaxVoltageLevel; 849 850 bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream; 851 bool NumberOfHDMIFRLSupport; 852 unsigned int MaxNumHDMIFRLOutputs; 853 int AudioSampleRate[DC__NUM_DPP__MAX]; 854 int AudioSampleLayout[DC__NUM_DPP__MAX]; 855 856 int PercentMarginOverMinimumRequiredDCFCLK; 857 bool DynamicMetadataSupported[DC__VOLTAGE_STATES + 1][2]; 858 enum immediate_flip_requirement ImmediateFlipRequirement; 859 double DETBufferSizeYThisState[DC__NUM_DPP__MAX]; 860 double DETBufferSizeCThisState[DC__NUM_DPP__MAX]; 861 bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX]; 862 bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX]; 863 int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX]; 864 int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX]; 865 double UrgLatency[DC__VOLTAGE_STATES + 1]; 866 double VActiveCursorBandwidth[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 867 double VActivePixelBandwidth[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 868 bool NoTimeForPrefetch[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 869 bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 870 double dpte_row_bandwidth[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 871 double meta_row_bandwidth[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 872 double DETBufferSizeYAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 873 double DETBufferSizeCAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 874 int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 875 int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 876 bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES + 1][2]; 877 unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 878 unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 879 unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 880 unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; 881 double TotalDPTERowBandwidth[DC__VOLTAGE_STATES + 1][2]; 882 double TotalMetaRowBandwidth[DC__VOLTAGE_STATES + 1][2]; 883 double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES + 1][2]; 884 double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES + 1][2]; 885 bool UseMinimumRequiredDCFCLK; 886 double WritebackDelayTime[DC__NUM_DPP__MAX]; 887 unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX]; 888 unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX]; 889 unsigned int dummyinteger15; 890 unsigned int dummyinteger16; 891 unsigned int dummyinteger17; 892 unsigned int dummyinteger18; 893 unsigned int dummyinteger19; 894 unsigned int dummyinteger20; 895 unsigned int dummyinteger21; 896 unsigned int dummyinteger22; 897 unsigned int dummyinteger23; 898 unsigned int dummyinteger24; 899 unsigned int dummyinteger25; 900 unsigned int dummyinteger26; 901 unsigned int dummyinteger27; 902 unsigned int dummyinteger28; 903 unsigned int dummyinteger29; 904 bool dummystring[DC__NUM_DPP__MAX]; 905 double BPP; 906 enum odm_combine_policy ODMCombinePolicy; 907 }; 908 909 bool CalculateMinAndMaxPrefetchMode( 910 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, 911 unsigned int *MinPrefetchMode, 912 unsigned int *MaxPrefetchMode); 913 914 double CalculateWriteBackDISPCLK( 915 enum source_format_class WritebackPixelFormat, 916 double PixelClock, 917 double WritebackHRatio, 918 double WritebackVRatio, 919 unsigned int WritebackLumaHTaps, 920 unsigned int WritebackLumaVTaps, 921 unsigned int WritebackChromaHTaps, 922 unsigned int WritebackChromaVTaps, 923 double WritebackDestinationWidth, 924 unsigned int HTotal, 925 unsigned int WritebackChromaLineBufferWidth); 926 927 #endif /* _DML2_DISPLAY_MODE_VBA_H_ */ 928