1 /* GNU PIC opcode definitions 2 Copyright (C) 2001, 2002, 2003, 2004, 2005 3 Craig Franklin 4 5 Copyright (C) 2014-2016 Molnar Karoly 6 7 This file is part of gputils. 8 9 gputils is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2, or (at your option) 12 any later version. 13 14 gputils is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with gputils; see the file COPYING. If not, write to 21 the Free Software Foundation, 59 Temple Place - Suite 330, 22 Boston, MA 02111-1307, USA. */ 23 24 #ifndef __GPOPCODE_H__ 25 #define __GPOPCODE_H__ 26 27 enum insn_class { 28 INSN_CLASS_LIT1, /* bit 0 contains a 1 bit literal */ 29 INSN_CLASS_LIT3, /* bits 2:0 contains a 3 bit literal */ 30 INSN_CLASS_LIT4H, /* bits 7:4 contain a 4 bit literal, bits 3:0 are unused */ 31 INSN_CLASS_LIT4L, /* bits 3:0 contain a 4 bit literal */ 32 INSN_CLASS_LIT5, /* bits 4:0 contain an 4 bit literal */ 33 INSN_CLASS_LIT6, /* bits 5:0 contain an 6 bit literal */ 34 INSN_CLASS_LITBSR_6, /* bits 6:0 contain an 6 bit literal for MOVLB (14bit enhX. cores) */ 35 INSN_CLASS_LIT7, /* bits 6:0 contain an 7 bit literal */ 36 INSN_CLASS_LIT8, /* bits 7:0 contain an 8 bit literal */ 37 INSN_CLASS_LIT8C12, /* bits 7:0 contain an 8 bit literal, 12 bit CALL */ 38 INSN_CLASS_LIT8C16, /* bits 7:0 contain an 8 bit literal, 16 bit CALL */ 39 INSN_CLASS_LIT9, /* bits 8:0 contain a 9 bit literal */ 40 INSN_CLASS_LIT11, /* bits 10:0 contain an 11 bit literal */ 41 INSN_CLASS_LIT13, /* bits 12:0 contain an 13 bit literal */ 42 INSN_CLASS_LITFSR_14, /* bits 5:0 contain an 6 bit literal for fsr (14bit enh. cores) */ 43 INSN_CLASS_LITFSR_16, /* bits 5:0 contain an 6 bit literal for fsr 7:6 (16bit cores) */ 44 INSN_CLASS_IMPLICIT, /* instruction has no variable bits at all */ 45 INSN_CLASS_OPF3, /* bits 2:0 contain a register address */ 46 INSN_CLASS_OPF5, /* bits 4:0 contain a register address */ 47 INSN_CLASS_OPWF5, /* as above, but bit 5 has a destination flag */ 48 INSN_CLASS_B5, /* as for OPF5, but bits 7:5 have bit number */ 49 INSN_CLASS_OPF7, /* bits 6:0 contain a register address */ 50 INSN_CLASS_OPWF7, /* as above, but bit 7 has destination flag */ 51 INSN_CLASS_B7, /* as for OPF7, but bits 9:7 have bit number */ 52 53 INSN_CLASS_OPF8, /* bits 7:0 contain a register address */ 54 INSN_CLASS_OPFA8, /* bits 7:0 contain a register address & bit has access flag */ 55 INSN_CLASS_OPWF8, /* as above, but bit 8 has dest flag */ 56 INSN_CLASS_OPWFA8, /* as above, but bit 9 has dest flag & bit 8 has access flag */ 57 INSN_CLASS_B8, /* like OPF7, but bits 9:11 have bit number */ 58 INSN_CLASS_BA8, /* like OPF7, but bits 9:11 have bit number & bit 8 has access flag */ 59 INSN_CLASS_LIT20, /* 20bit lit, bits 7:0 in first word bits 19:8 in second */ 60 INSN_CLASS_CALL20, /* Like LIT20, but bit 8 has fast push flag */ 61 INSN_CLASS_RBRA8, /* Bits 7:0 contain a relative branch address */ 62 INSN_CLASS_RBRA9, /* Bits 8:0 contain a relative branch address */ 63 INSN_CLASS_RBRA11, /* Bits 10:0 contain a relative branch address */ 64 INSN_CLASS_FLIT12, /* LFSR, 12bit lit loaded into 1 of 4 FSRs */ 65 INSN_CLASS_FF, /* two 12bit file addresses */ 66 INSN_CLASS_FP, /* Bits 7:0 contain a register address, bits 12:8 contains a peripheral address */ 67 INSN_CLASS_PF, /* Bits 7:0 contain a register address, bits 12:8 contains a peripheral address */ 68 69 INSN_CLASS_SF, /* 7 bit offset added to FSR2, fetched memory placed at 12 bit address */ 70 INSN_CLASS_SS, /* two 7 bit offsets, memory moved using FSR2 */ 71 72 INSN_CLASS_TBL, /* a table read or write instruction */ 73 INSN_CLASS_TBL2, /* a table read or write instruction. 74 Bits 7:0 contains a register address; Bit 8 is unused; 75 Bit 9, table byte select. (0:lower ; 1:upper) */ 76 INSN_CLASS_TBL3, /* a table read or write instruction. 77 Bits 7:0 contains a register address; 78 Bit 8, 1 if increment pointer, 0 otherwise; 79 Bit 9, table byte select. (0:lower ; 1:upper) */ 80 INSN_CLASS_FUNC, /* instruction is an assembler function */ 81 INSN_CLASS_LIT3_BANK, /* SX: bits 3:0 contain a 3 bit literal, shifted 5 bits */ 82 INSN_CLASS_LIT3_PAGE, /* SX: bits 3:0 contain a 3 bit literal, shifted 9 bits */ 83 INSN_CLASS_LIT4, /* SX: bits 3:0 contain a 4 bit literal */ 84 INSN_CLASS_MOVINDF /* enhanced 14-bit moviw and movwi insn arguments */ 85 }; 86 87 /****************************************** 88 PIC12 definitions 89 ******************************************/ 90 91 #define PIC12_CORE_MASK ((1u << 12) - 1) 92 #define PIC12_PC_MASK ((1u << 11) - 1) 93 94 /* General file bitmask. */ 95 #define PIC12_BMSK_FILE 0x01F 96 97 /* addwf : 0001 11df ffff 98 1111 1100 0000 <-- instruction mask */ 99 #define PIC12_INSN_ADDWF 0x1C0 100 #define PIC12_MASK_ADDWF 0xFC0 101 102 /* andlw : 1110 kkkk kkkk 103 1111 0000 0000 <-- instruction mask */ 104 #define PIC12_INSN_ANDLW 0xE00 105 #define PIC12_MASK_ANDLW 0xF00 106 107 /* andwf : 0001 01df ffff 108 1111 1100 0000 <-- instruction mask */ 109 #define PIC12_INSN_ANDWF 0x140 110 #define PIC12_MASK_ANDWF 0xFC0 111 112 /* bcf : 0100 bbbf ffff 113 1111 0000 0000 <-- instruction mask */ 114 #define PIC12_INSN_BCF 0x400 115 #define PIC12_MASK_BCF 0xF00 116 #define PIC12_BMSK_BCF (PIC12_MASK_BCF ^ PIC12_CORE_MASK) 117 118 /* bsf : 0101 bbbf ffff 119 1111 0000 0000 <-- instruction mask */ 120 #define PIC12_INSN_BSF 0x500 121 #define PIC12_MASK_BSF 0xF00 122 #define PIC12_BMSK_BSF (PIC12_MASK_BSF ^ PIC12_CORE_MASK) 123 124 /* PIC12_MASK_BCF == PIC12_MASK_BSF */ 125 #define PIC12_MASK_BxF PIC12_MASK_BCF 126 /* PIC12_BMSK_BCF == PIC12_BMSK_BSF */ 127 #define PIC12_BMSK_BxF PIC12_BMSK_BCF 128 129 #define PIC12_INSN_BxF_BITSHIFT 5 130 131 /* btfsc : 0110 bbbf ffff 132 1111 0000 0000 <-- instruction mask */ 133 #define PIC12_INSN_BTFSC 0x600 134 #define PIC12_MASK_BTFSC 0xF00 135 136 /* btfss : 0111 bbbf ffff 137 1111 0000 0000 <-- instruction mask */ 138 #define PIC12_INSN_BTFSS 0x700 139 #define PIC12_MASK_BTFSS 0xF00 140 141 /* call : 1001 kkkk kkkk 142 1111 0000 0000 <-- instruction mask */ 143 #define PIC12_INSN_CALL 0x900 144 #define PIC12_MASK_CALL 0xF00 145 /* Address mask. */ 146 #define PIC12_BMSK_CALL (PIC12_MASK_CALL ^ PIC12_CORE_MASK) 147 148 /* clrf : 0000 011f ffff 149 1111 1110 0000 <-- instruction mask */ 150 #define PIC12_INSN_CLRF 0x060 151 #define PIC12_MASK_CLRF 0xFE0 152 153 /* clrw : 0000 0100 0000 154 1111 1111 1111 <-- instruction mask */ 155 #define PIC12_INSN_CLRW 0x040 156 #define PIC12_MASK_CLRW 0xFFF 157 158 /* clrwdt: 0000 0000 0100 159 1111 1111 1111 <-- instruction mask */ 160 #define PIC12_INSN_CLRWDT 0x004 161 #define PIC12_MASK_CLRWDT 0xFFF 162 163 /* comf : 0010 01df ffff 164 1111 1100 0000 <-- instruction mask */ 165 #define PIC12_INSN_COMF 0x240 166 #define PIC12_MASK_COMF 0xFC0 167 168 /* decf : 0000 11df ffff 169 1111 1100 0000 <-- instruction mask */ 170 #define PIC12_INSN_DECF 0x0C0 171 #define PIC12_MASK_DECF 0xFC0 172 173 /* decfsz: 0010 11df ffff 174 1111 1100 0000 <-- instruction mask */ 175 #define PIC12_INSN_DECFSZ 0x2C0 176 #define PIC12_MASK_DECFSZ 0xFC0 177 178 /* goto : 101k kkkk kkkk 179 1110 0000 0000 <-- instruction mask */ 180 #define PIC12_INSN_GOTO 0xA00 181 #define PIC12_MASK_GOTO 0xE00 182 /* Address mask. */ 183 #define PIC12_BMSK_GOTO (PIC12_MASK_GOTO ^ PIC12_CORE_MASK) 184 185 /* incf : 0010 10df ffff 186 1111 1100 0000 <-- instruction mask */ 187 #define PIC12_INSN_INCF 0x280 188 #define PIC12_MASK_INCF 0xFC0 189 190 /* incfsz: 0011 11df ffff 191 1111 1100 0000 <-- instruction mask */ 192 #define PIC12_INSN_INCFSZ 0x3C0 193 #define PIC12_MASK_INCFSZ 0xFC0 194 195 /* iorlw : 1101 kkkk kkkk 196 1111 0000 0000 <-- instruction mask */ 197 #define PIC12_INSN_IORLW 0xD00 198 #define PIC12_MASK_IORLW 0xF00 199 200 /* iorwf : 0001 00df ffff 201 1111 1100 0000 <-- instruction mask */ 202 #define PIC12_INSN_IORWF 0x100 203 #define PIC12_MASK_IORWF 0xFC0 204 205 /* movf : 0010 00df ffff 206 1111 1100 0000 <-- instruction mask */ 207 #define PIC12_INSN_MOVF 0x200 208 #define PIC12_MASK_MOVF 0xFC0 209 210 /* movlw : 1100 kkkk kkkk 211 1111 0000 0000 <-- instruction mask */ 212 #define PIC12_INSN_MOVLW 0xC00 213 #define PIC12_MASK_MOVLW 0xF00 214 #define PIC12_BMSK_MOVLW (PIC12_MASK_MOVLW ^ PIC12_CORE_MASK) 215 216 /* movwf : 0000 001f ffff 217 1111 1110 0000 <-- instruction mask */ 218 #define PIC12_INSN_MOVWF 0x020 219 #define PIC12_MASK_MOVWF 0xFE0 220 221 /* nop : 0000 0000 0000 222 1111 1111 1111 <-- instruction mask */ 223 #define PIC12_INSN_NOP 0x000 224 #define PIC12_MASK_NOP 0xFFF 225 226 /* option: 0000 0000 0010 227 1111 1111 1111 <-- instruction mask */ 228 #define PIC12_INSN_OPTION 0x002 229 #define PIC12_MASK_OPTION 0xFFF 230 231 /* retlw : 1000 kkkk kkkk 232 1111 0000 0000 <-- instruction mask */ 233 #define PIC12_INSN_RETLW 0x800 234 #define PIC12_MASK_RETLW 0xF00 235 236 /* return: 1000 kkkk kkkk (Alias of retlw instruction.) 237 1111 1111 1111 <-- instruction mask */ 238 #define PIC12_INSN_RETURN 0x800 239 #define PIC12_MASK_RETURN 0xFFF 240 241 /* rlf : 0011 01df ffff 242 1111 1100 0000 <-- instruction mask */ 243 #define PIC12_INSN_RLF 0x340 244 #define PIC12_MASK_RLF 0xFC0 245 246 /* rrf : 0011 00df ffff 247 1111 1100 0000 <-- instruction mask */ 248 #define PIC12_INSN_RRF 0x300 249 #define PIC12_MASK_RRF 0xFC0 250 251 /* sleep : 0000 0000 0011 252 1111 1111 1111 <-- instruction mask */ 253 #define PIC12_INSN_SLEEP 0x003 254 #define PIC12_MASK_SLEEP 0xFFF 255 256 /* subwf : 0000 10df ffff 257 1111 1100 0000 <-- instruction mask */ 258 #define PIC12_INSN_SUBWF 0x080 259 #define PIC12_MASK_SUBWF 0xFC0 260 261 /* swapf : 0011 10df ffff 262 1111 1100 0000 <-- instruction mask */ 263 #define PIC12_INSN_SWAPF 0x380 264 #define PIC12_MASK_SWAPF 0xFC0 265 266 /* tris : 0000 0000 0fff 267 1111 1111 1000 <-- instruction mask */ 268 #define PIC12_INSN_TRIS 0x000 269 #define PIC12_MASK_TRIS 0xFF8 270 #define PIC12_BMSK_TRIS (PIC12_MASK_TRIS ^ PIC12_CORE_MASK) 271 272 /* xorlw : 1111 kkkk kkkk 273 1111 0000 0000 <-- instruction mask */ 274 #define PIC12_INSN_XORLW 0xF00 275 #define PIC12_MASK_XORLW 0xF00 276 277 /* xorwf : 0001 10df ffff 278 1111 1100 0000 <-- instruction mask */ 279 #define PIC12_INSN_XORWF 0x180 280 #define PIC12_MASK_XORWF 0xFC0 281 282 /****************************************** 283 PIC12E definitions 284 ******************************************/ 285 286 /* movlb : 0000 0001 0kkk 287 1111 1111 1000 <-- instruction mask */ 288 #define PIC12E_INSN_MOVLB 0x010 289 #define PIC12E_MASK_MOVLB 0xFF8 290 #define PIC12E_BMSK_MOVLB (PIC12E_MASK_MOVLB ^ PIC12_CORE_MASK) 291 292 /* retfie: 0000 0001 1111 293 1111 1111 1111 <-- instruction mask */ 294 #define PIC12E_INSN_RETFIE 0x01F 295 #define PIC12E_MASK_RETFIE 0xFFF 296 297 /* return: 0000 0001 1110 298 1111 1111 1111 <-- instruction mask */ 299 #define PIC12E_INSN_RETURN 0x01E 300 #define PIC12E_MASK_RETURN 0xFFF 301 302 /****************************************** 303 SX definitions 304 ******************************************/ 305 306 #define SX_PC_MASK ((1u << 12) - 1) 307 308 /* page : 0000 0001 1nnn 309 1111 1111 1000 <-- instruction mask */ 310 #define SX_INSN_BANK 0x018 311 #define SX_MASK_BANK 0xFF8 312 #define SX_BMSK_BANK (SX_MASK_BANK ^ PIC12_CORE_MASK) 313 314 /* iread : 0000 0100 0001 315 1111 1111 1111 <-- instruction mask */ 316 #define SX_INSN_IREAD 0x041 317 #define SX_MASK_IREAD 0xFFF 318 319 /* mov M,#lit : 0000 0101 kkkk 320 1111 1111 0000 <-- instruction mask */ 321 #define SX_INSN_MODE 0x050 322 #define SX_MASK_MODE 0xFF0 323 #define SX_BMSK_MODE (SX_MASK_MODE ^ PIC12_CORE_MASK) 324 325 /* mov W,M : 0000 0100 0010 326 1111 1111 1111 <-- instruction mask 327 M ==> W */ 328 #define SX_INSN_MOVMW 0x042 329 #define SX_MASK_MOVMW 0xFFF 330 331 /* mov M,W : 0000 0100 0011 332 1111 1111 1111 <-- instruction mask 333 W ==> M */ 334 #define SX_INSN_MOVWM 0x043 335 #define SX_MASK_MOVWM 0xFFF 336 337 /* page : 0000 0001 0nnn 338 1111 1111 1000 <-- instruction mask */ 339 #define SX_INSN_PAGE 0x010 340 #define SX_MASK_PAGE 0xFF8 341 #define SX_BMSK_PAGE (SX_MASK_PAGE ^ PIC12_CORE_MASK) 342 343 /* reti : 0000 0000 1110 344 1111 1111 1111 <-- instruction mask */ 345 #define SX_INSN_RETI 0x00E 346 #define SX_MASK_RETI 0xFFF 347 348 /* retiw : 0000 0000 1111 349 1111 1111 1111 <-- instruction mask */ 350 #define SX_INSN_RETIW 0x00F 351 #define SX_MASK_RETIW 0xFFF 352 353 /* retp : 0000 0000 1101 354 1111 1111 1111 <-- instruction mask */ 355 #define SX_INSN_RETP 0x00D 356 #define SX_MASK_RETP 0xFFF 357 358 /* ret : 0000 0000 1100 359 1111 1111 1111 <-- instruction mask */ 360 #define SX_INSN_RETURN 0x00C 361 #define SX_MASK_RETURN 0xFFF 362 363 /****************************************** 364 PIC14 definitions 365 ******************************************/ 366 367 #define PIC14_CORE_MASK ((1u << 14) - 1) 368 #define PIC14_PC_MASK ((1u << 13) - 1) 369 370 /* General file bitmask. */ 371 #define PIC14_BMSK_FILE 0x07F 372 #define PIC14_BMSK_TRIS 0x07 373 374 /* addlw : 11 111x kkkk kkkk 375 11 1110 0000 0000 <-- instruction mask */ 376 #define PIC14_INSN_ADDLW 0x3E00 377 #define PIC14_MASK_ADDLW 0x3E00 378 379 /* addwf : 00 0111 dfff ffff 380 11 1111 0000 0000 <-- instruction mask */ 381 #define PIC14_INSN_ADDWF 0x0700 382 #define PIC14_MASK_ADDWF 0x3F00 383 384 /* andlw : 11 1001 kkkk kkkk 385 11 1111 0000 0000 <-- instruction mask */ 386 #define PIC14_INSN_ANDLW 0x3900 387 #define PIC14_MASK_ANDLW 0x3F00 388 389 /* andwf : 00 0101 dfff ffff 390 11 1111 0000 0000 <-- instruction mask */ 391 #define PIC14_INSN_ANDWF 0x0500 392 #define PIC14_MASK_ANDWF 0x3F00 393 394 /* bcf : 01 00bb bfff ffff 395 11 1100 0000 0000 <-- instruction mask */ 396 #define PIC14_INSN_BCF 0x1000 397 #define PIC14_MASK_BCF 0x3C00 398 #define PIC14_BMSK_BCF (PIC14_MASK_BCF ^ PIC14_CORE_MASK) 399 400 /* bsf : 01 01bb bfff ffff 401 11 1100 0000 0000 <-- instruction mask */ 402 #define PIC14_INSN_BSF 0x1400 403 #define PIC14_MASK_BSF 0x3C00 404 #define PIC14_BMSK_BSF (PIC14_MASK_BSF ^ PIC14_CORE_MASK) 405 406 /* PIC14_MASK_BCF == PIC14_MASK_BSF */ 407 #define PIC14_MASK_BxF PIC14_MASK_BCF 408 /* PIC14_BMSK_BCF == PIC14_BMSK_BSF */ 409 #define PIC14_BMSK_BxF PIC14_BMSK_BCF 410 411 #define PIC14_INSN_BxF_BITSHIFT 7 412 413 /* btfsc : 01 10bb bfff ffff 414 11 1100 0000 0000 <-- instruction mask */ 415 #define PIC14_INSN_BTFSC 0x1800 416 #define PIC14_MASK_BTFSC 0x3C00 417 418 /* btfss : 01 11bb bfff ffff 419 11 1100 0000 0000 <-- instruction mask */ 420 #define PIC14_INSN_BTFSS 0x1C00 421 #define PIC14_MASK_BTFSS 0x3C00 422 423 /* call : 10 0kkk kkkk kkkk 424 11 1000 0000 0000 <-- instruction mask */ 425 #define PIC14_INSN_CALL 0x2000 426 #define PIC14_MASK_CALL 0x3800 427 #define PIC14_BMSK_CALL (PIC14_MASK_CALL ^ PIC14_CORE_MASK) 428 429 /* clrf : 00 0001 1fff ffff 430 11 1111 1000 0000 <-- instruction mask */ 431 #define PIC14_INSN_CLRF 0x0180 432 #define PIC14_MASK_CLRF 0x3F80 433 434 /* clrw : 00 0001 0xxx xxxx 435 11 1111 1111 1111 <-- instruction mask */ 436 #define PIC14_INSN_CLRW 0x0103 437 #define PIC14_MASK_CLRW 0x3FFF 438 439 /* clrwdt: 00 0000 0110 0100 440 11 1111 1111 1111 <-- instruction mask */ 441 #define PIC14_INSN_CLRWDT 0x0064 442 #define PIC14_MASK_CLRWDT 0x3FFF 443 444 /* comf : 00 1001 dfff ffff 445 11 1111 0000 0000 <-- instruction mask */ 446 #define PIC14_INSN_COMF 0x0900 447 #define PIC14_MASK_COMF 0x3F00 448 449 /* decf : 00 0011 dfff ffff 450 11 1111 0000 0000 <-- instruction mask */ 451 #define PIC14_INSN_DECF 0x0300 452 #define PIC14_MASK_DECF 0x3F00 453 454 /* decfsz: 00 1011 dfff ffff 455 11 1111 0000 0000 <-- instruction mask */ 456 #define PIC14_INSN_DECFSZ 0x0B00 457 #define PIC14_MASK_DECFSZ 0x3F00 458 459 /* goto : 10 1kkk kkkk kkkk 460 11 1000 0000 0000 <-- instruction mask */ 461 #define PIC14_INSN_GOTO 0x2800 462 #define PIC14_MASK_GOTO 0x3800 463 #define PIC14_BMSK_GOTO (PIC14_MASK_GOTO ^ PIC14_CORE_MASK) 464 465 /* halt : 00 0000 0110 0001 466 11 1111 1111 1111 <-- instruction mask */ 467 #define PIC14_INSN_HALT 0x0061 468 #define PIC14_MASK_HALT 0x3FFF 469 470 /* incf : 00 1010 dfff ffff 471 11 1111 0000 0000 <-- instruction mask */ 472 #define PIC14_INSN_INCF 0x0A00 473 #define PIC14_MASK_INCF 0x3F00 474 475 /* incfsz: 00 1111 dfff ffff 476 11 1111 0000 0000 <-- instruction mask */ 477 #define PIC14_INSN_INCFSZ 0x0F00 478 #define PIC14_MASK_INCFSZ 0x3F00 479 480 /* iorlw : 11 1000 kkkk kkkk 481 11 1111 0000 0000 <-- instruction mask */ 482 #define PIC14_INSN_IORLW 0x3800 483 #define PIC14_MASK_IORLW 0x3F00 484 485 /* iorwf : 00 0100 dfff ffff 486 11 1111 0000 0000 <-- instruction mask */ 487 #define PIC14_INSN_IORWF 0x0400 488 #define PIC14_MASK_IORWF 0x3F00 489 490 /* movf : 00 1000 dfff ffff 491 11 1111 0000 0000 <-- instruction mask */ 492 #define PIC14_INSN_MOVF 0x0800 493 #define PIC14_MASK_MOVF 0x3F00 494 495 /* movlw : 11 00xx kkkk kkkk 496 11 1100 0000 0000 <-- instruction mask */ 497 #define PIC14_INSN_MOVLW 0x3000 498 #define PIC14_MASK_MOVLW 0x3C00 499 #define PIC14_BMSK_MOVLW (PIC14_MASK_MOVLW ^ PIC14_CORE_MASK) 500 501 /* movwf : 00 0000 1fff ffff 502 11 1111 1000 0000 <-- instruction mask */ 503 #define PIC14_INSN_MOVWF 0x0080 504 #define PIC14_MASK_MOVWF 0x3F80 505 506 /* nop : 00 0000 0xx0 0000 507 11 1111 1001 1111 <-- instruction mask */ 508 #define PIC14_INSN_NOP 0x0000 509 #define PIC14_MASK_NOP 0x3F9F 510 511 /* option: 00 0000 0110 0010 512 11 1111 1111 1111 <-- instruction mask */ 513 #define PIC14_INSN_OPTION 0x0062 514 #define PIC14_MASK_OPTION 0x3FFF 515 516 /* retfie: 00 0000 0000 1001 517 11 1111 1111 1111 <-- instruction mask */ 518 #define PIC14_INSN_RETFIE 0x0009 519 #define PIC14_MASK_RETFIE 0x3FFF 520 521 /* retlw : 11 01xx kkkk kkkk 522 11 1100 0000 0000 <-- instruction mask */ 523 #define PIC14_INSN_RETLW 0x3400 524 #define PIC14_MASK_RETLW 0x3C00 525 526 /* return: 00 0000 0000 1000 527 11 1111 1111 1111 <-- instruction mask */ 528 #define PIC14_INSN_RETURN 0x0008 529 #define PIC14_MASK_RETURN 0x3FFF 530 531 /* rlf : 00 1101 dfff ffff 532 11 1111 0000 0000 <-- instruction mask */ 533 #define PIC14_INSN_RLF 0x0D00 534 #define PIC14_MASK_RLF 0x3F00 535 536 /* rrf : 00 1100 dfff ffff 537 11 1111 0000 0000 <-- instruction mask */ 538 #define PIC14_INSN_RRF 0x0C00 539 #define PIC14_MASK_RRF 0x3F00 540 541 /* sleep : 00 0000 0110 0011 542 11 1111 1111 1111 <-- instruction mask */ 543 #define PIC14_INSN_SLEEP 0x0063 544 #define PIC14_MASK_SLEEP 0x3FFF 545 546 /* sublw : 11 110x kkkk kkkk 547 11 1110 0000 0000 <-- instruction mask */ 548 #define PIC14_INSN_SUBLW 0x3C00 549 #define PIC14_MASK_SUBLW 0x3E00 550 551 /* subwf : 00 0010 dfff ffff 552 11 1111 0000 0000 <-- instruction mask */ 553 #define PIC14_INSN_SUBWF 0x0200 554 #define PIC14_MASK_SUBWF 0x3F00 555 556 /* swapf : 00 1110 dfff ffff 557 11 1111 0000 0000 <-- instruction mask */ 558 #define PIC14_INSN_SWAPF 0x0E00 559 #define PIC14_MASK_SWAPF 0x3F00 560 561 /* tris : 00 0000 0110 0fff 562 11 1111 1111 1000 <-- instruction mask */ 563 #define PIC14_INSN_TRIS 0x0060 564 #define PIC14_MASK_TRIS 0x3FF8 565 566 /* xorlw : 11 1010 kkkk kkkk 567 11 1111 0000 0000 <-- instruction mask */ 568 #define PIC14_INSN_XORLW 0x3A00 569 #define PIC14_MASK_XORLW 0x3F00 570 571 /* xorwf : 00 0110 dfff ffff 572 11 1111 0000 0000 <-- instruction mask */ 573 #define PIC14_INSN_XORWF 0x0600 574 #define PIC14_MASK_XORWF 0x3F00 575 576 /* Same the mask of call and goto. */ 577 #define PIC14_BMSK_BRANCH PIC14_BMSK_CALL 578 579 /****************************************** 580 PIC14E definitions 581 ******************************************/ 582 583 #define PIC14E_PC_MASK ((1u << 15) - 1) 584 585 /* addfsr: 11 0001 0nkk kkkk 586 11 1111 1000 0000 <-- instruction mask */ 587 #define PIC14E_INSN_ADDFSR 0x3100 588 #define PIC14E_MASK_ADDFSR 0x3F80 589 590 /* addlw : 11 1110 kkkk kkkk 591 11 1111 0000 0000 <-- instruction mask */ 592 #define PIC14E_INSN_ADDLW 0x3E00 593 #define PIC14E_MASK_ADDLW 0x3F00 594 595 /* addwfc: 11 1101 dfff ffff 596 11 1111 0000 0000 <-- instruction mask */ 597 #define PIC14E_INSN_ADDWFC 0x3D00 598 #define PIC14E_MASK_ADDWFC 0x3F00 599 600 /* asrf : 11 0111 dfff ffff 601 11 1111 0000 0000 <-- instruction mask */ 602 #define PIC14E_INSN_ASRF 0x3700 603 #define PIC14E_MASK_ASRF 0x3F00 604 605 /* bra : 11 001k kkkk kkkk 606 11 1110 0000 0000 <-- instruction mask */ 607 #define PIC14E_INSN_BRA 0x3200 608 #define PIC14E_MASK_BRA 0x3E00 609 #define PIC14E_BMSK_RBRA9 (PIC14E_MASK_BRA ^ PIC14_CORE_MASK) 610 611 /* brw : 00 0000 0000 1011 612 11 1111 1111 1111 <-- instruction mask */ 613 #define PIC14E_INSN_BRW 0x000B 614 #define PIC14E_MASK_BRW 0x3FFF 615 616 /* callw : 00 0000 0000 1010 617 11 1111 1111 1111 <-- instruction mask */ 618 #define PIC14E_INSN_CALLW 0x000A 619 #define PIC14E_MASK_CALLW 0x3FFF 620 621 /* lslf : 11 0101 dfff ffff 622 11 1111 0000 0000 <-- instruction mask */ 623 #define PIC14E_INSN_LSLF 0x3500 624 #define PIC14E_MASK_LSLF 0x3F00 625 626 /* lsrf : 11 0110 dfff ffff 627 11 1111 0000 0000 <-- instruction mask */ 628 #define PIC14E_INSN_LSRF 0x3600 629 #define PIC14E_MASK_LSRF 0x3F00 630 631 /* moviw : 00 0000 0001 0nmm 632 11 1111 1111 1000 <-- instruction mask */ 633 #define PIC14E_INSN_MOVIW 0x0010 634 #define PIC14E_MASK_MOVIW 0x3FF8 635 636 /* moviw : 11 1111 0nkk kkkk 637 11 1111 1000 0000 <-- instruction mask */ 638 #define PIC14E_INSN_MOVIW_IDX 0x3F00 639 #define PIC14E_MASK_MOVIW_IDX 0x3F80 640 641 /* movlw : 11 0000 kkkk kkkk 642 11 1111 0000 0000 <-- instruction mask */ 643 #define PIC14E_INSN_MOVLW 0x3000 644 #define PIC14E_MASK_MOVLW 0x3F00 645 646 /* movlb : 00 0000 001k kkkk 647 11 1111 1110 0000 <-- instruction mask */ 648 #define PIC14E_INSN_MOVLB 0x0020 649 #define PIC14E_MASK_MOVLB 0x3FE0 650 #define PIC14E_BMSK_MOVLB (PIC14E_MASK_MOVLB ^ PIC14_CORE_MASK) 651 652 /* movlp : 11 0001 1kkk kkkk 653 11 1111 1000 0000 <-- instruction mask */ 654 #define PIC14E_INSN_MOVLP 0x3180 655 #define PIC14E_MASK_MOVLP 0x3F80 656 #define PIC14E_BMSK_MOVLP (PIC14E_MASK_MOVLP ^ PIC14_CORE_MASK) 657 658 /* movwi : 00 0000 0001 1nmm 659 11 1111 1111 1000 <-- instruction mask */ 660 #define PIC14E_INSN_MOVWI 0x0018 661 #define PIC14E_MASK_MOVWI 0x3FF8 662 663 /* movwi : 11 1111 1nkk kkkk 664 11 1111 1000 0000 <-- instruction mask */ 665 #define PIC14E_INSN_MOVWI_IDX 0x3F80 666 #define PIC14E_MASK_MOVWI_IDX 0x3F80 667 668 /* nop : 00 0000 0000 0000 669 11 1111 1111 1111 <-- instruction mask */ 670 #define PIC14E_INSN_NOP 0x0000 671 #define PIC14E_MASK_NOP 0x3FFF 672 673 /* reset : 00 0000 0000 0001 674 11 1111 1111 1111 <-- instruction mask */ 675 #define PIC14E_INSN_RESET 0x0001 676 #define PIC14E_MASK_RESET 0x3FFF 677 678 /* retlw : 11 0100 kkkk kkkk 679 11 1111 0000 0000 <-- instruction mask */ 680 #define PIC14E_INSN_RETLW 0x3400 681 #define PIC14E_MASK_RETLW 0x3F00 682 683 /* sublw : 11 1100 kkkk kkkk 684 11 1111 0000 0000 <-- instruction mask */ 685 #define PIC14E_INSN_SUBLW 0x3C00 686 #define PIC14E_MASK_SUBLW 0x3F00 687 688 /* subwfb: 11 1011 dfff ffff 689 11 1111 0000 0000 <-- instruction mask */ 690 #define PIC14E_INSN_SUBWFB 0x3B00 691 #define PIC14E_MASK_SUBWFB 0x3F00 692 693 /****************************************** 694 PIC14EX definitions 695 ******************************************/ 696 697 /* movlb : 00 0001 01kk kkkk 698 11 1111 1100 0000 */ 699 #define PIC14EX_INSN_MOVLB 0x0140 700 #define PIC14EX_MASK_MOVLB 0x3FC0 701 #define PIC14EX_BMSK_MOVLB (PIC14EX_MASK_MOVLB ^ PIC14_CORE_MASK) 702 703 /****************************************** 704 PIC16 definitions 705 ******************************************/ 706 707 #define PIC16_CORE_MASK ((1u << 16) - 1) 708 #define PIC16_PC_MASK ((1u << 16) - 1) 709 710 /* General file bitmask. */ 711 #define PIC16_BMSK_FILE 0x0FF 712 713 /* addlw : 1011 0001 kkkk kkkk 714 1111 1111 0000 0000 <-- instruction mask */ 715 #define PIC16_INSN_ADDLW 0xB100 716 #define PIC16_MASK_ADDLW 0xFF00 717 718 /* addwf : 0000 111d ffff ffff 719 1111 1110 0000 0000 <-- instruction mask */ 720 #define PIC16_INSN_ADDWF 0x0E00 721 #define PIC16_MASK_ADDWF 0xFE00 722 723 /* addwf : 0001 000d ffff ffff 724 1111 1110 0000 0000 <-- instruction mask */ 725 #define PIC16_INSN_ADDWFC 0x1000 726 #define PIC16_MASK_ADDWFC 0xFE00 727 728 /* andlw : 1011 0101 kkkk kkkk 729 1111 1111 0000 0000 <-- instruction mask */ 730 #define PIC16_INSN_ANDLW 0xB500 731 #define PIC16_MASK_ANDLW 0xFF00 732 733 /* andwf : 0000 101d ffff ffff 734 1111 1110 0000 0000 <-- instruction mask */ 735 #define PIC16_INSN_ANDWF 0x0A00 736 #define PIC16_MASK_ANDWF 0xFE00 737 738 /* bcf : 1000 1bbb ffff ffff 739 1111 1000 0000 0000 <-- instruction mask */ 740 #define PIC16_INSN_BCF 0x8800 741 #define PIC16_MASK_BCF 0xF800 742 743 /* bsf : 1000 0bbb ffff ffff 744 1111 1000 0000 0000 <-- instruction mask */ 745 #define PIC16_INSN_BSF 0x8000 746 #define PIC16_MASK_BSF 0xF800 747 748 /* btfsc : 1001 1bbb ffff ffff 749 1111 1000 0000 0000 <-- instruction mask */ 750 #define PIC16_INSN_BTFSC 0x9800 751 #define PIC16_MASK_BTFSC 0xF800 752 753 #define PIC16_INSN_BxF_BITSHIFT 8 754 755 /* btfss : 1001 0bbb ffff ffff 756 1111 1000 0000 0000 <-- instruction mask */ 757 #define PIC16_INSN_BTFSS 0x9000 758 #define PIC16_MASK_BTFSS 0xF800 759 760 /* btg : 0011 1bbb ffff ffff 761 1111 1000 0000 0000 <-- instruction mask */ 762 #define PIC16_INSN_BTG 0x3800 763 #define PIC16_MASK_BTG 0xF800 764 765 /* call : 111k kkkk kkkk kkkk 766 1110 0000 0000 0000 <-- instruction mask */ 767 #define PIC16_INSN_CALL 0xE000 768 #define PIC16_MASK_CALL 0xE000 769 #define PIC16_BMSK_CALL (PIC16_MASK_CALL ^ PIC16_CORE_MASK) 770 771 /* clrf : 0010 100s ffff ffff 772 1111 1110 0000 0000 <-- instruction mask */ 773 #define PIC16_INSN_CLRF 0x2800 774 #define PIC16_MASK_CLRF 0xFE00 775 776 /* clrwdt: 0000 0000 0000 0100 777 1111 1111 1111 1111 <-- instruction mask */ 778 #define PIC16_INSN_CLRWDT 0x0004 779 #define PIC16_MASK_CLRWDT 0xFFFF 780 781 /* comf : 0001 001d ffff ffff 782 1111 1110 0000 0000 <-- instruction mask */ 783 #define PIC16_INSN_COMF 0x1200 784 #define PIC16_MASK_COMF 0xFE00 785 786 /* cpfseq: 0011 0001 ffff ffff 787 1111 1111 0000 0000 <-- instruction mask */ 788 #define PIC16_INSN_CPFSEQ 0x3100 789 #define PIC16_MASK_CPFSEQ 0xFF00 790 791 /* cpfsgt: 0011 0010 ffff ffff 792 1111 1111 0000 0000 <-- instruction mask */ 793 #define PIC16_INSN_CPFSGT 0x3200 794 #define PIC16_MASK_CPFSGT 0xFF00 795 796 /* cpfslt: 0011 0000 ffff ffff 797 1111 1111 0000 0000 <-- instruction mask */ 798 #define PIC16_INSN_CPFSLT 0x3000 799 #define PIC16_MASK_CPFSLT 0xFF00 800 801 /* daw : 0010 111s ffff ffff 802 1111 1110 0000 0000 <-- instruction mask */ 803 #define PIC16_INSN_DAW 0x2E00 804 #define PIC16_MASK_DAW 0xFE00 805 806 /* dcfsnz: 0010 011d ffff ffff 807 1111 1110 0000 0000 <-- instruction mask */ 808 #define PIC16_INSN_DCFSNZ 0x2600 809 #define PIC16_MASK_DCFSNZ 0xFE00 810 811 /* decf : 0000 011d ffff ffff 812 1111 1110 0000 0000 <-- instruction mask */ 813 #define PIC16_INSN_DECF 0x0600 814 #define PIC16_MASK_DECF 0xFE00 815 816 /* decfsz: 0001 011d ffff ffff 817 1111 1110 0000 0000 <-- instruction mask */ 818 #define PIC16_INSN_DECFSZ 0x1600 819 #define PIC16_MASK_DECFSZ 0xFE00 820 821 /* goto : 110k kkkk kkkk kkkk 822 1110 0000 0000 0000 <-- instruction mask */ 823 #define PIC16_INSN_GOTO 0xC000 824 #define PIC16_MASK_GOTO 0xE000 825 #define PIC16_BMSK_GOTO (PIC16_MASK_GOTO ^ PIC16_CORE_MASK) 826 827 /* incf : 0001 010d ffff ffff 828 1111 1110 0000 0000 <-- instruction mask */ 829 #define PIC16_INSN_INCF 0x1400 830 #define PIC16_MASK_INCF 0xFE00 831 832 /* incfsz: 0001 111d ffff ffff 833 1111 1110 0000 0000 <-- instruction mask */ 834 #define PIC16_INSN_INCFSZ 0x1E00 835 #define PIC16_MASK_INCFSZ 0xFE00 836 837 /* infsnz: 0010 010d ffff ffff 838 1111 1110 0000 0000 <-- instruction mask */ 839 #define PIC16_INSN_INFSNZ 0x2400 840 #define PIC16_MASK_INFSNZ 0xFE00 841 842 /* iorlw : 1011 0011 kkkk kkkk 843 1111 1111 0000 0000 <-- instruction mask */ 844 #define PIC16_INSN_IORLW 0xB300 845 #define PIC16_MASK_IORLW 0xFF00 846 847 /* iorwf : 0000 100d ffff ffff 848 1111 1110 0000 0000 <-- instruction mask */ 849 #define PIC16_INSN_IORWF 0x0800 850 #define PIC16_MASK_IORWF 0xFE00 851 852 /* lcall : 1011 0111 kkkk kkkk 853 1111 1111 0000 0000 <-- instruction mask */ 854 #define PIC16_INSN_LCALL 0xB700 855 #define PIC16_MASK_LCALL 0xFF00 856 857 /* movfp : 011p pppp ffff ffff 858 1110 0000 0000 0000 <-- instruction mask */ 859 #define PIC16_INSN_MOVFP 0x6000 860 #define PIC16_MASK_MOVFP 0xE000 861 #define PIC16_BMSK_MOVFP 0x1F00 862 863 /* movfp : 010p pppp ffff ffff 864 1110 0000 0000 0000 <-- instruction mask */ 865 #define PIC16_INSN_MOVPF 0x4000 866 #define PIC16_MASK_MOVPF 0xE000 867 #define PIC16_BMSK_MOVPF 0x1F00 868 869 /* movlb : 1011 1000 uuuu kkkk 870 1111 1111 0000 0000 <-- instruction mask */ 871 #define PIC16_INSN_MOVLB 0xB800 872 #define PIC16_MASK_MOVLB 0xFF00 873 #define PIC16_BMSK_MOVLB 0x000F 874 875 /* movlr : 1011 101x kkkk uuuu 876 1111 1110 0000 0000 <-- instruction mask */ 877 #define PIC16_INSN_MOVLR 0xBA00 878 #define PIC16_MASK_MOVLR 0xFE00 879 #define PIC16_BMSK_MOVLR 0x00F0 880 881 /* movlw : 1011 0000 kkkk kkkk 882 1111 1111 0000 0000 <-- instruction mask */ 883 #define PIC16_INSN_MOVLW 0xB000 884 #define PIC16_MASK_MOVLW 0xFF00 885 886 /* movwf : 0000 0001 ffff ffff 887 1111 1111 0000 0000 <-- instruction mask */ 888 #define PIC16_INSN_MOVWF 0x0100 889 #define PIC16_MASK_MOVWF 0xFF00 890 891 /* mullw : 1011 1100 kkkk kkkk 892 1111 1111 0000 0000 <-- instruction mask */ 893 #define PIC16_INSN_MULLW 0xBC00 894 #define PIC16_MASK_MULLW 0xFF00 895 896 /* mulwf : 0011 0100 ffff ffff 897 1111 1111 0000 0000 <-- instruction mask */ 898 #define PIC16_INSN_MULWF 0x3400 899 #define PIC16_MASK_MULWF 0xFF00 900 901 /* negw : 0010 110s ffff ffff 902 1111 1110 0000 0000 <-- instruction mask */ 903 #define PIC16_INSN_NEGW 0x2C00 904 #define PIC16_MASK_NEGW 0xFE00 905 906 /* nop : 0000 0000 0000 0000 907 1111 1111 1111 1111 <-- instruction mask */ 908 #define PIC16_INSN_NOP 0x0000 909 #define PIC16_MASK_NOP 0xFFFF 910 911 /* retfie: 0000 0000 0000 0101 912 1111 1111 1111 1111 <-- instruction mask */ 913 #define PIC16_INSN_RETFIE 0x0005 914 #define PIC16_MASK_RETFIE 0xFFFF 915 916 /* retlw : 1011 0110 kkkk kkkk 917 1111 1111 0000 0000 <-- instruction mask */ 918 #define PIC16_INSN_RETLW 0xB600 919 #define PIC16_MASK_RETLW 0xFF00 920 921 /* return: 0000 0000 0000 0010 922 1111 1111 1111 1111 <-- instruction mask */ 923 #define PIC16_INSN_RETURN 0x0002 924 #define PIC16_MASK_RETURN 0xFFFF 925 926 /* rlcf : 0001 101d ffff ffff 927 1111 1110 0000 0000 <-- instruction mask */ 928 #define PIC16_INSN_RLCF 0x1A00 929 #define PIC16_MASK_RLCF 0xFE00 930 931 /* rlncf : 0010 001d ffff ffff 932 1111 1110 0000 0000 <-- instruction mask */ 933 #define PIC16_INSN_RLNCF 0x2200 934 #define PIC16_MASK_RLNCF 0xFE00 935 936 /* rrcf : 0001 100d ffff ffff 937 1111 1110 0000 0000 <-- instruction mask */ 938 #define PIC16_INSN_RRCF 0x1800 939 #define PIC16_MASK_RRCF 0xFE00 940 941 /* rrncf : 0010 000d ffff ffff 942 1111 1110 0000 0000 <-- instruction mask */ 943 #define PIC16_INSN_RRNCF 0x2000 944 #define PIC16_MASK_RRNCF 0xFE00 945 946 /* setf : 0010 101s ffff ffff 947 1111 1110 0000 0000 <-- instruction mask */ 948 #define PIC16_INSN_SETF 0x2A00 949 #define PIC16_MASK_SETF 0xFE00 950 951 /* sleep : 0000 0000 0000 0011 952 1111 1111 1111 1111 <-- instruction mask */ 953 #define PIC16_INSN_SLEEP 0x0003 954 #define PIC16_MASK_SLEEP 0xFFFF 955 956 /* sublw : 1011 0010 kkkk kkkk 957 1111 1111 0000 0000 <-- instruction mask */ 958 #define PIC16_INSN_SUBLW 0xB200 959 #define PIC16_MASK_SUBLW 0xFF00 960 961 /* subwf : 0000 010d ffff ffff 962 1111 1110 0000 0000 <-- instruction mask */ 963 #define PIC16_INSN_SUBWF 0x0400 964 #define PIC16_MASK_SUBWF 0xFE00 965 966 /* subwfb: 0000 001d ffff ffff 967 1111 1110 0000 0000 <-- instruction mask */ 968 #define PIC16_INSN_SUBWFB 0x0200 969 #define PIC16_MASK_SUBWFB 0xFE00 970 971 /* swapf : 0001 110d ffff ffff 972 1111 1110 0000 0000 <-- instruction mask */ 973 #define PIC16_INSN_SWAPF 0x1C00 974 #define PIC16_MASK_SWAPF 0xFE00 975 976 /* tablrd: 1010 10ti ffff ffff 977 1111 1100 0000 0000 <-- instruction mask */ 978 #define PIC16_INSN_TABLRD 0xA800 979 #define PIC16_MASK_TABLRD 0xFC00 980 981 /* tablwt: 1010 11ti ffff ffff 982 1111 1100 0000 0000 <-- instruction mask */ 983 #define PIC16_INSN_TABLWT 0xAC00 984 #define PIC16_MASK_TABLWT 0xFC00 985 986 /* tlrd : 1010 00tx ffff ffff 987 1111 1100 0000 0000 <-- instruction mask */ 988 #define PIC16_INSN_TLRD 0xA000 989 #define PIC16_MASK_TLRD 0xFC00 990 991 /* tlwt : 1010 01tx ffff ffff 992 1111 1100 0000 0000 <-- instruction mask */ 993 #define PIC16_INSN_TLWT 0xA400 994 #define PIC16_MASK_TLWT 0xFC00 995 996 /* tstfsz: 0011 0011 ffff ffff 997 1111 1111 0000 0000 <-- instruction mask */ 998 #define PIC16_INSN_TSTFSZ 0x3300 999 #define PIC16_MASK_TSTFSZ 0xFF00 1000 1001 /* xorlw : 1011 0100 kkkk kkkk 1002 1111 1111 0000 0000 <-- instruction mask */ 1003 #define PIC16_INSN_XORLW 0xB400 1004 #define PIC16_MASK_XORLW 0xFF00 1005 1006 /* xorwf : 0000 110d ffff ffff 1007 1111 1110 0000 0000 <-- instruction mask */ 1008 #define PIC16_INSN_XORWF 0x0C00 1009 #define PIC16_MASK_XORWF 0xFE00 1010 1011 /* Same the mask of call and goto. */ 1012 #define PIC16_BMSK_BRANCH PIC16_BMSK_CALL 1013 1014 /****************************************** 1015 PIC16E definitions 1016 ******************************************/ 1017 1018 /* addlw : 0000 1111 kkkk kkkk 1019 1111 1111 0000 0000 <-- instruction mask */ 1020 #define PIC16E_INSN_ADDLW 0x0F00 1021 #define PIC16E_MASK_ADDLW 0xFF00 1022 1023 /* addwf : 0010 01da ffff ffff 1024 1111 1100 0000 0000 <-- instruction mask */ 1025 #define PIC16E_INSN_ADDWF 0x2400 1026 #define PIC16E_MASK_ADDWF 0xFC00 1027 1028 /* addwfc: 0010 00da ffff ffff 1029 1111 1100 0000 0000 <-- instruction mask */ 1030 #define PIC16E_INSN_ADDWFC 0x2000 1031 #define PIC16E_MASK_ADDWFC 0xFC00 1032 1033 /* andlw : 0000 1011 kkkk kkkk 1034 1111 1111 0000 0000 <-- instruction mask */ 1035 #define PIC16E_INSN_ANDLW 0x0B00 1036 #define PIC16E_MASK_ANDLW 0xFF00 1037 1038 /* andwf : 0001 01da ffff ffff 1039 1111 1100 0000 0000 <-- instruction mask */ 1040 #define PIC16E_INSN_ANDWF 0x1400 1041 #define PIC16E_MASK_ANDWF 0xFC00 1042 1043 /* bc : 1110 0010 nnnn nnnn 1044 1111 1111 0000 0000 <-- instruction mask */ 1045 #define PIC16E_INSN_BC 0xE200 1046 #define PIC16E_MASK_BC 0xFF00 1047 #define PIC16E_BMSK_BC (PIC16E_MASK_BC ^ PIC16_CORE_MASK) 1048 1049 /* bcf : 1001 bbba ffff ffff 1050 1111 0000 0000 0000 <-- instruction mask */ 1051 #define PIC16E_INSN_BCF 0x9000 1052 #define PIC16E_MASK_BCF 0xF000 1053 1054 /* bn : 1110 0110 nnnn nnnn 1055 1111 1111 0000 0000 <-- instruction mask */ 1056 #define PIC16E_INSN_BN 0xE600 1057 #define PIC16E_MASK_BN 0xFF00 1058 #define PIC16E_BMSK_BN (PIC16E_MASK_BN ^ PIC16_CORE_MASK) 1059 1060 /* bnc : 1110 0011 nnnn nnnn 1061 1111 1111 0000 0000 <-- instruction mask */ 1062 #define PIC16E_INSN_BNC 0xE300 1063 #define PIC16E_MASK_BNC 0xFF00 1064 #define PIC16E_BMSK_BNC (PIC16E_MASK_BNC ^ PIC16_CORE_MASK) 1065 1066 /* bnn : 1110 0111 nnnn nnnn 1067 1111 1111 0000 0000 <-- instruction mask */ 1068 #define PIC16E_INSN_BNN 0xE700 1069 #define PIC16E_MASK_BNN 0xFF00 1070 #define PIC16E_BMSK_BNN (PIC16E_MASK_BNN ^ PIC16_CORE_MASK) 1071 1072 /* bnov : 1110 0101 nnnn nnnn 1073 1111 1111 0000 0000 <-- instruction mask */ 1074 #define PIC16E_INSN_BNOV 0xE500 1075 #define PIC16E_MASK_BNOV 0xFF00 1076 #define PIC16E_BMSK_BNOV (PIC16E_MASK_BNOV ^ PIC16_CORE_MASK) 1077 1078 /* bnz : 1110 0001 nnnn nnnn 1079 1111 1111 0000 0000 <-- instruction mask */ 1080 #define PIC16E_INSN_BNZ 0xE100 1081 #define PIC16E_MASK_BNZ 0xFF00 1082 #define PIC16E_BMSK_BNZ (PIC16E_MASK_BNZ ^ PIC16_CORE_MASK) 1083 1084 /* bov : 1110 0100 nnnn nnnn 1085 1111 1111 0000 0000 <-- instruction mask */ 1086 #define PIC16E_INSN_BOV 0xE400 1087 #define PIC16E_MASK_BOV 0xFF00 1088 #define PIC16E_BMSK_BOV (PIC16E_MASK_BOV ^ PIC16_CORE_MASK) 1089 1090 /* bra : 1101 0nnn nnnn nnnn 1091 1111 1000 0000 0000 <-- instruction mask */ 1092 #define PIC16E_INSN_BRA 0xD000 1093 #define PIC16E_MASK_BRA 0xF800 1094 #define PIC16E_BMSK_RBRA11 (PIC16E_MASK_BRA ^ PIC16_CORE_MASK) 1095 1096 /* bsf : 1000 bbba ffff ffff 1097 1111 0000 0000 0000 <-- instruction mask */ 1098 #define PIC16E_INSN_BSF 0x8000 1099 #define PIC16E_MASK_BSF 0xF000 1100 1101 /* btfsc : 1011 bbba ffff ffff 1102 1111 0000 0000 0000 <-- instruction mask */ 1103 #define PIC16E_INSN_BTFSC 0xB000 1104 #define PIC16E_MASK_BTFSC 0xF000 1105 1106 /* btfss : 1010 bbba ffff ffff 1107 1111 0000 0000 0000 <-- instruction mask */ 1108 #define PIC16E_INSN_BTFSS 0xA000 1109 #define PIC16E_MASK_BTFSS 0xF000 1110 1111 /* btg : 0111 bbba ffff ffff 1112 1111 0000 0000 0000 <-- instruction mask */ 1113 #define PIC16E_INSN_BTG 0x7000 1114 #define PIC16E_MASK_BTG 0xF000 1115 1116 /* bz : 1110 0000 nnnn nnnn 1117 1111 1111 0000 0000 <-- instruction mask */ 1118 #define PIC16E_INSN_BZ 0xE000 1119 #define PIC16E_MASK_BZ 0xFF00 1120 #define PIC16E_BMSK_BZ (PIC16E_MASK_BZ ^ PIC16_CORE_MASK) 1121 1122 /* call : 1110 110s kkkk kkkk 1123 1111 kkkk kkkk kkkk 1124 1125 1111 1110 0000 0000 <-- instruction mask */ 1126 #define PIC16E_INSN_CALL 0xEC00 1127 #define PIC16E_MASK_CALL 0xFE00 1128 #define PIC16E_BMSK_CALL1 (PIC16E_MASK_CALL ^ PIC16_CORE_MASK) 1129 #define PIC16E_BMSK_CALL2 0x0FFF 1130 1131 /* clrf : 0110 101a ffff ffff 1132 1111 1110 0000 0000 <-- instruction mask */ 1133 #define PIC16E_INSN_CLRF 0x6A00 1134 #define PIC16E_MASK_CLRF 0xFE00 1135 1136 /* clrwdt: 0000 0000 0000 0100 1137 1111 1111 1111 1111 <-- instruction mask */ 1138 #define PIC16E_INSN_CLRWDT 0x0004 1139 #define PIC16E_MASK_CLRWDT 0xFFFF 1140 1141 /* comf : 0001 11da ffff ffff 1142 1111 1100 0000 0000 <-- instruction mask */ 1143 #define PIC16E_INSN_COMF 0x1C00 1144 #define PIC16E_MASK_COMF 0xFC00 1145 1146 /* cpfseq: 0110 001a ffff ffff 1147 1111 1110 0000 0000 <-- instruction mask */ 1148 #define PIC16E_INSN_CPFSEQ 0x6200 1149 #define PIC16E_MASK_CPFSEQ 0xFE00 1150 1151 /* cpfsgt: 0110 010a ffff ffff 1152 1111 1110 0000 0000 <-- instruction mask */ 1153 #define PIC16E_INSN_CPFSGT 0x6400 1154 #define PIC16E_MASK_CPFSGT 0xFE00 1155 1156 /* cpfslt: 0110 000a ffff ffff 1157 1111 1110 0000 0000 <-- instruction mask */ 1158 #define PIC16E_INSN_CPFSLT 0x6000 1159 #define PIC16E_MASK_CPFSLT 0xFE00 1160 1161 /* daw : 0000 0000 0000 0111 1162 1111 1111 1111 1111 <-- instruction mask */ 1163 #define PIC16E_INSN_DAW 0x0007 1164 #define PIC16E_MASK_DAW 0xFFFF 1165 1166 /* dcfsnz: 0100 11da ffff ffff 1167 1111 1100 0000 0000 <-- instruction mask */ 1168 #define PIC16E_INSN_DCFSNZ 0x4C00 1169 #define PIC16E_MASK_DCFSNZ 0xFC00 1170 1171 /* decf : 0000 01da ffff ffff 1172 1111 1100 0000 0000 <-- instruction mask */ 1173 #define PIC16E_INSN_DECF 0x0400 1174 #define PIC16E_MASK_DECF 0xFC00 1175 1176 /* decfsz: 0010 11da ffff ffff 1177 1111 1100 0000 0000 <-- instruction mask */ 1178 #define PIC16E_INSN_DECFSZ 0x2C00 1179 #define PIC16E_MASK_DECFSZ 0xFC00 1180 1181 /* goto : 1110 1111 kkkk kkkk 1182 1111 kkkk kkkk kkkk 1183 1184 1111 1111 0000 0000 <-- instruction mask */ 1185 #define PIC16E_INSN_GOTO 0xEF00 1186 #define PIC16E_MASK_GOTO 0xFF00 1187 #define PIC16E_BMSK_GOTO1 (PIC16E_MASK_GOTO ^ PIC16_CORE_MASK) 1188 #define PIC16E_BMSK_GOTO2 0x0FFF 1189 1190 /* halt : 0000 0000 0000 0001 1191 1111 1111 1111 1111 <-- instruction mask */ 1192 #define PIC16E_INSN_HALT 0x0001 1193 #define PIC16E_MASK_HALT 0xFFFF 1194 1195 /* incf : 0010 10da ffff ffff 1196 1111 1100 0000 0000 <-- instruction mask */ 1197 #define PIC16E_INSN_INCF 0x2800 1198 #define PIC16E_MASK_INCF 0xFC00 1199 1200 /* incfsz: 0011 11da ffff ffff 1201 1111 1100 0000 0000 <-- instruction mask */ 1202 #define PIC16E_INSN_INCFSZ 0x3C00 1203 #define PIC16E_MASK_INCFSZ 0xFC00 1204 1205 /* infsnz: 0100 10da ffff ffff 1206 1111 1100 0000 0000 <-- instruction mask */ 1207 #define PIC16E_INSN_INFSNZ 0x4800 1208 #define PIC16E_MASK_INFSNZ 0xFC00 1209 1210 /* iorlw : 0000 1001 kkkk kkkk 1211 1111 1111 0000 0000 <-- instruction mask */ 1212 #define PIC16E_INSN_IORLW 0x0900 1213 #define PIC16E_MASK_IORLW 0xFF00 1214 1215 /* iorwf : 0001 00da ffff ffff 1216 1111 1100 0000 0000 <-- instruction mask */ 1217 #define PIC16E_INSN_IORWF 0x1000 1218 #define PIC16E_MASK_IORWF 0xFC00 1219 1220 /* lfsr : 1110 1110 00ff kkkk 1221 1111 0000 kkkk kkkk 1222 1223 1111 1111 1100 0000 <-- instruction mask */ 1224 #define PIC16E_INSN_LFSR 0xEE00 1225 #define PIC16E_MASK_LFSR 0xFFC0 1226 #define PIC16E_BMSK_LFSR1 0x000F 1227 #define PIC16E_BMSK_LFSR2 0x00FF 1228 1229 /* movf : 0101 00da ffff ffff 1230 1111 1100 0000 0000 <-- instruction mask */ 1231 #define PIC16E_INSN_MOVF 0x5000 1232 #define PIC16E_MASK_MOVF 0xFC00 1233 1234 /* movff : 1100 ffff ffff ffff 1235 1111 ffff ffff ffff 1236 1237 1111 0000 0000 0000 <-- instruction mask */ 1238 #define PIC16E_INSN_MOVFF 0xC000 1239 #define PIC16E_MASK_MOVFF 0xF000 1240 #define PIC16E_BMSK_MOVFF1 0x0FFF 1241 #define PIC16E_BMSK_MOVFF2 0x0FFF 1242 1243 /* movlb : 0000 0001 0000 kkkk 1244 1111 1111 1111 0000 <-- instruction mask */ 1245 #define PIC16E_INSN_MOVLB 0x0100 1246 #define PIC16E_MASK_MOVLB 0xFFF0 1247 #define PIC16E_BMSK_MOVLB (PIC16E_MASK_MOVLB ^ PIC16_CORE_MASK) 1248 1249 /* movlw : 0000 1110 kkkk kkkk 1250 1111 1111 0000 0000 <-- instruction mask */ 1251 #define PIC16E_INSN_MOVLW 0x0E00 1252 #define PIC16E_MASK_MOVLW 0xFF00 1253 1254 /* movwf : 0110 111a ffff ffff 1255 1111 1110 0000 0000 <-- instruction mask */ 1256 #define PIC16E_INSN_MOVWF 0x6E00 1257 #define PIC16E_MASK_MOVWF 0xFE00 1258 1259 /* mullw : 0000 1101 kkkk kkkk 1260 1111 1111 0000 0000 <-- instruction mask */ 1261 #define PIC16E_INSN_MULLW 0x0D00 1262 #define PIC16E_MASK_MULLW 0xFF00 1263 1264 /* mulwf : 0000 001a ffff ffff 1265 1111 1110 0000 0000 <-- instruction mask */ 1266 #define PIC16E_INSN_MULWF 0x0200 1267 #define PIC16E_MASK_MULWF 0xFE00 1268 1269 /* negf : 0110 110a ffff ffff 1270 1111 1110 0000 0000 <-- instruction mask */ 1271 #define PIC16E_INSN_NEGF 0x6C00 1272 #define PIC16E_MASK_NEGF 0xFE00 1273 1274 /* nop : 0000 0000 0000 0000 */ 1275 /* nop : 1111 xxxx xxxx xxxx 1276 1277 1111 1111 1111 1111 <-- instruction mask */ 1278 #define PIC16E_INSN_NOP 0x0000 1279 #define PIC16E_MASK_NOP 0xFFFF 1280 1281 /* pop : 0000 0000 0000 0110 1282 1111 1111 1111 1111 <-- instruction mask */ 1283 #define PIC16E_INSN_POP 0x0006 1284 #define PIC16E_MASK_POP 0xFFFF 1285 1286 /* push : 0000 0000 0000 0101 1287 1111 1111 1111 1111 <-- instruction mask */ 1288 #define PIC16E_INSN_PUSH 0x0005 1289 #define PIC16E_MASK_PUSH 0xFFFF 1290 1291 /* rcall : 1101 1nnn nnnn nnnn 1292 1111 1000 0000 0000 <-- instruction mask */ 1293 #define PIC16E_INSN_RCALL 0xD800 1294 #define PIC16E_MASK_RCALL 0xF800 1295 1296 /* reset : 0000 0000 1111 1111 1297 1111 1111 1111 1111 <-- instruction mask */ 1298 #define PIC16E_INSN_RESET 0x00FF 1299 #define PIC16E_MASK_RESET 0xFFFF 1300 1301 /* retfie: 0000 0000 0001 000s 1302 1111 1111 1111 1110 <-- instruction mask */ 1303 #define PIC16E_INSN_RETFIE 0x0010 1304 #define PIC16E_MASK_RETFIE 0xFFFE 1305 1306 /* retlw : 0000 1100 kkkk kkkk 1307 1111 1111 0000 0000 <-- instruction mask */ 1308 #define PIC16E_INSN_RETLW 0x0C00 1309 #define PIC16E_MASK_RETLW 0xFF00 1310 1311 /* return: 0000 0000 0001 001s 1312 1111 1111 1111 1110 <-- instruction mask */ 1313 #define PIC16E_INSN_RETURN 0x0012 1314 #define PIC16E_MASK_RETURN 0xFFFE 1315 1316 /* rlcf : 0011 01da ffff ffff 1317 1111 1100 0000 0000 <-- instruction mask */ 1318 #define PIC16E_INSN_RLCF 0x3400 1319 #define PIC16E_MASK_RLCF 0xFC00 1320 1321 /* rlncf : 0100 01da ffff ffff 1322 1111 1100 0000 0000 <-- instruction mask */ 1323 #define PIC16E_INSN_RLNCF 0x4400 1324 #define PIC16E_MASK_RLNCF 0xFC00 1325 1326 /* rrcf : 0011 00da ffff ffff 1327 1111 1100 0000 0000 <-- instruction mask */ 1328 #define PIC16E_INSN_RRCF 0x3000 1329 #define PIC16E_MASK_RRCF 0xFC00 1330 1331 /* rrncf : 0100 00da ffff ffff 1332 1111 1100 0000 0000 <-- instruction mask */ 1333 #define PIC16E_INSN_RRNCF 0x4000 1334 #define PIC16E_MASK_RRNCF 0xFC00 1335 1336 /* setf : 0110 100a ffff ffff 1337 1111 1110 0000 0000 <-- instruction mask */ 1338 #define PIC16E_INSN_SETF 0x6800 1339 #define PIC16E_MASK_SETF 0xFE00 1340 1341 /* sleep : 0000 0000 0000 0011 1342 1111 1111 1111 1111 <-- instruction mask */ 1343 #define PIC16E_INSN_SLEEP 0x0003 1344 #define PIC16E_MASK_SLEEP 0xFFFF 1345 1346 /* subfwb: 0101 01da ffff ffff 1347 1111 1100 0000 0000 <-- instruction mask */ 1348 #define PIC16E_INSN_SUBFWB 0x5400 1349 #define PIC16E_MASK_SUBFWB 0xFC00 1350 1351 /* sublw : 0000 1000 kkkk kkkk 1352 1111 1111 0000 0000 <-- instruction mask */ 1353 #define PIC16E_INSN_SUBLW 0x0800 1354 #define PIC16E_MASK_SUBLW 0xFF00 1355 1356 /* subwf : 0101 11da ffff ffff 1357 1111 1100 0000 0000 <-- instruction mask */ 1358 #define PIC16E_INSN_SUBWF 0x5C00 1359 #define PIC16E_MASK_SUBWF 0xFC00 1360 1361 /* subwfb: 0101 10da ffff ffff 1362 1111 1100 0000 0000 <-- instruction mask */ 1363 #define PIC16E_INSN_SUBWFB 0x5800 1364 #define PIC16E_MASK_SUBWFB 0xFC00 1365 1366 /* swapf : 0011 10da ffff ffff 1367 1111 1100 0000 0000 <-- instruction mask */ 1368 #define PIC16E_INSN_SWAPF 0x3800 1369 #define PIC16E_MASK_SWAPF 0xFC00 1370 1371 /* tblrd : 0000 0000 0000 10ii 1372 1111 1111 1111 1100 <-- instruction mask */ 1373 #define PIC16E_INSN_TBLRD 0x0008 1374 #define PIC16E_MASK_TBLRD 0xFFFC 1375 1376 /* tblwt : 0000 0000 0000 11ii 1377 1111 1111 1111 1100 <-- instruction mask */ 1378 #define PIC16E_INSN_TBLWT 0x000C 1379 #define PIC16E_MASK_TBLWT 0xFFFC 1380 1381 /* trap : 0000 0000 1110 0000 1382 1111 1111 1111 1111 <-- instruction mask */ 1383 #define PIC16E_INSN_TRAP 0x00E0 1384 #define PIC16E_MASK_TRAP 0xFFFF 1385 1386 /* tret : 0000 0000 1110 0001 1387 1111 1111 1111 1111 <-- instruction mask */ 1388 #define PIC16E_INSN_TRET 0x00E1 1389 #define PIC16E_MASK_TRET 0xFFFF 1390 1391 /* tstfsz: 0110 011a ffff ffff 1392 1111 1110 0000 0000 <-- instruction mask */ 1393 #define PIC16E_INSN_TSTFSZ 0x6600 1394 #define PIC16E_MASK_TSTFSZ 0xFE00 1395 1396 /* xorlw : 0000 1010 kkkk kkkk 1397 1111 1111 0000 0000 <-- instruction mask */ 1398 #define PIC16E_INSN_XORLW 0x0A00 1399 #define PIC16E_MASK_XORLW 0xFF00 1400 1401 /* xorwf : 0001 10da ffff ffff 1402 1111 1100 0000 0000 <-- instruction mask */ 1403 #define PIC16E_INSN_XORWF 0x1800 1404 #define PIC16E_MASK_XORWF 0xFC00 1405 1406 /* This is identical to the following cases: 1407 PIC16E_BMSK_BC, PIC16E_BMSK_BN, PIC16E_BMSK_BNC, 1408 PIC16E_BMSK_BNN, PIC16E_BMSK_BNOV, PIC16E_BMSK_BNZ, 1409 PIC16E_BMSK_BOV, PIC16E_BMSK_BZ */ 1410 #define PIC16E_BMSK_RBRA8 PIC16E_BMSK_BC 1411 1412 /****************************************** 1413 PIC16E special instructions 1414 ******************************************/ 1415 1416 #define PIC16ES_INSN_CLRC 0x90D8 1417 #define PIC16ES_INSN_CLRDC 0x92D8 1418 #define PIC16ES_INSN_CLRN 0x98D8 1419 #define PIC16ES_INSN_CLROV 0x96D8 1420 #define PIC16ES_INSN_CLRW 0x6AE8 1421 #define PIC16ES_INSN_CLRZ 0x94D8 1422 #define PIC16ES_INSN_SETC 0x80D8 1423 #define PIC16ES_INSN_SETDC 0x82D8 1424 #define PIC16ES_INSN_SETN 0x88D8 1425 #define PIC16ES_INSN_SETOV 0x86D8 1426 #define PIC16ES_INSN_SETZ 0x84D8 1427 #define PIC16ES_INSN_SKPC 0xA0D8 1428 #define PIC16ES_INSN_SKPDC 0xA2D8 1429 #define PIC16ES_INSN_SKPN 0xA8D8 1430 #define PIC16ES_INSN_SKPOV 0xA6D8 1431 #define PIC16ES_INSN_SKPZ 0xA4D8 1432 #define PIC16ES_INSN_SKPNC 0xB0D8 1433 #define PIC16ES_INSN_SKPNDC 0xB2D8 1434 #define PIC16ES_INSN_SKPNN 0xB8D8 1435 #define PIC16ES_INSN_SKPNOV 0xB6D8 1436 #define PIC16ES_INSN_SKPNZ 0xB4D8 1437 #define PIC16ES_INSN_TGC 0x70D8 1438 #define PIC16ES_INSN_TGDC 0x72D8 1439 #define PIC16ES_INSN_TGN 0x78D8 1440 #define PIC16ES_INSN_TGOV 0x76D8 1441 #define PIC16ES_INSN_TGZ 0x74D8 1442 1443 1444 /****************************************** 1445 PIC16E extended instructions 1446 ******************************************/ 1447 1448 /* addfsr: 1110 1000 ffkk kkkk 1449 1111 1111 0000 0000 */ 1450 #define PIC16EX_INSN_ADDFSR 0xE800 1451 #define PIC16EX_MASK_ADDFSR 0xFF00 1452 1453 /* addulnk: 1110 1000 11kk kkkk 1454 1111 1111 1100 0000 */ 1455 #define PIC16EX_INSN_ADDULNK 0xE8C0 1456 #define PIC16EX_MASK_ADDULNK 0xFFC0 1457 #define PIC16EX_BMSK_ADDULNK (PIC16EX_MASK_ADDULNK ^ PIC16_CORE_MASK) 1458 1459 /* callw : 0000 0000 0001 0100 1460 1111 1111 1111 1111 */ 1461 #define PIC16EX_INSN_CALLW 0x0014 1462 #define PIC16EX_MASK_CALLW 0xFFFF 1463 1464 /* movsf : 1110 1011 0zzz zzzz 1465 1111 ffff ffff ffff 1466 1467 1111 1111 1000 0000 */ 1468 #define PIC16EX_INSN_MOVSF 0xEB00 1469 #define PIC16EX_MASK_MOVSF 0xFF80 1470 1471 /* movss : 1110 1011 1zzz zzzz 1472 1111 xxxx xzzz zzzz 1473 1474 1111 1111 1000 0000 */ 1475 #define PIC16EX_INSN_MOVSS 0xEB80 1476 #define PIC16EX_MASK_MOVSS 0xFF80 1477 1478 /* pushl : 1110 1010 kkkk kkkk 1479 1111 1111 0000 0000 */ 1480 #define PIC16EX_INSN_PUSHL 0xEA00 1481 #define PIC16EX_MASK_PUSHL 0xFF00 1482 1483 /* subfsr: 1110 1001 ffkk kkkk 1484 1111 1111 0000 0000 */ 1485 #define PIC16EX_INSN_SUBFSR 0xE900 1486 #define PIC16EX_MASK_SUBFSR 0xFF00 1487 1488 /* subulnk: 1110 1001 11kk kkkk 1489 1111 1111 1100 0000 */ 1490 #define PIC16EX_INSN_SUBULNK 0xE9C0 1491 #define PIC16EX_MASK_SUBULNK 0xFFC0 1492 #define PIC16EX_BMSK_SUBULNK (PIC16EX_MASK_SUBULNK ^ PIC16_CORE_MASK) 1493 1494 /* This is identical to PIC16EX_BMSK_SUBULNK. */ 1495 #define PIC16EX_BMSK_xxxULNK PIC16EX_BMSK_ADDULNK 1496 1497 enum common_insn { 1498 ICODE_ADDFSR, 1499 ICODE_ADDLW, 1500 ICODE_ADDULNK, 1501 ICODE_ADDWF, 1502 ICODE_ADDWFC, 1503 ICODE_ANDLW, 1504 ICODE_ANDWF, 1505 ICODE_ASRF, 1506 ICODE_BANK, 1507 ICODE_BC, 1508 ICODE_BCF, 1509 ICODE_BN, 1510 ICODE_BNC, 1511 ICODE_BNN, 1512 ICODE_BNOV, 1513 ICODE_BNZ, 1514 ICODE_BOV, 1515 ICODE_BRA, 1516 ICODE_BRW, 1517 ICODE_BSF, 1518 ICODE_BTFSC, 1519 ICODE_BTFSS, 1520 ICODE_BTG, 1521 ICODE_BZ, 1522 ICODE_CALL, 1523 ICODE_CALLW, 1524 ICODE_CLRF, 1525 ICODE_CLRW, 1526 ICODE_CLRWDT, 1527 ICODE_COMF, 1528 ICODE_CPFSEQ, 1529 ICODE_CPFSGT, 1530 ICODE_CPFSLT, 1531 ICODE_DAW, 1532 ICODE_DCFSNZ, 1533 ICODE_DECF, 1534 ICODE_DECFSZ, 1535 ICODE_GOTO, 1536 ICODE_HALT, 1537 ICODE_INCF, 1538 ICODE_INCFSZ, 1539 ICODE_INFSNZ, 1540 ICODE_IORLW, 1541 ICODE_IORWF, 1542 ICODE_IREAD, 1543 ICODE_LCALL, 1544 ICODE_LFSR, 1545 ICODE_LSLF, 1546 ICODE_LSRF, 1547 ICODE_MODE, 1548 ICODE_MOVF, 1549 ICODE_MOVFF, 1550 ICODE_MOVFP, 1551 ICODE_MOVIW, 1552 ICODE_MOVLB, 1553 ICODE_MOVLP, 1554 ICODE_MOVLR, 1555 ICODE_MOVLW, 1556 ICODE_MOVMW, 1557 ICODE_MOVPF, 1558 ICODE_MOVSF, 1559 ICODE_MOVSS, 1560 ICODE_MOVWF, 1561 ICODE_MOVWI, 1562 ICODE_MOVWM, 1563 ICODE_MULLW, 1564 ICODE_MULWF, 1565 ICODE_NEGF, 1566 ICODE_NEGW, 1567 ICODE_NOP, 1568 ICODE_OPTION, 1569 ICODE_PAGE, 1570 ICODE_POP, 1571 ICODE_PUSH, 1572 ICODE_PUSHL, 1573 ICODE_RCALL, 1574 ICODE_RESET, 1575 ICODE_RETFIE, 1576 ICODE_RETI, 1577 ICODE_RETIW, 1578 ICODE_RETLW, 1579 ICODE_RETP, 1580 ICODE_RETURN, 1581 ICODE_RLCF, 1582 ICODE_RLF, 1583 ICODE_RLNCF, 1584 ICODE_RRCF, 1585 ICODE_RRF, 1586 ICODE_RRNCF, 1587 ICODE_SETF, 1588 ICODE_SLEEP, 1589 ICODE_SUBFSR, 1590 ICODE_SUBFWB, 1591 ICODE_SUBLW, 1592 ICODE_SUBULNK, 1593 ICODE_SUBWF, 1594 ICODE_SUBWFB, 1595 ICODE_SWAPF, 1596 ICODE_TABLRD, 1597 ICODE_TABLWT, 1598 ICODE_TBLRD, 1599 ICODE_TBLWT, 1600 ICODE_TLRD, 1601 ICODE_TLWT, 1602 ICODE_TRAP, 1603 ICODE_TRET, 1604 ICODE_TRIS, 1605 ICODE_TSTFSZ, 1606 ICODE_XORLW, 1607 ICODE_XORWF 1608 }; 1609 1610 enum invalidate_mask { 1611 INV_MASK_NULL = 0, 1612 INV_MASK_BANK = (1 << 0), /* An instruction invalidates the selection of RAM Banks. 1613 (Only in "gpasm" and "absolute" mode.) */ 1614 INV_MASK_PAGE = (1 << 1), /* An instruction invalidates the selection of ROM Pages. 1615 (Only in "gpasm" and "absolute" mode.) */ 1616 INV_MASK_SKIP = (1 << 2) /* An instruction following this may be skipped. Will not invalidates Banks or Pages. 1617 (Only in "gpasm" and "absolute" mode.) */ 1618 }; 1619 1620 struct pnode; /* forward declaration; defined in gpasm.h for assembler and in 1621 * script.h for linker */ 1622 1623 typedef struct insn { 1624 const char *name; 1625 unsigned int mask; 1626 unsigned int opcode; 1627 enum common_insn icode; 1628 enum insn_class class; 1629 enum invalidate_mask inv_mask; 1630 unsigned int attribs; 1631 gpasmVal (*doer)(gpasmVal r, const char *name, int arity, struct pnode *parms); 1632 } insn_t; 1633 1634 typedef struct strict_insn { 1635 const char *name; 1636 unsigned int mask; 1637 } strict_insn_t; 1638 1639 #define TABLE_SIZE(X) (sizeof(X) / sizeof((X)[0])) 1640 1641 extern const insn_t op_12c5xx[]; 1642 extern const unsigned int num_op_12c5xx; 1643 1644 extern const insn_t op_16c5xx_enh[]; 1645 extern const unsigned int num_op_16c5xx_enh; 1646 1647 extern const insn_t op_sx[]; 1648 extern const unsigned int num_op_sx; 1649 1650 extern insn_t op_16cxx[]; 1651 extern const unsigned int num_op_16cxx; 1652 1653 extern const struct strict_insn op_16cxx_strict_mask[]; 1654 extern const unsigned int num_op_16cxx_strict_mask; 1655 1656 extern const insn_t op_16cxx_enh[]; 1657 extern const unsigned int num_op_16cxx_enh; 1658 1659 extern const insn_t op_16cxx_enhx[]; 1660 extern const unsigned int num_op_16cxx_enhx; 1661 1662 extern const insn_t op_17cxx[]; 1663 extern const unsigned int num_op_17cxx; 1664 1665 extern const insn_t op_18cxx[]; 1666 extern const unsigned int num_op_18cxx; 1667 1668 extern const insn_t op_18cxx_sp[]; 1669 extern const unsigned int num_op_18cxx_sp; 1670 1671 extern const insn_t op_18cxx_ext[]; 1672 extern const unsigned int num_op_18cxx_ext; 1673 1674 #endif 1675