1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH. 2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 3 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 4 Contributed by Steve Chamberlain (sac@cygnus.com). 5 Improved by Jim Wilson (wilson@cygnus.com). 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2, or (at your option) 12 any later version. 13 14 GCC is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING. If not, write to 21 the Free Software Foundation, 51 Franklin Street, Fifth Floor, 22 Boston, MA 02110-1301, USA. */ 23 24 #ifndef GCC_SH_H 25 #define GCC_SH_H 26 27 #define TARGET_VERSION \ 28 fputs (" (Hitachi SH)", stderr); 29 30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't 31 include it here, because bconfig.h is also included by gencodes.c . */ 32 /* ??? No longer true. */ 33 extern int code_for_indirect_jump_scratch; 34 35 #define TARGET_CPU_CPP_BUILTINS() \ 36 do { \ 37 builtin_define ("__sh__"); \ 38 builtin_assert ("cpu=sh"); \ 39 builtin_assert ("machine=sh"); \ 40 switch ((int) sh_cpu) \ 41 { \ 42 case PROCESSOR_SH1: \ 43 builtin_define ("__sh1__"); \ 44 break; \ 45 case PROCESSOR_SH2: \ 46 builtin_define ("__sh2__"); \ 47 break; \ 48 case PROCESSOR_SH2E: \ 49 builtin_define ("__SH2E__"); \ 50 break; \ 51 case PROCESSOR_SH2A: \ 52 builtin_define ("__SH2A__"); \ 53 builtin_define (TARGET_SH2A_DOUBLE \ 54 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \ 55 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \ 56 : "__SH2A_NOFPU__"); \ 57 break; \ 58 case PROCESSOR_SH3: \ 59 builtin_define ("__sh3__"); \ 60 builtin_define ("__SH3__"); \ 61 if (TARGET_HARD_SH4) \ 62 builtin_define ("__SH4_NOFPU__"); \ 63 break; \ 64 case PROCESSOR_SH3E: \ 65 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \ 66 break; \ 67 case PROCESSOR_SH4: \ 68 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \ 69 break; \ 70 case PROCESSOR_SH4A: \ 71 builtin_define ("__SH4A__"); \ 72 builtin_define (TARGET_SH4 \ 73 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \ 74 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \ 75 : "__SH4_NOFPU__"); \ 76 break; \ 77 case PROCESSOR_SH5: \ 78 { \ 79 builtin_define_with_value ("__SH5__", \ 80 TARGET_SHMEDIA64 ? "64" : "32", 0); \ 81 builtin_define_with_value ("__SHMEDIA__", \ 82 TARGET_SHMEDIA ? "1" : "0", 0); \ 83 if (! TARGET_FPU_DOUBLE) \ 84 builtin_define ("__SH4_NOFPU__"); \ 85 } \ 86 } \ 87 if (TARGET_FPU_ANY) \ 88 builtin_define ("__SH_FPU_ANY__"); \ 89 if (TARGET_FPU_DOUBLE) \ 90 builtin_define ("__SH_FPU_DOUBLE__"); \ 91 if (TARGET_HITACHI) \ 92 builtin_define ("__HITACHI__"); \ 93 builtin_define (TARGET_LITTLE_ENDIAN \ 94 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \ 95 } while (0) 96 97 /* We can not debug without a frame pointer. */ 98 /* #define CAN_DEBUG_WITHOUT_FP */ 99 100 #define CONDITIONAL_REGISTER_USAGE do \ 101 { \ 102 int regno; \ 103 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \ 104 if (! VALID_REGISTER_P (regno)) \ 105 fixed_regs[regno] = call_used_regs[regno] = 1; \ 106 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \ 107 if (TARGET_SH5) \ 108 { \ 109 call_used_regs[FIRST_GENERAL_REG + 8] \ 110 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \ 111 call_really_used_regs[FIRST_GENERAL_REG + 8] \ 112 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \ 113 } \ 114 if (TARGET_SHMEDIA) \ 115 { \ 116 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \ 117 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \ 118 regno_reg_class[FIRST_FP_REG] = FP_REGS; \ 119 } \ 120 if (flag_pic) \ 121 { \ 122 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 123 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 124 } \ 125 /* Renesas saves and restores mac registers on call. */ \ 126 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \ 127 { \ 128 call_really_used_regs[MACH_REG] = 0; \ 129 call_really_used_regs[MACL_REG] = 0; \ 130 } \ 131 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \ 132 regno <= LAST_FP_REG; regno += 2) \ 133 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \ 134 if (TARGET_SHMEDIA) \ 135 { \ 136 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\ 137 if (! fixed_regs[regno] && call_really_used_regs[regno]) \ 138 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \ 139 } \ 140 else \ 141 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \ 142 if (! fixed_regs[regno] && call_really_used_regs[regno]) \ 143 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \ 144 } while (0) 145 146 /* Nonzero if this is an ELF target - compile time only */ 147 #define TARGET_ELF 0 148 149 /* Nonzero if we should generate code using type 2E insns. */ 150 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E) 151 152 /* Nonzero if we should generate code using type 2A insns. */ 153 #define TARGET_SH2A TARGET_HARD_SH2A 154 /* Nonzero if we should generate code using type 2A SF insns. */ 155 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E) 156 /* Nonzero if we should generate code using type 2A DF insns. */ 157 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A) 158 159 /* Nonzero if we should generate code using type 3E insns. */ 160 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E) 161 162 /* Nonzero if the cache line size is 32. */ 163 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5) 164 165 /* Nonzero if we schedule for a superscalar implementation. */ 166 #define TARGET_SUPERSCALAR TARGET_HARD_SH4 167 168 /* Nonzero if the target has separate instruction and data caches. */ 169 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5) 170 171 /* Nonzero if a double-precision FPU is available. */ 172 #define TARGET_FPU_DOUBLE \ 173 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE) 174 175 /* Nonzero if an FPU is available. */ 176 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE) 177 178 /* Nonzero if we should generate code using type 4 insns. */ 179 #undef TARGET_SH4 180 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1) 181 182 /* Nonzero if we're generating code for the common subset of 183 instructions present on both SH4a and SH4al-dsp. */ 184 #define TARGET_SH4A_ARCH TARGET_SH4A 185 186 /* Nonzero if we're generating code for SH4a, unless the use of the 187 FPU is disabled (which makes it compatible with SH4al-dsp). */ 188 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY) 189 190 /* Nonzero if we should generate code using the SHcompact instruction 191 set and 32-bit ABI. */ 192 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1) 193 194 /* Nonzero if we should generate code using the SHmedia instruction 195 set and ABI. */ 196 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1) 197 198 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit 199 ABI. */ 200 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E) 201 202 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit 203 ABI. */ 204 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E) 205 206 /* Nonzero if we should generate code using SHmedia FPU instructions. */ 207 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE) 208 209 /* This is not used by the SH2E calling convention */ 210 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \ 211 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \ 212 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL))) 213 214 #ifndef TARGET_CPU_DEFAULT 215 #define TARGET_CPU_DEFAULT SELECT_SH1 216 #define SUPPORT_SH1 1 217 #define SUPPORT_SH2E 1 218 #define SUPPORT_SH4 1 219 #define SUPPORT_SH4_SINGLE 1 220 #define SUPPORT_SH2A 1 221 #define SUPPORT_SH2A_SINGLE 1 222 #endif 223 224 #define TARGET_DIVIDE_INV \ 225 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \ 226 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \ 227 || sh_div_strategy == SH_DIV_INV_CALL \ 228 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP) 229 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP) 230 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP) 231 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2) 232 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT) 233 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U) 234 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L) 235 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL) 236 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2) 237 238 #define SELECT_SH1 (MASK_SH1) 239 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1) 240 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \ 241 | MASK_FPU_SINGLE) 242 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \ 243 | MASK_HARD_SH2A_DOUBLE \ 244 | MASK_SH2 | MASK_SH1) 245 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1) 246 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \ 247 | MASK_SH1 | MASK_FPU_SINGLE) 248 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \ 249 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \ 250 | MASK_SH2 | MASK_SH1) 251 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2) 252 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3) 253 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3) 254 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E) 255 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \ 256 | SELECT_SH3) 257 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4) 258 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU) 259 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) 260 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) 261 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) 262 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4) 263 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5) 264 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E) 265 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E) 266 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E) 267 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3) 268 269 #if SUPPORT_SH1 270 #define SUPPORT_SH2 1 271 #endif 272 #if SUPPORT_SH2 273 #define SUPPORT_SH3 1 274 #endif 275 #if SUPPORT_SH3 276 #define SUPPORT_SH4_NOFPU 1 277 #endif 278 #if SUPPORT_SH4_NOFPU 279 #define SUPPORT_SH4A_NOFPU 1 280 #define SUPPORT_SH4AL 1 281 #define SUPPORT_SH2A_NOFPU 1 282 #endif 283 284 #if SUPPORT_SH2E 285 #define SUPPORT_SH3E 1 286 #endif 287 #if SUPPORT_SH3E 288 #define SUPPORT_SH4_SINGLE_ONLY 1 289 #define SUPPORT_SH4A_SINGLE_ONLY 1 290 #define SUPPORT_SH2A_SINGLE_ONLY 1 291 #endif 292 293 #if SUPPORT_SH4 294 #define SUPPORT_SH4A 1 295 #endif 296 297 #if SUPPORT_SH4_SINGLE 298 #define SUPPORT_SH4A_SINGLE 1 299 #endif 300 301 #if SUPPORT_SH5_COMPAT 302 #define SUPPORT_SH5_32MEDIA 1 303 #endif 304 305 #if SUPPORT_SH5_COMPACT_NOFPU 306 #define SUPPORT_SH5_32MEDIA_NOFPU 1 307 #endif 308 309 #define SUPPORT_ANY_SH5_32MEDIA \ 310 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU) 311 #define SUPPORT_ANY_SH5_64MEDIA \ 312 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU) 313 #define SUPPORT_ANY_SH5 \ 314 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA) 315 316 /* Reset all target-selection flags. */ 317 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ 318 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ 319 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5) 320 321 /* This defaults us to big-endian. */ 322 #ifndef TARGET_ENDIAN_DEFAULT 323 #define TARGET_ENDIAN_DEFAULT 0 324 #endif 325 326 #ifndef TARGET_OPT_DEFAULT 327 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL 328 #endif 329 330 #define TARGET_DEFAULT \ 331 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT) 332 333 #ifndef SH_MULTILIB_CPU_DEFAULT 334 #define SH_MULTILIB_CPU_DEFAULT "m1" 335 #endif 336 337 #if TARGET_ENDIAN_DEFAULT 338 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT } 339 #else 340 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT } 341 #endif 342 343 #define CPP_SPEC " %(subtarget_cpp_spec) " 344 345 #ifndef SUBTARGET_CPP_SPEC 346 #define SUBTARGET_CPP_SPEC "" 347 #endif 348 349 #ifndef SUBTARGET_EXTRA_SPECS 350 #define SUBTARGET_EXTRA_SPECS 351 #endif 352 353 #define EXTRA_SPECS \ 354 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 355 { "link_emul_prefix", LINK_EMUL_PREFIX }, \ 356 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \ 357 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \ 358 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \ 359 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \ 360 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \ 361 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \ 362 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ 363 SUBTARGET_EXTRA_SPECS 364 365 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 366 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}" 367 #else 368 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}" 369 #endif 370 371 #define SH_ASM_SPEC \ 372 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\ 373 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\ 374 %{m2a:--isa=sh2a} \ 375 %{m2a-single:--isa=sh2a} \ 376 %{m2a-single-only:--isa=sh2a} \ 377 %{m2a-nofpu:--isa=sh2a-nofpu} \ 378 %{m5-compact*:--isa=SHcompact} \ 379 %{m5-32media*:--isa=SHmedia --abi=32} \ 380 %{m5-64media*:--isa=SHmedia --abi=64} \ 381 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}" 382 383 #define ASM_SPEC SH_ASM_SPEC 384 385 #ifndef SUBTARGET_ASM_ENDIAN_SPEC 386 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN 387 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}" 388 #else 389 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}" 390 #endif 391 #endif 392 393 #if STRICT_NOFPU == 1 394 /* Strict nofpu means that the compiler should tell the assembler 395 to reject FPU instructions. E.g. from ASM inserts. */ 396 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E) 397 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}" 398 #else 399 /* If there were an -isa option for sh5-nofpu then it would also go here. */ 400 #define SUBTARGET_ASM_ISA_SPEC \ 401 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC 402 #endif 403 #else /* ! STRICT_NOFPU */ 404 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC 405 #endif 406 407 #ifndef SUBTARGET_ASM_SPEC 408 #define SUBTARGET_ASM_SPEC "" 409 #endif 410 411 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN 412 #define LINK_EMUL_PREFIX "sh%{!mb:l}" 413 #else 414 #define LINK_EMUL_PREFIX "sh%{ml:l}" 415 #endif 416 417 #if TARGET_CPU_DEFAULT & MASK_SH5 418 #if TARGET_CPU_DEFAULT & MASK_SH_E 419 #define LINK_DEFAULT_CPU_EMUL "32" 420 #if TARGET_CPU_DEFAULT & MASK_SH1 421 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact" 422 #else 423 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32" 424 #endif /* MASK_SH1 */ 425 #else /* !MASK_SH_E */ 426 #define LINK_DEFAULT_CPU_EMUL "64" 427 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64" 428 #endif /* MASK_SH_E */ 429 #define ASM_ISA_DEFAULT_SPEC \ 430 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}" 431 #else /* !MASK_SH5 */ 432 #define LINK_DEFAULT_CPU_EMUL "" 433 #define ASM_ISA_DEFAULT_SPEC "" 434 #endif /* MASK_SH5 */ 435 436 #define SUBTARGET_LINK_EMUL_SUFFIX "" 437 #define SUBTARGET_LINK_SPEC "" 438 439 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC, 440 so that we can undo the damage without code replication. */ 441 #define LINK_SPEC SH_LINK_SPEC 442 443 #define SH_LINK_SPEC "\ 444 -m %(link_emul_prefix)\ 445 %{m5-compact*|m5-32media*:32}\ 446 %{m5-64media*:64}\ 447 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\ 448 %(subtarget_link_emul_suffix) \ 449 %{mrelax:-relax} %(subtarget_link_spec)" 450 451 #ifndef SH_DIV_STR_FOR_SIZE 452 #define SH_DIV_STR_FOR_SIZE "call" 453 #endif 454 455 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}" 456 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ 457 do { \ 458 if (LEVEL) \ 459 { \ 460 flag_omit_frame_pointer = -1; \ 461 if (! SIZE) \ 462 sh_div_str = "inv:minlat"; \ 463 } \ 464 if (SIZE) \ 465 { \ 466 target_flags |= MASK_SMALLCODE; \ 467 sh_div_str = SH_DIV_STR_FOR_SIZE ; \ 468 } \ 469 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \ 470 haven't been parsed yet, hence we';d read only the default. \ 471 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \ 472 it's OK to always set flag_branch_target_load_optimize. */ \ 473 if (LEVEL > 1) \ 474 { \ 475 flag_branch_target_load_optimize = 1; \ 476 if (! (SIZE)) \ 477 target_flags |= MASK_SAVE_ALL_TARGET_REGS; \ 478 } \ 479 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE \ 480 here, so leave it to OVERRIDE_OPTIONS to set \ 481 flag_finite_math_only. We set it to 2 here so we know if the user \ 482 explicitly requested this to be on or off. */ \ 483 flag_finite_math_only = 2; \ 484 /* If flag_schedule_insns is 1, we set it to 2 here so we know if \ 485 the user explicitly requested this to be on or off. */ \ 486 if (flag_schedule_insns > 0) \ 487 flag_schedule_insns = 2; \ 488 } while (0) 489 490 #define ASSEMBLER_DIALECT assembler_dialect 491 492 extern int assembler_dialect; 493 494 enum sh_divide_strategy_e { 495 SH_DIV_CALL, 496 SH_DIV_CALL2, 497 SH_DIV_FP, 498 SH_DIV_INV, 499 SH_DIV_INV_MINLAT, 500 SH_DIV_INV20U, 501 SH_DIV_INV20L, 502 SH_DIV_INV_CALL, 503 SH_DIV_INV_CALL2, 504 SH_DIV_INV_FP 505 }; 506 507 extern enum sh_divide_strategy_e sh_div_strategy; 508 509 #ifndef SH_DIV_STRATEGY_DEFAULT 510 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL 511 #endif 512 513 #define OVERRIDE_OPTIONS sh_override_options () 514 515 /* Target machine storage layout. */ 516 517 /* Define this if most significant bit is lowest numbered 518 in instructions that operate on numbered bit-fields. */ 519 520 #define BITS_BIG_ENDIAN 0 521 522 /* Define this if most significant byte of a word is the lowest numbered. */ 523 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) 524 525 /* Define this if most significant word of a multiword number is the lowest 526 numbered. */ 527 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) 528 529 /* Define this to set the endianness to use in libgcc2.c, which can 530 not depend on target_flags. */ 531 #if defined(__LITTLE_ENDIAN__) 532 #define LIBGCC2_WORDS_BIG_ENDIAN 0 533 #else 534 #define LIBGCC2_WORDS_BIG_ENDIAN 1 535 #endif 536 537 #define MAX_BITS_PER_WORD 64 538 539 /* Width in bits of an `int'. We want just 32-bits, even if words are 540 longer. */ 541 #define INT_TYPE_SIZE 32 542 543 /* Width in bits of a `long'. */ 544 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32) 545 546 /* Width in bits of a `long long'. */ 547 #define LONG_LONG_TYPE_SIZE 64 548 549 /* Width in bits of a `long double'. */ 550 #define LONG_DOUBLE_TYPE_SIZE 64 551 552 /* Width of a word, in units (bytes). */ 553 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4) 554 #define MIN_UNITS_PER_WORD 4 555 556 /* Scaling factor for Dwarf data offsets for CFI information. 557 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for 558 SHmedia; however, since we do partial register saves for the registers 559 visible to SHcompact, and for target registers for SHMEDIA32, we have 560 to allow saves that are only 4-byte aligned. */ 561 #define DWARF_CIE_DATA_ALIGNMENT -4 562 563 /* Width in bits of a pointer. 564 See also the macro `Pmode' defined below. */ 565 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32) 566 567 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 568 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32) 569 570 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 571 #define STACK_BOUNDARY BIGGEST_ALIGNMENT 572 573 /* The log (base 2) of the cache line size, in bytes. Processors prior to 574 SH2 have no actual cache, but they fetch code in chunks of 4 bytes. 575 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */ 576 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2) 577 578 /* ABI given & required minimum allocation boundary (in *bits*) for the 579 code of a function. */ 580 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA) 581 582 /* On SH5, the lowest bit is used to indicate SHmedia functions, so 583 the vbit must go into the delta field of 584 pointers-to-member-functions. */ 585 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \ 586 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn) 587 588 /* Alignment of field after `int : 0' in a structure. */ 589 #define EMPTY_FIELD_BOUNDARY 32 590 591 /* No data type wants to be aligned rounder than this. */ 592 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) 593 594 /* The best alignment to use in cases where we have a choice. */ 595 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32) 596 597 /* Make strings word-aligned so strcpy from constants will be faster. */ 598 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 599 ((TREE_CODE (EXP) == STRING_CST \ 600 && (ALIGN) < FASTEST_ALIGNMENT) \ 601 ? FASTEST_ALIGNMENT : (ALIGN)) 602 603 /* get_mode_alignment assumes complex values are always held in multiple 604 registers, but that is not the case on the SH; CQImode and CHImode are 605 held in a single integer register. SH5 also holds CSImode and SCmode 606 values in integer registers. This is relevant for argument passing on 607 SHcompact as we use a stack temp in order to pass CSImode by reference. */ 608 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 609 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \ 610 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \ 611 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \ 612 : (unsigned) ALIGN) 613 614 /* Make arrays of chars word-aligned for the same reasons. */ 615 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 616 (TREE_CODE (TYPE) == ARRAY_TYPE \ 617 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 618 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 619 620 /* Number of bits which any structure or union's size must be a 621 multiple of. Each structure or union's size is rounded up to a 622 multiple of this. */ 623 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8) 624 625 /* Set this nonzero if move instructions will actually fail to work 626 when given unaligned data. */ 627 #define STRICT_ALIGNMENT 1 628 629 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */ 630 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \ 631 barrier_align (LABEL_AFTER_BARRIER) 632 633 #define LOOP_ALIGN(A_LABEL) \ 634 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \ 635 ? 0 : sh_loop_align (A_LABEL)) 636 637 #define LABEL_ALIGN(A_LABEL) \ 638 ( \ 639 (PREV_INSN (A_LABEL) \ 640 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \ 641 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \ 642 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \ 643 /* explicit alignment insn in constant tables. */ \ 644 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \ 645 : 0) 646 647 /* Jump tables must be 32 bit aligned, no matter the size of the element. */ 648 #define ADDR_VEC_ALIGN(ADDR_VEC) 2 649 650 /* The base two logarithm of the known minimum alignment of an insn length. */ 651 #define INSN_LENGTH_ALIGNMENT(A_INSN) \ 652 (GET_CODE (A_INSN) == INSN \ 653 ? 1 << TARGET_SHMEDIA \ 654 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \ 655 ? 1 << TARGET_SHMEDIA \ 656 : CACHE_LOG) 657 658 /* Standard register usage. */ 659 660 /* Register allocation for the Renesas calling convention: 661 662 r0 arg return 663 r1..r3 scratch 664 r4..r7 args in 665 r8..r13 call saved 666 r14 frame pointer/call saved 667 r15 stack pointer 668 ap arg pointer (doesn't really exist, always eliminated) 669 pr subroutine return address 670 t t bit 671 mach multiply/accumulate result, high part 672 macl multiply/accumulate result, low part. 673 fpul fp/int communication register 674 rap return address pointer register 675 fr0 fp arg return 676 fr1..fr3 scratch floating point registers 677 fr4..fr11 fp args in 678 fr12..fr15 call saved floating point registers */ 679 680 #define MAX_REGISTER_NAME_LENGTH 5 681 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1]; 682 683 #define SH_REGISTER_NAMES_INITIALIZER \ 684 { \ 685 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 686 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 687 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ 688 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ 689 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ 690 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \ 691 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ 692 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \ 693 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \ 694 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \ 695 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \ 696 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \ 697 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \ 698 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \ 699 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \ 700 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \ 701 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \ 702 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \ 703 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \ 704 "rap", "sfp" \ 705 } 706 707 #define REGNAMES_ARR_INDEX_1(index) \ 708 (sh_register_names[index]) 709 #define REGNAMES_ARR_INDEX_2(index) \ 710 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1) 711 #define REGNAMES_ARR_INDEX_4(index) \ 712 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2) 713 #define REGNAMES_ARR_INDEX_8(index) \ 714 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4) 715 #define REGNAMES_ARR_INDEX_16(index) \ 716 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8) 717 #define REGNAMES_ARR_INDEX_32(index) \ 718 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16) 719 #define REGNAMES_ARR_INDEX_64(index) \ 720 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32) 721 722 #define REGISTER_NAMES \ 723 { \ 724 REGNAMES_ARR_INDEX_64 (0), \ 725 REGNAMES_ARR_INDEX_64 (64), \ 726 REGNAMES_ARR_INDEX_8 (128), \ 727 REGNAMES_ARR_INDEX_8 (136), \ 728 REGNAMES_ARR_INDEX_8 (144), \ 729 REGNAMES_ARR_INDEX_2 (152) \ 730 } 731 732 #define ADDREGNAMES_SIZE 32 733 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4 734 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ 735 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]; 736 737 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \ 738 { \ 739 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \ 740 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \ 741 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \ 742 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \ 743 } 744 745 #define ADDREGNAMES_REGNO(index) \ 746 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \ 747 : (-1)) 748 749 #define ADDREGNAMES_ARR_INDEX_1(index) \ 750 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) } 751 #define ADDREGNAMES_ARR_INDEX_2(index) \ 752 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1) 753 #define ADDREGNAMES_ARR_INDEX_4(index) \ 754 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2) 755 #define ADDREGNAMES_ARR_INDEX_8(index) \ 756 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4) 757 #define ADDREGNAMES_ARR_INDEX_16(index) \ 758 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8) 759 #define ADDREGNAMES_ARR_INDEX_32(index) \ 760 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16) 761 762 #define ADDITIONAL_REGISTER_NAMES \ 763 { \ 764 ADDREGNAMES_ARR_INDEX_32 (0) \ 765 } 766 767 /* Number of actual hardware registers. 768 The hardware registers are assigned numbers for the compiler 769 from 0 to just below FIRST_PSEUDO_REGISTER. 770 All registers that the compiler knows about must be given numbers, 771 even those that are not normally considered general registers. */ 772 773 /* There are many other relevant definitions in sh.md's md_constants. */ 774 775 #define FIRST_GENERAL_REG R0_REG 776 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15)) 777 #define FIRST_FP_REG DR0_REG 778 #define LAST_FP_REG (FIRST_FP_REG + \ 779 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1)) 780 #define FIRST_XD_REG XD0_REG 781 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1)) 782 #define FIRST_TARGET_REG TR0_REG 783 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1)) 784 785 #define GENERAL_REGISTER_P(REGNO) \ 786 IN_RANGE ((REGNO), \ 787 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ 788 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG) 789 790 #define GENERAL_OR_AP_REGISTER_P(REGNO) \ 791 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \ 792 || ((REGNO) == FRAME_POINTER_REGNUM)) 793 794 #define FP_REGISTER_P(REGNO) \ 795 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG) 796 797 #define XD_REGISTER_P(REGNO) \ 798 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG) 799 800 #define FP_OR_XD_REGISTER_P(REGNO) \ 801 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO)) 802 803 #define FP_ANY_REGISTER_P(REGNO) \ 804 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG) 805 806 #define SPECIAL_REGISTER_P(REGNO) \ 807 ((REGNO) == GBR_REG || (REGNO) == T_REG \ 808 || (REGNO) == MACH_REG || (REGNO) == MACL_REG) 809 810 #define TARGET_REGISTER_P(REGNO) \ 811 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG) 812 813 #define SHMEDIA_REGISTER_P(REGNO) \ 814 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \ 815 || TARGET_REGISTER_P (REGNO)) 816 817 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers 818 that should be fixed. */ 819 #define VALID_REGISTER_P(REGNO) \ 820 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \ 821 || (REGNO) == AP_REG || (REGNO) == RAP_REG \ 822 || (REGNO) == FRAME_POINTER_REGNUM \ 823 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \ 824 || (TARGET_SH2E && (REGNO) == FPUL_REG)) 825 826 /* The mode that should be generally used to store a register by 827 itself in the stack, or to load it back. */ 828 #define REGISTER_NATURAL_MODE(REGNO) \ 829 (FP_REGISTER_P (REGNO) ? SFmode \ 830 : XD_REGISTER_P (REGNO) ? DFmode \ 831 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \ 832 ? DImode \ 833 : SImode) 834 835 #define FIRST_PSEUDO_REGISTER 154 836 837 /* Don't count soft frame pointer. */ 838 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1) 839 840 /* 1 for registers that have pervasive standard uses 841 and are not available for the register allocator. 842 843 Mach register is fixed 'cause it's only 10 bits wide for SH1. 844 It is 32 bits wide for SH2. */ 845 846 #define FIXED_REGISTERS \ 847 { \ 848 /* Regular registers. */ \ 849 0, 0, 0, 0, 0, 0, 0, 0, \ 850 0, 0, 0, 0, 0, 0, 0, 1, \ 851 /* r16 is reserved, r18 is the former pr. */ \ 852 1, 0, 0, 0, 0, 0, 0, 0, \ 853 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \ 854 /* r26 is a global variable data pointer; r27 is for constants. */ \ 855 1, 1, 1, 1, 0, 0, 0, 0, \ 856 0, 0, 0, 0, 0, 0, 0, 0, \ 857 0, 0, 0, 0, 0, 0, 0, 0, \ 858 0, 0, 0, 0, 0, 0, 0, 0, \ 859 0, 0, 0, 0, 0, 0, 0, 1, \ 860 /* FP registers. */ \ 861 0, 0, 0, 0, 0, 0, 0, 0, \ 862 0, 0, 0, 0, 0, 0, 0, 0, \ 863 0, 0, 0, 0, 0, 0, 0, 0, \ 864 0, 0, 0, 0, 0, 0, 0, 0, \ 865 0, 0, 0, 0, 0, 0, 0, 0, \ 866 0, 0, 0, 0, 0, 0, 0, 0, \ 867 0, 0, 0, 0, 0, 0, 0, 0, \ 868 0, 0, 0, 0, 0, 0, 0, 0, \ 869 /* Branch target registers. */ \ 870 0, 0, 0, 0, 0, 0, 0, 0, \ 871 /* XD registers. */ \ 872 0, 0, 0, 0, 0, 0, 0, 0, \ 873 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ 874 1, 1, 1, 1, 1, 1, 0, 1, \ 875 /*"rap", "sfp" */ \ 876 1, 1, \ 877 } 878 879 /* 1 for registers not available across function calls. 880 These must include the FIXED_REGISTERS and also any 881 registers that can be used without being saved. 882 The latter must include the registers where values are returned 883 and the register where structure-value addresses are passed. 884 Aside from that, you can include as many other registers as you like. */ 885 886 #define CALL_USED_REGISTERS \ 887 { \ 888 /* Regular registers. */ \ 889 1, 1, 1, 1, 1, 1, 1, 1, \ 890 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \ 891 Only the lower 32bits of R10-R14 are guaranteed to be preserved \ 892 across SH5 function calls. */ \ 893 0, 0, 0, 0, 0, 0, 0, 1, \ 894 1, 1, 1, 1, 1, 1, 1, 1, \ 895 1, 1, 1, 1, 0, 0, 0, 0, \ 896 0, 0, 0, 0, 1, 1, 1, 1, \ 897 1, 1, 1, 1, 0, 0, 0, 0, \ 898 0, 0, 0, 0, 0, 0, 0, 0, \ 899 0, 0, 0, 0, 1, 1, 1, 1, \ 900 /* FP registers. */ \ 901 1, 1, 1, 1, 1, 1, 1, 1, \ 902 1, 1, 1, 1, 0, 0, 0, 0, \ 903 1, 1, 1, 1, 1, 1, 1, 1, \ 904 1, 1, 1, 1, 1, 1, 1, 1, \ 905 1, 1, 1, 1, 0, 0, 0, 0, \ 906 0, 0, 0, 0, 0, 0, 0, 0, \ 907 0, 0, 0, 0, 0, 0, 0, 0, \ 908 0, 0, 0, 0, 0, 0, 0, 0, \ 909 /* Branch target registers. */ \ 910 1, 1, 1, 1, 1, 0, 0, 0, \ 911 /* XD registers. */ \ 912 1, 1, 1, 1, 1, 1, 0, 0, \ 913 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ 914 1, 1, 1, 1, 1, 1, 1, 1, \ 915 /*"rap", "sfp" */ \ 916 1, 1, \ 917 } 918 919 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet 920 fixed, like PIC_OFFSET_TABLE_REGNUM. */ 921 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS 922 923 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved 924 across SHcompact function calls. We can't tell whether a called 925 function is SHmedia or SHcompact, so we assume it may be when 926 compiling SHmedia code with the 32-bit ABI, since that's the only 927 ABI that can be linked with SHcompact code. */ 928 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \ 929 (TARGET_SHMEDIA32 \ 930 && GET_MODE_SIZE (MODE) > 4 \ 931 && (((REGNO) >= FIRST_GENERAL_REG + 10 \ 932 && (REGNO) <= FIRST_GENERAL_REG + 15) \ 933 || TARGET_REGISTER_P (REGNO) \ 934 || (REGNO) == PR_MEDIA_REG)) 935 936 /* Return number of consecutive hard regs needed starting at reg REGNO 937 to hold something of mode MODE. 938 This is ordinarily the length in words of a value of mode MODE 939 but can be less for certain modes in special long registers. 940 941 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */ 942 943 #define HARD_REGNO_NREGS(REGNO, MODE) \ 944 (XD_REGISTER_P (REGNO) \ 945 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \ 946 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \ 947 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \ 948 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 949 950 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 951 We can allow any mode in any general register. The special registers 952 only allow SImode. Don't allow any mode in the PR. */ 953 954 /* We cannot hold DCmode values in the XD registers because alter_reg 955 handles subregs of them incorrectly. We could work around this by 956 spacing the XD registers like the DR registers, but this would require 957 additional memory in every compilation to hold larger register vectors. 958 We could hold SFmode / SCmode values in XD registers, but that 959 would require a tertiary reload when reloading from / to memory, 960 and a secondary reload to reload from / to general regs; that 961 seems to be a loosing proposition. */ 962 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode, 963 it won't be ferried through GP registers first. */ 964 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 965 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \ 966 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \ 967 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \ 968 ? 1 \ 969 : (MODE) == V2SFmode \ 970 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \ 971 || GENERAL_REGISTER_P (REGNO)) \ 972 : (MODE) == V4SFmode \ 973 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \ 974 || GENERAL_REGISTER_P (REGNO)) \ 975 : (MODE) == V16SFmode \ 976 ? (TARGET_SHMEDIA \ 977 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \ 978 : (REGNO) == FIRST_XD_REG) \ 979 : FP_REGISTER_P (REGNO) \ 980 ? ((MODE) == SFmode || (MODE) == SImode \ 981 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \ 982 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \ 983 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \ 984 || (MODE) == V2SFmode || (MODE) == TImode))) \ 985 && (((REGNO) - FIRST_FP_REG) & 1) == 0) \ 986 || ((TARGET_SH4 || TARGET_SHMEDIA) \ 987 && (MODE) == TImode \ 988 && (((REGNO) - FIRST_FP_REG) & 3) == 0)) \ 989 : XD_REGISTER_P (REGNO) \ 990 ? (MODE) == DFmode \ 991 : TARGET_REGISTER_P (REGNO) \ 992 ? ((MODE) == DImode || (MODE) == SImode || (MODE) == PDImode) \ 993 : (REGNO) == PR_REG ? (MODE) == SImode \ 994 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \ 995 : 1) 996 997 /* Value is 1 if it is a good idea to tie two pseudo registers 998 when one has mode MODE1 and one has mode MODE2. 999 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1000 for any hard reg, then this must be 0 for correct output. 1001 That's the case for xd registers: we don't hold SFmode values in 1002 them, so we can't tie an SFmode pseudos with one in another 1003 floating-point mode. */ 1004 1005 #define MODES_TIEABLE_P(MODE1, MODE2) \ 1006 ((MODE1) == (MODE2) \ 1007 || (TARGET_SHMEDIA \ 1008 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \ 1009 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \ 1010 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ 1011 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \ 1012 && (GET_MODE_SIZE (MODE2) <= 4)) \ 1013 : ((MODE1) != SFmode && (MODE2) != SFmode)))) 1014 1015 /* A C expression that is nonzero if hard register NEW_REG can be 1016 considered for use as a rename register for OLD_REG register */ 1017 1018 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ 1019 sh_hard_regno_rename_ok (OLD_REG, NEW_REG) 1020 1021 /* Specify the registers used for certain standard purposes. 1022 The values of these macros are register numbers. */ 1023 1024 /* Define this if the program counter is overloaded on a register. */ 1025 /* #define PC_REGNUM 15*/ 1026 1027 /* Register to use for pushing function arguments. */ 1028 #define STACK_POINTER_REGNUM SP_REG 1029 1030 /* Base register for access to local variables of the function. */ 1031 #define HARD_FRAME_POINTER_REGNUM FP_REG 1032 1033 /* Base register for access to local variables of the function. */ 1034 #define FRAME_POINTER_REGNUM 153 1035 1036 /* Fake register that holds the address on the stack of the 1037 current function's return address. */ 1038 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG 1039 1040 /* Register to hold the addressing base for position independent 1041 code access to data items. */ 1042 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM) 1043 1044 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_" 1045 1046 /* Value should be nonzero if functions must have frame pointers. 1047 Zero means the frame pointer need not be set up (and parms may be accessed 1048 via the stack pointer) in functions that seem suitable. */ 1049 1050 #define FRAME_POINTER_REQUIRED 0 1051 1052 /* Definitions for register eliminations. 1053 1054 We have three registers that can be eliminated on the SH. First, the 1055 frame pointer register can often be eliminated in favor of the stack 1056 pointer register. Secondly, the argument pointer register can always be 1057 eliminated; it is replaced with either the stack or frame pointer. 1058 Third, there is the return address pointer, which can also be replaced 1059 with either the stack or the frame pointer. */ 1060 1061 /* This is an array of structures. Each structure initializes one pair 1062 of eliminable registers. The "from" register number is given first, 1063 followed by "to". Eliminations of the same "from" register are listed 1064 in order of preference. */ 1065 1066 /* If you add any registers here that are not actually hard registers, 1067 and that have any alternative of elimination that doesn't always 1068 apply, you need to amend calc_live_regs to exclude it, because 1069 reload spills all eliminable registers where it sees an 1070 can_eliminate == 0 entry, thus making them 'live' . 1071 If you add any hard registers that can be eliminated in different 1072 ways, you have to patch reload to spill them only when all alternatives 1073 of elimination fail. */ 1074 1075 #define ELIMINABLE_REGS \ 1076 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1077 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1078 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1079 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1080 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1081 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1082 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},} 1083 1084 /* Given FROM and TO register numbers, say whether this elimination 1085 is allowed. */ 1086 #define CAN_ELIMINATE(FROM, TO) \ 1087 (!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)) 1088 1089 /* Define the offset between two registers, one to be eliminated, and the other 1090 its replacement, at the start of a routine. */ 1091 1092 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1093 OFFSET = initial_elimination_offset ((FROM), (TO)) 1094 1095 /* Base register for access to arguments of the function. */ 1096 #define ARG_POINTER_REGNUM AP_REG 1097 1098 /* Register in which the static-chain is passed to a function. */ 1099 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3) 1100 1101 /* Don't default to pcc-struct-return, because we have already specified 1102 exactly how to return structures in the TARGET_RETURN_IN_MEMORY 1103 target hook. */ 1104 1105 #define DEFAULT_PCC_STRUCT_RETURN 0 1106 1107 #define SHMEDIA_REGS_STACK_ADJUST() \ 1108 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \ 1109 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \ 1110 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \ 1111 : 0) 1112 1113 1114 /* Define the classes of registers for register constraints in the 1115 machine description. Also define ranges of constants. 1116 1117 One of the classes must always be named ALL_REGS and include all hard regs. 1118 If there is more than one class, another class must be named NO_REGS 1119 and contain no registers. 1120 1121 The name GENERAL_REGS must be the name of a class (or an alias for 1122 another name such as ALL_REGS). This is the class of registers 1123 that is allowed by "g" or "r" in a register constraint. 1124 Also, registers outside this class are allocated only when 1125 instructions express preferences for them. 1126 1127 The classes must be numbered in nondecreasing order; that is, 1128 a larger-numbered class must never be contained completely 1129 in a smaller-numbered class. 1130 1131 For any two classes, it is very desirable that there be another 1132 class that represents their union. */ 1133 1134 /* The SH has two sorts of general registers, R0 and the rest. R0 can 1135 be used as the destination of some of the arithmetic ops. There are 1136 also some special purpose registers; the T bit register, the 1137 Procedure Return Register and the Multiply Accumulate Registers. */ 1138 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by 1139 reg_class_subunion. We don't want to have an actual union class 1140 of these, because it would only be used when both classes are calculated 1141 to give the same cost, but there is only one FPUL register. 1142 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS 1143 applying to the actual instruction alternative considered. E.g., the 1144 y/r alternative of movsi_ie is considered to have no more cost that 1145 the r/r alternative, which is patently untrue. */ 1146 1147 enum reg_class 1148 { 1149 NO_REGS, 1150 R0_REGS, 1151 PR_REGS, 1152 T_REGS, 1153 MAC_REGS, 1154 FPUL_REGS, 1155 SIBCALL_REGS, 1156 GENERAL_REGS, 1157 FP0_REGS, 1158 FP_REGS, 1159 DF_HI_REGS, 1160 DF_REGS, 1161 FPSCR_REGS, 1162 GENERAL_FP_REGS, 1163 GENERAL_DF_REGS, 1164 TARGET_REGS, 1165 ALL_REGS, 1166 LIM_REG_CLASSES 1167 }; 1168 1169 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1170 1171 /* Give names of register classes as strings for dump file. */ 1172 #define REG_CLASS_NAMES \ 1173 { \ 1174 "NO_REGS", \ 1175 "R0_REGS", \ 1176 "PR_REGS", \ 1177 "T_REGS", \ 1178 "MAC_REGS", \ 1179 "FPUL_REGS", \ 1180 "SIBCALL_REGS", \ 1181 "GENERAL_REGS", \ 1182 "FP0_REGS", \ 1183 "FP_REGS", \ 1184 "DF_HI_REGS", \ 1185 "DF_REGS", \ 1186 "FPSCR_REGS", \ 1187 "GENERAL_FP_REGS", \ 1188 "GENERAL_DF_REGS", \ 1189 "TARGET_REGS", \ 1190 "ALL_REGS", \ 1191 } 1192 1193 /* Define which registers fit in which classes. 1194 This is an initializer for a vector of HARD_REG_SET 1195 of length N_REG_CLASSES. */ 1196 1197 #define REG_CLASS_CONTENTS \ 1198 { \ 1199 /* NO_REGS: */ \ 1200 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 1201 /* R0_REGS: */ \ 1202 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 1203 /* PR_REGS: */ \ 1204 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \ 1205 /* T_REGS: */ \ 1206 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \ 1207 /* MAC_REGS: */ \ 1208 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \ 1209 /* FPUL_REGS: */ \ 1210 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \ 1211 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \ 1212 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 1213 /* GENERAL_REGS: */ \ 1214 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \ 1215 /* FP0_REGS: */ \ 1216 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \ 1217 /* FP_REGS: */ \ 1218 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ 1219 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \ 1220 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ 1221 /* DF_REGS: */ \ 1222 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ 1223 /* FPSCR_REGS: */ \ 1224 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \ 1225 /* GENERAL_FP_REGS: */ \ 1226 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \ 1227 /* GENERAL_DF_REGS: */ \ 1228 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \ 1229 /* TARGET_REGS: */ \ 1230 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \ 1231 /* ALL_REGS: */ \ 1232 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \ 1233 } 1234 1235 /* The same information, inverted: 1236 Return the class number of the smallest class containing 1237 reg number REGNO. This could be a conditional expression 1238 or could index an array. */ 1239 1240 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; 1241 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)] 1242 1243 /* When defined, the compiler allows registers explicitly used in the 1244 rtl to be used as spill registers but prevents the compiler from 1245 extending the lifetime of these registers. */ 1246 1247 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA) 1248 1249 /* The order in which register should be allocated. */ 1250 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo, 1251 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be 1252 spilled or used otherwise, we better have the FP_REGS allocated first. */ 1253 #define REG_ALLOC_ORDER \ 1254 {/* Caller-saved FPRs */ \ 1255 65, 66, 67, 68, 69, 70, 71, 64, \ 1256 72, 73, 74, 75, 80, 81, 82, 83, \ 1257 84, 85, 86, 87, 88, 89, 90, 91, \ 1258 92, 93, 94, 95, 96, 97, 98, 99, \ 1259 /* Callee-saved FPRs */ \ 1260 76, 77, 78, 79,100,101,102,103, \ 1261 104,105,106,107,108,109,110,111, \ 1262 112,113,114,115,116,117,118,119, \ 1263 120,121,122,123,124,125,126,127, \ 1264 136,137,138,139,140,141,142,143, \ 1265 /* FPSCR */ 151, \ 1266 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \ 1267 1, 2, 3, 7, 6, 5, 4, 0, \ 1268 8, 9, 17, 19, 20, 21, 22, 23, \ 1269 36, 37, 38, 39, 40, 41, 42, 43, \ 1270 60, 61, 62, \ 1271 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \ 1272 10, 11, 12, 13, 14, 18, \ 1273 /* SH5 callee-saved GPRs */ \ 1274 28, 29, 30, 31, 32, 33, 34, 35, \ 1275 44, 45, 46, 47, 48, 49, 50, 51, \ 1276 52, 53, 54, 55, 56, 57, 58, 59, \ 1277 /* FPUL */ 150, \ 1278 /* SH5 branch target registers */ \ 1279 128,129,130,131,132,133,134,135, \ 1280 /* Fixed registers */ \ 1281 15, 16, 24, 25, 26, 27, 63,144, \ 1282 145,146,147,148,149,152,153 } 1283 1284 /* The class value for index registers, and the one for base regs. */ 1285 #define INDEX_REG_CLASS \ 1286 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS) 1287 #define BASE_REG_CLASS GENERAL_REGS 1288 1289 /* Get reg_class from a letter such as appears in the machine 1290 description. */ 1291 extern enum reg_class reg_class_from_letter[]; 1292 1293 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/ 1294 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \ 1295 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS ) 1296 1297 /* Overview of uppercase letter constraints: 1298 A: Addresses (constraint len == 3) 1299 Ac4: sh4 cache operations 1300 Ac5: sh5 cache operations 1301 Bxx: miscellaneous constraints 1302 Bsc: SCRATCH - for the scratch register in movsi_ie in the 1303 fldi0 / fldi0 cases 1304 C: Constants other than only CONST_INT (constraint len == 3) 1305 Css: signed 16 bit constant, literal or symbolic 1306 Csu: unsigned 16 bit constant, literal or symbolic 1307 Csy: label or symbol 1308 Cpg: non-explicit constants that can be directly loaded into a general 1309 purpose register in PIC code. like 's' except we don't allow 1310 PIC_DIRECT_ADDR_P 1311 IJKLMNOP: CONT_INT constants 1312 Ixx: signed xx bit 1313 J16: 0xffffffff00000000 | 0x00000000ffffffff 1314 Kxx: unsigned xx bit 1315 M: 1 1316 N: 0 1317 P27: 1 | 2 | 8 | 16 1318 Q: pc relative load operand 1319 Rxx: reserved for exotic register classes. 1320 S: extra memory (storage) constraints (constraint len == 3) 1321 Sua: unaligned memory operations 1322 W: vector 1323 Z: zero in any mode 1324 1325 unused CONST_INT constraint letters: LO 1326 unused EXTRA_CONSTRAINT letters: D T U Y */ 1327 1328 #define CONSTRAINT_LEN(C,STR) \ 1329 (((C) == 'A' || (C) == 'B' || (C) == 'C' \ 1330 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \ 1331 || (C) == 'R' || (C) == 'S') \ 1332 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR))) 1333 1334 /* The letters I, J, K, L and M in a register constraint string 1335 can be used to stand for particular ranges of immediate operands. 1336 This macro defines what the ranges are. 1337 C is the letter, and VALUE is a constant value. 1338 Return 1 if VALUE is in the range specified by C. 1339 I08: arithmetic operand -127..128, as used in add, sub, etc 1340 I16: arithmetic operand -32768..32767, as used in SHmedia movi 1341 K16: arithmetic operand 0..65535, as used in SHmedia shori 1342 P27: shift operand 1,2,8 or 16 1343 K08: logical operand 0..255, as used in and, or, etc. 1344 M: constant 1 1345 N: constant 0 1346 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori 1347 I10: arithmetic operand -512..511, as used in SHmedia andi, ori 1348 */ 1349 1350 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \ 1351 && ((HOST_WIDE_INT)(VALUE)) <= 31) 1352 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \ 1353 && ((HOST_WIDE_INT)(VALUE)) <= 127) 1354 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \ 1355 && ((HOST_WIDE_INT)(VALUE)) <= 511) 1356 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \ 1357 && ((HOST_WIDE_INT)(VALUE)) <= 32767) 1358 #define CONST_OK_FOR_I20(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -524288 \ 1359 && ((HOST_WIDE_INT)(VALUE)) <= 524287 \ 1360 && TARGET_SH2A) 1361 #define CONST_OK_FOR_I(VALUE, STR) \ 1362 ((STR)[1] == '0' && (STR)[2] == '6' ? CONST_OK_FOR_I06 (VALUE) \ 1363 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \ 1364 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \ 1365 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \ 1366 : (STR)[1] == '2' && (STR)[2] == '0' ? CONST_OK_FOR_I20 (VALUE) \ 1367 : 0) 1368 1369 #define CONST_OK_FOR_J16(VALUE) \ 1370 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \ 1371 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32)) 1372 #define CONST_OK_FOR_J(VALUE, STR) \ 1373 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \ 1374 : 0) 1375 1376 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \ 1377 && ((HOST_WIDE_INT)(VALUE)) <= 255) 1378 #define CONST_OK_FOR_K16(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \ 1379 && ((HOST_WIDE_INT)(VALUE)) <= 65535) 1380 #define CONST_OK_FOR_K(VALUE, STR) \ 1381 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \ 1382 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_K16 (VALUE) \ 1383 : 0) 1384 #define CONST_OK_FOR_P27(VALUE) \ 1385 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16) 1386 #define CONST_OK_FOR_P(VALUE, STR) \ 1387 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \ 1388 : 0) 1389 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1) 1390 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0) 1391 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \ 1392 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \ 1393 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \ 1394 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \ 1395 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \ 1396 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \ 1397 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \ 1398 : 0) 1399 1400 /* Similar, but for floating constants, and defining letters G and H. 1401 Here VALUE is the CONST_DOUBLE rtx itself. */ 1402 1403 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1404 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \ 1405 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \ 1406 : (C) == 'F') 1407 1408 /* Given an rtx X being reloaded into a reg required to be 1409 in class CLASS, return the class of reg to actually use. 1410 In general this is just CLASS; but on some machines 1411 in some cases it is preferable to use a more restrictive class. */ 1412 1413 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1414 ((CLASS) == NO_REGS && TARGET_SHMEDIA \ 1415 && (GET_CODE (X) == CONST_DOUBLE \ 1416 || GET_CODE (X) == SYMBOL_REF \ 1417 || PIC_DIRECT_ADDR_P (X)) \ 1418 ? GENERAL_REGS \ 1419 : (CLASS)) \ 1420 1421 #if 0 1422 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \ 1423 ((((REGCLASS_HAS_FP_REG (CLASS) \ 1424 && (GET_CODE (X) == REG \ 1425 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \ 1426 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \ 1427 && TARGET_FMOVD)))) \ 1428 || (REGCLASS_HAS_GENERAL_REG (CLASS) \ 1429 && GET_CODE (X) == REG \ 1430 && FP_REGISTER_P (REGNO (X)))) \ 1431 && ! TARGET_SHMEDIA \ 1432 && ((MODE) == SFmode || (MODE) == SImode)) \ 1433 ? FPUL_REGS \ 1434 : (((CLASS) == FPUL_REGS \ 1435 || (REGCLASS_HAS_FP_REG (CLASS) \ 1436 && ! TARGET_SHMEDIA && MODE == SImode)) \ 1437 && (GET_CODE (X) == MEM \ 1438 || (GET_CODE (X) == REG \ 1439 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1440 || REGNO (X) == T_REG \ 1441 || system_reg_operand (X, VOIDmode))))) \ 1442 ? GENERAL_REGS \ 1443 : (((CLASS) == TARGET_REGS \ 1444 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \ 1445 && !EXTRA_CONSTRAINT_Csy (X) \ 1446 && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \ 1447 ? GENERAL_REGS \ 1448 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \ 1449 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \ 1450 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \ 1451 ? GENERAL_REGS \ 1452 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \ 1453 && TARGET_REGISTER_P (REGNO (X))) \ 1454 ? GENERAL_REGS : (ELSE)) 1455 1456 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ 1457 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS) 1458 1459 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \ 1460 ((REGCLASS_HAS_FP_REG (CLASS) \ 1461 && ! TARGET_SHMEDIA \ 1462 && immediate_operand ((X), (MODE)) \ 1463 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \ 1464 && (MODE) == SFmode && fldi_ok ())) \ 1465 ? R0_REGS \ 1466 : ((CLASS) == FPUL_REGS \ 1467 && ((GET_CODE (X) == REG \ 1468 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \ 1469 || REGNO (X) == T_REG)) \ 1470 || GET_CODE (X) == PLUS)) \ 1471 ? GENERAL_REGS \ 1472 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \ 1473 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \ 1474 ? GENERAL_REGS \ 1475 : R0_REGS) \ 1476 : ((CLASS) == FPSCR_REGS \ 1477 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1478 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\ 1479 ? GENERAL_REGS \ 1480 : (REGCLASS_HAS_FP_REG (CLASS) \ 1481 && TARGET_SHMEDIA \ 1482 && immediate_operand ((X), (MODE)) \ 1483 && (X) != CONST0_RTX (GET_MODE (X)) \ 1484 && GET_MODE (X) != V4SFmode) \ 1485 ? GENERAL_REGS \ 1486 : (((MODE) == QImode || (MODE) == HImode) \ 1487 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \ 1488 ? GENERAL_REGS \ 1489 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \ 1490 && (GET_CODE (X) == LABEL_REF || PIC_DIRECT_ADDR_P (X))) \ 1491 ? TARGET_REGS \ 1492 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS)) 1493 #else 1494 #define HAVE_SECONDARY_RELOADS 1495 #endif 1496 1497 /* Return the maximum number of consecutive registers 1498 needed to represent mode MODE in a register of class CLASS. 1499 1500 If TARGET_SHMEDIA, we need two FP registers per word. 1501 Otherwise we will need at most one register per word. */ 1502 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1503 (TARGET_SHMEDIA \ 1504 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \ 1505 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \ 1506 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1507 1508 /* If defined, gives a class of registers that cannot be used as the 1509 operand of a SUBREG that changes the mode of the object illegally. */ 1510 /* ??? We need to renumber the internal numbers for the frnn registers 1511 when in little endian in order to allow mode size changes. */ 1512 1513 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1514 sh_cannot_change_mode_class (FROM, TO, CLASS) 1515 1516 /* Stack layout; function entry, exit and calling. */ 1517 1518 /* Define the number of registers that can hold parameters. 1519 These macros are used only in other macro definitions below. */ 1520 1521 #define NPARM_REGS(MODE) \ 1522 (TARGET_FPU_ANY && (MODE) == SFmode \ 1523 ? (TARGET_SH5 ? 12 : 8) \ 1524 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1525 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ 1526 ? (TARGET_SH5 ? 12 : 8) \ 1527 : (TARGET_SH5 ? 8 : 4)) 1528 1529 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4)) 1530 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0)) 1531 1532 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4)) 1533 #define FIRST_FP_RET_REG FIRST_FP_REG 1534 1535 /* Define this if pushing a word on the stack 1536 makes the stack pointer a smaller address. */ 1537 #define STACK_GROWS_DOWNWARD 1538 1539 /* Define this macro to nonzero if the addresses of local variable slots 1540 are at negative offsets from the frame pointer. */ 1541 #define FRAME_GROWS_DOWNWARD 1 1542 1543 /* Offset from the frame pointer to the first local variable slot to 1544 be allocated. */ 1545 #define STARTING_FRAME_OFFSET 0 1546 1547 /* If we generate an insn to push BYTES bytes, 1548 this says how many the stack pointer really advances by. */ 1549 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this. 1550 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to 1551 do correct alignment. */ 1552 #if 0 1553 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) 1554 #endif 1555 1556 /* Offset of first parameter from the argument pointer register value. */ 1557 #define FIRST_PARM_OFFSET(FNDECL) 0 1558 1559 /* Value is the number of byte of arguments automatically 1560 popped when returning from a subroutine call. 1561 FUNDECL is the declaration node of the function (as a tree), 1562 FUNTYPE is the data type of the function (as a tree), 1563 or for a library call it is an identifier node for the subroutine name. 1564 SIZE is the number of bytes of arguments passed on the stack. 1565 1566 On the SH, the caller does not pop any of its arguments that were passed 1567 on the stack. */ 1568 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1569 1570 /* Value is the number of bytes of arguments automatically popped when 1571 calling a subroutine. 1572 CUM is the accumulated argument list. 1573 1574 On SHcompact, the call trampoline pops arguments off the stack. */ 1575 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0) 1576 1577 /* Some subroutine macros specific to this machine. */ 1578 1579 #define BASE_RETURN_VALUE_REG(MODE) \ 1580 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \ 1581 ? FIRST_FP_RET_REG \ 1582 : TARGET_FPU_ANY && (MODE) == SCmode \ 1583 ? FIRST_FP_RET_REG \ 1584 : (TARGET_FPU_DOUBLE \ 1585 && ((MODE) == DFmode || (MODE) == SFmode \ 1586 || (MODE) == DCmode || (MODE) == SCmode )) \ 1587 ? FIRST_FP_RET_REG \ 1588 : FIRST_RET_REG) 1589 1590 #define BASE_ARG_REG(MODE) \ 1591 ((TARGET_SH2E && ((MODE) == SFmode)) \ 1592 ? FIRST_FP_PARM_REG \ 1593 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1594 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\ 1595 ? FIRST_FP_PARM_REG \ 1596 : FIRST_PARM_REG) 1597 1598 /* Define how to find the value returned by a function. 1599 VALTYPE is the data type of the value (as a tree). 1600 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1601 otherwise, FUNC is 0. 1602 For the SH, this is like LIBCALL_VALUE, except that we must change the 1603 mode like PROMOTE_MODE does. 1604 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types 1605 tested here has to be kept in sync with the one in explow.c:promote_mode. */ 1606 1607 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1608 gen_rtx_REG ( \ 1609 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \ 1610 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \ 1611 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \ 1612 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \ 1613 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \ 1614 || TREE_CODE (VALTYPE) == REAL_TYPE \ 1615 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \ 1616 && sh_promote_prototypes (VALTYPE) \ 1617 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \ 1618 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE))) 1619 1620 /* Define how to find the value returned by a library function 1621 assuming the value has mode MODE. */ 1622 #define LIBCALL_VALUE(MODE) \ 1623 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE)); 1624 1625 /* 1 if N is a possible register number for a function value. */ 1626 #define FUNCTION_VALUE_REGNO_P(REGNO) \ 1627 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \ 1628 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG)) 1629 1630 /* 1 if N is a possible register number for function argument passing. */ 1631 /* ??? There are some callers that pass REGNO as int, and others that pass 1632 it as unsigned. We get warnings unless we do casts everywhere. */ 1633 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1634 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \ 1635 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\ 1636 || (TARGET_FPU_ANY \ 1637 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \ 1638 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \ 1639 + NPARM_REGS (SFmode)))) 1640 1641 /* Define a data type for recording info about an argument list 1642 during the scan of that argument list. This data type should 1643 hold all necessary information about the function itself 1644 and about the args processed so far, enough to enable macros 1645 such as FUNCTION_ARG to determine where the next arg should go. 1646 1647 On SH, this is a single integer, which is a number of words 1648 of arguments scanned so far (including the invisible argument, 1649 if any, which holds the structure-value-address). 1650 Thus NARGREGS or more means all following args should go on the stack. */ 1651 1652 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 }; 1653 struct sh_args { 1654 int arg_count[2]; 1655 int force_mem; 1656 /* Nonzero if a prototype is available for the function. */ 1657 int prototype_p; 1658 /* The number of an odd floating-point register, that should be used 1659 for the next argument of type float. */ 1660 int free_single_fp_reg; 1661 /* Whether we're processing an outgoing function call. */ 1662 int outgoing; 1663 /* The number of general-purpose registers that should have been 1664 used to pass partial arguments, that are passed totally on the 1665 stack. On SHcompact, a call trampoline will pop them off the 1666 stack before calling the actual function, and, if the called 1667 function is implemented in SHcompact mode, the incoming arguments 1668 decoder will push such arguments back onto the stack. For 1669 incoming arguments, STACK_REGS also takes into account other 1670 arguments passed by reference, that the decoder will also push 1671 onto the stack. */ 1672 int stack_regs; 1673 /* The number of general-purpose registers that should have been 1674 used to pass arguments, if the arguments didn't have to be passed 1675 by reference. */ 1676 int byref_regs; 1677 /* Set as by shcompact_byref if the current argument is to be passed 1678 by reference. */ 1679 int byref; 1680 1681 /* call_cookie is a bitmask used by call expanders, as well as 1682 function prologue and epilogues, to allow SHcompact to comply 1683 with the SH5 32-bit ABI, that requires 64-bit registers to be 1684 used even though only the lower 32-bit half is visible in 1685 SHcompact mode. The strategy is to call SHmedia trampolines. 1686 1687 The alternatives for each of the argument-passing registers are 1688 (a) leave it unchanged; (b) pop it off the stack; (c) load its 1689 contents from the address in it; (d) add 8 to it, storing the 1690 result in the next register, then (c); (e) copy it from some 1691 floating-point register, 1692 1693 Regarding copies from floating-point registers, r2 may only be 1694 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe 1695 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2, 1696 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8. 1697 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or 1698 dr10. 1699 1700 The bit mask is structured as follows: 1701 1702 - 1 bit to tell whether to set up a return trampoline. 1703 1704 - 3 bits to count the number consecutive registers to pop off the 1705 stack. 1706 1707 - 4 bits for each of r9, r8, r7 and r6. 1708 1709 - 3 bits for each of r5, r4, r3 and r2. 1710 1711 - 3 bits set to 0 (the most significant ones) 1712 1713 3 2 1 0 1714 1098 7654 3210 9876 5432 1098 7654 3210 1715 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST 1716 2223 3344 4555 6666 7777 8888 9999 SSS- 1717 1718 - If F is set, the register must be copied from an FP register, 1719 whose number is encoded in the remaining bits. 1720 1721 - Else, if L is set, the register must be loaded from the address 1722 contained in it. If the P bit is *not* set, the address of the 1723 following dword should be computed first, and stored in the 1724 following register. 1725 1726 - Else, if P is set, the register alone should be popped off the 1727 stack. 1728 1729 - After all this processing, the number of registers represented 1730 in SSS will be popped off the stack. This is an optimization 1731 for pushing/popping consecutive registers, typically used for 1732 varargs and large arguments partially passed in registers. 1733 1734 - If T is set, a return trampoline will be set up for 64-bit 1735 return values to be split into 2 32-bit registers. */ 1736 #define CALL_COOKIE_RET_TRAMP_SHIFT 0 1737 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT) 1738 #define CALL_COOKIE_STACKSEQ_SHIFT 1 1739 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT) 1740 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \ 1741 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7) 1742 #define CALL_COOKIE_INT_REG_SHIFT(REG) \ 1743 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3) 1744 #define CALL_COOKIE_INT_REG(REG, VAL) \ 1745 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG)) 1746 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \ 1747 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15)) 1748 long call_cookie; 1749 1750 /* This is set to nonzero when the call in question must use the Renesas ABI, 1751 even without the -mrenesas option. */ 1752 int renesas_abi; 1753 }; 1754 1755 #define CUMULATIVE_ARGS struct sh_args 1756 1757 #define GET_SH_ARG_CLASS(MODE) \ 1758 ((TARGET_FPU_ANY && (MODE) == SFmode) \ 1759 ? SH_ARG_FLOAT \ 1760 /* There's no mention of complex float types in the SH5 ABI, so we 1761 should presumably handle them as aggregate types. */ \ 1762 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \ 1763 ? SH_ARG_INT \ 1764 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1765 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ 1766 ? SH_ARG_FLOAT : SH_ARG_INT) 1767 1768 #define ROUND_ADVANCE(SIZE) \ 1769 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1770 1771 /* Round a register number up to a proper boundary for an arg of mode 1772 MODE. 1773 1774 The SH doesn't care about double alignment, so we only 1775 round doubles to even regs when asked to explicitly. */ 1776 1777 #define ROUND_REG(CUM, MODE) \ 1778 (((TARGET_ALIGN_DOUBLE \ 1779 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \ 1780 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\ 1781 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \ 1782 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \ 1783 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \ 1784 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)]) 1785 1786 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1787 for a call to a function whose data type is FNTYPE. 1788 For a library call, FNTYPE is 0. 1789 1790 On SH, the offset always starts at 0: the first parm reg is always 1791 the same reg for a given argument class. 1792 1793 For TARGET_HITACHI, the structure value pointer is passed in memory. */ 1794 1795 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1796 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode) 1797 1798 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1799 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE)) 1800 1801 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1802 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1803 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1804 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1805 1806 /* Return boolean indicating arg of mode MODE will be passed in a reg. 1807 This macro is only used in this file. */ 1808 1809 #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 1810 (((TYPE) == 0 \ 1811 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \ 1812 && (! (TARGET_HITACHI || (CUM).renesas_abi) \ 1813 || ! (AGGREGATE_TYPE_P (TYPE) \ 1814 || (!TARGET_FPU_ANY \ 1815 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1816 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \ 1817 && ! (CUM).force_mem \ 1818 && (TARGET_SH2E \ 1819 ? ((MODE) == BLKmode \ 1820 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \ 1821 + int_size_in_bytes (TYPE)) \ 1822 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \ 1823 : ((ROUND_REG((CUM), (MODE)) \ 1824 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \ 1825 <= NPARM_REGS (MODE))) \ 1826 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE))) 1827 1828 /* By accident we got stuck with passing SCmode on SH4 little endian 1829 in two registers that are nominally successive - which is different from 1830 two single SFmode values, where we take endianness translation into 1831 account. That does not work at all if an odd number of registers is 1832 already in use, so that got fixed, but library functions are still more 1833 likely to use complex numbers without mixing them with SFmode arguments 1834 (which in C would have to be structures), so for the sake of ABI 1835 compatibility the way SCmode values are passed when an even number of 1836 FP registers is in use remains different from a pair of SFmode values for 1837 now. 1838 I.e.: 1839 foo (double); a: fr5,fr4 1840 foo (float a, float b); a: fr5 b: fr4 1841 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency, 1842 this should be the other way round... 1843 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */ 1844 #define FUNCTION_ARG_SCmode_WART 1 1845 1846 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit 1847 register in SHcompact mode, it must be padded in the most 1848 significant end. This means that passing it by reference wouldn't 1849 pad properly on a big-endian machine. In this particular case, we 1850 pass this argument on the stack, in a way that the call trampoline 1851 will load its value into the appropriate register. */ 1852 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \ 1853 ((MODE) == BLKmode \ 1854 && TARGET_SHCOMPACT \ 1855 && ! TARGET_LITTLE_ENDIAN \ 1856 && int_size_in_bytes (TYPE) > 4 \ 1857 && int_size_in_bytes (TYPE) < 8) 1858 1859 /* Minimum alignment for an argument to be passed by callee-copy 1860 reference. We need such arguments to be aligned to 8 byte 1861 boundaries, because they'll be loaded using quad loads. */ 1862 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT) 1863 1864 /* The SH5 ABI requires floating-point arguments to be passed to 1865 functions without a prototype in both an FP register and a regular 1866 register or the stack. When passing the argument in both FP and 1867 general-purpose registers, list the FP register first. */ 1868 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \ 1869 (gen_rtx_PARALLEL \ 1870 ((MODE), \ 1871 gen_rtvec (2, \ 1872 gen_rtx_EXPR_LIST \ 1873 (VOIDmode, \ 1874 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ 1875 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \ 1876 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \ 1877 : NULL_RTX), \ 1878 const0_rtx), \ 1879 gen_rtx_EXPR_LIST \ 1880 (VOIDmode, \ 1881 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ 1882 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \ 1883 + (CUM).arg_count[(int) SH_ARG_INT]) \ 1884 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \ 1885 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \ 1886 const0_rtx)))) 1887 1888 /* The SH5 ABI requires regular registers or stack slots to be 1889 reserved for floating-point arguments. Registers are taken care of 1890 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here. 1891 Unfortunately, there's no way to just reserve a stack slot, so 1892 we'll end up needlessly storing a copy of the argument in the 1893 stack. For incoming arguments, however, the PARALLEL will be 1894 optimized to the register-only form, and the value in the stack 1895 slot won't be used at all. */ 1896 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \ 1897 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ 1898 ? gen_rtx_REG ((MODE), (REG)) \ 1899 : gen_rtx_PARALLEL ((MODE), \ 1900 gen_rtvec (2, \ 1901 gen_rtx_EXPR_LIST \ 1902 (VOIDmode, NULL_RTX, \ 1903 const0_rtx), \ 1904 gen_rtx_EXPR_LIST \ 1905 (VOIDmode, gen_rtx_REG ((MODE), \ 1906 (REG)), \ 1907 const0_rtx)))) 1908 1909 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1910 (TARGET_SH5 \ 1911 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \ 1912 || (MODE) == DCmode) \ 1913 && ((CUM).arg_count[(int) SH_ARG_INT] \ 1914 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \ 1915 : GET_MODE_SIZE (MODE)) \ 1916 + 7) / 8) > NPARM_REGS (SImode)) 1917 1918 /* Perform any needed actions needed for a function that is receiving a 1919 variable number of arguments. */ 1920 1921 /* Implement `va_start' for varargs and stdarg. */ 1922 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 1923 sh_va_start (valist, nextarg) 1924 1925 /* Call the function profiler with a given profile label. 1926 We use two .aligns, so as to make sure that both the .long is aligned 1927 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes) 1928 from the trapa instruction. */ 1929 1930 #define FUNCTION_PROFILER(STREAM,LABELNO) \ 1931 { \ 1932 if (TARGET_SHMEDIA) \ 1933 { \ 1934 fprintf((STREAM), "\tmovi\t33,r0\n"); \ 1935 fprintf((STREAM), "\ttrapa\tr0\n"); \ 1936 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ 1937 } \ 1938 else \ 1939 { \ 1940 fprintf((STREAM), "\t.align\t2\n"); \ 1941 fprintf((STREAM), "\ttrapa\t#33\n"); \ 1942 fprintf((STREAM), "\t.align\t2\n"); \ 1943 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ 1944 } \ 1945 } 1946 1947 /* Define this macro if the code for function profiling should come 1948 before the function prologue. Normally, the profiling code comes 1949 after. */ 1950 1951 #define PROFILE_BEFORE_PROLOGUE 1952 1953 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1954 the stack pointer does not matter. The value is tested only in 1955 functions that have frame pointers. 1956 No definition is equivalent to always zero. */ 1957 1958 #define EXIT_IGNORE_STACK 1 1959 1960 /* 1961 On the SH, the trampoline looks like 1962 2 0002 D202 mov.l l2,r2 1963 1 0000 D301 mov.l l1,r3 1964 3 0004 422B jmp @r2 1965 4 0006 0009 nop 1966 5 0008 00000000 l1: .long area 1967 6 000c 00000000 l2: .long function */ 1968 1969 /* Length in units of the trampoline for entering a nested function. */ 1970 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16) 1971 1972 /* Alignment required for a trampoline in bits . */ 1973 #define TRAMPOLINE_ALIGNMENT \ 1974 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \ 1975 : TARGET_SHMEDIA ? 256 : 64) 1976 1977 /* Emit RTL insns to initialize the variable parts of a trampoline. 1978 FNADDR is an RTX for the address of the function's pure code. 1979 CXT is an RTX for the static chain value for the function. */ 1980 1981 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1982 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1983 1984 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */ 1985 1986 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \ 1987 { \ 1988 if (TARGET_SHMEDIA) \ 1989 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \ 1990 gen_reg_rtx (Pmode), 0, \ 1991 OPTAB_LIB_WIDEN); \ 1992 } while (0) 1993 1994 /* A C expression whose value is RTL representing the value of the return 1995 address for the frame COUNT steps up from the current frame. 1996 FRAMEADDR is already the frame pointer of the COUNT frame, so we 1997 can ignore COUNT. */ 1998 1999 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2000 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0) 2001 2002 /* A C expression whose value is RTL representing the location of the 2003 incoming return address at the beginning of any function, before the 2004 prologue. This RTL is either a REG, indicating that the return 2005 value is saved in REG, or a MEM representing a location in 2006 the stack. */ 2007 #define INCOMING_RETURN_ADDR_RTX \ 2008 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) 2009 2010 /* Addressing modes, and classification of registers for them. */ 2011 #define HAVE_POST_INCREMENT TARGET_SH1 2012 #define HAVE_PRE_DECREMENT TARGET_SH1 2013 2014 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \ 2015 ? 0 : TARGET_SH1) 2016 #define USE_LOAD_PRE_DECREMENT(mode) 0 2017 #define USE_STORE_POST_INCREMENT(mode) 0 2018 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \ 2019 ? 0 : TARGET_SH1) 2020 2021 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ 2022 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \ 2023 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2))) 2024 2025 #define STORE_BY_PIECES_P(SIZE, ALIGN) \ 2026 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \ 2027 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2))) 2028 2029 /* Macros to check register numbers against specific register classes. */ 2030 2031 /* These assume that REGNO is a hard or pseudo reg number. 2032 They give nonzero only if REGNO is a hard reg of the suitable class 2033 or a pseudo reg currently allocated to a suitable hard reg. 2034 Since they use reg_renumber, they are safe only once reg_renumber 2035 has been allocated, which happens in local-alloc.c. */ 2036 2037 #define REGNO_OK_FOR_BASE_P(REGNO) \ 2038 (GENERAL_OR_AP_REGISTER_P (REGNO) \ 2039 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)])) 2040 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 2041 (TARGET_SHMEDIA \ 2042 ? (GENERAL_REGISTER_P (REGNO) \ 2043 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \ 2044 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG) 2045 2046 /* Maximum number of registers that can appear in a valid memory 2047 address. */ 2048 2049 #define MAX_REGS_PER_ADDRESS 2 2050 2051 /* Recognize any constant value that is a valid address. */ 2052 2053 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) 2054 2055 /* Nonzero if the constant value X is a legitimate general operand. */ 2056 2057 #define LEGITIMATE_CONSTANT_P(X) \ 2058 (TARGET_SHMEDIA \ 2059 ? ((GET_MODE (X) != DFmode \ 2060 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \ 2061 || (X) == CONST0_RTX (GET_MODE (X)) \ 2062 || ! TARGET_SHMEDIA_FPU \ 2063 || TARGET_SHMEDIA64) \ 2064 : (GET_CODE (X) != CONST_DOUBLE \ 2065 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \ 2066 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X))))) 2067 2068 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2069 and check its validity for a certain class. 2070 We have two alternate definitions for each of them. 2071 The usual definition accepts all pseudo regs; the other rejects 2072 them unless they have been allocated suitable hard regs. 2073 The symbol REG_OK_STRICT causes the latter definition to be used. */ 2074 2075 #ifndef REG_OK_STRICT 2076 2077 /* Nonzero if X is a hard reg that can be used as a base reg 2078 or if it is a pseudo reg. */ 2079 #define REG_OK_FOR_BASE_P(X) \ 2080 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER) 2081 2082 /* Nonzero if X is a hard reg that can be used as an index 2083 or if it is a pseudo reg. */ 2084 #define REG_OK_FOR_INDEX_P(X) \ 2085 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \ 2086 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER) 2087 2088 /* Nonzero if X/OFFSET is a hard reg that can be used as an index 2089 or if X is a pseudo reg. */ 2090 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \ 2091 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \ 2092 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER) 2093 2094 #else 2095 2096 /* Nonzero if X is a hard reg that can be used as a base reg. */ 2097 #define REG_OK_FOR_BASE_P(X) \ 2098 REGNO_OK_FOR_BASE_P (REGNO (X)) 2099 2100 /* Nonzero if X is a hard reg that can be used as an index. */ 2101 #define REG_OK_FOR_INDEX_P(X) \ 2102 REGNO_OK_FOR_INDEX_P (REGNO (X)) 2103 2104 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */ 2105 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \ 2106 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0) 2107 2108 #endif 2109 2110 /* The 'Q' constraint is a pc relative load operand. */ 2111 #define EXTRA_CONSTRAINT_Q(OP) \ 2112 (GET_CODE (OP) == MEM \ 2113 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \ 2114 || (GET_CODE (XEXP ((OP), 0)) == CONST \ 2115 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \ 2116 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \ 2117 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT))) 2118 2119 /* Extra address constraints. */ 2120 #define EXTRA_CONSTRAINT_A(OP, STR) 0 2121 2122 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber 2123 operand is not SCRATCH (i.e. REG) then R0 is probably being 2124 used, hence mova is being used, hence do not select this pattern */ 2125 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH) 2126 #define EXTRA_CONSTRAINT_B(OP, STR) \ 2127 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \ 2128 : 0) 2129 2130 /* The `Css' constraint is a signed 16-bit constant, literal or symbolic. */ 2131 #define EXTRA_CONSTRAINT_Css(OP) \ 2132 (GET_CODE (OP) == CONST \ 2133 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \ 2134 && (GET_MODE (XEXP ((OP), 0)) == DImode \ 2135 || GET_MODE (XEXP ((OP), 0)) == SImode) \ 2136 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \ 2137 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \ 2138 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \ 2139 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \ 2140 && (MOVI_SHORI_BASE_OPERAND_P \ 2141 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \ 2142 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \ 2143 1)) == CONST_INT))) 2144 2145 /* The `Csu' constraint is an unsigned 16-bit constant, literal or symbolic. */ 2146 #define EXTRA_CONSTRAINT_Csu(OP) \ 2147 (GET_CODE (OP) == CONST \ 2148 && GET_CODE (XEXP ((OP), 0)) == ZERO_EXTEND \ 2149 && (GET_MODE (XEXP ((OP), 0)) == DImode \ 2150 || GET_MODE (XEXP ((OP), 0)) == SImode) \ 2151 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \ 2152 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \ 2153 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \ 2154 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \ 2155 && (MOVI_SHORI_BASE_OPERAND_P \ 2156 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \ 2157 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \ 2158 1)) == CONST_INT))) 2159 2160 /* Check whether OP is a datalabel unspec. */ 2161 #define DATALABEL_REF_NO_CONST_P(OP) \ 2162 (GET_CODE (OP) == UNSPEC \ 2163 && XINT ((OP), 1) == UNSPEC_DATALABEL \ 2164 && XVECLEN ((OP), 0) == 1 \ 2165 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF) 2166 2167 #define GOT_ENTRY_P(OP) \ 2168 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ 2169 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT) 2170 2171 #define GOTPLT_ENTRY_P(OP) \ 2172 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ 2173 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT) 2174 2175 #define UNSPEC_GOTOFF_P(OP) \ 2176 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF) 2177 2178 #define GOTOFF_P(OP) \ 2179 (GET_CODE (OP) == CONST \ 2180 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \ 2181 || (GET_CODE (XEXP ((OP), 0)) == PLUS \ 2182 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \ 2183 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))) 2184 2185 #define PIC_ADDR_P(OP) \ 2186 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ 2187 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC) 2188 2189 #define PIC_OFFSET_P(OP) \ 2190 (PIC_ADDR_P (OP) \ 2191 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \ 2192 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1))) 2193 2194 #define PIC_DIRECT_ADDR_P(OP) \ 2195 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS) 2196 2197 #define NON_PIC_REFERENCE_P(OP) \ 2198 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \ 2199 || (GET_CODE (OP) == CONST \ 2200 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \ 2201 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \ 2202 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \ 2203 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \ 2204 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \ 2205 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \ 2206 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \ 2207 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)) 2208 2209 #define PIC_REFERENCE_P(OP) \ 2210 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \ 2211 || GOTOFF_P (OP) || PIC_ADDR_P (OP)) 2212 2213 #define MOVI_SHORI_BASE_OPERAND_P(OP) \ 2214 (flag_pic \ 2215 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \ 2216 || PIC_OFFSET_P (OP)) \ 2217 : NON_PIC_REFERENCE_P (OP)) 2218 2219 /* The `Csy' constraint is a label or a symbol. */ 2220 #define EXTRA_CONSTRAINT_Csy(OP) \ 2221 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP)) 2222 2223 /* A zero in any shape or form. */ 2224 #define EXTRA_CONSTRAINT_Z(OP) \ 2225 ((OP) == CONST0_RTX (GET_MODE (OP))) 2226 2227 /* Any vector constant we can handle. */ 2228 #define EXTRA_CONSTRAINT_W(OP) \ 2229 (GET_CODE (OP) == CONST_VECTOR \ 2230 && (sh_rep_vec ((OP), VOIDmode) \ 2231 || (HOST_BITS_PER_WIDE_INT >= 64 \ 2232 ? sh_const_vec ((OP), VOIDmode) \ 2233 : sh_1el_vec ((OP), VOIDmode)))) 2234 2235 /* A non-explicit constant that can be loaded directly into a general purpose 2236 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */ 2237 #define EXTRA_CONSTRAINT_Cpg(OP) \ 2238 (CONSTANT_P (OP) \ 2239 && GET_CODE (OP) != CONST_INT \ 2240 && GET_CODE (OP) != CONST_DOUBLE \ 2241 && (!flag_pic \ 2242 || (LEGITIMATE_PIC_OPERAND_P (OP) \ 2243 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \ 2244 && GET_CODE (OP) != LABEL_REF))) 2245 #define EXTRA_CONSTRAINT_C(OP, STR) \ 2246 ((STR)[1] == 's' && (STR)[2] == 's' ? EXTRA_CONSTRAINT_Css (OP) \ 2247 : (STR)[1] == 's' && (STR)[2] == 'u' ? EXTRA_CONSTRAINT_Csu (OP) \ 2248 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \ 2249 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \ 2250 : 0) 2251 2252 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S') 2253 #define EXTRA_CONSTRAINT_Sr0(OP) \ 2254 (memory_operand((OP), GET_MODE (OP)) \ 2255 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0)) 2256 #define EXTRA_CONSTRAINT_Sua(OP) \ 2257 (memory_operand((OP), GET_MODE (OP)) \ 2258 && GET_CODE (XEXP (OP, 0)) != PLUS) 2259 #define EXTRA_CONSTRAINT_S(OP, STR) \ 2260 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \ 2261 : (STR)[1] == 'u' && (STR)[2] == 'a' ? EXTRA_CONSTRAINT_Sua (OP) \ 2262 : 0) 2263 2264 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \ 2265 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \ 2266 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \ 2267 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \ 2268 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \ 2269 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \ 2270 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \ 2271 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \ 2272 : 0) 2273 2274 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 2275 that is a valid memory address for an instruction. 2276 The MODE argument is the machine mode for the MEM expression 2277 that wants to use this address. */ 2278 2279 #define MODE_DISP_OK_4(X,MODE) \ 2280 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \ 2281 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) 2282 2283 #define MODE_DISP_OK_8(X,MODE) \ 2284 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \ 2285 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode)) 2286 2287 #undef MODE_DISP_OK_4 2288 #define MODE_DISP_OK_4(X,MODE) \ 2289 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \ 2290 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \ 2291 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \ 2292 && ! (INTVAL(X) & 3) && TARGET_SH2A)) 2293 2294 #undef MODE_DISP_OK_8 2295 #define MODE_DISP_OK_8(X,MODE) \ 2296 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \ 2297 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \ 2298 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \ 2299 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode))) 2300 2301 #define BASE_REGISTER_RTX_P(X) \ 2302 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 2303 || (GET_CODE (X) == SUBREG \ 2304 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \ 2305 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \ 2306 && GET_CODE (SUBREG_REG (X)) == REG \ 2307 && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 2308 2309 /* Since this must be r0, which is a single register class, we must check 2310 SUBREGs more carefully, to be sure that we don't accept one that extends 2311 outside the class. */ 2312 #define INDEX_REGISTER_RTX_P(X) \ 2313 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 2314 || (GET_CODE (X) == SUBREG \ 2315 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \ 2316 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \ 2317 && GET_CODE (SUBREG_REG (X)) == REG \ 2318 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X)))) 2319 2320 /* Jump to LABEL if X is a valid address RTX. This must also take 2321 REG_OK_STRICT into account when deciding about valid registers, but it uses 2322 the above macros so we are in luck. 2323 2324 Allow REG 2325 REG+disp 2326 REG+r0 2327 REG++ 2328 --REG */ 2329 2330 /* ??? The SH2e does not have the REG+disp addressing mode when loading values 2331 into the FRx registers. We implement this by setting the maximum offset 2332 to zero when the value is SFmode. This also restricts loading of SFmode 2333 values into the integer registers, but that can't be helped. */ 2334 2335 /* The SH allows a displacement in a QI or HI amode, but only when the 2336 other operand is R0. GCC doesn't handle this very well, so we forgo 2337 all of that. 2338 2339 A legitimate index for a QI or HI is 0, SI can be any number 0..63, 2340 DI can be any number 0..60. */ 2341 2342 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \ 2343 do { \ 2344 if (GET_CODE (OP) == CONST_INT) \ 2345 { \ 2346 if (TARGET_SHMEDIA) \ 2347 { \ 2348 int MODE_SIZE; \ 2349 /* Check if this the address of an unaligned load / store. */\ 2350 if ((MODE) == VOIDmode) \ 2351 { \ 2352 if (CONST_OK_FOR_I06 (INTVAL (OP))) \ 2353 goto LABEL; \ 2354 break; \ 2355 } \ 2356 MODE_SIZE = GET_MODE_SIZE (MODE); \ 2357 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \ 2358 && INTVAL (OP) >= -512 * MODE_SIZE \ 2359 && INTVAL (OP) < 512 * MODE_SIZE) \ 2360 goto LABEL; \ 2361 else \ 2362 break; \ 2363 } \ 2364 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \ 2365 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \ 2366 } \ 2367 } while(0) 2368 2369 #define ALLOW_INDEXED_ADDRESS \ 2370 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS) 2371 2372 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ 2373 { \ 2374 if (BASE_REGISTER_RTX_P (X)) \ 2375 goto LABEL; \ 2376 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ 2377 && ! TARGET_SHMEDIA \ 2378 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \ 2379 goto LABEL; \ 2380 else if (GET_CODE (X) == PLUS \ 2381 && ((MODE) != PSImode || reload_completed)) \ 2382 { \ 2383 rtx xop0 = XEXP ((X), 0); \ 2384 rtx xop1 = XEXP ((X), 1); \ 2385 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \ 2386 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \ 2387 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode \ 2388 || ((xop0 == stack_pointer_rtx \ 2389 || xop0 == hard_frame_pointer_rtx) \ 2390 && REG_P (xop1) && REGNO (xop1) == R0_REG) \ 2391 || ((xop1 == stack_pointer_rtx \ 2392 || xop1 == hard_frame_pointer_rtx) \ 2393 && REG_P (xop0) && REGNO (xop0) == R0_REG)) \ 2394 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4) \ 2395 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \ 2396 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \ 2397 && TARGET_FMOVD && MODE == DFmode))) \ 2398 { \ 2399 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\ 2400 goto LABEL; \ 2401 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\ 2402 goto LABEL; \ 2403 } \ 2404 } \ 2405 } 2406 2407 /* Try machine-dependent ways of modifying an illegitimate address 2408 to be legitimate. If we find one, return the new, valid address. 2409 This macro is used in only one place: `memory_address' in explow.c. 2410 2411 OLDX is the address as it was before break_out_memory_refs was called. 2412 In some cases it is useful to look at this to decide what needs to be done. 2413 2414 MODE and WIN are passed so that this macro can use 2415 GO_IF_LEGITIMATE_ADDRESS. 2416 2417 It is always safe for this macro to do nothing. It exists to recognize 2418 opportunities to optimize the output. 2419 2420 For the SH, if X is almost suitable for indexing, but the offset is 2421 out of range, convert it into a normal form so that cse has a chance 2422 of reducing the number of address registers used. */ 2423 2424 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 2425 { \ 2426 if (flag_pic) \ 2427 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \ 2428 if (GET_CODE (X) == PLUS \ 2429 && (GET_MODE_SIZE (MODE) == 4 \ 2430 || GET_MODE_SIZE (MODE) == 8) \ 2431 && GET_CODE (XEXP ((X), 1)) == CONST_INT \ 2432 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \ 2433 && ! TARGET_SHMEDIA \ 2434 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \ 2435 && ! (TARGET_SH2E && (MODE) == SFmode)) \ 2436 { \ 2437 rtx index_rtx = XEXP ((X), 1); \ 2438 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \ 2439 rtx sum; \ 2440 \ 2441 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \ 2442 /* On rare occasions, we might get an unaligned pointer \ 2443 that is indexed in a way to give an aligned address. \ 2444 Therefore, keep the lower two bits in offset_base. */ \ 2445 /* Instead of offset_base 128..131 use 124..127, so that \ 2446 simple add suffices. */ \ 2447 if (offset > 127) \ 2448 { \ 2449 offset_base = ((offset + 4) & ~60) - 4; \ 2450 } \ 2451 else \ 2452 offset_base = offset & ~60; \ 2453 /* Sometimes the normal form does not suit DImode. We \ 2454 could avoid that by using smaller ranges, but that \ 2455 would give less optimized code when SImode is \ 2456 prevalent. */ \ 2457 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \ 2458 { \ 2459 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \ 2460 GEN_INT (offset_base), NULL_RTX, 0, \ 2461 OPTAB_LIB_WIDEN); \ 2462 \ 2463 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \ 2464 goto WIN; \ 2465 } \ 2466 } \ 2467 } 2468 2469 /* A C compound statement that attempts to replace X, which is an address 2470 that needs reloading, with a valid memory address for an operand of 2471 mode MODE. WIN is a C statement label elsewhere in the code. 2472 2473 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form 2474 of the address. That will allow inheritance of the address reloads. */ 2475 2476 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 2477 { \ 2478 if (GET_CODE (X) == PLUS \ 2479 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \ 2480 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 2481 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \ 2482 && ! TARGET_SHMEDIA \ 2483 && ! (TARGET_SH4 && (MODE) == DFmode) \ 2484 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \ 2485 && (ALLOW_INDEXED_ADDRESS \ 2486 || XEXP ((X), 0) == stack_pointer_rtx \ 2487 || XEXP ((X), 0) == hard_frame_pointer_rtx)) \ 2488 { \ 2489 rtx index_rtx = XEXP (X, 1); \ 2490 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \ 2491 rtx sum; \ 2492 \ 2493 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \ 2494 { \ 2495 push_reload (X, NULL_RTX, &X, NULL, \ 2496 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \ 2497 (TYPE)); \ 2498 goto WIN; \ 2499 } \ 2500 if (TARGET_SH2E && MODE == SFmode) \ 2501 { \ 2502 X = copy_rtx (X); \ 2503 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \ 2504 R0_REGS, Pmode, VOIDmode, 0, 0, (OPNUM), \ 2505 (TYPE)); \ 2506 goto WIN; \ 2507 } \ 2508 /* Instead of offset_base 128..131 use 124..127, so that \ 2509 simple add suffices. */ \ 2510 if (offset > 127) \ 2511 { \ 2512 offset_base = ((offset + 4) & ~60) - 4; \ 2513 } \ 2514 else \ 2515 offset_base = offset & ~60; \ 2516 /* Sometimes the normal form does not suit DImode. We \ 2517 could avoid that by using smaller ranges, but that \ 2518 would give less optimized code when SImode is \ 2519 prevalent. */ \ 2520 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \ 2521 { \ 2522 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \ 2523 GEN_INT (offset_base)); \ 2524 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\ 2525 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \ 2526 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \ 2527 (TYPE)); \ 2528 goto WIN; \ 2529 } \ 2530 } \ 2531 /* We must re-recognize what we created before. */ \ 2532 else if (GET_CODE (X) == PLUS \ 2533 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \ 2534 && GET_CODE (XEXP (X, 0)) == PLUS \ 2535 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ 2536 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \ 2537 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 2538 && ! TARGET_SHMEDIA \ 2539 && ! (TARGET_SH2E && MODE == SFmode)) \ 2540 { \ 2541 /* Because this address is so complex, we know it must have \ 2542 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \ 2543 it is already unshared, and needs no further unsharing. */ \ 2544 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \ 2545 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\ 2546 goto WIN; \ 2547 } \ 2548 } 2549 2550 /* Go to LABEL if ADDR (a legitimate address expression) 2551 has an effect that depends on the machine mode it is used for. 2552 2553 ??? Strictly speaking, we should also include all indexed addressing, 2554 because the index scale factor is the length of the operand. 2555 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to 2556 high if we did that. So we rely on reload to fix things up. */ 2557 2558 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 2559 { \ 2560 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \ 2561 goto LABEL; \ 2562 } 2563 2564 /* Specify the machine mode that this machine uses 2565 for the index in the tablejump instruction. */ 2566 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode) 2567 2568 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \ 2569 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \ 2570 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \ 2571 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \ 2572 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \ 2573 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \ 2574 : SImode) 2575 2576 /* Define as C expression which evaluates to nonzero if the tablejump 2577 instruction expects the table to contain offsets from the address of the 2578 table. 2579 Do not define this if the table should contain absolute addresses. */ 2580 #define CASE_VECTOR_PC_RELATIVE 1 2581 2582 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */ 2583 #define FLOAT_TYPE_SIZE 32 2584 2585 /* Since the SH2e has only `float' support, it is desirable to make all 2586 floating point types equivalent to `float'. */ 2587 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64) 2588 2589 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH4_SINGLE_ONLY__) 2590 #define LIBGCC2_DOUBLE_TYPE_SIZE 32 2591 #else 2592 #define LIBGCC2_DOUBLE_TYPE_SIZE 64 2593 #endif 2594 2595 /* 'char' is signed by default. */ 2596 #define DEFAULT_SIGNED_CHAR 1 2597 2598 /* The type of size_t unsigned int. */ 2599 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int") 2600 2601 #undef PTRDIFF_TYPE 2602 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int") 2603 2604 #define WCHAR_TYPE "short unsigned int" 2605 #define WCHAR_TYPE_SIZE 16 2606 2607 #define SH_ELF_WCHAR_TYPE "long int" 2608 2609 /* Max number of bytes we can move from memory to memory 2610 in one reasonably fast instruction. */ 2611 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4) 2612 2613 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever 2614 MOVE_MAX is not a compile-time constant. */ 2615 #define MAX_MOVE_MAX 8 2616 2617 /* Max number of bytes we want move_by_pieces to be able to copy 2618 efficiently. */ 2619 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4) 2620 2621 /* Define if operations between registers always perform the operation 2622 on the full register even if a narrower mode is specified. */ 2623 #define WORD_REGISTER_OPERATIONS 2624 2625 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2626 will either zero-extend or sign-extend. The value of this macro should 2627 be the code that says which one of the two operations is implicitly 2628 done, UNKNOWN if none. */ 2629 /* For SHmedia, we can truncate to QImode easier using zero extension. */ 2630 /* FP registers can load SImode values, but don't implicitly sign-extend 2631 them to DImode. */ 2632 #define LOAD_EXTEND_OP(MODE) \ 2633 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \ 2634 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN) 2635 2636 /* Define if loading short immediate values into registers sign extends. */ 2637 #define SHORT_IMMEDIATES_SIGN_EXTEND 2638 2639 /* Nonzero if access to memory by bytes is no faster than for words. */ 2640 #define SLOW_BYTE_ACCESS 1 2641 2642 /* Immediate shift counts are truncated by the output routines (or was it 2643 the assembler?). Shift counts in a register are truncated by SH. Note 2644 that the native compiler puts too large (> 32) immediate shift counts 2645 into a register and shifts by the register, letting the SH decide what 2646 to do instead of doing that itself. */ 2647 /* ??? The library routines in lib1funcs.asm truncate the shift count. 2648 However, the SH3 has hardware shifts that do not truncate exactly as gcc 2649 expects - the sign bit is significant - so it appears that we need to 2650 leave this zero for correct SH3 code. */ 2651 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A) 2652 2653 /* All integers have the same format so truncation is easy. */ 2654 /* But SHmedia must sign-extend DImode when truncating to SImode. */ 2655 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \ 2656 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64) 2657 2658 /* Define this if addresses of constant functions 2659 shouldn't be put through pseudo regs where they can be cse'd. 2660 Desirable on machines where ordinary constants are expensive 2661 but a CALL with constant address is cheap. */ 2662 /*#define NO_FUNCTION_CSE 1*/ 2663 2664 /* The machine modes of pointers and functions. */ 2665 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode) 2666 #define FUNCTION_MODE Pmode 2667 2668 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2 2669 are actually function calls with some special constraints on arguments 2670 and register usage. 2671 2672 These macros tell reorg that the references to arguments and 2673 register clobbers for insns of type sfunc do not appear to happen 2674 until after the millicode call. This allows reorg to put insns 2675 which set the argument registers into the delay slot of the millicode 2676 call -- thus they act more like traditional CALL_INSNs. 2677 2678 get_attr_is_sfunc will try to recognize the given insn, so make sure to 2679 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns 2680 in particular. */ 2681 2682 #define INSN_SETS_ARE_DELAYED(X) \ 2683 ((GET_CODE (X) == INSN \ 2684 && GET_CODE (PATTERN (X)) != SEQUENCE \ 2685 && GET_CODE (PATTERN (X)) != USE \ 2686 && GET_CODE (PATTERN (X)) != CLOBBER \ 2687 && get_attr_is_sfunc (X))) 2688 2689 #define INSN_REFERENCES_ARE_DELAYED(X) \ 2690 ((GET_CODE (X) == INSN \ 2691 && GET_CODE (PATTERN (X)) != SEQUENCE \ 2692 && GET_CODE (PATTERN (X)) != USE \ 2693 && GET_CODE (PATTERN (X)) != CLOBBER \ 2694 && get_attr_is_sfunc (X))) 2695 2696 2697 /* Position Independent Code. */ 2698 2699 /* We can't directly access anything that contains a symbol, 2700 nor can we indirect via the constant pool. */ 2701 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2702 ((! nonpic_symbol_mentioned_p (X) \ 2703 && (GET_CODE (X) != SYMBOL_REF \ 2704 || ! CONSTANT_POOL_ADDRESS_P (X) \ 2705 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \ 2706 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF)) 2707 2708 #define SYMBOLIC_CONST_P(X) \ 2709 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \ 2710 && nonpic_symbol_mentioned_p (X)) 2711 2712 /* Compute extra cost of moving data between one register class 2713 and another. */ 2714 2715 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass 2716 uses this information. Hence, the general register <-> floating point 2717 register information here is not used for SFmode. */ 2718 2719 #define REGCLASS_HAS_GENERAL_REG(CLASS) \ 2720 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \ 2721 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) 2722 2723 #define REGCLASS_HAS_FP_REG(CLASS) \ 2724 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \ 2725 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS) 2726 2727 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \ 2728 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS)) 2729 2730 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This 2731 would be so that people with slow memory systems could generate 2732 different code that does fewer memory accesses. */ 2733 2734 /* A C expression for the cost of a branch instruction. A value of 1 2735 is the default; other values are interpreted relative to that. 2736 The SH1 does not have delay slots, hence we get a pipeline stall 2737 at every branch. The SH4 is superscalar, so the single delay slot 2738 is not sufficient to keep both pipelines filled. */ 2739 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1) 2740 2741 /* Assembler output control. */ 2742 2743 /* A C string constant describing how to begin a comment in the target 2744 assembler language. The compiler assumes that the comment will end at 2745 the end of the line. */ 2746 #define ASM_COMMENT_START "!" 2747 2748 #define ASM_APP_ON "" 2749 #define ASM_APP_OFF "" 2750 #define FILE_ASM_OP "\t.file\n" 2751 #define SET_ASM_OP "\t.set\t" 2752 2753 /* How to change between sections. */ 2754 2755 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text") 2756 #define DATA_SECTION_ASM_OP "\t.data" 2757 2758 #if defined CRT_BEGIN || defined CRT_END 2759 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */ 2760 # undef TEXT_SECTION_ASM_OP 2761 # if __SHMEDIA__ == 1 && __SH5__ == 32 2762 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\"" 2763 # else 2764 # define TEXT_SECTION_ASM_OP "\t.text" 2765 # endif 2766 #endif 2767 2768 2769 /* If defined, a C expression whose value is a string containing the 2770 assembler operation to identify the following data as 2771 uninitialized global data. If not defined, and neither 2772 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined, 2773 uninitialized global data will be output in the data section if 2774 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be 2775 used. */ 2776 #ifndef BSS_SECTION_ASM_OP 2777 #define BSS_SECTION_ASM_OP "\t.section\t.bss" 2778 #endif 2779 2780 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a 2781 separate, explicit argument. If you define this macro, it is used 2782 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in 2783 handling the required alignment of the variable. The alignment is 2784 specified as the number of bits. 2785 2786 Try to use function `asm_output_aligned_bss' defined in file 2787 `varasm.c' when defining this macro. */ 2788 #ifndef ASM_OUTPUT_ALIGNED_BSS 2789 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 2790 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) 2791 #endif 2792 2793 /* Define this so that jump tables go in same section as the current function, 2794 which could be text or it could be a user defined section. */ 2795 #define JUMP_TABLES_IN_TEXT_SECTION 1 2796 2797 #undef DO_GLOBAL_CTORS_BODY 2798 #define DO_GLOBAL_CTORS_BODY \ 2799 { \ 2800 typedef (*pfunc)(); \ 2801 extern pfunc __ctors[]; \ 2802 extern pfunc __ctors_end[]; \ 2803 pfunc *p; \ 2804 for (p = __ctors_end; p > __ctors; ) \ 2805 { \ 2806 (*--p)(); \ 2807 } \ 2808 } 2809 2810 #undef DO_GLOBAL_DTORS_BODY 2811 #define DO_GLOBAL_DTORS_BODY \ 2812 { \ 2813 typedef (*pfunc)(); \ 2814 extern pfunc __dtors[]; \ 2815 extern pfunc __dtors_end[]; \ 2816 pfunc *p; \ 2817 for (p = __dtors; p < __dtors_end; p++) \ 2818 { \ 2819 (*p)(); \ 2820 } \ 2821 } 2822 2823 #define ASM_OUTPUT_REG_PUSH(file, v) \ 2824 { \ 2825 if (TARGET_SHMEDIA) \ 2826 { \ 2827 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \ 2828 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \ 2829 } \ 2830 else \ 2831 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \ 2832 } 2833 2834 #define ASM_OUTPUT_REG_POP(file, v) \ 2835 { \ 2836 if (TARGET_SHMEDIA) \ 2837 { \ 2838 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \ 2839 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \ 2840 } \ 2841 else \ 2842 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \ 2843 } 2844 2845 /* DBX register number for a given compiler register number. */ 2846 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers 2847 to match gdb. */ 2848 /* svr4.h undefines this macro, yet we really want to use the same numbers 2849 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */ 2850 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a 2851 register exists, so we should return -1 for invalid register numbers. */ 2852 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO) 2853 2854 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers 2855 used to use the encodings 245..260, but that doesn't make sense: 2856 PR_REG and PR_MEDIA_REG are actually the same register, and likewise 2857 the FP registers stay the same when switching between compact and media 2858 mode. Hence, we also need to use the same dwarf frame columns. 2859 Likewise, we need to support unwind information for SHmedia registers 2860 even in compact code. */ 2861 #define SH_DBX_REGISTER_NUMBER(REGNO) \ 2862 (IN_RANGE ((REGNO), \ 2863 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ 2864 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \ 2865 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \ 2866 : ((int) (REGNO) >= FIRST_FP_REG \ 2867 && ((int) (REGNO) \ 2868 <= (FIRST_FP_REG + \ 2869 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \ 2870 ? ((unsigned) (REGNO) - FIRST_FP_REG \ 2871 + (TARGET_SH5 ? 77 : 25)) \ 2872 : XD_REGISTER_P (REGNO) \ 2873 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \ 2874 : TARGET_REGISTER_P (REGNO) \ 2875 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \ 2876 : (REGNO) == PR_REG \ 2877 ? (TARGET_SH5 ? 18 : 17) \ 2878 : (REGNO) == PR_MEDIA_REG \ 2879 ? (TARGET_SH5 ? 18 : (unsigned) -1) \ 2880 : (REGNO) == T_REG \ 2881 ? (TARGET_SH5 ? 242 : 18) \ 2882 : (REGNO) == GBR_REG \ 2883 ? (TARGET_SH5 ? 238 : 19) \ 2884 : (REGNO) == MACH_REG \ 2885 ? (TARGET_SH5 ? 239 : 20) \ 2886 : (REGNO) == MACL_REG \ 2887 ? (TARGET_SH5 ? 240 : 21) \ 2888 : (REGNO) == FPUL_REG \ 2889 ? (TARGET_SH5 ? 244 : 23) \ 2890 : (unsigned) -1) 2891 2892 /* This is how to output a reference to a symbol_ref. On SH5, 2893 references to non-code symbols must be preceded by `datalabel'. */ 2894 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \ 2895 do \ 2896 { \ 2897 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \ 2898 fputs ("datalabel ", (FILE)); \ 2899 assemble_name ((FILE), XSTR ((SYM), 0)); \ 2900 } \ 2901 while (0) 2902 2903 /* This is how to output an assembler line 2904 that says to advance the location counter 2905 to a multiple of 2**LOG bytes. */ 2906 2907 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2908 if ((LOG) != 0) \ 2909 fprintf ((FILE), "\t.align %d\n", (LOG)) 2910 2911 /* Globalizing directive for a label. */ 2912 #define GLOBAL_ASM_OP "\t.global\t" 2913 2914 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ 2915 2916 /* Output a relative address table. */ 2917 2918 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ 2919 switch (GET_MODE (BODY)) \ 2920 { \ 2921 case SImode: \ 2922 if (TARGET_SH5) \ 2923 { \ 2924 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \ 2925 (VALUE), (REL)); \ 2926 break; \ 2927 } \ 2928 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \ 2929 break; \ 2930 case HImode: \ 2931 if (TARGET_SH5) \ 2932 { \ 2933 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \ 2934 (VALUE), (REL)); \ 2935 break; \ 2936 } \ 2937 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \ 2938 break; \ 2939 case QImode: \ 2940 if (TARGET_SH5) \ 2941 { \ 2942 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \ 2943 (VALUE), (REL)); \ 2944 break; \ 2945 } \ 2946 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \ 2947 break; \ 2948 default: \ 2949 break; \ 2950 } 2951 2952 /* Output an absolute table element. */ 2953 2954 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ 2955 if (! optimize || TARGET_BIGTABLE) \ 2956 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \ 2957 else \ 2958 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); 2959 2960 2961 /* A C statement to be executed just prior to the output of 2962 assembler code for INSN, to modify the extracted operands so 2963 they will be output differently. 2964 2965 Here the argument OPVEC is the vector containing the operands 2966 extracted from INSN, and NOPERANDS is the number of elements of 2967 the vector which contain meaningful data for this insn. 2968 The contents of this vector are what will be used to convert the insn 2969 template into assembler code, so you can change the assembler output 2970 by changing the contents of the vector. */ 2971 2972 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2973 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS)) 2974 2975 /* Print operand X (an rtx) in assembler syntax to file FILE. 2976 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2977 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2978 2979 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE)) 2980 2981 /* Print a memory address as an operand to reference that memory location. */ 2982 2983 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X)) 2984 2985 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 2986 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \ 2987 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>') 2988 2989 /* Recognize machine-specific patterns that may appear within 2990 constants. Used for PIC-specific UNSPECs. */ 2991 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \ 2992 do \ 2993 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \ 2994 { \ 2995 switch (XINT ((X), 1)) \ 2996 { \ 2997 case UNSPEC_DATALABEL: \ 2998 fputs ("datalabel ", (STREAM)); \ 2999 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 3000 break; \ 3001 case UNSPEC_PIC: \ 3002 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \ 3003 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 3004 break; \ 3005 case UNSPEC_GOT: \ 3006 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 3007 fputs ("@GOT", (STREAM)); \ 3008 break; \ 3009 case UNSPEC_GOTOFF: \ 3010 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 3011 fputs ("@GOTOFF", (STREAM)); \ 3012 break; \ 3013 case UNSPEC_PLT: \ 3014 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 3015 fputs ("@PLT", (STREAM)); \ 3016 break; \ 3017 case UNSPEC_GOTPLT: \ 3018 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 3019 fputs ("@GOTPLT", (STREAM)); \ 3020 break; \ 3021 case UNSPEC_DTPOFF: \ 3022 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 3023 fputs ("@DTPOFF", (STREAM)); \ 3024 break; \ 3025 case UNSPEC_GOTTPOFF: \ 3026 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 3027 fputs ("@GOTTPOFF", (STREAM)); \ 3028 break; \ 3029 case UNSPEC_TPOFF: \ 3030 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 3031 fputs ("@TPOFF", (STREAM)); \ 3032 break; \ 3033 case UNSPEC_CALLER: \ 3034 { \ 3035 char name[32]; \ 3036 /* LPCS stands for Label for PIC Call Site. */ \ 3037 ASM_GENERATE_INTERNAL_LABEL \ 3038 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \ 3039 assemble_name ((STREAM), name); \ 3040 } \ 3041 break; \ 3042 default: \ 3043 goto FAIL; \ 3044 } \ 3045 break; \ 3046 } \ 3047 else \ 3048 goto FAIL; \ 3049 while (0) 3050 3051 3052 extern struct rtx_def *sh_compare_op0; 3053 extern struct rtx_def *sh_compare_op1; 3054 3055 /* Which processor to schedule for. The elements of the enumeration must 3056 match exactly the cpu attribute in the sh.md file. */ 3057 3058 enum processor_type { 3059 PROCESSOR_SH1, 3060 PROCESSOR_SH2, 3061 PROCESSOR_SH2E, 3062 PROCESSOR_SH2A, 3063 PROCESSOR_SH3, 3064 PROCESSOR_SH3E, 3065 PROCESSOR_SH4, 3066 PROCESSOR_SH4A, 3067 PROCESSOR_SH5 3068 }; 3069 3070 #define sh_cpu_attr ((enum attr_cpu)sh_cpu) 3071 extern enum processor_type sh_cpu; 3072 3073 extern int optimize; /* needed for gen_casesi. */ 3074 3075 enum mdep_reorg_phase_e 3076 { 3077 SH_BEFORE_MDEP_REORG, 3078 SH_INSERT_USES_LABELS, 3079 SH_SHORTEN_BRANCHES0, 3080 SH_FIXUP_PCLOAD, 3081 SH_SHORTEN_BRANCHES1, 3082 SH_AFTER_MDEP_REORG 3083 }; 3084 3085 extern enum mdep_reorg_phase_e mdep_reorg_phase; 3086 3087 /* Handle Renesas compiler's pragmas. */ 3088 #define REGISTER_TARGET_PRAGMAS() do { \ 3089 c_register_pragma (0, "interrupt", sh_pr_interrupt); \ 3090 c_register_pragma (0, "trapa", sh_pr_trapa); \ 3091 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \ 3092 } while (0) 3093 3094 extern tree sh_deferred_function_attributes; 3095 extern tree *sh_deferred_function_attributes_tail; 3096 3097 /* Set when processing a function with interrupt attribute. */ 3098 3099 extern int current_function_interrupt; 3100 3101 3102 /* Instructions with unfilled delay slots take up an 3103 extra two bytes for the nop in the delay slot. 3104 sh-dsp parallel processing insns are four bytes long. */ 3105 3106 #define ADJUST_INSN_LENGTH(X, LENGTH) \ 3107 (LENGTH) += sh_insn_length_adjustment (X); 3108 3109 /* Define this macro if it is advisable to hold scalars in registers 3110 in a wider mode than that declared by the program. In such cases, 3111 the value is constrained to be within the bounds of the declared 3112 type, but kept valid in the wider mode. The signedness of the 3113 extension may differ from that of the type. 3114 3115 Leaving the unsignedp unchanged gives better code than always setting it 3116 to 0. This is despite the fact that we have only signed char and short 3117 load instructions. */ 3118 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 3119 if (GET_MODE_CLASS (MODE) == MODE_INT \ 3120 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\ 3121 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \ 3122 (MODE) = (TARGET_SH1 ? SImode \ 3123 : TARGET_SHMEDIA32 ? SImode : DImode); 3124 3125 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64) 3126 3127 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4) 3128 3129 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing 3130 and popping arguments. However, we do have push/pop instructions, and 3131 rather limited offsets (4 bits) in load/store instructions, so it isn't 3132 clear if this would give better code. If implemented, should check for 3133 compatibility problems. */ 3134 3135 #define SH_DYNAMIC_SHIFT_COST \ 3136 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20) 3137 3138 3139 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE } 3140 3141 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE) 3142 3143 #define ACTUAL_NORMAL_MODE(ENTITY) \ 3144 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE) 3145 3146 #define NORMAL_MODE(ENTITY) \ 3147 (sh_cfun_interrupt_handler_p () \ 3148 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \ 3149 : ACTUAL_NORMAL_MODE (ENTITY)) 3150 3151 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY) 3152 3153 #define MODE_EXIT(ENTITY) \ 3154 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY)) 3155 3156 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \ 3157 && (REGNO) == FPSCR_REG) 3158 3159 #define MODE_NEEDED(ENTITY, INSN) \ 3160 (recog_memoized (INSN) >= 0 \ 3161 ? get_attr_fp_mode (INSN) \ 3162 : FP_MODE_NONE) 3163 3164 #define MODE_AFTER(MODE, INSN) \ 3165 (TARGET_HITACHI \ 3166 && recog_memoized (INSN) >= 0 \ 3167 && get_attr_fp_set (INSN) != FP_SET_NONE \ 3168 ? (int) get_attr_fp_set (INSN) \ 3169 : (MODE)) 3170 3171 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \ 3172 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE) 3173 3174 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 3175 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE)) 3176 3177 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \ 3178 sh_can_redirect_branch ((INSN), (SEQ)) 3179 3180 #define DWARF_FRAME_RETURN_COLUMN \ 3181 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG)) 3182 3183 #define EH_RETURN_DATA_REGNO(N) \ 3184 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM) 3185 3186 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM 3187 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) 3188 3189 /* We have to distinguish between code and data, so that we apply 3190 datalabel where and only where appropriate. Use sdataN for data. */ 3191 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 3192 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \ 3193 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \ 3194 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4))) 3195 3196 /* Handle special EH pointer encodings. Absolute, pc-relative, and 3197 indirect are handled automatically. */ 3198 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \ 3199 do { \ 3200 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \ 3201 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \ 3202 { \ 3203 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \ 3204 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \ 3205 if (0) goto DONE; \ 3206 } \ 3207 } while (0) 3208 3209 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ 3210 /* SH constant pool breaks the devices in crtstuff.c to control section 3211 in where code resides. We have to write it as asm code. */ 3212 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 3213 asm (SECTION_OP "\n\ 3214 mov.l 1f,r1\n\ 3215 mova 2f,r0\n\ 3216 braf r1\n\ 3217 lds r0,pr\n\ 3218 0: .p2align 2\n\ 3219 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\ 3220 2:\n" TEXT_SECTION_ASM_OP); 3221 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */ 3222 3223 #define SIMULTANEOUS_PREFETCHES 2 3224 3225 /* FIXME: middle-end support for highpart optimizations is missing. */ 3226 #define high_life_started reload_in_progress 3227 3228 #endif /* ! GCC_SH_H */ 3229