1 /* $NetBSD: piixpm.c,v 1.72 2023/01/12 10:10:10 msaitoh Exp $ */
2 /* $OpenBSD: piixpm.c,v 1.39 2013/10/01 20:06:02 sf Exp $ */
3
4 /*
5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 /*
21 * Intel PIIX and compatible Power Management controller driver.
22 */
23
24 #include <sys/cdefs.h>
25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.72 2023/01/12 10:10:10 msaitoh Exp $");
26
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/device.h>
30 #include <sys/kernel.h>
31 #include <sys/mutex.h>
32 #include <sys/condvar.h>
33 #include <sys/proc.h>
34
35 #include <sys/bus.h>
36
37 #include <dev/pci/pcidevs.h>
38 #include <dev/pci/pcireg.h>
39 #include <dev/pci/pcivar.h>
40
41 #include <dev/pci/piixpmreg.h>
42
43 #include <dev/i2c/i2cvar.h>
44
45 #include <dev/ic/acpipmtimer.h>
46
47 #ifdef PIIXPM_DEBUG
48 #define DPRINTF(x) printf x
49 #else
50 #define DPRINTF(x)
51 #endif
52
53 #define PIIXPM_IS_CSB5(sc) \
54 (PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_SERVERWORKS && \
55 PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_SERVERWORKS_CSB5)
56 #define PIIXPM_DELAY 200
57 #define PIIXPM_TIMEOUT 1
58
59 #define PIIXPM_IS_SB800GRP(sc) \
60 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_ATI) && \
61 ((PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_ATI_SB600_SMB) && \
62 ((sc)->sc_rev >= 0x40)))
63
64 #define PIIXPM_IS_HUDSON(sc) \
65 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \
66 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_HUDSON_SMB))
67
68 #define PIIXPM_IS_KERNCZ(sc) \
69 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \
70 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_KERNCZ_SMB))
71
72 #define PIIXPM_IS_FCHGRP(sc) (PIIXPM_IS_HUDSON(sc) || PIIXPM_IS_KERNCZ(sc))
73
74 #define PIIX_SB800_TIMEOUT 500
75
76 struct piixpm_smbus {
77 int sda;
78 int sda_save;
79 struct piixpm_softc *softc;
80 };
81
82 struct piixpm_softc {
83 device_t sc_dev;
84
85 bus_space_tag_t sc_iot;
86 bus_space_tag_t sc_sb800_bt;
87 bus_space_handle_t sc_pm_ioh;
88 bus_space_handle_t sc_sb800_bh;
89 bus_space_handle_t sc_smb_ioh;
90 void * sc_smb_ih;
91 int sc_poll;
92 bool sc_sb800_mmio; /* Use MMIO access */
93 bool sc_sb800_selen; /* Use SMBUS0SEL */
94
95 pci_chipset_tag_t sc_pc;
96 pcitag_t sc_pcitag;
97 pcireg_t sc_id;
98 pcireg_t sc_rev;
99
100 int sc_numbusses;
101 device_t sc_i2c_device[4];
102 struct piixpm_smbus sc_busses[4];
103 struct i2c_controller sc_i2c_tags[4];
104
105 kmutex_t sc_exec_lock;
106 kcondvar_t sc_exec_wait;
107
108 struct {
109 i2c_op_t op;
110 void * buf;
111 size_t len;
112 int flags;
113 int error;
114 bool done;
115 } sc_i2c_xfer;
116
117 pcireg_t sc_devact[2];
118 };
119
120 static int piixpm_match(device_t, cfdata_t, void *);
121 static void piixpm_attach(device_t, device_t, void *);
122 static int piixpm_rescan(device_t, const char *, const int *);
123 static void piixpm_chdet(device_t, device_t);
124
125 static bool piixpm_suspend(device_t, const pmf_qual_t *);
126 static bool piixpm_resume(device_t, const pmf_qual_t *);
127
128 static uint8_t piixpm_sb800_pmread(struct piixpm_softc *, bus_size_t);
129 static int piixpm_sb800_init(struct piixpm_softc *);
130 static void piixpm_csb5_reset(void *);
131 static int piixpm_i2c_sb800_acquire_bus(void *, int);
132 static void piixpm_i2c_sb800_release_bus(void *, int);
133 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *,
134 size_t, void *, size_t, int);
135
136 static int piixpm_intr(void *);
137
138 CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc),
139 piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0);
140
141 static int
piixpm_match(device_t parent,cfdata_t match,void * aux)142 piixpm_match(device_t parent, cfdata_t match, void *aux)
143 {
144 struct pci_attach_args *pa;
145
146 pa = (struct pci_attach_args *)aux;
147 switch (PCI_VENDOR(pa->pa_id)) {
148 case PCI_VENDOR_INTEL:
149 switch (PCI_PRODUCT(pa->pa_id)) {
150 case PCI_PRODUCT_INTEL_82371AB_PMC:
151 case PCI_PRODUCT_INTEL_82440MX_PMC:
152 return 1;
153 }
154 break;
155 case PCI_VENDOR_ATI:
156 switch (PCI_PRODUCT(pa->pa_id)) {
157 case PCI_PRODUCT_ATI_SB200_SMB:
158 case PCI_PRODUCT_ATI_SB300_SMB:
159 case PCI_PRODUCT_ATI_SB400_SMB:
160 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */
161 return 1;
162 }
163 break;
164 case PCI_VENDOR_SERVERWORKS:
165 switch (PCI_PRODUCT(pa->pa_id)) {
166 case PCI_PRODUCT_SERVERWORKS_OSB4:
167 case PCI_PRODUCT_SERVERWORKS_CSB5:
168 case PCI_PRODUCT_SERVERWORKS_CSB6:
169 case PCI_PRODUCT_SERVERWORKS_HT1000SB:
170 case PCI_PRODUCT_SERVERWORKS_HT1100SB:
171 return 1;
172 }
173 break;
174 case PCI_VENDOR_AMD:
175 switch (PCI_PRODUCT(pa->pa_id)) {
176 case PCI_PRODUCT_AMD_HUDSON_SMB:
177 case PCI_PRODUCT_AMD_KERNCZ_SMB:
178 return 1;
179 }
180 break;
181 }
182
183 return 0;
184 }
185
186 static void
piixpm_attach(device_t parent,device_t self,void * aux)187 piixpm_attach(device_t parent, device_t self, void *aux)
188 {
189 struct piixpm_softc *sc = device_private(self);
190 struct pci_attach_args *pa = aux;
191 pcireg_t base, conf;
192 pcireg_t pmmisc;
193 pci_intr_handle_t ih;
194 bool usesmi = false;
195 const char *intrstr = NULL;
196 int i;
197 char intrbuf[PCI_INTRSTR_LEN];
198
199 sc->sc_dev = self;
200 sc->sc_iot = pa->pa_iot;
201 sc->sc_id = pa->pa_id;
202 sc->sc_rev = PCI_REVISION(pa->pa_class);
203 sc->sc_pc = pa->pa_pc;
204 sc->sc_pcitag = pa->pa_tag;
205 sc->sc_numbusses = 1;
206
207 pci_aprint_devinfo(pa, NULL);
208
209 mutex_init(&sc->sc_exec_lock, MUTEX_DEFAULT, IPL_BIO);
210 cv_init(&sc->sc_exec_wait, device_xname(self));
211
212 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume))
213 aprint_error_dev(self, "couldn't establish power handler\n");
214
215 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) ||
216 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC))
217 goto nopowermanagement;
218
219 /* check whether I/O access to PM regs is enabled */
220 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC);
221 if (!(pmmisc & 1))
222 goto nopowermanagement;
223
224 /* Map I/O space */
225 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE);
226 if (base == 0 || bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(base),
227 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) {
228 aprint_error_dev(self,
229 "can't map power management I/O space\n");
230 goto nopowermanagement;
231 }
232
233 /*
234 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M.
235 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20
236 * in the "Specification update" (document #297738).
237 */
238 acpipmtimer_attach(self, sc->sc_iot, sc->sc_pm_ioh, PIIX_PM_PMTMR,
239 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0);
240
241 nopowermanagement:
242
243 /* SB800 rev 0x40+, AMD HUDSON and newer need special initialization */
244 if (PIIXPM_IS_FCHGRP(sc) || PIIXPM_IS_SB800GRP(sc)) {
245 /* Newer chips don't support I/O access */
246 if (PIIXPM_IS_KERNCZ(sc) && (sc->sc_rev >= 0x51)) {
247 sc->sc_sb800_mmio = true;
248 sc->sc_sb800_bt = pa->pa_memt;
249 } else {
250 sc->sc_sb800_mmio = false;
251 sc->sc_sb800_bt = pa->pa_iot;
252 }
253
254 if (piixpm_sb800_init(sc) == 0) {
255 /* Read configuration */
256 conf = bus_space_read_1(sc->sc_iot,
257 sc->sc_smb_ioh, SB800_SMB_HOSTC);
258 usesmi = ((conf & SB800_SMB_HOSTC_IRQ) == 0);
259 goto setintr;
260 }
261 aprint_normal_dev(self, "SMBus initialization failed\n");
262 return;
263 }
264
265 /* Read configuration */
266 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC);
267 DPRINTF(("%s: conf 0x%08x\n", device_xname(self), conf));
268
269 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) {
270 aprint_normal_dev(self, "SMBus disabled\n");
271 return;
272 }
273 usesmi = (conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI;
274
275 /* Map I/O space */
276 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff;
277 if (base == 0 ||
278 bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(base),
279 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) {
280 aprint_error_dev(self, "can't map smbus I/O space\n");
281 return;
282 }
283
284 setintr:
285 sc->sc_poll = 1;
286 aprint_normal_dev(self, "");
287 if (usesmi) {
288 /* No PCI IRQ */
289 aprint_normal("interrupting at SMI, ");
290 } else {
291 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) {
292 /* Install interrupt handler */
293 if (pci_intr_map(pa, &ih) == 0) {
294 intrstr = pci_intr_string(pa->pa_pc, ih,
295 intrbuf, sizeof(intrbuf));
296 pci_intr_setattr(pa->pa_pc, &ih,
297 PCI_INTR_MPSAFE, true);
298 sc->sc_smb_ih = pci_intr_establish_xname(
299 pa->pa_pc, ih, IPL_BIO, piixpm_intr,
300 sc, device_xname(sc->sc_dev));
301 if (sc->sc_smb_ih != NULL) {
302 aprint_normal("interrupting at %s",
303 intrstr);
304 sc->sc_poll = 0;
305 }
306 }
307 }
308 if (sc->sc_poll)
309 aprint_normal("polling");
310 }
311
312 aprint_normal("\n");
313
314 for (i = 0; i < sc->sc_numbusses; i++)
315 sc->sc_i2c_device[i] = NULL;
316
317 piixpm_rescan(self, NULL, NULL);
318 }
319
320 static int
piixpm_iicbus_print(void * aux,const char * pnp)321 piixpm_iicbus_print(void *aux, const char *pnp)
322 {
323 struct i2cbus_attach_args *iba = aux;
324 struct i2c_controller *tag = iba->iba_tag;
325 struct piixpm_smbus *bus = tag->ic_cookie;
326 struct piixpm_softc *sc = bus->softc;
327
328 iicbus_print(aux, pnp);
329 if (sc->sc_numbusses != 0)
330 aprint_normal(" port %d", bus->sda);
331
332 return UNCONF;
333 }
334
335 static int
piixpm_rescan(device_t self,const char * ifattr,const int * locators)336 piixpm_rescan(device_t self, const char *ifattr, const int *locators)
337 {
338 struct piixpm_softc *sc = device_private(self);
339 struct i2cbus_attach_args iba;
340 int i;
341
342 /* Attach I2C bus */
343
344 for (i = 0; i < sc->sc_numbusses; i++) {
345 struct i2c_controller *tag = &sc->sc_i2c_tags[i];
346
347 if (sc->sc_i2c_device[i] != NULL)
348 continue;
349 sc->sc_busses[i].sda = i;
350 sc->sc_busses[i].softc = sc;
351 iic_tag_init(tag);
352 tag->ic_cookie = &sc->sc_busses[i];
353 if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_FCHGRP(sc)) {
354 tag->ic_acquire_bus = piixpm_i2c_sb800_acquire_bus;
355 tag->ic_release_bus = piixpm_i2c_sb800_release_bus;
356 } else {
357 tag->ic_acquire_bus = NULL;
358 tag->ic_release_bus = NULL;
359 }
360 tag->ic_exec = piixpm_i2c_exec;
361 memset(&iba, 0, sizeof(iba));
362 iba.iba_tag = tag;
363 sc->sc_i2c_device[i] =
364 config_found(self, &iba, piixpm_iicbus_print, CFARGS_NONE);
365 if (sc->sc_i2c_device[i] == NULL)
366 iic_tag_fini(tag);
367 }
368
369 return 0;
370 }
371
372 static void
piixpm_chdet(device_t self,device_t child)373 piixpm_chdet(device_t self, device_t child)
374 {
375 struct piixpm_softc *sc = device_private(self);
376 int i;
377
378 for (i = 0; i < sc->sc_numbusses; i++) {
379 if (sc->sc_i2c_device[i] == child) {
380
381 struct i2c_controller *tag = &sc->sc_i2c_tags[i];
382
383 iic_tag_fini(tag);
384 sc->sc_i2c_device[i] = NULL;
385 break;
386 }
387 }
388 }
389
390
391 static bool
piixpm_suspend(device_t dv,const pmf_qual_t * qual)392 piixpm_suspend(device_t dv, const pmf_qual_t *qual)
393 {
394 struct piixpm_softc *sc = device_private(dv);
395
396 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
397 PIIX_DEVACTA);
398 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
399 PIIX_DEVACTB);
400
401 return true;
402 }
403
404 static bool
piixpm_resume(device_t dv,const pmf_qual_t * qual)405 piixpm_resume(device_t dv, const pmf_qual_t *qual)
406 {
407 struct piixpm_softc *sc = device_private(dv);
408
409 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA,
410 sc->sc_devact[0]);
411 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB,
412 sc->sc_devact[1]);
413
414 return true;
415 }
416
417 static uint8_t
piixpm_sb800_pmread(struct piixpm_softc * sc,bus_size_t offset)418 piixpm_sb800_pmread(struct piixpm_softc *sc, bus_size_t offset)
419 {
420 bus_space_tag_t sbt = sc->sc_sb800_bt;
421 bus_space_handle_t sbh = sc->sc_sb800_bh;
422 uint8_t val;
423
424 if (sc->sc_sb800_mmio)
425 val = bus_space_read_1(sbt, sbh, offset);
426 else {
427 bus_space_write_1(sbt, sbh, SB800_INDIRECTIO_INDEX, offset);
428 val = bus_space_read_1(sbt, sbh, SB800_INDIRECTIO_DATA);
429 }
430
431 return val;
432 }
433
434 /*
435 * Extract SMBus base address from SB800 Power Management (PM) registers.
436 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or
437 * direct mapping if AcpiMMioDecodeEn is enabled. Newer devices support MMIO
438 * access only.
439 */
440 static int
piixpm_sb800_init(struct piixpm_softc * sc)441 piixpm_sb800_init(struct piixpm_softc *sc)
442 {
443 bus_space_tag_t sbt = sc->sc_sb800_bt;
444 bus_space_handle_t sbh; /* indirect memory or I/O handle */
445 int rv;
446 uint16_t base_addr;
447 uint8_t lo, hi;
448 bool enabled;
449
450 if (PIIXPM_IS_KERNCZ(sc) ||
451 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f)))
452 sc->sc_numbusses = 2;
453 else
454 sc->sc_numbusses = 4;
455
456 /* Check SMBus enable bit and Fetch SMB base address */
457 if (sc->sc_sb800_mmio)
458 rv = bus_space_map(sbt, SB800_FCH_PM_BASE,
459 SB800_FCH_PM_SIZE, 0, &sbh);
460 else
461 rv = bus_space_map(sbt, SB800_INDIRECTIO_BASE,
462 SB800_INDIRECTIO_SIZE, 0, &sbh);
463 if (rv != 0) {
464 device_printf(sc->sc_dev, "couldn't map indirect space\n");
465 return EBUSY;
466 }
467 sc->sc_sb800_bh = sbh;
468 if (PIIXPM_IS_FCHGRP(sc)) {
469 lo = piixpm_sb800_pmread(sc, AMDFCH41_PM_DECODE_EN0);
470 enabled = lo & AMDFCH41_SMBUS_EN;
471 if (!enabled)
472 return ENOENT;
473
474 hi = piixpm_sb800_pmread(sc, AMDFCH41_PM_DECODE_EN1);
475 base_addr = (uint16_t)hi << 8;
476 } else {
477 uint8_t data;
478
479 lo = piixpm_sb800_pmread(sc, SB800_PM_SMBUS0EN_LO);
480 enabled = lo & SB800_PM_SMBUS0EN_ENABLE;
481 if (!enabled)
482 return ENOENT;
483
484 hi = piixpm_sb800_pmread(sc, SB800_PM_SMBUS0EN_HI);
485 base_addr = ((uint16_t)hi << 8) & SB800_PM_SMBUS0EN_BADDR;
486
487 bus_space_write_1(sbt, sbh, SB800_INDIRECTIO_INDEX,
488 SB800_PM_SMBUS0SELEN);
489 data = bus_space_read_1(sbt, sbh, SB800_INDIRECTIO_DATA);
490 if ((data & SB800_PM_USE_SMBUS0SEL) != 0)
491 sc->sc_sb800_selen = true;
492 }
493
494 aprint_debug_dev(sc->sc_dev, "SMBus %s access @ 0x%04x\n",
495 sc->sc_sb800_mmio ? "memory" : "I/O", base_addr);
496
497 if (bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(base_addr),
498 SB800_SMB_SIZE, 0, &sc->sc_smb_ioh)) {
499 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n");
500 return EBUSY;
501 }
502
503 return 0;
504 }
505
506 static void
piixpm_csb5_reset(void * arg)507 piixpm_csb5_reset(void *arg)
508 {
509 struct piixpm_softc *sc = arg;
510 pcireg_t base, hostc, pmbase;
511
512 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE);
513 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC);
514
515 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE);
516 pmbase |= PIIX_PM_BASE_CSB5_RESET;
517 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase);
518 pmbase &= ~PIIX_PM_BASE_CSB5_RESET;
519 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase);
520
521 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base);
522 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc);
523
524 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2);
525 }
526
527 static int
piixpm_i2c_sb800_acquire_bus(void * cookie,int flags)528 piixpm_i2c_sb800_acquire_bus(void *cookie, int flags)
529 {
530 struct piixpm_smbus *smbus = cookie;
531 struct piixpm_softc *sc = smbus->softc;
532 uint8_t sctl, old_sda, index, mask, reg;
533 int i;
534
535 sctl = bus_space_read_1(sc->sc_iot, sc->sc_smb_ioh, PIIX_SMB_SC);
536 for (i = 0; i < PIIX_SB800_TIMEOUT; i++) {
537 /* Try to acquire the host semaphore */
538 sctl &= ~PIIX_SMB_SC_SEMMASK;
539 bus_space_write_1(sc->sc_iot, sc->sc_smb_ioh, PIIX_SMB_SC,
540 sctl | PIIX_SMB_SC_HOSTSEM);
541
542 sctl = bus_space_read_1(sc->sc_iot, sc->sc_smb_ioh,
543 PIIX_SMB_SC);
544 if ((sctl & PIIX_SMB_SC_HOSTSEM) != 0)
545 break;
546
547 delay(1000);
548 }
549 if (i >= PIIX_SB800_TIMEOUT) {
550 device_printf(sc->sc_dev,
551 "Failed to acquire the host semaphore\n");
552 return -1;
553 }
554
555 if (PIIXPM_IS_KERNCZ(sc) ||
556 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) {
557 index = AMDFCH41_PM_PORT_INDEX;
558 mask = AMDFCH41_SMBUS_PORTMASK;
559 } else if (sc->sc_sb800_selen) {
560 index = SB800_PM_SMBUS0SEL;
561 mask = SB800_PM_SMBUS0_MASK_E;
562 } else {
563 index = SB800_PM_SMBUS0EN_LO;
564 mask = SB800_PM_SMBUS0_MASK_C;
565 }
566
567 reg = piixpm_sb800_pmread(sc, index);
568
569 old_sda = __SHIFTOUT(reg, mask);
570 if (smbus->sda != old_sda) {
571 reg &= ~mask;
572 reg |= __SHIFTIN(smbus->sda, mask);
573 /*
574 * SB800_INDIRECTIO_INDEX is already set on I/O access,
575 * so it's not required to write it again.
576 */
577 bus_space_write_1(sc->sc_sb800_bt, sc->sc_sb800_bh,
578 sc->sc_sb800_mmio ? index : SB800_INDIRECTIO_DATA, reg);
579 }
580
581 /* Save the old port number */
582 smbus->sda_save = old_sda;
583
584 return 0;
585 }
586
587 static void
piixpm_i2c_sb800_release_bus(void * cookie,int flags)588 piixpm_i2c_sb800_release_bus(void *cookie, int flags)
589 {
590 struct piixpm_smbus *smbus = cookie;
591 struct piixpm_softc *sc = smbus->softc;
592 uint8_t sctl, index, mask, reg;
593
594 if (PIIXPM_IS_KERNCZ(sc) ||
595 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) {
596 index = AMDFCH41_PM_PORT_INDEX;
597 mask = AMDFCH41_SMBUS_PORTMASK;
598 } else if (sc->sc_sb800_selen) {
599 index = SB800_PM_SMBUS0SEL;
600 mask = SB800_PM_SMBUS0_MASK_E;
601 } else {
602 index = SB800_PM_SMBUS0EN_LO;
603 mask = SB800_PM_SMBUS0_MASK_C;
604 }
605
606 if (smbus->sda != smbus->sda_save) {
607 /* Restore the port number */
608 reg = piixpm_sb800_pmread(sc, index);
609 reg &= ~mask;
610 reg |= __SHIFTIN(smbus->sda_save, mask);
611 /*
612 * SB800_INDIRECTIO_INDEX is already set on I/O access,
613 * so it's not required to write it again.
614 */
615 bus_space_write_1(sc->sc_sb800_bt, sc->sc_sb800_bh,
616 sc->sc_sb800_mmio ? index : SB800_INDIRECTIO_DATA, reg);
617 }
618
619 /* Release the host semaphore */
620 sctl = bus_space_read_1(sc->sc_iot, sc->sc_smb_ioh, PIIX_SMB_SC);
621 sctl &= ~PIIX_SMB_SC_SEMMASK;
622 bus_space_write_1(sc->sc_iot, sc->sc_smb_ioh, PIIX_SMB_SC,
623 sctl | PIIX_SMB_SC_CLRHOSTSEM);
624 }
625
626 static int
piixpm_i2c_exec(void * cookie,i2c_op_t op,i2c_addr_t addr,const void * cmdbuf,size_t cmdlen,void * buf,size_t len,int flags)627 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr,
628 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
629 {
630 struct piixpm_smbus *smbus = cookie;
631 struct piixpm_softc *sc = smbus->softc;
632 const uint8_t *b;
633 uint8_t ctl = 0, st;
634 int retries;
635
636 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, "
637 "flags 0x%x\n",
638 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags));
639
640 mutex_enter(&sc->sc_exec_lock);
641
642 /* Clear status bits */
643 bus_space_write_1(sc->sc_iot, sc->sc_smb_ioh, PIIX_SMB_HS,
644 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR |
645 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED);
646 bus_space_barrier(sc->sc_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1,
647 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
648
649 /* Wait for bus to be idle */
650 for (retries = 100; retries > 0; retries--) {
651 st = bus_space_read_1(sc->sc_iot, sc->sc_smb_ioh,
652 PIIX_SMB_HS);
653 if (!(st & PIIX_SMB_HS_BUSY))
654 break;
655 DELAY(PIIXPM_DELAY);
656 }
657 DPRINTF(("%s: exec: st %#x\n", device_xname(sc->sc_dev), st & 0xff));
658 if (st & PIIX_SMB_HS_BUSY) {
659 mutex_exit(&sc->sc_exec_lock);
660 return (EBUSY);
661 }
662
663 if (sc->sc_poll)
664 flags |= I2C_F_POLL;
665
666 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 ||
667 (cmdlen == 0 && len > 1)) {
668 mutex_exit(&sc->sc_exec_lock);
669 return (EINVAL);
670 }
671
672 /* Setup transfer */
673 sc->sc_i2c_xfer.op = op;
674 sc->sc_i2c_xfer.buf = buf;
675 sc->sc_i2c_xfer.len = len;
676 sc->sc_i2c_xfer.flags = flags;
677 sc->sc_i2c_xfer.error = 0;
678 sc->sc_i2c_xfer.done = false;
679
680 /* Set slave address and transfer direction */
681 bus_space_write_1(sc->sc_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA,
682 PIIX_SMB_TXSLVA_ADDR(addr) |
683 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0));
684
685 b = cmdbuf;
686 if (cmdlen > 0)
687 /* Set command byte */
688 bus_space_write_1(sc->sc_iot, sc->sc_smb_ioh,
689 PIIX_SMB_HCMD, b[0]);
690
691 if (I2C_OP_WRITE_P(op)) {
692 /* Write data */
693 b = buf;
694 if (cmdlen == 0 && len == 1)
695 bus_space_write_1(sc->sc_iot, sc->sc_smb_ioh,
696 PIIX_SMB_HCMD, b[0]);
697 else if (len > 0)
698 bus_space_write_1(sc->sc_iot, sc->sc_smb_ioh,
699 PIIX_SMB_HD0, b[0]);
700 if (len > 1)
701 bus_space_write_1(sc->sc_iot, sc->sc_smb_ioh,
702 PIIX_SMB_HD1, b[1]);
703 }
704
705 /* Set SMBus command */
706 if (cmdlen == 0) {
707 if (len == 0)
708 ctl = PIIX_SMB_HC_CMD_QUICK;
709 else
710 ctl = PIIX_SMB_HC_CMD_BYTE;
711 } else if (len == 1)
712 ctl = PIIX_SMB_HC_CMD_BDATA;
713 else if (len == 2)
714 ctl = PIIX_SMB_HC_CMD_WDATA;
715 else
716 panic("%s: unexpected len %zu", __func__, len);
717
718 if ((flags & I2C_F_POLL) == 0)
719 ctl |= PIIX_SMB_HC_INTREN;
720
721 /* Start transaction */
722 ctl |= PIIX_SMB_HC_START;
723 bus_space_write_1(sc->sc_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl);
724
725 if (flags & I2C_F_POLL) {
726 /* Poll for completion */
727 if (PIIXPM_IS_CSB5(sc))
728 DELAY(2*PIIXPM_DELAY);
729 else
730 DELAY(PIIXPM_DELAY);
731 for (retries = 1000; retries > 0; retries--) {
732 st = bus_space_read_1(sc->sc_iot, sc->sc_smb_ioh,
733 PIIX_SMB_HS);
734 if ((st & PIIX_SMB_HS_BUSY) == 0)
735 break;
736 DELAY(PIIXPM_DELAY);
737 }
738 if (st & PIIX_SMB_HS_BUSY)
739 goto timeout;
740 piixpm_intr(sc);
741 } else {
742 /* Wait for interrupt */
743 while (! sc->sc_i2c_xfer.done) {
744 if (cv_timedwait(&sc->sc_exec_wait, &sc->sc_exec_lock,
745 PIIXPM_TIMEOUT * hz))
746 goto timeout;
747 }
748 }
749
750 int error = sc->sc_i2c_xfer.error;
751 mutex_exit(&sc->sc_exec_lock);
752
753 return (error);
754
755 timeout:
756 /*
757 * Transfer timeout. Kill the transaction and clear status bits.
758 */
759 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st);
760 bus_space_write_1(sc->sc_iot, sc->sc_smb_ioh, PIIX_SMB_HC,
761 PIIX_SMB_HC_KILL);
762 DELAY(PIIXPM_DELAY);
763 st = bus_space_read_1(sc->sc_iot, sc->sc_smb_ioh, PIIX_SMB_HS);
764 if ((st & PIIX_SMB_HS_FAILED) == 0)
765 aprint_error_dev(sc->sc_dev,
766 "transaction abort failed, status 0x%x\n", st);
767 bus_space_write_1(sc->sc_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st);
768 /*
769 * CSB5 needs hard reset to unlock the smbus after timeout.
770 */
771 if (PIIXPM_IS_CSB5(sc))
772 piixpm_csb5_reset(sc);
773 mutex_exit(&sc->sc_exec_lock);
774 return (ETIMEDOUT);
775 }
776
777 static int
piixpm_intr(void * arg)778 piixpm_intr(void *arg)
779 {
780 struct piixpm_softc *sc = arg;
781 uint8_t st;
782 uint8_t *b;
783 size_t len;
784
785 /* Read status */
786 st = bus_space_read_1(sc->sc_iot, sc->sc_smb_ioh, PIIX_SMB_HS);
787 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR |
788 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR |
789 PIIX_SMB_HS_FAILED)) == 0)
790 /* Interrupt was not for us */
791 return (0);
792
793 DPRINTF(("%s: intr st %#x\n", device_xname(sc->sc_dev), st & 0xff));
794
795 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0)
796 mutex_enter(&sc->sc_exec_lock);
797
798 /* Clear status bits */
799 bus_space_write_1(sc->sc_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st);
800
801 /* Check for errors */
802 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR |
803 PIIX_SMB_HS_FAILED)) {
804 sc->sc_i2c_xfer.error = EIO;
805 goto done;
806 }
807
808 if (st & PIIX_SMB_HS_INTR) {
809 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op))
810 goto done;
811
812 /* Read data */
813 b = sc->sc_i2c_xfer.buf;
814 len = sc->sc_i2c_xfer.len;
815 if (len > 0)
816 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_smb_ioh,
817 PIIX_SMB_HD0);
818 if (len > 1)
819 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_smb_ioh,
820 PIIX_SMB_HD1);
821 }
822
823 done:
824 sc->sc_i2c_xfer.done = true;
825 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) {
826 cv_signal(&sc->sc_exec_wait);
827 mutex_exit(&sc->sc_exec_lock);
828 }
829 return (1);
830 }
831