1 /* $OpenBSD: ogxreg.h,v 1.3 2021/01/01 14:11:10 visa Exp $ */ 2 3 /* 4 * Copyright (c) 2019 Visa Hankala 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _OGXREG_H_ 20 #define _OGXREG_H_ 21 22 #define BGX_CMR_CONFIG 0x00000 23 #define BGX_CMR_CONFIG_ENABLE 0x0000000000008000ULL 24 #define BGX_CMR_CONFIG_DATA_PKT_RX_EN 0x0000000000004000ULL 25 #define BGX_CMR_CONFIG_DATA_PKT_TX_EN 0x0000000000002000ULL 26 #define BGX_CMR_CONFIG_INT_BEAT_GEN 0x0000000000001000ULL 27 #define BGX_CMR_CONFIG_MIX_EN 0x0000000000000800ULL 28 #define BGX_CMR_CONFIG_LMAC_TYPE_M 0x0000000000000700ULL 29 #define BGX_CMR_CONFIG_LMAC_TYPE_S 8 30 #define BGX_CMR_CONFIG_LANE_TO_SDS 0x00000000000000ffULL 31 32 #define BGX_CMR_RX_ID_MAP 0x00028 33 #define BGX_CMR_RX_ID_MAP_RID_M 0x0000000000007f00ULL 34 #define BGX_CMR_RX_ID_MAP_RID_S 8 35 #define BGX_CMR_RX_ID_MAP_PKND_M 0x00000000000000ffULL 36 #define BGX_CMR_RX_ID_MAP_PKND_S 0 37 38 #define BGX_CMR_RX_STAT0 0x00038 39 #define BGX_CMR_RX_STAT1 0x00040 40 #define BGX_CMR_RX_STAT2 0x00048 41 #define BGX_CMR_RX_STAT3 0x00050 42 #define BGX_CMR_RX_STAT4 0x00058 43 #define BGX_CMR_RX_STAT5 0x00060 44 #define BGX_CMR_RX_STAT6 0x00068 45 #define BGX_CMR_RX_STAT7 0x00070 46 #define BGX_CMR_RX_STAT8 0x00078 47 #define BGX_CMR_STAT_MASK 0x0000ffffffffffffULL 48 49 #define BGX_CMR_RX_ADR_CTL 0x000a0 50 #define BGX_CMR_RX_ADR_CTL_CAM_ACCEPT 0x0000000000000008ULL 51 #define BGX_CMR_RX_ADR_CTL_MCST_MODE 0x0000000000000006ULL 52 #define BGX_CMR_RX_ADR_CTL_MCST_MODE_ALL 0x0000000000000002ULL 53 #define BGX_CMR_RX_ADR_CTL_MCST_MODE_CAM 0x0000000000000004ULL 54 #define BGX_CMR_RX_ADR_CTL_BCST_ACCEPT 0x0000000000000001ULL 55 56 #define BGX_CMR_RX_FIFO_LEN 0x000c0 57 58 #define BGX_CMR_RX_ADR_CAM(i) (0x00100 + (i) * 8) 59 #define BGX_CMR_RX_ADR_CAM_ID 0x0030000000000000ULL 60 #define BGX_CMR_RX_ADR_CAM_ID_S 52 61 #define BGX_CMR_RX_ADR_CAM_EN 0x0001000000000000ULL 62 #define BGX_CMR_RX_ADR_CAM_ADR 0x0000ffffffffffffULL 63 64 #define BGX_CMR_CHAN_MSK_AND 0x00200 65 #define BGX_CMR_CHAN_MSK_OR 0x00208 66 67 #define BGX_CMR_RX_LMACS 0x00308 68 69 #define BGX_CMR_TX_FIFO_LEN 0x00418 70 71 #define BGX_CMR_TX_STAT0 0x00508 72 #define BGX_CMR_TX_STAT1 0x00510 73 #define BGX_CMR_TX_STAT2 0x00518 74 #define BGX_CMR_TX_STAT3 0x00520 75 #define BGX_CMR_TX_STAT4 0x00528 76 #define BGX_CMR_TX_STAT5 0x00530 77 #define BGX_CMR_TX_STAT6 0x00538 78 #define BGX_CMR_TX_STAT7 0x00540 79 #define BGX_CMR_TX_STAT8 0x00548 80 #define BGX_CMR_TX_STAT9 0x00550 81 #define BGX_CMR_TX_STAT10 0x00558 82 #define BGX_CMR_TX_STAT11 0x00560 83 #define BGX_CMR_TX_STAT12 0x00568 84 #define BGX_CMR_TX_STAT13 0x00570 85 #define BGX_CMR_TX_STAT14 0x00578 86 #define BGX_CMR_TX_STAT15 0x00580 87 #define BGX_CMR_TX_STAT16 0x00588 88 #define BGX_CMR_TX_STAT17 0x00590 89 90 #define BGX_CMR_TX_LMACS 0x01000 91 #define BGX_CMR_TX_LMACS_NUM_M 0x0000000000000007ULL 92 #define BGX_CMR_TX_LMACS_NUM_S 0 93 94 #define BGX_GMP_PCS_MR_CONTROL 0x30000 95 #define BGX_GMP_PCS_MR_CONTROL_RESET 0x0000000000008000ULL 96 #define BGX_GMP_PCS_MR_CONTROL_LOOPBCK1 0x0000000000004000ULL 97 #define BGX_GMP_PCS_MR_CONTROL_SPDLSB 0x0000000000002000ULL 98 #define BGX_GMP_PCS_MR_CONTROL_AN_EN 0x0000000000001000ULL 99 #define BGX_GMP_PCS_MR_CONTROL_PWR_DN 0x0000000000000800ULL 100 #define BGX_GMP_PCS_MR_CONTROL_RST_AN 0x0000000000000200ULL 101 #define BGX_GMP_PCS_MR_CONTROL_DUP 0x0000000000000100ULL 102 #define BGX_GMP_PCS_MR_CONTROL_COLTST 0x0000000000000080ULL 103 #define BGX_GMP_PCS_MR_CONTROL_SPDMSB 0x0000000000000040ULL 104 #define BGX_GMP_PCS_MR_CONTROL_UNI 0x0000000000000020ULL 105 106 #define BGX_GMP_PCS_MR_STATUS 0x30008 107 #define BGX_GMP_PCS_MR_STATUS_AN_CPT 0x0000000000000020ULL 108 109 #define BGX_GMP_PCS_LINK_TIMER 0x30040 110 #define BGX_GMP_PCS_LINK_TIMER_COUNT_M 0x000000000000ffffULL 111 112 #define BGX_GMP_PCS_RX_SYNC 0x30050 113 114 #define BGX_GMP_SGM_LP_ADV 0x30070 115 116 #define BGX_GMP_PCS_MISC_CTL 0x30078 117 #define BGX_GMP_PCS_MISC_CTL_SGMII 0x0000000000001000ULL 118 #define BGX_GMP_PCS_MISC_CTL_GMXENO 0x0000000000000800ULL 119 #define BGX_GMP_PCS_MISC_CTL_LOOPBCK2 0x0000000000000400ULL 120 #define BGX_GMP_PCS_MISC_CTL_MAC_PHY 0x0000000000000200ULL 121 #define BGX_GMP_PCS_MISC_CTL_MODE 0x0000000000000100ULL 122 #define BGX_GMP_PCS_MISC_CTL_AN_OVRD 0x0000000000000080ULL 123 #define BGX_GMP_PCS_MISC_CTL_SAMP_PT_M 0x000000000000007fULL 124 #define BGX_GMP_PCS_MISC_CTL_SAMP_PT_S 0 125 126 #define BGX_GMP_PCS_INT 0x30080 127 128 #define BGX_GMP_GMI_PRT_CFG 0x38010 129 #define BGX_GMP_GMI_PRT_CFG_TX_IDLE 0x0000000000002000ULL 130 #define BGX_GMP_GMI_PRT_CFG_RX_IDLE 0x0000000000001000ULL 131 #define BGX_GMP_GMI_PRT_CFG_SPEED_MSB 0x0000000000000100ULL 132 #define BGX_GMP_GMI_PRT_CFG_SLOTTIME 0x0000000000000008ULL 133 #define BGX_GMP_GMI_PRT_CFG_DUPLEX 0x0000000000000004ULL 134 #define BGX_GMP_GMI_PRT_CFG_SPEED 0x0000000000000002ULL 135 136 #define BGX_GMP_GMI_TX_THRESH 0x38210 137 #define BGX_GMP_GMI_TX_THRESH_M 0x00000000000007ffULL 138 139 #define BGX_GMP_GMI_TX_APPEND 0x38218 140 #define BGX_GMP_GMI_TX_APPEND_FORCE_FCS 0x0000000000000008ULL 141 #define BGX_GMP_GMI_TX_APPEND_FCS 0x0000000000000004ULL 142 #define BGX_GMP_GMI_TX_APPEND_PAD 0x0000000000000002ULL 143 #define BGX_GMP_GMI_TX_APPEND_PREAMBLE 0x0000000000000001ULL 144 145 #define BGX_GMP_GMI_TX_SLOT 0x38220 146 #define BGX_GMP_GMI_TX_SLOT_M 0x000000000000ffffULL 147 148 #define BGX_GMP_GMI_TX_BURST 0x38228 149 #define BGX_GMP_GMI_TX_BURST_M 0x000000000000ffffULL 150 151 #define BGX_GMP_GMI_TX_MIN_PKT 0x38240 152 #define BGX_GMP_GMI_TX_MIN_PKT_M 0x00000000000000ffULL 153 154 #define BGX_GMP_GMI_TX_SGMII_CTL 0x38300 155 #define BGX_GMP_GMI_TX_SGMII_CTL_ALIGN 0x0000000000000001ULL 156 157 #define FPA3_BASE 0x0001280000000000ULL 158 #define FPA3_SIZE 0x0000000100000000ULL 159 160 #define FPA3_LD_IO 0x0001000000000000ULL 161 #define FPA3_LD_DID 0x0000290000000000ULL 162 #define FPA3_LD_NODE_M 0x000000f000000000ULL 163 #define FPA3_LD_NODE_S 36 164 #define FPA3_LD_RED 0x0000000800000000ULL 165 #define FPA3_LD_AURA_M 0x0000000003ff0000ULL 166 #define FPA3_LD_AURA_S 16 167 168 #define FPA3_ST_IO 0x0001000000000000ULL 169 #define FPA3_ST_DID_FPA 0x0000290000000000ULL 170 #define FPA3_ST_DID_M 0x0000ff0000000000ULL 171 #define FPA3_ST_NODE_M 0x000000f000000000ULL 172 #define FPA3_ST_NODE_S 36 173 #define FPA3_ST_AURA_M 0x0000000003ff0000ULL 174 #define FPA3_ST_AURA_S 16 175 #define FPA3_ST_FABS 0x0000000000008000ULL 176 #define FPA3_ST_DWB_COUNT_M 0x0000000000000ff8ULL 177 #define FPA3_ST_DWB_COUNT_S 3 178 179 #define FPA3_POOL_CFG(i) (0x10000000ULL + (i) * 8) 180 #define FPA3_POOL_CFG_ENA 0x0000000000000001ULL 181 #define FPA3_POOL_START_ADDR(i) (0x10500000ULL + (i) * 8) 182 #define FPA3_POOL_END_ADDR(i) (0x10600000ULL + (i) * 8) 183 #define FPA3_POOL_STACK_BASE(i) (0x10700000ULL + (i) * 8) 184 #define FPA3_POOL_STACK_END(i) (0x10800000ULL + (i) * 8) 185 #define FPA3_POOL_STACK_ADDR(i) (0x10900000ULL + (i) * 8) 186 187 #define FPA3_AURA_POOL(i) (0x20000000ULL + (i) * 8) 188 #define FPA3_AURA_CFG(i) (0x20100000ULL + (i) * 8) 189 #define FPA3_AURA_CNT(i) (0x20200000ULL + (i) * 8) 190 #define FPA3_AURA_CNT_LIMIT(i) (0x20400000ULL + (i) * 8) 191 #define FPA3_AURA_CNT_THRESHOLD(i) (0x20500000ULL + (i) * 8) 192 #define FPA3_AURA_CNT_INT(i) (0x20600000ULL + (i) * 8) 193 #define FPA3_AURA_POOL_LEVELS(i) (0x20700000ULL + (i) * 8) 194 #define FPA3_AURA_CNT_LEVELS(i) (0x20800000ULL + (i) * 8) 195 196 /* 197 * PKO3 registers 198 */ 199 200 #define PKO3_BASE 0x0001540000000000ULL 201 #define PKO3_SIZE 0x0000000001000000ULL 202 203 #define PKO3_LD_IO 0x0001000000000000ULL 204 #define PKO3_LD_DID 0x0000510000000000ULL 205 #define PKO3_LD_NODE_M 0x000000f000000000ULL 206 #define PKO3_LD_NODE_S 36 207 #define PKO3_LD_OP_M 0x0000000300000000ULL 208 #define PKO3_LD_OP_S 32 209 #define PKO3_LD_DQ_M 0x0000000003ff0000ULL 210 #define PKO3_LD_DQ_S 16 211 212 #define PKO3_CHANNEL_LEVEL (0x000800f0ULL) 213 214 #define PKO3_L1_SQ_SHAPE(i) (0x00000010ULL + (i) * 512) 215 #define PKO3_L1_SQ_SHAPE_LINK_M 0x000000000003e000ULL 216 #define PKO3_L1_SQ_SHAPE_LINK_S 13 217 218 #define PKO3_L2_SQ_SHAPE(i) (0x00080010ULL + (i) * 512) 219 #define PKO3_L3_SQ_SHAPE(i) (0x00100010ULL + (i) * 512) 220 221 #define PKO3_L1_SQ_LINK(i) (0x00000038ULL + (i) * 512) 222 #define PKO3_L1_SQ_LINK_LINK_M 0x0001f00000000000ULL 223 #define PKO3_L1_SQ_LINK_LINK_S 44 224 #define PKO3_L1_SQ_LINK_CC_WORD_CNT_M 0x00000000fffff000ULL 225 #define PKO3_L1_SQ_LINK_CC_WORD_CNT_S 12 226 #define PKO3_L1_SQ_LINK_CC_PACKET_CNT_M 0x0000000000000ffcULL 227 #define PKO3_L1_SQ_LINK_CC_PACKET_CNT_S 2 228 #define PKO3_L1_SQ_LINK_CC_ENABLE 0x0000000000000002ULL 229 230 #define PKO3_DQ_WM_CTL(i) (0x00000040ULL + (i) * 512) 231 #define PKO3_DQ_WM_CTL_KIND 0x0002000000000000ULL 232 233 #define PKO3_L1_SQ_SW_XOFF(i) (0x000000e0ULL + (i) * 512) 234 #define PKO3_DQ_SW_XOFF(i) (0x002800e0ULL + (i) * 512) 235 #define PKO3_LX_SQ_SW_XOFF_DRAIN_NULL_LINK 0x0000000000000004ULL 236 #define PKO3_LX_SQ_SW_XOFF_DRAIN 0x0000000000000002ULL 237 238 #define PKO3_L1_SQ_SCHEDULE(i) (0x00000008ULL + (i) * 512) 239 #define PKO3_L2_SQ_SCHEDULE(i) (0x00080008ULL + (i) * 512) 240 #define PKO3_L3_SQ_SCHEDULE(i) (0x00100008ULL + (i) * 512) 241 #define PKO3_L4_SQ_SCHEDULE(i) (0x00180008ULL + (i) * 512) 242 #define PKO3_L5_SQ_SCHEDULE(i) (0x00200008ULL + (i) * 512) 243 #define PKO3_DQ_SCHEDULE(i) (0x00280008ULL + (i) * 512) 244 #define PKO3_LX_SQ_SCHEDULE_PRIO_M 0x000000000f000000ULL 245 #define PKO3_LX_SQ_SCHEDULE_PRIO_S 24 246 #define PKO3_LX_SQ_SCHEDULE_RR_QUANTUM_M 0x0000000000ffffffULL 247 #define PKO3_LX_SQ_SCHEDULE_RR_QUANTUM_S 0 248 249 #define PKO3_L1_SQ_TOPOLOGY(i) (0x00080000ULL + (i) * 512) 250 #define PKO3_L1_SQ_TOPOLOGY_PRIO_ANCHOR_M 0x000001ff00000000ULL 251 #define PKO3_L1_SQ_TOPOLOGY_PRIO_ANCHOR_S 32 252 #define PKO3_L1_SQ_TOPOLOGY_LINK_M 0x00000000001f0000ULL 253 #define PKO3_L1_SQ_TOPOLOGY_LINK_S 16 254 #define PKO3_L1_SQ_TOPOLOGY_RR_PRIO_M 0x000000000000001eULL 255 #define PKO3_L1_SQ_TOPOLOGY_RR_PRIO_S 1 256 257 #define PKO3_L3_L2_SQ_CHANNEL(i) (0x00080038ULL + (i) * 512) 258 #define PKO3_L3_L2_SQ_CHANNEL_M 0x00000fff00000000ULL 259 #define PKO3_L3_L2_SQ_CHANNEL_S 32 260 #define PKO3_L3_L2_SQ_CHANNEL_CC_ENABLE 0x0000000000000002ULL 261 262 #define PKO3_L2_SQ_TOPOLOGY(i) (0x00100000ULL + (i) * 512) 263 #define PKO3_L2_SQ_TOPOLOGY_PRIO_ANCHOR_M 0x000001ff00000000ULL 264 #define PKO3_L2_SQ_TOPOLOGY_PRIO_ANCHOR_S 32 265 #define PKO3_L2_SQ_TOPOLOGY_PARENT_M 0x00000000001f0000ULL 266 #define PKO3_L2_SQ_TOPOLOGY_PARENT_S 16 267 #define PKO3_L2_SQ_TOPOLOGY_RR_PRIO_M 0x000000000000001eULL 268 #define PKO3_L2_SQ_TOPOLOGY_RR_PRIO_S 1 269 270 #define PKO3_L3_SQ_TOPOLOGY(i) (0x00180000ULL + (i) * 512) 271 #define PKO3_L3_SQ_TOPOLOGY_PRIO_ANCHOR_M 0x000003ff00000000ULL 272 #define PKO3_L3_SQ_TOPOLOGY_PRIO_ANCHOR_S 32 273 #define PKO3_L3_SQ_TOPOLOGY_PARENT_M 0x0000000001ff0000ULL 274 #define PKO3_L3_SQ_TOPOLOGY_PARENT_S 16 275 #define PKO3_L3_SQ_TOPOLOGY_RR_PRIO_M 0x000000000000001eULL 276 #define PKO3_L3_SQ_TOPOLOGY_RR_PRIO_S 1 277 278 #define PKO3_L4_SQ_TOPOLOGY(i) (0x00200000ULL + (i) * 512) 279 #define PKO3_L4_SQ_TOPOLOGY_PRIO_ANCHOR_M 0x000003ff00000000ULL 280 #define PKO3_L4_SQ_TOPOLOGY_PRIO_ANCHOR_S 32 281 #define PKO3_L4_SQ_TOPOLOGY_PARENT_M 0x0000000001ff0000ULL 282 #define PKO3_L4_SQ_TOPOLOGY_PARENT_S 16 283 #define PKO3_L4_SQ_TOPOLOGY_RR_PRIO_M 0x000000000000001eULL 284 #define PKO3_L4_SQ_TOPOLOGY_RR_PRIO_S 1 285 286 #define PKO3_L5_SQ_TOPOLOGY(i) (0x00280000ULL + (i) * 512) 287 #define PKO3_L5_SQ_TOPOLOGY_PRIO_ANCHOR_M 0x000003ff00000000ULL 288 #define PKO3_L5_SQ_TOPOLOGY_PRIO_ANCHOR_S 32 289 #define PKO3_L5_SQ_TOPOLOGY_PARENT_M 0x0000000003ff0000ULL 290 #define PKO3_L5_SQ_TOPOLOGY_PARENT_S 16 291 #define PKO3_L5_SQ_TOPOLOGY_RR_PRIO_M 0x000000000000001eULL 292 #define PKO3_L5_SQ_TOPOLOGY_RR_PRIO_S 1 293 294 #define PKO3_DQ_TOPOLOGY(i) (0x00300000ULL + (i) * 512) 295 #define PKO3_DQ_TOPOLOGY_PARENT_M 0x0000000003ff0000ULL 296 #define PKO3_DQ_TOPOLOGY_PARENT_S 16 297 298 #define PKO3_PDM_CFG 0x00800000ULL 299 #define PKO3_PDM_CFG_DIS_LPD_W2R_FILL 0x0000000000001000ULL 300 #define PKO3_PDM_CFG_EN_FR_W2R_PTR_SWP 0x0000000000000800ULL 301 #define PKO3_PDM_CFG_DIS_FLSH_CACHE 0x0000000000000400ULL 302 #define PKO3_PDM_CFG_MIN_PAD_LEN_M 0x00000000000002f8ULL 303 #define PKO3_PDM_CFG_MIN_PAD_LEN_S 3 304 #define PKO3_PDM_CFG_DIAG_MODE 0x0000000000000004ULL 305 #define PKO3_PDM_CFG_ALLOC_LDS 0x0000000000000002ULL 306 #define PKO3_PDM_CFG_ALLOC_STS 0x0000000000000001ULL 307 308 #define PKO3_PDM_DQ_MINPAD(dq) (0x008f0000ULL + (dq) * 8) 309 #define PKO3_PDM_DQ_MINPAD_MINPAD 0x0000000000000001ULL 310 311 #define PKO3_MAC_CFG(mac) (0x00900000ULL + (mac) * 8) 312 #define PKO3_MAC_CFG_MIN_PAD_ENA 0x0000000000010000ULL 313 #define PKO3_MAC_CFG_FCS_ENA 0x0000000000008000ULL 314 #define PKO3_MAC_CFG_FCS_SOP_OFF_M 0x0000000000007f80ULL 315 #define PKO3_MAC_CFG_FCS_SOP_OFF_S 7 316 #define PKO3_MAC_CFG_SKID_MAX_CNT_M 0x0000000000000060ULL 317 #define PKO3_MAC_CFG_SKID_MAX_CNT_S 5 318 #define PKO3_MAC_CFG_FIFO_NUM_M 0x000000000000001fULL 319 #define PKO3_MAC_CFG_FIFO_NUM_S 0 320 321 #define PKO3_PTGF_CFG(i) (0x00900200ULL + (i) * 8) 322 #define PKO3_PTGF_CFG_RESET 0x0000000000000040ULL 323 #define PKO3_PTGF_CFG_RATE_M 0x0000000000000038ULL 324 #define PKO3_PTGF_CFG_RATE_S 3 325 #define PKO3_PTGF_CFG_SIZE_M 0x0000000000000007ULL 326 #define PKO3_PTGF_CFG_SIZE_S 0 327 328 #define PKO3_PTF_IOBP_CFG 0x00900300ULL 329 #define PKO3_PTF_IOBP_CFG_MAX_RD_SZ_M 0x000000000000007fULL 330 #define PKO3_PTF_IOBP_CFG_MAX_RD_SZ_S 0 331 332 #define PKO3_MCI0_MAX_CRED(mac) (0x00a00000ULL + (mac) * 8) 333 #define PKO3_MCI0_MAC_CRED_LIMIT 0x0000000000000fffULL 334 335 #define PKO3_MCI1_MAX_CRED(mac) (0x00a80000ULL + (mac) * 8) 336 #define PKO3_MCI1_CRED_CNT(mac) (0x00a80100ULL + (mac) * 8) 337 338 #define PKO3_LUT(i) (0x00b00000ULL + (i) * 8) 339 #define PKO3_LUT_VALID 0x0000000000008000ULL 340 #define PKO3_LUT_PQ_IDX_M 0x0000000000003e00ULL 341 #define PKO3_LUT_PQ_IDX_S 9 342 #define PKO3_LUT_QUEUE_NUM_M 0x00000000000001ffULL 343 #define PKO3_LUT_QUEUE_NUM_S 0 344 345 #define PKO3_DPFI_FLUSH 0x00c00008ULL 346 347 #define PKO3_DPFI_FPA_AURA 0x00c00010ULL 348 #define PKO3_DPFI_FPA_AURA_NODE_S 10 349 #define PKO3_DPFI_FPA_AURA_AURA_S 0 350 351 #define PKO3_DPFI_FPA_ENA 0x00c00018ULL 352 #define PKO3_DPFI_FPA_ENA_ENABLE 0x0000000000000001ULL 353 354 #define PKO3_STATUS 0x00d00000ULL 355 #define PKO3_STATUS_PKO_RDY 0x8000000000000000ULL 356 357 #define PKO3_ENABLE 0x00d00008ULL 358 #define PKO3_ENABLE_ENABLE 0x0000000000000001ULL 359 360 /* 361 * PKO commands 362 */ 363 364 #define PKO3_SEND_HDR_AURA 0x0fff000000000000ULL 365 #define PKO3_SEND_HDR_CKL4_M 0x0000c00000000000ULL 366 #define PKO3_SEND_HDR_CKL4_TCP 0x0000800000000000ULL 367 #define PKO3_SEND_HDR_CKL4_UDP 0x0000400000000000ULL 368 #define PKO3_SEND_HDR_CKL3 0x0000200000000000ULL 369 #define PKO3_SEND_HDR_DS 0x0000100000000000ULL 370 #define PKO3_SEND_HDR_LE 0x0000080000000000ULL 371 #define PKO3_SEND_HDR_N2 0x0000040000000000ULL 372 #define PKO3_SEND_HDR_II 0x0000020000000000ULL 373 #define PKO3_SEND_HDR_DF 0x0000010000000000ULL 374 #define PKO3_SEND_HDR_FORMAT 0x0000007f00000000ULL 375 #define PKO3_SEND_HDR_L4PTR_M 0x00000000ff000000ULL 376 #define PKO3_SEND_HDR_L4PTR_S 24 377 #define PKO3_SEND_HDR_L3PTR_M 0x0000000000ff0000ULL 378 #define PKO3_SEND_HDR_L3PTR_S 16 379 #define PKO3_SEND_HDR_TOTAL_M 0x000000000000ffffULL 380 #define PKO3_SEND_HDR_TOTAL_S 0 381 382 #define PKO3_LMTDMA_SCRADDR_M 0xff00000000000000ULL 383 #define PKO3_LMTDMA_SCRADDR_S 56 384 #define PKO3_LMTDMA_RTNLEN_M 0x00ff000000000000ULL 385 #define PKO3_LMTDMA_RTNLEN_S 48 386 #define PKO3_LMTDMA_DID 0x0000510000000000ULL 387 #define PKO3_LMTDMA_DID_M 0x0000ff0000000000ULL 388 #define PKO3_LMTDMA_NODE 0x000000f000000000ULL 389 #define PKO3_LMTDMA_DQOP 0x0000000300000000ULL 390 #define PKO3_LMTDMA_DQ_M 0x0000000003ff0000ULL 391 #define PKO3_LMTDMA_DQ_S 16 392 393 #define PKO3_DQOP_SEND 0x0ULL 394 #define PKO3_DQOP_OPEN 0x1ULL 395 #define PKO3_DQOP_CLOSE 0x2ULL 396 397 #define PKO3_SUBDC3_SEND_GATHER 0x1ULL 398 399 #define PKO3_SEND_SUBDC4_CODE_S 44 400 #define PKO3_SEND_SUBDC4_WORK 0xaULL 401 402 #define PKO3_SEND_WORK_CODE 0xaULL 403 404 #define PKO3_SEND_WORK_GRP_S 52 405 #define PKO3_SEND_WORK_TT_S 50 406 #define PKO3_SEND_WORK_ADDR_S 0 407 408 #define PKO3_SEND_ADDR_M 0x000003ffffffffffULL 409 #define PKO3_SEND_ADDR_S 0 410 411 #define PKO3_SUBC_BUF_PTR_SIZE_M 0xffff000000000000ULL 412 #define PKO3_SUBC_BUF_PTR_SIZE_S 48 413 #define PKO3_SUBC_BUF_PTR_SUBDC3_M 0x0000e00000000000ULL 414 #define PKO3_SUBC_BUF_PTR_SUBDC3_S 45 415 #define PKO3_SUBC_BUF_PTR_ADDR_M 0x000003ffffffffffULL 416 #define PKO3_SUBC_BUF_PTR_ADDR_S 0 417 418 /* 419 * PKI registers 420 */ 421 422 #define PKI_BASE 0x0001180044000000ULL 423 #define PKI_SIZE 0x0000000001000000ULL 424 425 #define PKI_ICG_CFG(i) (0x0000a000ULL + (i) * 8) 426 #define PKI_ICG_CFG_PENA 0x0000000001000000ULL 427 428 #define PKI_SFT_RST 0x00000010ULL 429 #define PKI_SFT_RST_BUSY 0x8000000000000000ULL 430 431 #define PKI_BUF_CTL 0x00000100ULL 432 #define PKI_BUF_CTL_PBP_EN 0x0000000000000001ULL 433 #define PKI_BUF_CTL_PKI_EN 0x0000000000000001ULL 434 435 #define PKI_STAT_CTL 0x00000110ULL 436 437 #define PKI_GBL_PEN 0x00000200ULL 438 #define PKI_GBL_PEN_M 0x00000000000003ffULL 439 #define PKI_GBL_PEN_VIRT 0x0000000000000200ULL 440 #define PKI_GBL_PEN_CLG 0x0000000000000100ULL 441 #define PKI_GBL_PEN_CL2 0x0000000000000080ULL 442 #define PKI_GBL_PEN_L4 0x0000000000000040ULL 443 #define PKI_GBL_PEN_IL3 0x0000000000000020ULL 444 #define PKI_GBL_PEN_L3 0x0000000000000010ULL 445 #define PKI_GBL_PEN_MPLS 0x0000000000000008ULL 446 #define PKI_GBL_PEN_FULC 0x0000000000000004ULL 447 #define PKI_GBL_PEN_DSA 0x0000000000000002ULL 448 #define PKI_GBL_PEN_HG 0x0000000000000001ULL 449 450 #define PKI_FRM_LEN_CHK(i) (0x00004000ULL + (i) * 8) 451 #define PKI_FRM_LEN_CHK_MAXLEN_M 0x00000000ffff0000ULL 452 #define PKI_FRM_LEN_CHK_MAXLEN_S 16 453 #define PKI_FRM_LEN_CHK_MINLEN_M 0x000000000000ffffULL 454 #define PKI_FRM_LEN_CHK_MINLEN_S 0 455 456 #define PKI_LTYPE_MAP(i) (0x00005000ULL + (i) * 8) 457 458 #define PKI_IMEM(i) (0x00100000ULL + (i) * 8) 459 460 #define PKI_QPG_TBL(i) (0x00800000ULL + (i) * 8) 461 #define PKI_QPG_TBL_PADD 0x0fff000000000000ULL 462 #define PKI_QPG_TBL_GRPTAG_OK 0x0000c00000000000ULL 463 #define PKI_QPG_TBL_GRP_OK_M 0x000003ff00000000ULL 464 #define PKI_QPG_TBL_GRP_OK_S 32 465 #define PKI_QPG_TBL_GRPTAG_BAD 0x00000000c0000000ULL 466 #define PKI_QPG_TBL_GRP_BAD_M 0x0000000003ff0000ULL 467 #define PKI_QPG_TBL_GRP_BAD_S 16 468 #define PKI_QPG_TBL_AURA_NODE_M 0x0000000000000c00ULL 469 #define PKI_QPG_TBL_AURA_NODE_S 10 470 #define PKI_QPG_TBL_LAURA_M 0x00000000000003ffULL 471 #define PKI_QPG_TBL_LAURA_S 0 472 473 #define PKI_STAT_BASE(i) (0x00e00000ULL + (i) * PKI_STAT_SIZE) 474 #define PKI_STAT_SIZE 0x100 475 476 #define PKI_STAT_HIST0 0x00 477 #define PKI_STAT_HIST1 0x08 478 #define PKI_STAT_HIST2 0x10 479 #define PKI_STAT_HIST3 0x18 480 #define PKI_STAT_HIST4 0x20 481 #define PKI_STAT_HIST5 0x28 482 #define PKI_STAT_HIST6 0x30 483 #define PKI_STAT_STAT0 0x38 484 #define PKI_STAT_STAT1 0x40 485 #define PKI_STAT_STAT2 0x48 486 #define PKI_STAT_STAT3 0x50 487 #define PKI_STAT_STAT4 0x58 488 #define PKI_STAT_STAT5 0x60 489 #define PKI_STAT_STAT6 0x68 490 #define PKI_STAT_STAT7 0x70 491 #define PKI_STAT_STAT8 0x78 492 #define PKI_STAT_STAT9 0x80 493 #define PKI_STAT_STAT10 0x88 494 #define PKI_STAT_STAT11 0x90 495 #define PKI_STAT_STAT12 0x98 496 #define PKI_STAT_STAT13 0xa0 497 #define PKI_STAT_STAT14 0xa8 498 #define PKI_STAT_STAT15 0xb0 499 #define PKI_STAT_STAT16 0xb8 500 #define PKI_STAT_STAT17 0xc0 501 #define PKI_STAT_STAT18 0xc8 502 #define PKI_STAT_MASK 0x0000ffffffffffffULL 503 504 #define PKI_STYLE_BUF(style) (0x0024000ULL + (style) * 8) 505 #define PKI_STYLE_BUF_PKT_LEND 0x0000000100000000ULL 506 #define PKI_STYLE_BUF_WQE_HSZ_M 0x00000000c0000000ULL 507 #define PKI_STYLE_BUF_WQE_HSZ_S 30 508 #define PKI_STYLE_BUF_WQE_SKIP_M 0x0000000030000000ULL 509 #define PKI_STYLE_BUF_WQE_SKIP_S 28 510 #define PKI_STYLE_BUF_FIRST_SKIP_M 0x000000000fc00000ULL 511 #define PKI_STYLE_BUF_FIRST_SKIP_S 22 512 #define PKI_STYLE_BUF_LATER_SKIP_M 0x00000000003f0000ULL 513 #define PKI_STYLE_BUF_LATER_SKIP_S 16 514 #define PKI_STYLE_BUF_OPC_MODE_M 0x000000000000c000ULL 515 #define PKI_STYLE_BUF_OPC_MODE_S 14 516 #define PKI_STYLE_BUF_DIS_WQ_DAT 0x0000000000002000ULL 517 #define PKI_STYLE_BUF_MB_SIZE_M 0x0000000000001fffULL 518 #define PKI_STYLE_BUF_MB_SIZE_S 0 519 520 #define PKI_CL_STYLE_CFG(cl, style) (0x00500000ULL + (cl) * 0x10000 + \ 521 (style) * 8) 522 #define PKI_CL_STYLE_CFG_IP6_UDP_OPT 0x0000000100000000ULL 523 #define PKI_CL_STYLE_CFG_LENERR_EN 0x0000000080000000ULL 524 #define PKI_CL_STYLE_CFG_LENERR_EQPAD 0x0000000040000000ULL 525 #define PKI_CL_STYLE_CFG_MINMAX_SEL 0x0000000020000000ULL 526 #define PKI_CL_STYLE_CFG_MAXERR_EN 0x0000000010000000ULL 527 #define PKI_CL_STYLE_CFG_MINERR_EN 0x0000000008000000ULL 528 #define PKI_CL_STYLE_CFG_QPG_DIS_GRPTAG 0x0000000004000000ULL 529 #define PKI_CL_STYLE_CFG_FCS_STRIP 0x0000000002000000ULL 530 #define PKI_CL_STYLE_CFG_FCS_CHK 0x0000000001000000ULL 531 #define PKI_CL_STYLE_CFG_RAWDRP 0x0000000000800000ULL 532 #define PKI_CL_STYLE_CFG_DROP 0x0000000000400000ULL 533 #define PKI_CL_STYLE_CFG_NODROP 0x0000000000200000ULL 534 #define PKI_CL_STYLE_CFG_QPG_DIS_PADD 0x0000000000100000ULL 535 #define PKI_CL_STYLE_CFG_QPG_DIS_GRP 0x0000000000080000ULL 536 #define PKI_CL_STYLE_CFG_QPG_DIS_AURA 0x0000000000040000ULL 537 #define PKI_CL_STYLE_CFG_QPG_BASE_M 0x00000000000007ffULL 538 #define PKI_CL_STYLE_CFG_QPG_BASE_S 0 539 540 #define PKI_CL_PKIND_STYLE(cl, pkind) (0x00300048ULL + (cl) * 0x10000 + \ 541 (pkind) * 0x100) 542 #define PKI_CL_PKIND_STYLE_PM_M 0x0000000000007f00ULL 543 #define PKI_CL_PKIND_STYLE_PM_S 8 544 #define PKI_CL_PKIND_STYLE_STYLE_M 0x00000000000000ffULL 545 #define PKI_CL_PKIND_STYLE_STYLE_S 0 546 547 #define PKI_CL_STYLE_CFG2(cl, style) (0x00500800ULL + (cl) * 0x10000 + \ 548 (style) * 8) 549 #define PKI_CL_STYLE_ALG(cl, style) (0x00501000ULL + (cl) * 0x10000 + \ 550 (style) * 8) 551 552 #define PKI_CL_PCAM_TERM(cl, bank, i) (0x00700000ULL + (cl) * 0x10000 + \ 553 (bank) * 0x100 + (i) * 8) 554 555 /* 556 * SSO registers 557 */ 558 559 #define SSO_BASE 0x0001670000000000ULL 560 #define SSO_SIZE 0x0000000100000000ULL 561 562 #define SSO_LD_IO 0x0001000000000000ULL 563 #define SSO_LD_DID 0x0000600000000000ULL 564 #define SSO_LD_NODE_M 0x000000f000000000ULL 565 #define SSO_LD_NODE_S 36 566 #define SSO_LD_INDEXED 0x0000000080000000ULL 567 #define SSO_LD_GROUPED 0x0000000040000000ULL 568 #define SSO_LD_RTNGRP 0x0000000020000000ULL 569 #define SSO_LD_INDEX_M 0x000000000000fff0ULL 570 #define SSO_LD_INDEX_S 4 571 #define SSO_LD_WAIT 0x0000000000000008ULL 572 573 /* SSO LD response */ 574 #define SSO_LD_RTN_NO_WORK 0x8000000000000000ULL 575 #define SSO_LD_RTN_ADDR_M 0x000003ffffffffffULL 576 577 #define SSO_WQ_INT 0x00001000ULL 578 579 #define SSO_ERR0 0x00001240ULL 580 #define SSO_ERR1 0x00001248ULL 581 582 #define SSO_AW_CFG 0x000010f0ULL 583 #define SSO_AW_CFG_STT 0x0000000000000008ULL 584 #define SSO_AW_CFG_LDT 0x0000000000000004ULL 585 #define SSO_AW_CFG_LDWB 0x0000000000000002ULL 586 #define SSO_AW_CFG_RWEN 0x0000000000000001ULL 587 588 #define SSO_XAQ_AURA 0x00002100ULL 589 #define SSO_XAQ_AURA_NODE_M 0x0000000000000c00ULL 590 #define SSO_XAQ_AURA_NODE_S 10 591 #define SSO_XAQ_AURA_LAURA_M 0x00000000000003ffULL 592 #define SSO_XAQ_AURA_LAURA_S 0 593 594 #define SSO_XAQ_HEAD_PTR(i) (0x00080000ULL + (i) * 8) 595 #define SSO_XAQ_TAIL_PTR(i) (0x00090000ULL + (i) * 8) 596 #define SSO_XAQ_HEAD_NEXT(i) (0x000a0000ULL + (i) * 8) 597 #define SSO_XAQ_TAIL_NEXT(i) (0x000b0000ULL + (i) * 8) 598 599 #define SSO_GRP_PRI(group) (0x20000200ULL + (group) * 0x10000) 600 #define SSO_GRP_PRI_WEIGHT_M 0x00000000003f0000ULL 601 #define SSO_GRP_PRI_WEIGHT_S 16 602 603 #define SSO_GRP_INT(group) (0x20000400ULL + (group) * 0x10000) 604 #define SSO_GRP_INT_EXE_DIS 0x8000000000000000ULL 605 #define SSO_GRP_INT_EXE_INT 0x0000000000000002ULL 606 607 #define SSO_GRP_INT_THR(group) (0x20000500ULL + (group) * 0x10000) 608 #define SSO_GRP_INT_THR_IAQ_THR_M 0x0000000000001fffULL 609 610 #define SSO_GRP_AQ_CNT(group) (0x20000700ULL + (group) * 0x10000) 611 612 #define SSO_PP_GRPMSK(core, set, i) (0x40001000ULL + (core) * 0x10000 + \ 613 (set) * 0x20 + (i) * 8) 614 615 #define PKI_WORD0_BUFS_M 0x00000000ff000000ULL 616 #define PKI_WORD0_BUFS_S 24 617 #define PKI_WORD0_PKIND_M 0x000000000000003fULL 618 #define PKI_WORD0_PKIND_S 0 619 620 #define PKI_WORD1_LEN_M 0xffff000000000000ULL 621 #define PKI_WORD1_LEN_S 48 622 #define PKI_WORD1_TAG_M 0x00000000ffffffffULL 623 #define PKI_WORD1_TAG_S 0 624 625 #define PKI_WORD2_SW_FLAG 0x8000000000000000ULL 626 #define PKI_WORD2_LG_HDR_TYPE 0x7c00000000000000ULL 627 #define PKI_WORD2_LF_HDR_TYPE 0x03e0000000000000ULL 628 #define PKI_WORD2_LE_HDR_TYPE 0x001f000000000000ULL 629 #define PKI_WORD2_LD_HDR_TYPE 0x0000f80000000000ULL 630 #define PKI_WORD2_LC_HDR_TYPE 0x000007c000000000ULL 631 #define PKI_WORD2_LB_HDR_TYPE 0x0000003e00000000ULL 632 #define PKI_WORD2_IS_LA_ETHER 0x0000000100000000ULL 633 #define PKI_WORD2_VLAN_VALID 0x0000000000800000ULL 634 #define PKI_WORD2_VLAN_STACKED 0x0000000000400000ULL 635 #define PKI_WORD2_STAT_INC 0x0000000000200000ULL 636 #define PKI_WORD2_PCAM_FLAG_M 0x00000000001e0000ULL 637 #define PKI_WORD2_IS_FRAG 0x0000000000010000ULL 638 #define PKI_WORD2_IS_L3_BCAST 0x0000000000008000ULL 639 #define PKI_WORD2_IS_L3_MCAST 0x0000000000004000ULL 640 #define PKI_WORD2_IS_L2_BCAST 0x0000000000002000ULL 641 #define PKI_WORD2_IS_L2_MCAST 0x0000000000001000ULL 642 #define PKI_WORD2_IS_RAW 0x0000000000000800ULL 643 #define PKI_WORD2_ERR_LEVEL_M 0x0000000000000700ULL 644 #define PKI_WORD2_ERR_LEVEL_S 8 645 #define PKI_WORD2_ERR_CODE_M 0x00000000000000ffULL 646 #define PKI_WORD2_ERR_CODE_S 0 647 648 #define PKI_WORD3_SIZE_M 0xffff000000000000ULL 649 #define PKI_WORD3_SIZE_S 48 650 #define PKI_WORD3_ADDR_M 0x000003ffffffffffULL 651 #define PKI_WORD3_ADDR_S 0 652 653 #define PKO3_L1_SQ_SHAPE_STATE(i) (0x00000030ULL + (i) * 512) 654 #define PKO3_L2_SQ_SHAPE_STATE(i) (0x00080030ULL + (i) * 512) 655 #define PKO3_L3_SQ_SHAPE_STATE(i) (0x00100030ULL + (i) * 512) 656 #define PKO3_DQ_SHAPE_STATE(i) (0x00280030ULL + (i) * 512) 657 658 #define PKO3_PTF_STATUS(i) (0x00900100ULL + (i) * 8) 659 660 #endif /* !_OGXREG_H_ */ 661