1 //===- AArch64RegisterBankInfo -----------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the RegisterBankInfo class for AArch64. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H 14 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H 15 16 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 17 18 #define GET_REGBANK_DECLARATIONS 19 #include "AArch64GenRegisterBank.inc" 20 21 namespace llvm { 22 23 class TargetRegisterInfo; 24 25 class AArch64GenRegisterBankInfo : public RegisterBankInfo { 26 protected: 27 enum PartialMappingIdx { 28 PMI_None = -1, 29 PMI_FPR16 = 1, 30 PMI_FPR32, 31 PMI_FPR64, 32 PMI_FPR128, 33 PMI_FPR256, 34 PMI_FPR512, 35 PMI_GPR32, 36 PMI_GPR64, 37 PMI_GPR128, 38 PMI_FirstGPR = PMI_GPR32, 39 PMI_LastGPR = PMI_GPR128, 40 PMI_FirstFPR = PMI_FPR16, 41 PMI_LastFPR = PMI_FPR512, 42 PMI_Min = PMI_FirstFPR, 43 }; 44 45 static RegisterBankInfo::PartialMapping PartMappings[]; 46 static RegisterBankInfo::ValueMapping ValMappings[]; 47 static PartialMappingIdx BankIDToCopyMapIdx[]; 48 49 enum ValueMappingIdx { 50 InvalidIdx = 0, 51 First3OpsIdx = 1, 52 Last3OpsIdx = 25, 53 DistanceBetweenRegBanks = 3, 54 FirstCrossRegCpyIdx = 28, 55 LastCrossRegCpyIdx = 42, 56 DistanceBetweenCrossRegCpy = 2, 57 FPExt16To32Idx = 44, 58 FPExt16To64Idx = 46, 59 FPExt32To64Idx = 48, 60 FPExt64To128Idx = 50, 61 Shift64Imm = 52, 62 }; 63 64 static bool checkPartialMap(unsigned Idx, unsigned ValStartIdx, 65 unsigned ValLength, const RegisterBank &RB); 66 static bool checkValueMapImpl(unsigned Idx, unsigned FirstInBank, 67 unsigned Size, unsigned Offset); 68 static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias, 69 PartialMappingIdx LastAlias, 70 ArrayRef<PartialMappingIdx> Order); 71 72 static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size); 73 74 /// Get the pointer to the ValueMapping representing the RegisterBank 75 /// at \p RBIdx with a size of \p Size. 76 /// 77 /// The returned mapping works for instructions with the same kind of 78 /// operands for up to 3 operands. 79 /// 80 /// \pre \p RBIdx != PartialMappingIdx::None 81 static const RegisterBankInfo::ValueMapping * 82 getValueMapping(PartialMappingIdx RBIdx, unsigned Size); 83 84 /// Get the pointer to the ValueMapping of the operands of a copy 85 /// instruction from the \p SrcBankID register bank to the \p DstBankID 86 /// register bank with a size of \p Size. 87 static const RegisterBankInfo::ValueMapping * 88 getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size); 89 90 /// Get the instruction mapping for G_FPEXT. 91 /// 92 /// \pre (DstSize, SrcSize) pair is one of the following: 93 /// (32, 16), (64, 16), (64, 32), (128, 64) 94 /// 95 /// \return An InstructionMapping with statically allocated OperandsMapping. 96 static const RegisterBankInfo::ValueMapping * 97 getFPExtMapping(unsigned DstSize, unsigned SrcSize); 98 99 #define GET_TARGET_REGBANK_CLASS 100 #include "AArch64GenRegisterBank.inc" 101 }; 102 103 /// This class provides the information for the target register banks. 104 class AArch64RegisterBankInfo final : public AArch64GenRegisterBankInfo { 105 /// See RegisterBankInfo::applyMapping. 106 void applyMappingImpl(const OperandsMapper &OpdMapper) const override; 107 108 /// Get an instruction mapping where all the operands map to 109 /// the same register bank and have similar size. 110 /// 111 /// \pre MI.getNumOperands() <= 3 112 /// 113 /// \return An InstructionMappings with a statically allocated 114 /// OperandsMapping. 115 const InstructionMapping & 116 getSameKindOfOperandsMapping(const MachineInstr &MI) const; 117 118 /// Maximum recursion depth for hasFPConstraints. 119 const unsigned MaxFPRSearchDepth = 2; 120 121 /// \returns true if \p MI only uses and defines FPRs. 122 bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI, 123 const TargetRegisterInfo &TRI, unsigned Depth = 0) const; 124 125 /// \returns true if \p MI only uses FPRs. 126 bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI, 127 const TargetRegisterInfo &TRI, unsigned Depth = 0) const; 128 129 /// \returns true if \p MI only defines FPRs. 130 bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI, 131 const TargetRegisterInfo &TRI, unsigned Depth = 0) const; 132 133 public: 134 AArch64RegisterBankInfo(const TargetRegisterInfo &TRI); 135 136 unsigned copyCost(const RegisterBank &A, const RegisterBank &B, 137 unsigned Size) const override; 138 139 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, 140 LLT) const override; 141 142 InstructionMappings 143 getInstrAlternativeMappings(const MachineInstr &MI) const override; 144 145 const InstructionMapping & 146 getInstrMapping(const MachineInstr &MI) const override; 147 }; 148 } // End llvm namespace. 149 #endif 150