1 //! Static, named definitions of instruction opcodes. 2 3 /// Empty opcode for use as a default. 4 pub static EMPTY: [u8; 0] = []; 5 6 /// Add with carry flag r{16,32,64} to r/m of the same size. 7 pub static ADC: [u8; 1] = [0x11]; 8 9 /// Add r{16,32,64} to r/m of the same size. 10 pub static ADD: [u8; 1] = [0x01]; 11 12 /// Add imm{16,32} to r/m{16,32,64}, possibly sign-extended. 13 pub static ADD_IMM: [u8; 1] = [0x81]; 14 15 /// Add sign-extended imm8 to r/m{16,32,64}. 16 pub static ADD_IMM8_SIGN_EXTEND: [u8; 1] = [0x83]; 17 18 /// Add packed double-precision floating-point values from xmm2/mem to xmm1 and store result in 19 /// xmm1 (SSE2). 20 pub static ADDPD: [u8; 3] = [0x66, 0x0f, 0x58]; 21 22 /// Add packed single-precision floating-point values from xmm2/mem to xmm1 and store result in 23 /// xmm1 (SSE). 24 pub static ADDPS: [u8; 2] = [0x0f, 0x58]; 25 26 /// Add the low double-precision floating-point value from xmm2/mem to xmm1 27 /// and store the result in xmm1. 28 pub static ADDSD: [u8; 3] = [0xf2, 0x0f, 0x58]; 29 30 /// Add the low single-precision floating-point value from xmm2/mem to xmm1 31 /// and store the result in xmm1. 32 pub static ADDSS: [u8; 3] = [0xf3, 0x0f, 0x58]; 33 34 /// r/m{16,32,64} AND register of the same size (Intel docs have a typo). 35 pub static AND: [u8; 1] = [0x21]; 36 37 /// imm{16,32} AND r/m{16,32,64}, possibly sign-extended. 38 pub static AND_IMM: [u8; 1] = [0x81]; 39 40 /// r/m{16,32,64} AND sign-extended imm8. 41 pub static AND_IMM8_SIGN_EXTEND: [u8; 1] = [0x83]; 42 43 /// Return the bitwise logical AND NOT of packed single-precision floating-point 44 /// values in xmm1 and xmm2/mem. 45 pub static ANDNPS: [u8; 2] = [0x0f, 0x55]; 46 47 /// Return the bitwise logical AND of packed single-precision floating-point values 48 /// in xmm1 and xmm2/mem. 49 pub static ANDPS: [u8; 2] = [0x0f, 0x54]; 50 51 /// Bit scan forward (stores index of first encountered 1 from the front). 52 pub static BIT_SCAN_FORWARD: [u8; 2] = [0x0f, 0xbc]; 53 54 /// Bit scan reverse (stores index of first encountered 1 from the back). 55 pub static BIT_SCAN_REVERSE: [u8; 2] = [0x0f, 0xbd]; 56 57 /// Call near, relative, displacement relative to next instruction (sign-extended). 58 pub static CALL_RELATIVE: [u8; 1] = [0xe8]; 59 60 /// Move r/m{16,32,64} if overflow (OF=1). 61 pub static CMOV_OVERFLOW: [u8; 2] = [0x0f, 0x40]; 62 63 /// Compare imm{16,32} with r/m{16,32,64} (sign-extended if 64). 64 pub static CMP_IMM: [u8; 1] = [0x81]; 65 66 /// Compare imm8 with r/m{16,32,64}. 67 pub static CMP_IMM8: [u8; 1] = [0x83]; 68 69 /// Compare r{16,32,64} with r/m of the same size. 70 pub static CMP_REG: [u8; 1] = [0x39]; 71 72 /// Compare packed double-precision floating-point value in xmm2/m32 and xmm1 using bits 2:0 of 73 /// imm8 as comparison predicate (SSE2). 74 pub static CMPPD: [u8; 3] = [0x66, 0x0f, 0xc2]; 75 76 /// Compare packed single-precision floating-point value in xmm2/m32 and xmm1 using bits 2:0 of 77 /// imm8 as comparison predicate (SSE). 78 pub static CMPPS: [u8; 2] = [0x0f, 0xc2]; 79 80 /// Convert four packed signed doubleword integers from xmm2/mem to four packed single-precision 81 /// floating-point values in xmm1 (SSE2). 82 pub static CVTDQ2PS: [u8; 2] = [0x0f, 0x5b]; 83 84 /// Convert scalar double-precision floating-point value to scalar single-precision 85 /// floating-point value. 86 pub static CVTSD2SS: [u8; 3] = [0xf2, 0x0f, 0x5a]; 87 88 /// Convert doubleword integer to scalar double-precision floating-point value. 89 pub static CVTSI2SD: [u8; 3] = [0xf2, 0x0f, 0x2a]; 90 91 /// Convert doubleword integer to scalar single-precision floating-point value. 92 pub static CVTSI2SS: [u8; 3] = [0xf3, 0x0f, 0x2a]; 93 94 /// Convert scalar single-precision floating-point value to scalar double-precision 95 /// float-point value. 96 pub static CVTSS2SD: [u8; 3] = [0xf3, 0x0f, 0x5a]; 97 98 /// Convert with truncation scalar double-precision floating-point value to signed 99 /// integer. 100 pub static CVTTSD2SI: [u8; 3] = [0xf2, 0x0f, 0x2c]; 101 102 /// Convert with truncation scalar single-precision floating-point value to integer. 103 pub static CVTTSS2SI: [u8; 3] = [0xf3, 0x0f, 0x2c]; 104 105 /// Unsigned divide for {16,32,64}-bit. 106 pub static DIV: [u8; 1] = [0xf7]; 107 108 /// Divide packed double-precision floating-point values in xmm1 by packed double-precision 109 /// floating-point values in xmm2/mem (SSE2). 110 pub static DIVPD: [u8; 3] = [0x66, 0x0f, 0x5e]; 111 112 /// Divide packed single-precision floating-point values in xmm1 by packed single-precision 113 /// floating-point values in xmm2/mem (SSE). 114 pub static DIVPS: [u8; 2] = [0x0f, 0x5e]; 115 116 /// Divide low double-precision floating-point value in xmm1 by low double-precision 117 /// floating-point value in xmm2/m64. 118 pub static DIVSD: [u8; 3] = [0xf2, 0x0f, 0x5e]; 119 120 /// Divide low single-precision floating-point value in xmm1 by low single-precision 121 /// floating-point value in xmm2/m32. 122 pub static DIVSS: [u8; 3] = [0xf3, 0x0f, 0x5e]; 123 124 /// Signed divide for {16,32,64}-bit. 125 pub static IDIV: [u8; 1] = [0xf7]; 126 127 /// Signed multiply for {16,32,64}-bit, generic registers. 128 pub static IMUL: [u8; 2] = [0x0f, 0xaf]; 129 130 /// Signed multiply for {16,32,64}-bit, storing into RDX:RAX. 131 pub static IMUL_RDX_RAX: [u8; 1] = [0xf7]; 132 133 /// Insert scalar single-precision floating-point value. 134 pub static INSERTPS: [u8; 4] = [0x66, 0x0f, 0x3a, 0x21]; 135 136 /// Either: 137 /// 1. Jump near, absolute indirect, RIP = 64-bit offset from register or memory. 138 /// 2. Jump far, absolute indirect, address given in m16:64. 139 pub static JUMP_ABSOLUTE: [u8; 1] = [0xff]; 140 141 /// Jump near, relative, RIP = RIP + 32-bit displacement sign extended to 64 bits. 142 pub static JUMP_NEAR_RELATIVE: [u8; 1] = [0xe9]; 143 144 /// Jump near (rel32) if overflow (OF=1). 145 pub static JUMP_NEAR_IF_OVERFLOW: [u8; 2] = [0x0f, 0x80]; 146 147 /// Jump short, relative, RIP = RIP + 8-bit displacement sign extended to 64 bits. 148 pub static JUMP_SHORT: [u8; 1] = [0xeb]; 149 150 /// Jump short (rel8) if equal (ZF=1). 151 pub static JUMP_SHORT_IF_EQUAL: [u8; 1] = [0x74]; 152 153 /// Jump short (rel8) if not equal (ZF=0). 154 pub static JUMP_SHORT_IF_NOT_EQUAL: [u8; 1] = [0x75]; 155 156 /// Jump short (rel8) if overflow (OF=1). 157 pub static JUMP_SHORT_IF_OVERFLOW: [u8; 1] = [0x70]; 158 159 /// Store effective address for m in register r{16,32,64}. 160 pub static LEA: [u8; 1] = [0x8d]; 161 162 /// Count the number of leading zero bits. 163 pub static LZCNT: [u8; 3] = [0xf3, 0x0f, 0xbd]; 164 165 /// Return the maximum packed double-precision floating-point values between xmm1 and xmm2/m128 166 /// (SSE2). 167 pub static MAXPD: [u8; 3] = [0x66, 0x0f, 0x5f]; 168 169 /// Return the maximum packed single-precision floating-point values between xmm1 and xmm2/m128 170 /// (SSE). 171 pub static MAXPS: [u8; 2] = [0x0f, 0x5f]; 172 173 /// Return the maximum scalar double-precision floating-point value between 174 /// xmm2/m64 and xmm1. 175 pub static MAXSD: [u8; 3] = [0xf2, 0x0f, 0x5f]; 176 177 /// Return the maximum scalar single-precision floating-point value between 178 /// xmm2/m32 and xmm1. 179 pub static MAXSS: [u8; 3] = [0xf3, 0x0f, 0x5f]; 180 181 /// Return the minimum packed double-precision floating-point values between xmm1 and xmm2/m128 182 /// (SSE2). 183 pub static MINPD: [u8; 3] = [0x66, 0x0f, 0x5d]; 184 185 /// Return the minimum packed single-precision floating-point values between xmm1 and xmm2/m128 186 /// (SSE). 187 pub static MINPS: [u8; 2] = [0x0f, 0x5d]; 188 189 /// Return the minimum scalar double-precision floating-point value between 190 /// xmm2/m64 and xmm1. 191 pub static MINSD: [u8; 3] = [0xf2, 0x0f, 0x5d]; 192 193 /// Return the minimum scalar single-precision floating-point value between 194 /// xmm2/m32 and xmm1. 195 pub static MINSS: [u8; 3] = [0xf3, 0x0f, 0x5d]; 196 197 /// Move r8 to r/m8. 198 pub static MOV_BYTE_STORE: [u8; 1] = [0x88]; 199 200 /// Move imm{16,32,64} to same-sized register. 201 pub static MOV_IMM: [u8; 1] = [0xb8]; 202 203 /// Move imm{16,32} to r{16,32,64}, sign-extended if 64-bit target. 204 pub static MOV_IMM_SIGNEXTEND: [u8; 1] = [0xc7]; 205 206 /// Move {r/m16, r/m32, r/m64} to same-sized register. 207 pub static MOV_LOAD: [u8; 1] = [0x8b]; 208 209 /// Move r16 to r/m16. 210 pub static MOV_STORE_16: [u8; 2] = [0x66, 0x89]; 211 212 /// Move {r16, r32, r64} to same-sized register or memory. 213 pub static MOV_STORE: [u8; 1] = [0x89]; 214 215 /// Move aligned packed single-precision floating-point values from x/m to xmm (SSE). 216 pub static MOVAPS_LOAD: [u8; 2] = [0x0f, 0x28]; 217 218 /// Move doubleword from r/m32 to xmm (SSE2). Quadword with REX prefix. 219 pub static MOVD_LOAD_XMM: [u8; 3] = [0x66, 0x0f, 0x6e]; 220 221 /// Move doubleword from xmm to r/m32 (SSE2). Quadword with REX prefix. 222 pub static MOVD_STORE_XMM: [u8; 3] = [0x66, 0x0f, 0x7e]; 223 224 /// Move packed single-precision floating-point values low to high (SSE). 225 pub static MOVLHPS: [u8; 2] = [0x0f, 0x16]; 226 227 /// Move scalar double-precision floating-point value (from reg/mem to reg). 228 pub static MOVSD_LOAD: [u8; 3] = [0xf2, 0x0f, 0x10]; 229 230 /// Move scalar double-precision floating-point value (from reg to reg/mem). 231 pub static MOVSD_STORE: [u8; 3] = [0xf2, 0x0f, 0x11]; 232 233 /// Move scalar single-precision floating-point value (from reg to reg/mem). 234 pub static MOVSS_STORE: [u8; 3] = [0xf3, 0x0f, 0x11]; 235 236 /// Move scalar single-precision floating-point-value (from reg/mem to reg). 237 pub static MOVSS_LOAD: [u8; 3] = [0xf3, 0x0f, 0x10]; 238 239 /// Move byte to register with sign-extension. 240 pub static MOVSX_BYTE: [u8; 2] = [0x0f, 0xbe]; 241 242 /// Move word to register with sign-extension. 243 pub static MOVSX_WORD: [u8; 2] = [0x0f, 0xbf]; 244 245 /// Move doubleword to register with sign-extension. 246 pub static MOVSXD: [u8; 1] = [0x63]; 247 248 /// Move unaligned packed single-precision floating-point from x/m to xmm (SSE). 249 pub static MOVUPS_LOAD: [u8; 2] = [0x0f, 0x10]; 250 251 /// Move unaligned packed single-precision floating-point value from xmm to x/m (SSE). 252 pub static MOVUPS_STORE: [u8; 2] = [0x0f, 0x11]; 253 254 /// Move byte to register with zero-extension. 255 pub static MOVZX_BYTE: [u8; 2] = [0x0f, 0xb6]; 256 257 /// Move word to register with zero-extension. 258 pub static MOVZX_WORD: [u8; 2] = [0x0f, 0xb7]; 259 260 /// Unsigned multiply for {16,32,64}-bit. 261 pub static MUL: [u8; 1] = [0xf7]; 262 263 /// Multiply packed double-precision floating-point values from xmm2/mem to xmm1 and store result 264 /// in xmm1 (SSE2). 265 pub static MULPD: [u8; 3] = [0x66, 0x0f, 0x59]; 266 267 /// Multiply packed single-precision floating-point values from xmm2/mem to xmm1 and store result 268 /// in xmm1 (SSE). 269 pub static MULPS: [u8; 2] = [0x0f, 0x59]; 270 271 /// Multiply the low double-precision floating-point value in xmm2/m64 by the 272 /// low double-precision floating-point value in xmm1. 273 pub static MULSD: [u8; 3] = [0xf2, 0x0f, 0x59]; 274 275 /// Multiply the low single-precision floating-point value in xmm2/m32 by the 276 /// low single-precision floating-point value in xmm1. 277 pub static MULSS: [u8; 3] = [0xf3, 0x0f, 0x59]; 278 279 /// Reverse each bit of r/m{16,32,64}. 280 pub static NOT: [u8; 1] = [0xf7]; 281 282 /// r{16,32,64} OR register of same size. 283 pub static OR: [u8; 1] = [0x09]; 284 285 /// imm{16,32} OR r/m{16,32,64}, possibly sign-extended. 286 pub static OR_IMM: [u8; 1] = [0x81]; 287 288 /// r/m{16,32,64} OR sign-extended imm8. 289 pub static OR_IMM8_SIGN_EXTEND: [u8; 1] = [0x83]; 290 291 /// Return the bitwise logical OR of packed single-precision values in xmm and x/m (SSE). 292 pub static ORPS: [u8; 2] = [0x0f, 0x56]; 293 294 /// Converts 8 packed signed word integers from xmm1 and from xxm2/m128 into 16 packed signed byte 295 /// integers in xmm1 using signed saturation (SSE2). 296 pub static PACKSSWB: [u8; 3] = [0x66, 0x0f, 0x63]; 297 298 /// Converts 4 packed signed doubleword integers from xmm1 and from xmm2/m128 into 8 packed signed 299 /// word integers in xmm1 using signed saturation (SSE2). 300 pub static PACKSSDW: [u8; 3] = [0x66, 0x0f, 0x6b]; 301 302 /// Add packed byte integers from xmm2/m128 and xmm1 (SSE2). 303 pub static PADDB: [u8; 3] = [0x66, 0x0f, 0xfc]; 304 305 /// Add packed doubleword integers from xmm2/m128 and xmm1 (SSE2). 306 pub static PADDD: [u8; 3] = [0x66, 0x0f, 0xfe]; 307 308 /// Add packed quadword integers from xmm2/m128 and xmm1 (SSE2). 309 pub static PADDQ: [u8; 3] = [0x66, 0x0f, 0xd4]; 310 311 /// Add packed word integers from xmm2/m128 and xmm1 (SSE2). 312 pub static PADDW: [u8; 3] = [0x66, 0x0f, 0xfd]; 313 314 /// Add packed signed byte integers from xmm2/m128 and xmm1 saturate the results (SSE). 315 pub static PADDSB: [u8; 3] = [0x66, 0x0f, 0xec]; 316 317 /// Add packed signed word integers from xmm2/m128 and xmm1 saturate the results (SSE). 318 pub static PADDSW: [u8; 3] = [0x66, 0x0f, 0xed]; 319 320 /// Add packed unsigned byte integers from xmm2/m128 and xmm1 saturate the results (SSE). 321 pub static PADDUSB: [u8; 3] = [0x66, 0x0f, 0xdc]; 322 323 /// Add packed unsigned word integers from xmm2/m128 and xmm1 saturate the results (SSE). 324 pub static PADDUSW: [u8; 3] = [0x66, 0x0f, 0xdd]; 325 326 /// Bitwise AND of xmm2/m128 and xmm1 (SSE2). 327 pub static PAND: [u8; 3] = [0x66, 0x0f, 0xdb]; 328 329 /// Bitwise AND NOT of xmm2/m128 and xmm1 (SSE2). 330 pub static PANDN: [u8; 3] = [0x66, 0x0f, 0xdf]; 331 332 /// Average packed unsigned byte integers from xmm2/m128 and xmm1 with rounding (SSE2). 333 pub static PAVGB: [u8; 3] = [0x66, 0x0f, 0xE0]; 334 335 /// Average packed unsigned word integers from xmm2/m128 and xmm1 with rounding (SSE2). 336 pub static PAVGW: [u8; 3] = [0x66, 0x0f, 0xE3]; 337 338 /// Compare packed data for equal (SSE2). 339 pub static PCMPEQB: [u8; 3] = [0x66, 0x0f, 0x74]; 340 341 /// Compare packed data for equal (SSE2). 342 pub static PCMPEQD: [u8; 3] = [0x66, 0x0f, 0x76]; 343 344 /// Compare packed data for equal (SSE4.1). 345 pub static PCMPEQQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x29]; 346 347 /// Compare packed data for equal (SSE2). 348 pub static PCMPEQW: [u8; 3] = [0x66, 0x0f, 0x75]; 349 350 /// Compare packed signed byte integers for greater than (SSE2). 351 pub static PCMPGTB: [u8; 3] = [0x66, 0x0f, 0x64]; 352 353 /// Compare packed signed doubleword integers for greater than (SSE2). 354 pub static PCMPGTD: [u8; 3] = [0x66, 0x0f, 0x66]; 355 356 /// Compare packed signed quadword integers for greater than (SSE4.2). 357 pub static PCMPGTQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x37]; 358 359 /// Compare packed signed word integers for greater than (SSE2). 360 pub static PCMPGTW: [u8; 3] = [0x66, 0x0f, 0x65]; 361 362 /// Extract doubleword or quadword, depending on REX.W (SSE4.1). 363 pub static PEXTR: [u8; 4] = [0x66, 0x0f, 0x3a, 0x16]; 364 365 /// Extract byte (SSE4.1). 366 pub static PEXTRB: [u8; 4] = [0x66, 0x0f, 0x3a, 0x14]; 367 368 /// Extract word (SSE4.1). There is a 3-byte SSE2 variant that can also move to m/16. 369 pub static PEXTRW: [u8; 4] = [0x66, 0x0f, 0x3a, 0x15]; 370 371 /// Insert doubleword or quadword, depending on REX.W (SSE4.1). 372 pub static PINSR: [u8; 4] = [0x66, 0x0f, 0x3a, 0x22]; 373 374 /// Insert byte (SSE4.1). 375 pub static PINSRB: [u8; 4] = [0x66, 0x0f, 0x3a, 0x20]; 376 377 /// Insert word (SSE2). 378 pub static PINSRW: [u8; 3] = [0x66, 0x0f, 0xc4]; 379 380 /// Compare packed signed byte integers in xmm1 and xmm2/m128 and store packed maximum values in 381 /// xmm1 (SSE4.1). 382 pub static PMAXSB: [u8; 4] = [0x66, 0x0f, 0x38, 0x3c]; 383 384 /// Compare packed signed doubleword integers in xmm1 and xmm2/m128 and store packed maximum 385 /// values in xmm1 (SSE4.1). 386 pub static PMAXSD: [u8; 4] = [0x66, 0x0f, 0x38, 0x3d]; 387 388 /// Compare packed signed word integers in xmm1 and xmm2/m128 and store packed maximum values in 389 /// xmm1 (SSE2). 390 pub static PMAXSW: [u8; 3] = [0x66, 0x0f, 0xee]; 391 392 /// Compare packed unsigned byte integers in xmm1 and xmm2/m128 and store packed maximum values in 393 /// xmm1 (SSE2). 394 pub static PMAXUB: [u8; 3] = [0x66, 0x0f, 0xde]; 395 396 /// Compare packed unsigned doubleword integers in xmm1 and xmm2/m128 and store packed maximum 397 /// values in xmm1 (SSE4.1). 398 pub static PMAXUD: [u8; 4] = [0x66, 0x0f, 0x38, 0x3f]; 399 400 /// Compare packed unsigned word integers in xmm1 and xmm2/m128 and store packed maximum values in 401 /// xmm1 (SSE4.1). 402 pub static PMAXUW: [u8; 4] = [0x66, 0x0f, 0x38, 0x3e]; 403 404 /// Compare packed signed byte integers in xmm1 and xmm2/m128 and store packed minimum values in 405 /// xmm1 (SSE4.1). 406 pub static PMINSB: [u8; 4] = [0x66, 0x0f, 0x38, 0x38]; 407 408 /// Compare packed signed doubleword integers in xmm1 and xmm2/m128 and store packed minimum 409 /// values in xmm1 (SSE4.1). 410 pub static PMINSD: [u8; 4] = [0x66, 0x0f, 0x38, 0x39]; 411 412 /// Compare packed signed word integers in xmm1 and xmm2/m128 and store packed minimum values in 413 /// xmm1 (SSE2). 414 pub static PMINSW: [u8; 3] = [0x66, 0x0f, 0xea]; 415 416 /// Compare packed unsigned byte integers in xmm1 and xmm2/m128 and store packed minimum values in 417 /// xmm1 (SSE2). 418 pub static PMINUB: [u8; 3] = [0x66, 0x0f, 0xda]; 419 420 /// Compare packed unsigned doubleword integers in xmm1 and xmm2/m128 and store packed minimum 421 /// values in xmm1 (SSE4.1). 422 pub static PMINUD: [u8; 4] = [0x66, 0x0f, 0x38, 0x3b]; 423 424 /// Compare packed unsigned word integers in xmm1 and xmm2/m128 and store packed minimum values in 425 /// xmm1 (SSE4.1). 426 pub static PMINUW: [u8; 4] = [0x66, 0x0f, 0x38, 0x3a]; 427 428 /// Sign extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 16-bit 429 /// integers in xmm1 (SSE4.1). 430 pub static PMOVSXBW: [u8; 4] = [0x66, 0x0f, 0x38, 0x20]; 431 432 /// Sign extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 32-bit 433 /// integers in xmm1 (SSE4.1). 434 pub static PMOVSXWD: [u8; 4] = [0x66, 0x0f, 0x38, 0x23]; 435 436 /// Sign extend 2 packed 32-bit integers in the low 8 bytes of xmm2/m64 to 2 packed 64-bit 437 /// integers in xmm1. 438 pub static PMOVSXDQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x25]; 439 440 /// Zero extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 16-bit 441 /// integers in xmm1 (SSE4.1). 442 pub static PMOVZXBW: [u8; 4] = [0x66, 0x0f, 0x38, 0x30]; 443 444 /// Zero extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 32-bit 445 /// integers in xmm1 (SSE4.1). 446 pub static PMOVZXWD: [u8; 4] = [0x66, 0x0f, 0x38, 0x33]; 447 448 /// Zero extend 2 packed 32-bit integers in the low 8 bytes of xmm2/m64 to 2 packed 64-bit 449 /// integers in xmm1. 450 pub static PMOVZXDQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x35]; 451 452 /// Multiply the packed signed word integers in xmm1 and xmm2/m128, and store the low 16 bits of 453 /// the results in xmm1 (SSE2). 454 pub static PMULLW: [u8; 3] = [0x66, 0x0f, 0xd5]; 455 456 /// Multiply the packed doubleword signed integers in xmm1 and xmm2/m128 and store the low 32 457 /// bits of each product in xmm1 (SSE4.1). 458 pub static PMULLD: [u8; 4] = [0x66, 0x0f, 0x38, 0x40]; 459 460 /// Multiply the packed quadword signed integers in xmm2 and xmm3/m128 and store the low 64 461 /// bits of each product in xmm1 (AVX512VL/DQ). Requires an EVEX encoding. 462 pub static PMULLQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x40]; 463 464 /// Pop top of stack into r{16,32,64}; increment stack pointer. 465 pub static POP_REG: [u8; 1] = [0x58]; 466 467 /// Returns the count of number of bits set to 1. 468 pub static POPCNT: [u8; 3] = [0xf3, 0x0f, 0xb8]; 469 470 /// Bitwise OR of xmm2/m128 and xmm1 (SSE2). 471 pub static POR: [u8; 3] = [0x66, 0x0f, 0xeb]; 472 473 /// Shuffle bytes in xmm1 according to contents of xmm2/m128 (SSE3). 474 pub static PSHUFB: [u8; 4] = [0x66, 0x0f, 0x38, 0x00]; 475 476 /// Shuffle the doublewords in xmm2/m128 based on the encoding in imm8 and 477 /// store the result in xmm1 (SSE2). 478 pub static PSHUFD: [u8; 3] = [0x66, 0x0f, 0x70]; 479 480 /// Shift words in xmm1 by imm8; the direction and sign-bit behavior is controlled by the RRR 481 /// digit used in the ModR/M byte (SSE2). 482 pub static PS_W_IMM: [u8; 3] = [0x66, 0x0f, 0x71]; 483 484 /// Shift doublewords in xmm1 by imm8; the direction and sign-bit behavior is controlled by the RRR 485 /// digit used in the ModR/M byte (SSE2). 486 pub static PS_D_IMM: [u8; 3] = [0x66, 0x0f, 0x72]; 487 488 /// Shift quadwords in xmm1 by imm8; the direction and sign-bit behavior is controlled by the RRR 489 /// digit used in the ModR/M byte (SSE2). 490 pub static PS_Q_IMM: [u8; 3] = [0x66, 0x0f, 0x73]; 491 492 /// Shift words in xmm1 left by xmm2/m128 while shifting in 0s (SSE2). 493 pub static PSLLW: [u8; 3] = [0x66, 0x0f, 0xf1]; 494 495 /// Shift doublewords in xmm1 left by xmm2/m128 while shifting in 0s (SSE2). 496 pub static PSLLD: [u8; 3] = [0x66, 0x0f, 0xf2]; 497 498 /// Shift quadwords in xmm1 left by xmm2/m128 while shifting in 0s (SSE2). 499 pub static PSLLQ: [u8; 3] = [0x66, 0x0f, 0xf3]; 500 501 /// Shift words in xmm1 right by xmm2/m128 while shifting in 0s (SSE2). 502 pub static PSRLW: [u8; 3] = [0x66, 0x0f, 0xd1]; 503 504 /// Shift doublewords in xmm1 right by xmm2/m128 while shifting in 0s (SSE2). 505 pub static PSRLD: [u8; 3] = [0x66, 0x0f, 0xd2]; 506 507 /// Shift quadwords in xmm1 right by xmm2/m128 while shifting in 0s (SSE2). 508 pub static PSRLQ: [u8; 3] = [0x66, 0x0f, 0xd3]; 509 510 /// Shift words in xmm1 right by xmm2/m128 while shifting in sign bits (SSE2). 511 pub static PSRAW: [u8; 3] = [0x66, 0x0f, 0xe1]; 512 513 /// Shift doublewords in xmm1 right by xmm2/m128 while shifting in sign bits (SSE2). 514 pub static PSRAD: [u8; 3] = [0x66, 0x0f, 0xe2]; 515 516 /// Subtract packed byte integers in xmm2/m128 from packed byte integers in xmm1 (SSE2). 517 pub static PSUBB: [u8; 3] = [0x66, 0x0f, 0xf8]; 518 519 /// Subtract packed word integers in xmm2/m128 from packed word integers in xmm1 (SSE2). 520 pub static PSUBW: [u8; 3] = [0x66, 0x0f, 0xf9]; 521 522 /// Subtract packed doubleword integers in xmm2/m128 from doubleword byte integers in xmm1 (SSE2). 523 pub static PSUBD: [u8; 3] = [0x66, 0x0f, 0xfa]; 524 525 /// Subtract packed quadword integers in xmm2/m128 from xmm1 (SSE2). 526 pub static PSUBQ: [u8; 3] = [0x66, 0x0f, 0xfb]; 527 528 /// Subtract packed signed byte integers in xmm2/m128 from packed signed byte integers in xmm1 529 /// and saturate results (SSE2). 530 pub static PSUBSB: [u8; 3] = [0x66, 0x0f, 0xe8]; 531 532 /// Subtract packed signed word integers in xmm2/m128 from packed signed word integers in xmm1 533 /// and saturate results (SSE2). 534 pub static PSUBSW: [u8; 3] = [0x66, 0x0f, 0xe9]; 535 536 /// Subtract packed unsigned byte integers in xmm2/m128 from packed unsigned byte integers in xmm1 537 /// and saturate results (SSE2). 538 pub static PSUBUSB: [u8; 3] = [0x66, 0x0f, 0xd8]; 539 540 /// Subtract packed unsigned word integers in xmm2/m128 from packed unsigned word integers in xmm1 541 /// and saturate results (SSE2). 542 pub static PSUBUSW: [u8; 3] = [0x66, 0x0f, 0xd9]; 543 544 /// Set ZF if xmm2/m128 AND xmm1 result is all 0s; set CF if xmm2/m128 AND NOT xmm1 result is all 545 /// 0s (SSE4.1). 546 pub static PTEST: [u8; 4] = [0x66, 0x0f, 0x38, 0x17]; 547 548 /// Unpack and interleave high-order bytes from xmm1 and xmm2/m128 into xmm1 (SSE2). 549 pub static PUNPCKHBW: [u8; 3] = [0x66, 0x0f, 0x68]; 550 551 /// Unpack and interleave high-order words from xmm1 and xmm2/m128 into xmm1 (SSE2). 552 pub static PUNPCKHWD: [u8; 3] = [0x66, 0x0f, 0x69]; 553 554 /// Unpack and interleave high-order doublewords from xmm1 and xmm2/m128 into xmm1 (SSE2). 555 pub static PUNPCKHDQ: [u8; 3] = [0x66, 0x0f, 0x6A]; 556 557 /// Unpack and interleave high-order quadwords from xmm1 and xmm2/m128 into xmm1 (SSE2). 558 pub static PUNPCKHQDQ: [u8; 3] = [0x66, 0x0f, 0x6D]; 559 560 /// Unpack and interleave low-order bytes from xmm1 and xmm2/m128 into xmm1 (SSE2). 561 pub static PUNPCKLBW: [u8; 3] = [0x66, 0x0f, 0x60]; 562 563 /// Unpack and interleave low-order words from xmm1 and xmm2/m128 into xmm1 (SSE2). 564 pub static PUNPCKLWD: [u8; 3] = [0x66, 0x0f, 0x61]; 565 566 /// Unpack and interleave low-order doublewords from xmm1 and xmm2/m128 into xmm1 (SSE2). 567 pub static PUNPCKLDQ: [u8; 3] = [0x66, 0x0f, 0x62]; 568 569 /// Unpack and interleave low-order quadwords from xmm1 and xmm2/m128 into xmm1 (SSE2). 570 pub static PUNPCKLQDQ: [u8; 3] = [0x66, 0x0f, 0x6C]; 571 572 /// Push r{16,32,64}. 573 pub static PUSH_REG: [u8; 1] = [0x50]; 574 575 /// Logical exclusive OR (SSE2). 576 pub static PXOR: [u8; 3] = [0x66, 0x0f, 0xef]; 577 578 /// Near return to calling procedure. 579 pub static RET_NEAR: [u8; 1] = [0xc3]; 580 581 /// General rotation opcode. Kind of rotation depends on encoding. 582 pub static ROTATE_CL: [u8; 1] = [0xd3]; 583 584 /// General rotation opcode. Kind of rotation depends on encoding. 585 pub static ROTATE_IMM8: [u8; 1] = [0xc1]; 586 587 /// Round scalar doubl-precision floating-point values. 588 pub static ROUNDSD: [u8; 4] = [0x66, 0x0f, 0x3a, 0x0b]; 589 590 /// Round scalar single-precision floating-point values. 591 pub static ROUNDSS: [u8; 4] = [0x66, 0x0f, 0x3a, 0x0a]; 592 593 /// Subtract with borrow r{16,32,64} from r/m of the same size. 594 pub static SBB: [u8; 1] = [0x19]; 595 596 /// Set byte if overflow (OF=1). 597 pub static SET_BYTE_IF_OVERFLOW: [u8; 2] = [0x0f, 0x90]; 598 599 /// Compute the square root of the packed double-precision floating-point values and store the 600 /// result in xmm1 (SSE2). 601 pub static SQRTPD: [u8; 3] = [0x66, 0x0f, 0x51]; 602 603 /// Compute the square root of the packed double-precision floating-point values and store the 604 /// result in xmm1 (SSE). 605 pub static SQRTPS: [u8; 2] = [0x0f, 0x51]; 606 607 /// Compute square root of scalar double-precision floating-point value. 608 pub static SQRTSD: [u8; 3] = [0xf2, 0x0f, 0x51]; 609 610 /// Compute square root of scalar single-precision value. 611 pub static SQRTSS: [u8; 3] = [0xf3, 0x0f, 0x51]; 612 613 /// Subtract r{16,32,64} from r/m of same size. 614 pub static SUB: [u8; 1] = [0x29]; 615 616 /// Subtract packed double-precision floating-point values in xmm2/mem from xmm1 and store result 617 /// in xmm1 (SSE2). 618 pub static SUBPD: [u8; 3] = [0x66, 0x0f, 0x5c]; 619 620 /// Subtract packed single-precision floating-point values in xmm2/mem from xmm1 and store result 621 /// in xmm1 (SSE). 622 pub static SUBPS: [u8; 2] = [0x0f, 0x5c]; 623 624 /// Subtract the low double-precision floating-point value in xmm2/m64 from xmm1 625 /// and store the result in xmm1. 626 pub static SUBSD: [u8; 3] = [0xf2, 0x0f, 0x5c]; 627 628 /// Subtract the low single-precision floating-point value in xmm2/m32 from xmm1 629 /// and store the result in xmm1. 630 pub static SUBSS: [u8; 3] = [0xf3, 0x0f, 0x5c]; 631 632 /// AND r8 with r/m8; set SF, ZF, PF according to result. 633 pub static TEST_BYTE_REG: [u8; 1] = [0x84]; 634 635 /// AND {r16, r32, r64} with r/m of the same size; set SF, ZF, PF according to result. 636 pub static TEST_REG: [u8; 1] = [0x85]; 637 638 /// Count the number of trailing zero bits. 639 pub static TZCNT: [u8; 3] = [0xf3, 0x0f, 0xbc]; 640 641 /// Compare low double-precision floating-point values in xmm1 and xmm2/mem64 642 /// and set the EFLAGS flags accordingly. 643 pub static UCOMISD: [u8; 3] = [0x66, 0x0f, 0x2e]; 644 645 /// Compare low single-precision floating-point values in xmm1 and xmm2/mem32 646 /// and set the EFLAGS flags accordingly. 647 pub static UCOMISS: [u8; 2] = [0x0f, 0x2e]; 648 649 /// Raise invalid opcode instruction. 650 pub static UNDEFINED2: [u8; 2] = [0x0f, 0x0b]; 651 652 /// imm{16,32} XOR r/m{16,32,64}, possibly sign-extended. 653 pub static XOR_IMM: [u8; 1] = [0x81]; 654 655 /// r/m{16,32,64} XOR sign-extended imm8. 656 pub static XOR_IMM8_SIGN_EXTEND: [u8; 1] = [0x83]; 657 658 /// r/m{16,32,64} XOR register of the same size. 659 pub static XOR: [u8; 1] = [0x31]; 660 661 /// r/m8 XOR r8. 662 pub static XORB: [u8; 1] = [0x30]; 663 664 /// Bitwise logical XOR of packed double-precision floating-point values. 665 pub static XORPD: [u8; 3] = [0x66, 0x0f, 0x57]; 666 667 /// Bitwise logical XOR of packed single-precision floating-point values. 668 pub static XORPS: [u8; 2] = [0x0f, 0x57]; 669