xref: /dragonfly/sys/dev/drm/radeon/radeon.h (revision 3f2dd94a)
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30 
31 /* TODO: Here are things that needs to be done :
32  *	- surface allocator & initializer : (bit like scratch reg) should
33  *	  initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34  *	  related to surface
35  *	- WB : write back stuff (do it bit like scratch reg things)
36  *	- Vblank : look at Jesse's rework and what we should do
37  *	- r600/r700: gart & cp
38  *	- cs : clean cs ioctl use bitmap & things like that.
39  *	- power management stuff
40  *	- Barrier in gart code
41  *	- Unmappabled vram ?
42  *	- TESTING, TESTING, TESTING
43  */
44 
45 /* Initialization path:
46  *  We expect that acceleration initialization might fail for various
47  *  reasons even thought we work hard to make it works on most
48  *  configurations. In order to still have a working userspace in such
49  *  situation the init path must succeed up to the memory controller
50  *  initialization point. Failure before this point are considered as
51  *  fatal error. Here is the init callchain :
52  *      radeon_device_init  perform common structure, mutex initialization
53  *      asic_init           setup the GPU memory layout and perform all
54  *                          one time initialization (failure in this
55  *                          function are considered fatal)
56  *      asic_startup        setup the GPU acceleration, in order to
57  *                          follow guideline the first thing this
58  *                          function should do is setting the GPU
59  *                          memory controller (only MC setup failure
60  *                          are considered as fatal)
61  */
62 
63 #include <contrib/dev/acpica/source/include/acpi.h>
64 #include <dev/acpica/acpivar.h>
65 
66 #include <linux/atomic.h>
67 #include <linux/wait.h>
68 #include <linux/list.h>
69 #include <linux/kref.h>
70 #include <linux/interval_tree.h>
71 #include <linux/hashtable.h>
72 #include <linux/dma-fence.h>
73 
74 #include <drm/ttm/ttm_bo_api.h>
75 #include <drm/ttm/ttm_bo_driver.h>
76 #include <drm/ttm/ttm_placement.h>
77 #include <drm/ttm/ttm_module.h>
78 #include <drm/ttm/ttm_execbuf_util.h>
79 
80 #include <drm/drm_gem.h>
81 
82 #include "radeon_family.h"
83 #include "radeon_mode.h"
84 #include "radeon_reg.h"
85 
86 /*
87  * Modules parameters.
88  */
89 extern int radeon_no_wb;
90 extern int radeon_modeset;
91 extern int radeon_dynclks;
92 extern int radeon_r4xx_atom;
93 extern int radeon_agpmode;
94 extern int radeon_vram_limit;
95 extern int radeon_gart_size;
96 extern int radeon_benchmarking;
97 extern int radeon_testing;
98 extern int radeon_connector_table;
99 extern int radeon_tv;
100 extern int radeon_audio;
101 extern int radeon_disp_priority;
102 extern int radeon_hw_i2c;
103 extern int radeon_pcie_gen2;
104 extern int radeon_msi;
105 extern int radeon_lockup_timeout;
106 extern int radeon_fastfb;
107 extern int radeon_dpm;
108 extern int radeon_aspm;
109 extern int radeon_runtime_pm;
110 extern int radeon_hard_reset;
111 extern int radeon_vm_size;
112 extern int radeon_vm_block_size;
113 extern int radeon_deep_color;
114 extern int radeon_use_pflipirq;
115 extern int radeon_bapm;
116 extern int radeon_backlight;
117 extern int radeon_auxch;
118 extern int radeon_mst;
119 extern int radeon_uvd;
120 extern int radeon_vce;
121 extern int radeon_si_support;
122 extern int radeon_cik_support;
123 
124 #ifdef CONFIG_DRM_AMDGPU_CIK
125 extern int radeon_cik_support;
126 #endif
127 
128 /*
129  * Copy from radeon_drv.h so we don't have to include both and have conflicting
130  * symbol;
131  */
132 #define RADEON_MAX_USEC_TIMEOUT			100000	/* 100 ms */
133 #define RADEON_FENCE_JIFFIES_TIMEOUT		(HZ / 2)
134 #define RADEON_USEC_IB_TEST_TIMEOUT		1000000 /* 1s */
135 /* RADEON_IB_POOL_SIZE must be a power of 2 */
136 #define RADEON_IB_POOL_SIZE			16
137 #define RADEON_DEBUGFS_MAX_COMPONENTS		32
138 #define RADEONFB_CONN_LIMIT			4
139 #define RADEON_BIOS_NUM_SCRATCH			8
140 
141 /* internal ring indices */
142 /* r1xx+ has gfx CP ring */
143 #define RADEON_RING_TYPE_GFX_INDEX		0
144 
145 /* cayman has 2 compute CP rings */
146 #define CAYMAN_RING_TYPE_CP1_INDEX		1
147 #define CAYMAN_RING_TYPE_CP2_INDEX		2
148 
149 /* R600+ has an async dma ring */
150 #define R600_RING_TYPE_DMA_INDEX		3
151 /* cayman add a second async dma ring */
152 #define CAYMAN_RING_TYPE_DMA1_INDEX		4
153 
154 /* R600+ */
155 #define R600_RING_TYPE_UVD_INDEX		5
156 
157 /* TN+ */
158 #define TN_RING_TYPE_VCE1_INDEX			6
159 #define TN_RING_TYPE_VCE2_INDEX			7
160 
161 /* max number of rings */
162 #define RADEON_NUM_RINGS			8
163 
164 /* number of hw syncs before falling back on blocking */
165 #define RADEON_NUM_SYNCS			4
166 
167 /* hardcode those limit for now */
168 #define RADEON_VA_IB_OFFSET			(1 << 20)
169 #define RADEON_VA_RESERVED_SIZE			(8 << 20)
170 #define RADEON_IB_VM_MAX_SIZE			(64 << 10)
171 
172 /* hard reset data */
173 #define RADEON_ASIC_RESET_DATA                  0x39d5e86b
174 
175 /* reset flags */
176 #define RADEON_RESET_GFX			(1 << 0)
177 #define RADEON_RESET_COMPUTE			(1 << 1)
178 #define RADEON_RESET_DMA			(1 << 2)
179 #define RADEON_RESET_CP				(1 << 3)
180 #define RADEON_RESET_GRBM			(1 << 4)
181 #define RADEON_RESET_DMA1			(1 << 5)
182 #define RADEON_RESET_RLC			(1 << 6)
183 #define RADEON_RESET_SEM			(1 << 7)
184 #define RADEON_RESET_IH				(1 << 8)
185 #define RADEON_RESET_VMC			(1 << 9)
186 #define RADEON_RESET_MC				(1 << 10)
187 #define RADEON_RESET_DISPLAY			(1 << 11)
188 
189 /* CG block flags */
190 #define RADEON_CG_BLOCK_GFX			(1 << 0)
191 #define RADEON_CG_BLOCK_MC			(1 << 1)
192 #define RADEON_CG_BLOCK_SDMA			(1 << 2)
193 #define RADEON_CG_BLOCK_UVD			(1 << 3)
194 #define RADEON_CG_BLOCK_VCE			(1 << 4)
195 #define RADEON_CG_BLOCK_HDP			(1 << 5)
196 #define RADEON_CG_BLOCK_BIF			(1 << 6)
197 
198 /* CG flags */
199 #define RADEON_CG_SUPPORT_GFX_MGCG		(1 << 0)
200 #define RADEON_CG_SUPPORT_GFX_MGLS		(1 << 1)
201 #define RADEON_CG_SUPPORT_GFX_CGCG		(1 << 2)
202 #define RADEON_CG_SUPPORT_GFX_CGLS		(1 << 3)
203 #define RADEON_CG_SUPPORT_GFX_CGTS		(1 << 4)
204 #define RADEON_CG_SUPPORT_GFX_CGTS_LS		(1 << 5)
205 #define RADEON_CG_SUPPORT_GFX_CP_LS		(1 << 6)
206 #define RADEON_CG_SUPPORT_GFX_RLC_LS		(1 << 7)
207 #define RADEON_CG_SUPPORT_MC_LS			(1 << 8)
208 #define RADEON_CG_SUPPORT_MC_MGCG		(1 << 9)
209 #define RADEON_CG_SUPPORT_SDMA_LS		(1 << 10)
210 #define RADEON_CG_SUPPORT_SDMA_MGCG		(1 << 11)
211 #define RADEON_CG_SUPPORT_BIF_LS		(1 << 12)
212 #define RADEON_CG_SUPPORT_UVD_MGCG		(1 << 13)
213 #define RADEON_CG_SUPPORT_VCE_MGCG		(1 << 14)
214 #define RADEON_CG_SUPPORT_HDP_LS		(1 << 15)
215 #define RADEON_CG_SUPPORT_HDP_MGCG		(1 << 16)
216 
217 /* PG flags */
218 #define RADEON_PG_SUPPORT_GFX_PG		(1 << 0)
219 #define RADEON_PG_SUPPORT_GFX_SMG		(1 << 1)
220 #define RADEON_PG_SUPPORT_GFX_DMG		(1 << 2)
221 #define RADEON_PG_SUPPORT_UVD			(1 << 3)
222 #define RADEON_PG_SUPPORT_VCE			(1 << 4)
223 #define RADEON_PG_SUPPORT_CP			(1 << 5)
224 #define RADEON_PG_SUPPORT_GDS			(1 << 6)
225 #define RADEON_PG_SUPPORT_RLC_SMU_HS		(1 << 7)
226 #define RADEON_PG_SUPPORT_SDMA			(1 << 8)
227 #define RADEON_PG_SUPPORT_ACP			(1 << 9)
228 #define RADEON_PG_SUPPORT_SAMU			(1 << 10)
229 
230 /* max cursor sizes (in pixels) */
231 #define CURSOR_WIDTH 64
232 #define CURSOR_HEIGHT 64
233 
234 #define CIK_CURSOR_WIDTH 128
235 #define CIK_CURSOR_HEIGHT 128
236 
237 /*
238  * Errata workarounds.
239  */
240 enum radeon_pll_errata {
241 	CHIP_ERRATA_R300_CG             = 0x00000001,
242 	CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
243 	CHIP_ERRATA_PLL_DELAY           = 0x00000004
244 };
245 
246 
247 struct radeon_device;
248 
249 
250 /*
251  * BIOS.
252  */
253 bool radeon_get_bios(struct radeon_device *rdev);
254 
255 /*
256  * Dummy page
257  */
258 struct radeon_dummy_page {
259 	uint64_t	entry;
260 	struct drm_dma_handle *dmah;
261 	dma_addr_t	addr;
262 };
263 int radeon_dummy_page_init(struct radeon_device *rdev);
264 void radeon_dummy_page_fini(struct radeon_device *rdev);
265 
266 
267 /*
268  * Clocks
269  */
270 struct radeon_clock {
271 	struct radeon_pll p1pll;
272 	struct radeon_pll p2pll;
273 	struct radeon_pll dcpll;
274 	struct radeon_pll spll;
275 	struct radeon_pll mpll;
276 	/* 10 Khz units */
277 	uint32_t default_mclk;
278 	uint32_t default_sclk;
279 	uint32_t default_dispclk;
280 	uint32_t current_dispclk;
281 	uint32_t dp_extclk;
282 	uint32_t max_pixel_clock;
283 	uint32_t vco_freq;
284 };
285 
286 /*
287  * Power management
288  */
289 int radeon_pm_init(struct radeon_device *rdev);
290 int radeon_pm_late_init(struct radeon_device *rdev);
291 void radeon_pm_fini(struct radeon_device *rdev);
292 void radeon_pm_compute_clocks(struct radeon_device *rdev);
293 void radeon_pm_suspend(struct radeon_device *rdev);
294 void radeon_pm_resume(struct radeon_device *rdev);
295 void radeon_combios_get_power_modes(struct radeon_device *rdev);
296 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
297 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
298 				   u8 clock_type,
299 				   u32 clock,
300 				   bool strobe_mode,
301 				   struct atom_clock_dividers *dividers);
302 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
303 					u32 clock,
304 					bool strobe_mode,
305 					struct atom_mpll_param *mpll_param);
306 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
307 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
308 					  u16 voltage_level, u8 voltage_type,
309 					  u32 *gpio_value, u32 *gpio_mask);
310 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
311 					 u32 eng_clock, u32 mem_clock);
312 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
313 				 u8 voltage_type, u16 *voltage_step);
314 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
315 			     u16 voltage_id, u16 *voltage);
316 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
317 						      u16 *voltage,
318 						      u16 leakage_idx);
319 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
320 					  u16 *leakage_id);
321 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
322 							 u16 *vddc, u16 *vddci,
323 							 u16 virtual_voltage_id,
324 							 u16 vbios_voltage_id);
325 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
326 				u16 virtual_voltage_id,
327 				u16 *voltage);
328 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
329 				      u8 voltage_type,
330 				      u16 nominal_voltage,
331 				      u16 *true_voltage);
332 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
333 				u8 voltage_type, u16 *min_voltage);
334 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
335 				u8 voltage_type, u16 *max_voltage);
336 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
337 				  u8 voltage_type, u8 voltage_mode,
338 				  struct atom_voltage_table *voltage_table);
339 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
340 				 u8 voltage_type, u8 voltage_mode);
341 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
342 			      u8 voltage_type,
343 			      u8 *svd_gpio_id, u8 *svc_gpio_id);
344 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
345 				   u32 mem_clock);
346 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
347 			       u32 mem_clock);
348 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
349 				  u8 module_index,
350 				  struct atom_mc_reg_table *reg_table);
351 int radeon_atom_get_memory_info(struct radeon_device *rdev,
352 				u8 module_index, struct atom_memory_info *mem_info);
353 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
354 				     bool gddr5, u8 module_index,
355 				     struct atom_memory_clock_range_table *mclk_range_table);
356 void rs690_pm_info(struct radeon_device *rdev);
357 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
358 				    unsigned *bankh, unsigned *mtaspect,
359 				    unsigned *tile_split);
360 
361 /*
362  * Fences.
363  */
364 struct radeon_fence_driver {
365 	struct radeon_device		*rdev;
366 	uint32_t			scratch_reg;
367 	uint64_t			gpu_addr;
368 	volatile uint32_t		*cpu_addr;
369 	/* sync_seq is protected by ring emission lock */
370 	uint64_t			sync_seq[RADEON_NUM_RINGS];
371 	atomic64_t			last_seq;
372 	bool				initialized, delayed_irq;
373 	struct delayed_work		lockup_work;
374 };
375 
376 struct radeon_fence {
377 	struct dma_fence		base;
378 
379 	struct radeon_device	*rdev;
380 	uint64_t		seq;
381 	/* RB, DMA, etc. */
382 	unsigned		ring;
383 	bool			is_vm_update;
384 
385 	wait_queue_entry_t		fence_wake;
386 };
387 
388 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
389 int radeon_fence_driver_init(struct radeon_device *rdev);
390 void radeon_fence_driver_fini(struct radeon_device *rdev);
391 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
392 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
393 void radeon_fence_process(struct radeon_device *rdev, int ring);
394 bool radeon_fence_signaled(struct radeon_fence *fence);
395 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
396 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
397 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
398 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
399 int radeon_fence_wait_any(struct radeon_device *rdev,
400 			  struct radeon_fence **fences,
401 			  bool intr);
402 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
403 void radeon_fence_unref(struct radeon_fence **fence);
404 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
405 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
406 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
radeon_fence_later(struct radeon_fence * a,struct radeon_fence * b)407 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
408 						      struct radeon_fence *b)
409 {
410 	if (!a) {
411 		return b;
412 	}
413 
414 	if (!b) {
415 		return a;
416 	}
417 
418 	BUG_ON(a->ring != b->ring);
419 
420 	if (a->seq > b->seq) {
421 		return a;
422 	} else {
423 		return b;
424 	}
425 }
426 
radeon_fence_is_earlier(struct radeon_fence * a,struct radeon_fence * b)427 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
428 					   struct radeon_fence *b)
429 {
430 	if (!a) {
431 		return false;
432 	}
433 
434 	if (!b) {
435 		return true;
436 	}
437 
438 	BUG_ON(a->ring != b->ring);
439 
440 	return a->seq < b->seq;
441 }
442 
443 /*
444  * Tiling registers
445  */
446 struct radeon_surface_reg {
447 	struct radeon_bo *bo;
448 };
449 
450 #define RADEON_GEM_MAX_SURFACES 8
451 
452 /*
453  * TTM.
454  */
455 struct radeon_mman {
456 	struct ttm_bo_global_ref        bo_global_ref;
457 	struct drm_global_reference	mem_global_ref;
458 	struct ttm_bo_device		bdev;
459 	bool				mem_global_referenced;
460 	bool				initialized;
461 
462 #if defined(CONFIG_DEBUG_FS)
463 	struct dentry			*vram;
464 	struct dentry			*gtt;
465 #endif
466 };
467 
468 struct radeon_bo_list {
469 	struct radeon_bo		*robj;
470 	struct ttm_validate_buffer	tv;
471 	uint64_t			gpu_offset;
472 	unsigned			preferred_domains;
473 	unsigned			allowed_domains;
474 	uint32_t			tiling_flags;
475 };
476 
477 /* bo virtual address in a specific vm */
478 struct radeon_bo_va {
479 	/* protected by bo being reserved */
480 	struct list_head		bo_list;
481 	uint32_t			flags;
482 	struct radeon_fence		*last_pt_update;
483 	unsigned			ref_count;
484 
485 	/* protected by vm mutex */
486 	struct interval_tree_node	it;
487 	struct list_head		vm_status;
488 
489 	/* constant after initialization */
490 	struct radeon_vm		*vm;
491 	struct radeon_bo		*bo;
492 };
493 
494 struct radeon_bo {
495 	/* Protected by gem.mutex */
496 	struct list_head		list;
497 	/* Protected by tbo.reserved */
498 	u32				initial_domain;
499 	struct ttm_place		placements[4];
500 	struct ttm_placement		placement;
501 	struct ttm_buffer_object	tbo;
502 	struct ttm_bo_kmap_obj		kmap;
503 	u32				flags;
504 	unsigned			pin_count;
505 	void				*kptr;
506 	u32				tiling_flags;
507 	u32				pitch;
508 	int				surface_reg;
509 	unsigned			prime_shared_count;
510 	/* list of all virtual address to which this bo
511 	 * is associated to
512 	 */
513 	struct list_head		va;
514 	/* Constant after initialization */
515 	struct radeon_device		*rdev;
516 	struct drm_gem_object		gem_base;
517 
518 	struct ttm_bo_kmap_obj		dma_buf_vmap;
519 	pid_t				pid;
520 
521 	struct radeon_mn		*mn;
522 	struct list_head		mn_list;
523 };
524 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
525 
526 int radeon_gem_debugfs_init(struct radeon_device *rdev);
527 
528 /* sub-allocation manager, it has to be protected by another lock.
529  * By conception this is an helper for other part of the driver
530  * like the indirect buffer or semaphore, which both have their
531  * locking.
532  *
533  * Principe is simple, we keep a list of sub allocation in offset
534  * order (first entry has offset == 0, last entry has the highest
535  * offset).
536  *
537  * When allocating new object we first check if there is room at
538  * the end total_size - (last_object_offset + last_object_size) >=
539  * alloc_size. If so we allocate new object there.
540  *
541  * When there is not enough room at the end, we start waiting for
542  * each sub object until we reach object_offset+object_size >=
543  * alloc_size, this object then become the sub object we return.
544  *
545  * Alignment can't be bigger than page size.
546  *
547  * Hole are not considered for allocation to keep things simple.
548  * Assumption is that there won't be hole (all object on same
549  * alignment).
550  */
551 struct radeon_sa_manager {
552 	wait_queue_head_t	wq;
553 	struct radeon_bo	*bo;
554 	struct list_head	*hole;
555 	struct list_head	flist[RADEON_NUM_RINGS];
556 	struct list_head	olist;
557 	unsigned		size;
558 	u64			gpu_addr;
559 	void			*cpu_ptr;
560 	uint32_t		domain;
561 	uint32_t		align;
562 };
563 
564 struct radeon_sa_bo;
565 
566 /* sub-allocation buffer */
567 struct radeon_sa_bo {
568 	struct list_head		olist;
569 	struct list_head		flist;
570 	struct radeon_sa_manager	*manager;
571 	unsigned			soffset;
572 	unsigned			eoffset;
573 	struct radeon_fence		*fence;
574 };
575 
576 /*
577  * GEM objects.
578  */
579 struct radeon_gem {
580 	struct lock		mutex;
581 	struct list_head	objects;
582 };
583 
584 int radeon_gem_init(struct radeon_device *rdev);
585 void radeon_gem_fini(struct radeon_device *rdev);
586 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
587 				int alignment, int initial_domain,
588 				u32 flags, bool kernel,
589 				struct drm_gem_object **obj);
590 
591 int radeon_mode_dumb_create(struct drm_file *file_priv,
592 			    struct drm_device *dev,
593 			    struct drm_mode_create_dumb *args);
594 int radeon_mode_dumb_mmap(struct drm_file *filp,
595 			  struct drm_device *dev,
596 			  uint32_t handle, uint64_t *offset_p);
597 
598 /*
599  * Semaphores.
600  */
601 struct radeon_semaphore {
602 	struct radeon_sa_bo	*sa_bo;
603 	signed			waiters;
604 	uint64_t		gpu_addr;
605 };
606 
607 int radeon_semaphore_create(struct radeon_device *rdev,
608 			    struct radeon_semaphore **semaphore);
609 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
610 				  struct radeon_semaphore *semaphore);
611 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
612 				struct radeon_semaphore *semaphore);
613 void radeon_semaphore_free(struct radeon_device *rdev,
614 			   struct radeon_semaphore **semaphore,
615 			   struct radeon_fence *fence);
616 
617 /*
618  * Synchronization
619  */
620 struct radeon_sync {
621 	struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
622 	struct radeon_fence	*sync_to[RADEON_NUM_RINGS];
623 	struct radeon_fence	*last_vm_update;
624 };
625 
626 void radeon_sync_create(struct radeon_sync *sync);
627 void radeon_sync_fence(struct radeon_sync *sync,
628 		       struct radeon_fence *fence);
629 int radeon_sync_resv(struct radeon_device *rdev,
630 		     struct radeon_sync *sync,
631 		     struct reservation_object *resv,
632 		     bool shared);
633 int radeon_sync_rings(struct radeon_device *rdev,
634 		      struct radeon_sync *sync,
635 		      int waiting_ring);
636 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
637 		      struct radeon_fence *fence);
638 
639 /*
640  * GART structures, functions & helpers
641  */
642 struct radeon_mc;
643 
644 #define RADEON_GPU_PAGE_SIZE 4096
645 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
646 #define RADEON_GPU_PAGE_SHIFT 12
647 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
648 
649 #define RADEON_GART_PAGE_DUMMY  0
650 #define RADEON_GART_PAGE_VALID	(1 << 0)
651 #define RADEON_GART_PAGE_READ	(1 << 1)
652 #define RADEON_GART_PAGE_WRITE	(1 << 2)
653 #define RADEON_GART_PAGE_SNOOP	(1 << 3)
654 
655 struct radeon_gart {
656 	struct drm_dma_handle		*dmah;
657 	dma_addr_t			table_addr;
658 	struct radeon_bo		*robj;
659 	void				*ptr;
660 	unsigned			num_gpu_pages;
661 	unsigned			num_cpu_pages;
662 	unsigned			table_size;
663 	struct page			**pages;
664 	uint64_t			*pages_entry;
665 	bool				ready;
666 };
667 
668 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
669 void radeon_gart_table_ram_free(struct radeon_device *rdev);
670 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
671 void radeon_gart_table_vram_free(struct radeon_device *rdev);
672 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
673 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
674 int radeon_gart_init(struct radeon_device *rdev);
675 void radeon_gart_fini(struct radeon_device *rdev);
676 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
677 			int pages);
678 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
679 		     int pages, struct page **pagelist,
680 		     dma_addr_t *dma_addr, uint32_t flags);
681 
682 
683 /*
684  * GPU MC structures, functions & helpers
685  */
686 struct radeon_mc {
687 	resource_size_t		aper_size;
688 	resource_size_t		aper_base;
689 	resource_size_t		agp_base;
690 	/* for some chips with <= 32MB we need to lie
691 	 * about vram size near mc fb location */
692 	u64			mc_vram_size;
693 	u64			visible_vram_size;
694 	u64			gtt_size;
695 	u64			gtt_start;
696 	u64			gtt_end;
697 	u64			vram_start;
698 	u64			vram_end;
699 	unsigned		vram_width;
700 	u64			real_vram_size;
701 	int			vram_mtrr;
702 	bool			vram_is_ddr;
703 	bool			igp_sideport_enabled;
704 	u64                     gtt_base_align;
705 	u64                     mc_mask;
706 };
707 
708 bool radeon_combios_sideport_present(struct radeon_device *rdev);
709 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
710 
711 /*
712  * GPU scratch registers structures, functions & helpers
713  */
714 struct radeon_scratch {
715 	unsigned		num_reg;
716 	uint32_t                reg_base;
717 	bool			free[32];
718 	uint32_t		reg[32];
719 };
720 
721 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
722 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
723 
724 /*
725  * GPU doorbell structures, functions & helpers
726  */
727 #define RADEON_MAX_DOORBELLS 1024	/* Reserve at most 1024 doorbell slots for radeon-owned rings. */
728 
729 struct radeon_doorbell {
730 	/* doorbell mmio */
731 	resource_size_t		base;
732 	resource_size_t		size;
733 	u32 __iomem		*ptr;
734 	u32			num_doorbells;	/* Number of doorbells actually reserved for radeon. */
735 	DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
736 };
737 
738 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
739 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
740 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
741 				  phys_addr_t *aperture_base,
742 				  size_t *aperture_size,
743 				  size_t *start_offset);
744 
745 /*
746  * IRQS.
747  */
748 
749 struct radeon_flip_work {
750 	struct work_struct		flip_work;
751 	struct work_struct		unpin_work;
752 	struct radeon_device		*rdev;
753 	int				crtc_id;
754 	u32				target_vblank;
755 	uint64_t			base;
756 	struct drm_pending_vblank_event *event;
757 	struct radeon_bo		*old_rbo;
758 	struct dma_fence		*fence;
759 	bool				async;
760 };
761 
762 struct r500_irq_stat_regs {
763 	u32 disp_int;
764 	u32 hdmi0_status;
765 };
766 
767 struct r600_irq_stat_regs {
768 	u32 disp_int;
769 	u32 disp_int_cont;
770 	u32 disp_int_cont2;
771 	u32 d1grph_int;
772 	u32 d2grph_int;
773 	u32 hdmi0_status;
774 	u32 hdmi1_status;
775 };
776 
777 struct evergreen_irq_stat_regs {
778 	u32 disp_int[6];
779 	u32 grph_int[6];
780 	u32 afmt_status[6];
781 };
782 
783 struct cik_irq_stat_regs {
784 	u32 disp_int;
785 	u32 disp_int_cont;
786 	u32 disp_int_cont2;
787 	u32 disp_int_cont3;
788 	u32 disp_int_cont4;
789 	u32 disp_int_cont5;
790 	u32 disp_int_cont6;
791 	u32 d1grph_int;
792 	u32 d2grph_int;
793 	u32 d3grph_int;
794 	u32 d4grph_int;
795 	u32 d5grph_int;
796 	u32 d6grph_int;
797 };
798 
799 union radeon_irq_stat_regs {
800 	struct r500_irq_stat_regs r500;
801 	struct r600_irq_stat_regs r600;
802 	struct evergreen_irq_stat_regs evergreen;
803 	struct cik_irq_stat_regs cik;
804 };
805 
806 struct radeon_irq {
807 	bool				installed;
808 	struct lock			lock;
809 	atomic_t			ring_int[RADEON_NUM_RINGS];
810 	bool				crtc_vblank_int[RADEON_MAX_CRTCS];
811 	atomic_t			pflip[RADEON_MAX_CRTCS];
812 	wait_queue_head_t		vblank_queue;
813 	bool				hpd[RADEON_MAX_HPD_PINS];
814 	bool				afmt[RADEON_MAX_AFMT_BLOCKS];
815 	union radeon_irq_stat_regs	stat_regs;
816 	bool				dpm_thermal;
817 };
818 
819 int radeon_irq_kms_init(struct radeon_device *rdev);
820 void radeon_irq_kms_fini(struct radeon_device *rdev);
821 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
822 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
823 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
824 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
825 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
826 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
827 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
828 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
829 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
830 
831 /*
832  * CP & rings.
833  */
834 
835 struct radeon_ib {
836 	struct radeon_sa_bo		*sa_bo;
837 	uint32_t			length_dw;
838 	uint64_t			gpu_addr;
839 	uint32_t			*ptr;
840 	int				ring;
841 	struct radeon_fence		*fence;
842 	struct radeon_vm		*vm;
843 	bool				is_const_ib;
844 	struct radeon_sync		sync;
845 };
846 
847 struct radeon_ring {
848 	struct radeon_bo	*ring_obj;
849 	volatile uint32_t	*ring;
850 	unsigned		rptr_offs;
851 	unsigned		rptr_save_reg;
852 	u64			next_rptr_gpu_addr;
853 	volatile u32		*next_rptr_cpu_addr;
854 	unsigned		wptr;
855 	unsigned		wptr_old;
856 	unsigned		ring_size;
857 	unsigned		ring_free_dw;
858 	int			count_dw;
859 	atomic_t		last_rptr;
860 	atomic64_t		last_activity;
861 	uint64_t		gpu_addr;
862 	uint32_t		align_mask;
863 	uint32_t		ptr_mask;
864 	bool			ready;
865 	u32			nop;
866 	u32			idx;
867 	u64			last_semaphore_signal_addr;
868 	u64			last_semaphore_wait_addr;
869 	/* for CIK queues */
870 	u32 me;
871 	u32 pipe;
872 	u32 queue;
873 	struct radeon_bo	*mqd_obj;
874 	u32 doorbell_index;
875 	unsigned		wptr_offs;
876 };
877 
878 struct radeon_mec {
879 	struct radeon_bo	*hpd_eop_obj;
880 	u64			hpd_eop_gpu_addr;
881 	u32 num_pipe;
882 	u32 num_mec;
883 	u32 num_queue;
884 };
885 
886 /*
887  * VM
888  */
889 
890 /* maximum number of VMIDs */
891 #define RADEON_NUM_VM	16
892 
893 /* number of entries in page table */
894 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
895 
896 /* PTBs (Page Table Blocks) need to be aligned to 32K */
897 #define RADEON_VM_PTB_ALIGN_SIZE   32768
898 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
899 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
900 
901 #define R600_PTE_VALID		(1 << 0)
902 #define R600_PTE_SYSTEM		(1 << 1)
903 #define R600_PTE_SNOOPED	(1 << 2)
904 #define R600_PTE_READABLE	(1 << 5)
905 #define R600_PTE_WRITEABLE	(1 << 6)
906 
907 /* PTE (Page Table Entry) fragment field for different page sizes */
908 #define R600_PTE_FRAG_4KB	(0 << 7)
909 #define R600_PTE_FRAG_64KB	(4 << 7)
910 #define R600_PTE_FRAG_256KB	(6 << 7)
911 
912 /* flags needed to be set so we can copy directly from the GART table */
913 #define R600_PTE_GART_MASK	( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
914 				  R600_PTE_SYSTEM | R600_PTE_VALID )
915 
916 struct radeon_vm_pt {
917 	struct radeon_bo		*bo;
918 	uint64_t			addr;
919 };
920 
921 struct radeon_vm_id {
922 	unsigned		id;
923 	uint64_t		pd_gpu_addr;
924 	/* last flushed PD/PT update */
925 	struct radeon_fence	*flushed_updates;
926 	/* last use of vmid */
927 	struct radeon_fence	*last_id_use;
928 };
929 
930 struct radeon_vm {
931 	struct lock		mutex;
932 
933 	struct rb_root		va;
934 
935 	/* protecting invalidated and freed */
936 	spinlock_t		status_lock;
937 
938 	/* BOs moved, but not yet updated in the PT */
939 	struct list_head	invalidated;
940 
941 	/* BOs freed, but not yet updated in the PT */
942 	struct list_head	freed;
943 
944 	/* BOs cleared in the PT */
945 	struct list_head	cleared;
946 
947 	/* contains the page directory */
948 	struct radeon_bo	*page_directory;
949 	unsigned		max_pde_used;
950 
951 	/* array of page tables, one for each page directory entry */
952 	struct radeon_vm_pt	*page_tables;
953 
954 	struct radeon_bo_va	*ib_bo_va;
955 
956 	/* for id and flush management per ring */
957 	struct radeon_vm_id	ids[RADEON_NUM_RINGS];
958 };
959 
960 struct radeon_vm_manager {
961 	struct radeon_fence		*active[RADEON_NUM_VM];
962 	uint32_t			max_pfn;
963 	/* number of VMIDs */
964 	unsigned			nvm;
965 	/* vram base address for page table entry  */
966 	u64				vram_base_offset;
967 	/* is vm enabled? */
968 	bool				enabled;
969 	/* for hw to save the PD addr on suspend/resume */
970 	uint32_t			saved_table_addr[RADEON_NUM_VM];
971 };
972 
973 /*
974  * file private structure
975  */
976 struct radeon_fpriv {
977 	struct radeon_vm		vm;
978 };
979 
980 /*
981  * R6xx+ IH ring
982  */
983 struct r600_ih {
984 	struct radeon_bo	*ring_obj;
985 	volatile uint32_t	*ring;
986 	unsigned		rptr;
987 	unsigned		ring_size;
988 	uint64_t		gpu_addr;
989 	uint32_t		ptr_mask;
990 	atomic_t		lock;
991 	bool                    enabled;
992 };
993 
994 /*
995  * RLC stuff
996  */
997 #include "clearstate_defs.h"
998 
999 struct radeon_rlc {
1000 	/* for power gating */
1001 	struct radeon_bo	*save_restore_obj;
1002 	u64			save_restore_gpu_addr;
1003 	volatile uint32_t	*sr_ptr;
1004 	const u32               *reg_list;
1005 	u32                     reg_list_size;
1006 	/* for clear state */
1007 	struct radeon_bo	*clear_state_obj;
1008 	u64			clear_state_gpu_addr;
1009 	volatile uint32_t	*cs_ptr;
1010 	const struct cs_section_def   *cs_data;
1011 	u32                     clear_state_size;
1012 	/* for cp tables */
1013 	struct radeon_bo	*cp_table_obj;
1014 	u64			cp_table_gpu_addr;
1015 	volatile uint32_t	*cp_table_ptr;
1016 	u32                     cp_table_size;
1017 };
1018 
1019 int radeon_ib_get(struct radeon_device *rdev, int ring,
1020 		  struct radeon_ib *ib, struct radeon_vm *vm,
1021 		  unsigned size);
1022 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1023 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1024 		       struct radeon_ib *const_ib, bool hdp_flush);
1025 int radeon_ib_pool_init(struct radeon_device *rdev);
1026 void radeon_ib_pool_fini(struct radeon_device *rdev);
1027 int radeon_ib_ring_tests(struct radeon_device *rdev);
1028 /* Ring access between begin & end cannot sleep */
1029 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1030 				      struct radeon_ring *ring);
1031 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1032 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1033 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1034 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1035 			bool hdp_flush);
1036 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1037 			       bool hdp_flush);
1038 void radeon_ring_undo(struct radeon_ring *ring);
1039 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1040 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1041 void radeon_ring_lockup_update(struct radeon_device *rdev,
1042 			       struct radeon_ring *ring);
1043 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1044 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1045 			    uint32_t **data);
1046 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1047 			unsigned size, uint32_t *data);
1048 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1049 		     unsigned rptr_offs, u32 nop);
1050 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1051 
1052 
1053 /* r600 async dma */
1054 void r600_dma_stop(struct radeon_device *rdev);
1055 int r600_dma_resume(struct radeon_device *rdev);
1056 void r600_dma_fini(struct radeon_device *rdev);
1057 
1058 void cayman_dma_stop(struct radeon_device *rdev);
1059 int cayman_dma_resume(struct radeon_device *rdev);
1060 void cayman_dma_fini(struct radeon_device *rdev);
1061 
1062 /*
1063  * CS.
1064  */
1065 struct radeon_cs_chunk {
1066 	uint32_t		length_dw;
1067 	uint32_t		*kdata;
1068 	void __user		*user_ptr;
1069 };
1070 
1071 struct radeon_cs_parser {
1072 	struct device		*dev;
1073 	struct radeon_device	*rdev;
1074 	struct drm_file		*filp;
1075 	/* chunks */
1076 	unsigned		nchunks;
1077 	struct radeon_cs_chunk	*chunks;
1078 	uint64_t		*chunks_array;
1079 	/* IB */
1080 	unsigned		idx;
1081 	/* relocations */
1082 	unsigned		nrelocs;
1083 	struct radeon_bo_list	*relocs;
1084 	struct radeon_bo_list	*vm_bos;
1085 	struct list_head	validated;
1086 	unsigned		dma_reloc_idx;
1087 	/* indices of various chunks */
1088 	struct radeon_cs_chunk  *chunk_ib;
1089 	struct radeon_cs_chunk  *chunk_relocs;
1090 	struct radeon_cs_chunk  *chunk_flags;
1091 	struct radeon_cs_chunk  *chunk_const_ib;
1092 	struct radeon_ib	ib;
1093 	struct radeon_ib	const_ib;
1094 	void			*track;
1095 	unsigned		family;
1096 	int			parser_error;
1097 	u32			cs_flags;
1098 	u32			ring;
1099 	s32			priority;
1100 	struct ww_acquire_ctx	ticket;
1101 };
1102 
radeon_get_ib_value(struct radeon_cs_parser * p,int idx)1103 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1104 {
1105 	struct radeon_cs_chunk *ibc = p->chunk_ib;
1106 
1107 	if (ibc->kdata)
1108 		return ibc->kdata[idx];
1109 	return p->ib.ptr[idx];
1110 }
1111 
1112 
1113 struct radeon_cs_packet {
1114 	unsigned	idx;
1115 	unsigned	type;
1116 	unsigned	reg;
1117 	unsigned	opcode;
1118 	int		count;
1119 	unsigned	one_reg_wr;
1120 };
1121 
1122 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1123 				      struct radeon_cs_packet *pkt,
1124 				      unsigned idx, unsigned reg);
1125 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1126 				      struct radeon_cs_packet *pkt);
1127 
1128 
1129 /*
1130  * AGP
1131  */
1132 int radeon_agp_init(struct radeon_device *rdev);
1133 void radeon_agp_resume(struct radeon_device *rdev);
1134 void radeon_agp_suspend(struct radeon_device *rdev);
1135 void radeon_agp_fini(struct radeon_device *rdev);
1136 
1137 
1138 /*
1139  * Writeback
1140  */
1141 struct radeon_wb {
1142 	struct radeon_bo	*wb_obj;
1143 	volatile uint32_t	*wb;
1144 	uint64_t		gpu_addr;
1145 	bool                    enabled;
1146 	bool                    use_event;
1147 };
1148 
1149 #define RADEON_WB_SCRATCH_OFFSET 0
1150 #define RADEON_WB_RING0_NEXT_RPTR 256
1151 #define RADEON_WB_CP_RPTR_OFFSET 1024
1152 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1153 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1154 #define R600_WB_DMA_RPTR_OFFSET   1792
1155 #define R600_WB_IH_WPTR_OFFSET   2048
1156 #define CAYMAN_WB_DMA1_RPTR_OFFSET   2304
1157 #define R600_WB_EVENT_OFFSET     3072
1158 #define CIK_WB_CP1_WPTR_OFFSET     3328
1159 #define CIK_WB_CP2_WPTR_OFFSET     3584
1160 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1161 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1162 
1163 /**
1164  * struct radeon_pm - power management datas
1165  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
1166  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1167  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
1168  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
1169  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
1170  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
1171  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1172  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
1173  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
1174  * @sclk:          	GPU clock Mhz (core bandwidth depends of this clock)
1175  * @needed_bandwidth:   current bandwidth needs
1176  *
1177  * It keeps track of various data needed to take powermanagement decision.
1178  * Bandwidth need is used to determine minimun clock of the GPU and memory.
1179  * Equation between gpu/memory clock and available bandwidth is hw dependent
1180  * (type of memory, bus size, efficiency, ...)
1181  */
1182 
1183 enum radeon_pm_method {
1184 	PM_METHOD_PROFILE,
1185 	PM_METHOD_DYNPM,
1186 	PM_METHOD_DPM,
1187 };
1188 
1189 enum radeon_dynpm_state {
1190 	DYNPM_STATE_DISABLED,
1191 	DYNPM_STATE_MINIMUM,
1192 	DYNPM_STATE_PAUSED,
1193 	DYNPM_STATE_ACTIVE,
1194 	DYNPM_STATE_SUSPENDED,
1195 };
1196 enum radeon_dynpm_action {
1197 	DYNPM_ACTION_NONE,
1198 	DYNPM_ACTION_MINIMUM,
1199 	DYNPM_ACTION_DOWNCLOCK,
1200 	DYNPM_ACTION_UPCLOCK,
1201 	DYNPM_ACTION_DEFAULT
1202 };
1203 
1204 enum radeon_voltage_type {
1205 	VOLTAGE_NONE = 0,
1206 	VOLTAGE_GPIO,
1207 	VOLTAGE_VDDC,
1208 	VOLTAGE_SW
1209 };
1210 
1211 enum radeon_pm_state_type {
1212 	/* not used for dpm */
1213 	POWER_STATE_TYPE_DEFAULT,
1214 	POWER_STATE_TYPE_POWERSAVE,
1215 	/* user selectable states */
1216 	POWER_STATE_TYPE_BATTERY,
1217 	POWER_STATE_TYPE_BALANCED,
1218 	POWER_STATE_TYPE_PERFORMANCE,
1219 	/* internal states */
1220 	POWER_STATE_TYPE_INTERNAL_UVD,
1221 	POWER_STATE_TYPE_INTERNAL_UVD_SD,
1222 	POWER_STATE_TYPE_INTERNAL_UVD_HD,
1223 	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1224 	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1225 	POWER_STATE_TYPE_INTERNAL_BOOT,
1226 	POWER_STATE_TYPE_INTERNAL_THERMAL,
1227 	POWER_STATE_TYPE_INTERNAL_ACPI,
1228 	POWER_STATE_TYPE_INTERNAL_ULV,
1229 	POWER_STATE_TYPE_INTERNAL_3DPERF,
1230 };
1231 
1232 enum radeon_pm_profile_type {
1233 	PM_PROFILE_DEFAULT,
1234 	PM_PROFILE_AUTO,
1235 	PM_PROFILE_LOW,
1236 	PM_PROFILE_MID,
1237 	PM_PROFILE_HIGH,
1238 };
1239 
1240 #define PM_PROFILE_DEFAULT_IDX 0
1241 #define PM_PROFILE_LOW_SH_IDX  1
1242 #define PM_PROFILE_MID_SH_IDX  2
1243 #define PM_PROFILE_HIGH_SH_IDX 3
1244 #define PM_PROFILE_LOW_MH_IDX  4
1245 #define PM_PROFILE_MID_MH_IDX  5
1246 #define PM_PROFILE_HIGH_MH_IDX 6
1247 #define PM_PROFILE_MAX         7
1248 
1249 struct radeon_pm_profile {
1250 	int dpms_off_ps_idx;
1251 	int dpms_on_ps_idx;
1252 	int dpms_off_cm_idx;
1253 	int dpms_on_cm_idx;
1254 };
1255 
1256 enum radeon_int_thermal_type {
1257 	THERMAL_TYPE_NONE,
1258 	THERMAL_TYPE_EXTERNAL,
1259 	THERMAL_TYPE_EXTERNAL_GPIO,
1260 	THERMAL_TYPE_RV6XX,
1261 	THERMAL_TYPE_RV770,
1262 	THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1263 	THERMAL_TYPE_EVERGREEN,
1264 	THERMAL_TYPE_SUMO,
1265 	THERMAL_TYPE_NI,
1266 	THERMAL_TYPE_SI,
1267 	THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1268 	THERMAL_TYPE_CI,
1269 	THERMAL_TYPE_KV,
1270 };
1271 
1272 struct radeon_voltage {
1273 	enum radeon_voltage_type type;
1274 	/* gpio voltage */
1275 	struct radeon_gpio_rec gpio;
1276 	u32 delay; /* delay in usec from voltage drop to sclk change */
1277 	bool active_high; /* voltage drop is active when bit is high */
1278 	/* VDDC voltage */
1279 	u8 vddc_id; /* index into vddc voltage table */
1280 	u8 vddci_id; /* index into vddci voltage table */
1281 	bool vddci_enabled;
1282 	/* r6xx+ sw */
1283 	u16 voltage;
1284 	/* evergreen+ vddci */
1285 	u16 vddci;
1286 };
1287 
1288 /* clock mode flags */
1289 #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
1290 
1291 struct radeon_pm_clock_info {
1292 	/* memory clock */
1293 	u32 mclk;
1294 	/* engine clock */
1295 	u32 sclk;
1296 	/* voltage info */
1297 	struct radeon_voltage voltage;
1298 	/* standardized clock flags */
1299 	u32 flags;
1300 };
1301 
1302 /* state flags */
1303 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1304 
1305 struct radeon_power_state {
1306 	enum radeon_pm_state_type type;
1307 	struct radeon_pm_clock_info *clock_info;
1308 	/* number of valid clock modes in this power state */
1309 	int num_clock_modes;
1310 	struct radeon_pm_clock_info *default_clock_mode;
1311 	/* standardized state flags */
1312 	u32 flags;
1313 	u32 misc; /* vbios specific flags */
1314 	u32 misc2; /* vbios specific flags */
1315 	int pcie_lanes; /* pcie lanes */
1316 };
1317 
1318 /*
1319  * Some modes are overclocked by very low value, accept them
1320  */
1321 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1322 
1323 enum radeon_dpm_auto_throttle_src {
1324 	RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1325 	RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1326 };
1327 
1328 enum radeon_dpm_event_src {
1329 	RADEON_DPM_EVENT_SRC_ANALOG = 0,
1330 	RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1331 	RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1332 	RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1333 	RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1334 };
1335 
1336 #define RADEON_MAX_VCE_LEVELS 6
1337 
1338 enum radeon_vce_level {
1339 	RADEON_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
1340 	RADEON_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
1341 	RADEON_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
1342 	RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1343 	RADEON_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
1344 	RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1345 };
1346 
1347 struct radeon_ps {
1348 	u32 caps; /* vbios flags */
1349 	u32 class; /* vbios flags */
1350 	u32 class2; /* vbios flags */
1351 	/* UVD clocks */
1352 	u32 vclk;
1353 	u32 dclk;
1354 	/* VCE clocks */
1355 	u32 evclk;
1356 	u32 ecclk;
1357 	bool vce_active;
1358 	enum radeon_vce_level vce_level;
1359 	/* asic priv */
1360 	void *ps_priv;
1361 };
1362 
1363 struct radeon_dpm_thermal {
1364 	/* thermal interrupt work */
1365 	struct work_struct work;
1366 	/* low temperature threshold */
1367 	int                min_temp;
1368 	/* high temperature threshold */
1369 	int                max_temp;
1370 	/* was interrupt low to high or high to low */
1371 	bool               high_to_low;
1372 };
1373 
1374 enum radeon_clk_action
1375 {
1376 	RADEON_SCLK_UP = 1,
1377 	RADEON_SCLK_DOWN
1378 };
1379 
1380 struct radeon_blacklist_clocks
1381 {
1382 	u32 sclk;
1383 	u32 mclk;
1384 	enum radeon_clk_action action;
1385 };
1386 
1387 struct radeon_clock_and_voltage_limits {
1388 	u32 sclk;
1389 	u32 mclk;
1390 	u16 vddc;
1391 	u16 vddci;
1392 };
1393 
1394 struct radeon_clock_array {
1395 	u32 count;
1396 	u32 *values;
1397 };
1398 
1399 struct radeon_clock_voltage_dependency_entry {
1400 	u32 clk;
1401 	u16 v;
1402 };
1403 
1404 struct radeon_clock_voltage_dependency_table {
1405 	u32 count;
1406 	struct radeon_clock_voltage_dependency_entry *entries;
1407 };
1408 
1409 union radeon_cac_leakage_entry {
1410 	struct {
1411 		u16 vddc;
1412 		u32 leakage;
1413 	};
1414 	struct {
1415 		u16 vddc1;
1416 		u16 vddc2;
1417 		u16 vddc3;
1418 	};
1419 };
1420 
1421 struct radeon_cac_leakage_table {
1422 	u32 count;
1423 	union radeon_cac_leakage_entry *entries;
1424 };
1425 
1426 struct radeon_phase_shedding_limits_entry {
1427 	u16 voltage;
1428 	u32 sclk;
1429 	u32 mclk;
1430 };
1431 
1432 struct radeon_phase_shedding_limits_table {
1433 	u32 count;
1434 	struct radeon_phase_shedding_limits_entry *entries;
1435 };
1436 
1437 struct radeon_uvd_clock_voltage_dependency_entry {
1438 	u32 vclk;
1439 	u32 dclk;
1440 	u16 v;
1441 };
1442 
1443 struct radeon_uvd_clock_voltage_dependency_table {
1444 	u8 count;
1445 	struct radeon_uvd_clock_voltage_dependency_entry *entries;
1446 };
1447 
1448 struct radeon_vce_clock_voltage_dependency_entry {
1449 	u32 ecclk;
1450 	u32 evclk;
1451 	u16 v;
1452 };
1453 
1454 struct radeon_vce_clock_voltage_dependency_table {
1455 	u8 count;
1456 	struct radeon_vce_clock_voltage_dependency_entry *entries;
1457 };
1458 
1459 struct radeon_ppm_table {
1460 	u8 ppm_design;
1461 	u16 cpu_core_number;
1462 	u32 platform_tdp;
1463 	u32 small_ac_platform_tdp;
1464 	u32 platform_tdc;
1465 	u32 small_ac_platform_tdc;
1466 	u32 apu_tdp;
1467 	u32 dgpu_tdp;
1468 	u32 dgpu_ulv_power;
1469 	u32 tj_max;
1470 };
1471 
1472 struct radeon_cac_tdp_table {
1473 	u16 tdp;
1474 	u16 configurable_tdp;
1475 	u16 tdc;
1476 	u16 battery_power_limit;
1477 	u16 small_power_limit;
1478 	u16 low_cac_leakage;
1479 	u16 high_cac_leakage;
1480 	u16 maximum_power_delivery_limit;
1481 };
1482 
1483 struct radeon_dpm_dynamic_state {
1484 	struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1485 	struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1486 	struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1487 	struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1488 	struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1489 	struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1490 	struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1491 	struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1492 	struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1493 	struct radeon_clock_array valid_sclk_values;
1494 	struct radeon_clock_array valid_mclk_values;
1495 	struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1496 	struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1497 	u32 mclk_sclk_ratio;
1498 	u32 sclk_mclk_delta;
1499 	u16 vddc_vddci_delta;
1500 	u16 min_vddc_for_pcie_gen2;
1501 	struct radeon_cac_leakage_table cac_leakage_table;
1502 	struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1503 	struct radeon_ppm_table *ppm_table;
1504 	struct radeon_cac_tdp_table *cac_tdp_table;
1505 };
1506 
1507 struct radeon_dpm_fan {
1508 	u16 t_min;
1509 	u16 t_med;
1510 	u16 t_high;
1511 	u16 pwm_min;
1512 	u16 pwm_med;
1513 	u16 pwm_high;
1514 	u8 t_hyst;
1515 	u32 cycle_delay;
1516 	u16 t_max;
1517 	u8 control_mode;
1518 	u16 default_max_fan_pwm;
1519 	u16 default_fan_output_sensitivity;
1520 	u16 fan_output_sensitivity;
1521 	bool ucode_fan_control;
1522 };
1523 
1524 enum radeon_pcie_gen {
1525 	RADEON_PCIE_GEN1 = 0,
1526 	RADEON_PCIE_GEN2 = 1,
1527 	RADEON_PCIE_GEN3 = 2,
1528 	RADEON_PCIE_GEN_INVALID = 0xffff
1529 };
1530 
1531 enum radeon_dpm_forced_level {
1532 	RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1533 	RADEON_DPM_FORCED_LEVEL_LOW = 1,
1534 	RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1535 };
1536 
1537 struct radeon_vce_state {
1538 	/* vce clocks */
1539 	u32 evclk;
1540 	u32 ecclk;
1541 	/* gpu clocks */
1542 	u32 sclk;
1543 	u32 mclk;
1544 	u8 clk_idx;
1545 	u8 pstate;
1546 };
1547 
1548 struct radeon_dpm {
1549 	struct radeon_ps        *ps;
1550 	/* number of valid power states */
1551 	int                     num_ps;
1552 	/* current power state that is active */
1553 	struct radeon_ps        *current_ps;
1554 	/* requested power state */
1555 	struct radeon_ps        *requested_ps;
1556 	/* boot up power state */
1557 	struct radeon_ps        *boot_ps;
1558 	/* default uvd power state */
1559 	struct radeon_ps        *uvd_ps;
1560 	/* vce requirements */
1561 	struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1562 	enum radeon_vce_level vce_level;
1563 	enum radeon_pm_state_type state;
1564 	enum radeon_pm_state_type user_state;
1565 	u32                     platform_caps;
1566 	u32                     voltage_response_time;
1567 	u32                     backbias_response_time;
1568 	void                    *priv;
1569 	u32			new_active_crtcs;
1570 	int			new_active_crtc_count;
1571 	u32			current_active_crtcs;
1572 	int			current_active_crtc_count;
1573 	bool single_display;
1574 	struct radeon_dpm_dynamic_state dyn_state;
1575 	struct radeon_dpm_fan fan;
1576 	u32 tdp_limit;
1577 	u32 near_tdp_limit;
1578 	u32 near_tdp_limit_adjusted;
1579 	u32 sq_ramping_threshold;
1580 	u32 cac_leakage;
1581 	u16 tdp_od_limit;
1582 	u32 tdp_adjustment;
1583 	u16 load_line_slope;
1584 	bool power_control;
1585 	bool ac_power;
1586 	/* special states active */
1587 	bool                    thermal_active;
1588 	bool                    uvd_active;
1589 	bool                    vce_active;
1590 	/* thermal handling */
1591 	struct radeon_dpm_thermal thermal;
1592 	/* forced levels */
1593 	enum radeon_dpm_forced_level forced_level;
1594 	/* track UVD streams */
1595 	unsigned sd;
1596 	unsigned hd;
1597 };
1598 
1599 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1600 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1601 
1602 struct radeon_pm {
1603 	struct lock		mutex;
1604 	/* write locked while reprogramming mclk */
1605 	struct lock		mclk_lock;
1606 	u32			active_crtcs;
1607 	int			active_crtc_count;
1608 	int			req_vblank;
1609 	bool			vblank_sync;
1610 	fixed20_12		max_bandwidth;
1611 	fixed20_12		igp_sideport_mclk;
1612 	fixed20_12		igp_system_mclk;
1613 	fixed20_12		igp_ht_link_clk;
1614 	fixed20_12		igp_ht_link_width;
1615 	fixed20_12		k8_bandwidth;
1616 	fixed20_12		sideport_bandwidth;
1617 	fixed20_12		ht_bandwidth;
1618 	fixed20_12		core_bandwidth;
1619 	fixed20_12		sclk;
1620 	fixed20_12		mclk;
1621 	fixed20_12		needed_bandwidth;
1622 	struct radeon_power_state *power_state;
1623 	/* number of valid power states */
1624 	int                     num_power_states;
1625 	int                     current_power_state_index;
1626 	int                     current_clock_mode_index;
1627 	int                     requested_power_state_index;
1628 	int                     requested_clock_mode_index;
1629 	int                     default_power_state_index;
1630 	u32                     current_sclk;
1631 	u32                     current_mclk;
1632 	u16                     current_vddc;
1633 	u16                     current_vddci;
1634 	u32                     default_sclk;
1635 	u32                     default_mclk;
1636 	u16                     default_vddc;
1637 	u16                     default_vddci;
1638 	struct radeon_i2c_chan *i2c_bus;
1639 	/* selected pm method */
1640 	enum radeon_pm_method     pm_method;
1641 	/* dynpm power management */
1642 	struct delayed_work	dynpm_idle_work;
1643 	enum radeon_dynpm_state	dynpm_state;
1644 	enum radeon_dynpm_action	dynpm_planned_action;
1645 	unsigned long		dynpm_action_timeout;
1646 	bool                    dynpm_can_upclock;
1647 	bool                    dynpm_can_downclock;
1648 	/* profile-based power management */
1649 	enum radeon_pm_profile_type profile;
1650 	int                     profile_index;
1651 	struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1652 	/* internal thermal controller on rv6xx+ */
1653 	enum radeon_int_thermal_type int_thermal_type;
1654 	struct ksensor		*int_sensor;
1655 	struct ksensordev	*int_sensordev;
1656 	/* fan control parameters */
1657 	bool                    no_fan;
1658 	u8                      fan_pulses_per_revolution;
1659 	u8                      fan_min_rpm;
1660 	u8                      fan_max_rpm;
1661 	/* dpm */
1662 	bool                    dpm_enabled;
1663 	bool                    sysfs_initialized;
1664 	struct radeon_dpm       dpm;
1665 };
1666 
1667 int radeon_pm_get_type_index(struct radeon_device *rdev,
1668 			     enum radeon_pm_state_type ps_type,
1669 			     int instance);
1670 /*
1671  * UVD
1672  */
1673 #define RADEON_DEFAULT_UVD_HANDLES	10
1674 #define RADEON_MAX_UVD_HANDLES		30
1675 #define RADEON_UVD_STACK_SIZE		(200*1024)
1676 #define RADEON_UVD_HEAP_SIZE		(256*1024)
1677 #define RADEON_UVD_SESSION_SIZE		(50*1024)
1678 
1679 struct radeon_uvd {
1680 	bool			fw_header_present;
1681 	struct radeon_bo	*vcpu_bo;
1682 	void			*cpu_addr;
1683 	u64			gpu_addr;
1684 	unsigned		max_handles;
1685 	atomic_t		handles[RADEON_MAX_UVD_HANDLES];
1686 	struct drm_file		*filp[RADEON_MAX_UVD_HANDLES];
1687 	unsigned		img_size[RADEON_MAX_UVD_HANDLES];
1688 	struct delayed_work	idle_work;
1689 };
1690 
1691 int radeon_uvd_init(struct radeon_device *rdev);
1692 void radeon_uvd_fini(struct radeon_device *rdev);
1693 int radeon_uvd_suspend(struct radeon_device *rdev);
1694 int radeon_uvd_resume(struct radeon_device *rdev);
1695 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1696 			      uint32_t handle, struct radeon_fence **fence);
1697 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1698 			       uint32_t handle, struct radeon_fence **fence);
1699 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1700 				       uint32_t allowed_domains);
1701 void radeon_uvd_free_handles(struct radeon_device *rdev,
1702 			     struct drm_file *filp);
1703 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1704 void radeon_uvd_note_usage(struct radeon_device *rdev);
1705 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1706 				  unsigned vclk, unsigned dclk,
1707 				  unsigned vco_min, unsigned vco_max,
1708 				  unsigned fb_factor, unsigned fb_mask,
1709 				  unsigned pd_min, unsigned pd_max,
1710 				  unsigned pd_even,
1711 				  unsigned *optimal_fb_div,
1712 				  unsigned *optimal_vclk_div,
1713 				  unsigned *optimal_dclk_div);
1714 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1715                                 unsigned cg_upll_func_cntl);
1716 
1717 /*
1718  * VCE
1719  */
1720 #define RADEON_MAX_VCE_HANDLES	16
1721 
1722 struct radeon_vce {
1723 	struct radeon_bo	*vcpu_bo;
1724 	u64			gpu_addr;
1725 	unsigned		fw_version;
1726 	unsigned		fb_version;
1727 	atomic_t		handles[RADEON_MAX_VCE_HANDLES];
1728 	struct drm_file		*filp[RADEON_MAX_VCE_HANDLES];
1729 	unsigned		img_size[RADEON_MAX_VCE_HANDLES];
1730 	struct delayed_work	idle_work;
1731 	uint32_t		keyselect;
1732 };
1733 
1734 int radeon_vce_init(struct radeon_device *rdev);
1735 void radeon_vce_fini(struct radeon_device *rdev);
1736 int radeon_vce_suspend(struct radeon_device *rdev);
1737 int radeon_vce_resume(struct radeon_device *rdev);
1738 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1739 			      uint32_t handle, struct radeon_fence **fence);
1740 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1741 			       uint32_t handle, struct radeon_fence **fence);
1742 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1743 void radeon_vce_note_usage(struct radeon_device *rdev);
1744 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1745 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1746 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1747 			       struct radeon_ring *ring,
1748 			       struct radeon_semaphore *semaphore,
1749 			       bool emit_wait);
1750 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1751 void radeon_vce_fence_emit(struct radeon_device *rdev,
1752 			   struct radeon_fence *fence);
1753 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1754 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1755 
1756 struct r600_audio_pin {
1757 	int			channels;
1758 	int			rate;
1759 	int			bits_per_sample;
1760 	u8			status_bits;
1761 	u8			category_code;
1762 	u32			offset;
1763 	bool			connected;
1764 	u32			id;
1765 };
1766 
1767 struct r600_audio {
1768 	bool enabled;
1769 	struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1770 	int num_pins;
1771 	struct radeon_audio_funcs *hdmi_funcs;
1772 	struct radeon_audio_funcs *dp_funcs;
1773 	struct radeon_audio_basic_funcs *funcs;
1774 };
1775 
1776 /*
1777  * Benchmarking
1778  */
1779 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1780 
1781 
1782 /*
1783  * Testing
1784  */
1785 void radeon_test_moves(struct radeon_device *rdev);
1786 void radeon_test_ring_sync(struct radeon_device *rdev,
1787 			   struct radeon_ring *cpA,
1788 			   struct radeon_ring *cpB);
1789 void radeon_test_syncing(struct radeon_device *rdev);
1790 
1791 /*
1792  * MMU Notifier
1793  */
1794 #if defined(CONFIG_MMU_NOTIFIER)
1795 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1796 void radeon_mn_unregister(struct radeon_bo *bo);
1797 #else
radeon_mn_register(struct radeon_bo * bo,unsigned long addr)1798 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1799 {
1800 	return -ENODEV;
1801 }
radeon_mn_unregister(struct radeon_bo * bo)1802 static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1803 #endif
1804 
1805 /*
1806  * Debugfs
1807  */
1808 struct radeon_debugfs {
1809 	struct drm_info_list	*files;
1810 	unsigned		num_files;
1811 };
1812 
1813 int radeon_debugfs_add_files(struct radeon_device *rdev,
1814 			     struct drm_info_list *files,
1815 			     unsigned nfiles);
1816 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1817 
1818 /*
1819  * ASIC ring specific functions.
1820  */
1821 struct radeon_asic_ring {
1822 	/* ring read/write ptr handling */
1823 	u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1824 	u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1825 	void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1826 
1827 	/* validating and patching of IBs */
1828 	int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1829 	int (*cs_parse)(struct radeon_cs_parser *p);
1830 
1831 	/* command emmit functions */
1832 	void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1833 	void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1834 	void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1835 	bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1836 			       struct radeon_semaphore *semaphore, bool emit_wait);
1837 	void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1838 			 unsigned vm_id, uint64_t pd_addr);
1839 
1840 	/* testing functions */
1841 	int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1842 	int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1843 	bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1844 
1845 	/* deprecated */
1846 	void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1847 };
1848 
1849 /*
1850  * ASIC specific functions.
1851  */
1852 struct radeon_asic {
1853 	int (*init)(struct radeon_device *rdev);
1854 	void (*fini)(struct radeon_device *rdev);
1855 	int (*resume)(struct radeon_device *rdev);
1856 	int (*suspend)(struct radeon_device *rdev);
1857 	void (*vga_set_state)(struct radeon_device *rdev, bool state);
1858 	int (*asic_reset)(struct radeon_device *rdev, bool hard);
1859 	/* Flush the HDP cache via MMIO */
1860 	void (*mmio_hdp_flush)(struct radeon_device *rdev);
1861 	/* check if 3D engine is idle */
1862 	bool (*gui_idle)(struct radeon_device *rdev);
1863 	/* wait for mc_idle */
1864 	int (*mc_wait_for_idle)(struct radeon_device *rdev);
1865 	/* get the reference clock */
1866 	u32 (*get_xclk)(struct radeon_device *rdev);
1867 	/* get the gpu clock counter */
1868 	uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1869 	/* get register for info ioctl */
1870 	int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1871 	/* gart */
1872 	struct {
1873 		void (*tlb_flush)(struct radeon_device *rdev);
1874 		uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1875 		void (*set_page)(struct radeon_device *rdev, unsigned i,
1876 				 uint64_t entry);
1877 	} gart;
1878 	struct {
1879 		int (*init)(struct radeon_device *rdev);
1880 		void (*fini)(struct radeon_device *rdev);
1881 		void (*copy_pages)(struct radeon_device *rdev,
1882 				   struct radeon_ib *ib,
1883 				   uint64_t pe, uint64_t src,
1884 				   unsigned count);
1885 		void (*write_pages)(struct radeon_device *rdev,
1886 				    struct radeon_ib *ib,
1887 				    uint64_t pe,
1888 				    uint64_t addr, unsigned count,
1889 				    uint32_t incr, uint32_t flags);
1890 		void (*set_pages)(struct radeon_device *rdev,
1891 				  struct radeon_ib *ib,
1892 				  uint64_t pe,
1893 				  uint64_t addr, unsigned count,
1894 				  uint32_t incr, uint32_t flags);
1895 		void (*pad_ib)(struct radeon_ib *ib);
1896 	} vm;
1897 	/* ring specific callbacks */
1898 	const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1899 	/* irqs */
1900 	struct {
1901 		int (*set)(struct radeon_device *rdev);
1902 		irqreturn_t (*process)(struct radeon_device *rdev);
1903 	} irq;
1904 	/* displays */
1905 	struct {
1906 		/* display watermarks */
1907 		void (*bandwidth_update)(struct radeon_device *rdev);
1908 		/* get frame count */
1909 		u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1910 		/* wait for vblank */
1911 		void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1912 		/* set backlight level */
1913 		void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1914 		/* get backlight level */
1915 		u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1916 		/* audio callbacks */
1917 		void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1918 		void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1919 	} display;
1920 	/* copy functions for bo handling */
1921 	struct {
1922 		struct radeon_fence *(*blit)(struct radeon_device *rdev,
1923 					     uint64_t src_offset,
1924 					     uint64_t dst_offset,
1925 					     unsigned num_gpu_pages,
1926 					     struct reservation_object *resv);
1927 		u32 blit_ring_index;
1928 		struct radeon_fence *(*dma)(struct radeon_device *rdev,
1929 					    uint64_t src_offset,
1930 					    uint64_t dst_offset,
1931 					    unsigned num_gpu_pages,
1932 					    struct reservation_object *resv);
1933 		u32 dma_ring_index;
1934 		/* method used for bo copy */
1935 		struct radeon_fence *(*copy)(struct radeon_device *rdev,
1936 					     uint64_t src_offset,
1937 					     uint64_t dst_offset,
1938 					     unsigned num_gpu_pages,
1939 					     struct reservation_object *resv);
1940 		/* ring used for bo copies */
1941 		u32 copy_ring_index;
1942 	} copy;
1943 	/* surfaces */
1944 	struct {
1945 		int (*set_reg)(struct radeon_device *rdev, int reg,
1946 				       uint32_t tiling_flags, uint32_t pitch,
1947 				       uint32_t offset, uint32_t obj_size);
1948 		void (*clear_reg)(struct radeon_device *rdev, int reg);
1949 	} surface;
1950 	/* hotplug detect */
1951 	struct {
1952 		void (*init)(struct radeon_device *rdev);
1953 		void (*fini)(struct radeon_device *rdev);
1954 		bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1955 		void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1956 	} hpd;
1957 	/* static power management */
1958 	struct {
1959 		void (*misc)(struct radeon_device *rdev);
1960 		void (*prepare)(struct radeon_device *rdev);
1961 		void (*finish)(struct radeon_device *rdev);
1962 		void (*init_profile)(struct radeon_device *rdev);
1963 		void (*get_dynpm_state)(struct radeon_device *rdev);
1964 		uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1965 		void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1966 		uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1967 		void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1968 		int (*get_pcie_lanes)(struct radeon_device *rdev);
1969 		void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1970 		void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1971 		int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1972 		int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1973 		int (*get_temperature)(struct radeon_device *rdev);
1974 	} pm;
1975 	/* dynamic power management */
1976 	struct {
1977 		int (*init)(struct radeon_device *rdev);
1978 		void (*setup_asic)(struct radeon_device *rdev);
1979 		int (*enable)(struct radeon_device *rdev);
1980 		int (*late_enable)(struct radeon_device *rdev);
1981 		void (*disable)(struct radeon_device *rdev);
1982 		int (*pre_set_power_state)(struct radeon_device *rdev);
1983 		int (*set_power_state)(struct radeon_device *rdev);
1984 		void (*post_set_power_state)(struct radeon_device *rdev);
1985 		void (*display_configuration_changed)(struct radeon_device *rdev);
1986 		void (*fini)(struct radeon_device *rdev);
1987 		u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1988 		u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1989 		void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1990 		void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1991 		int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1992 		bool (*vblank_too_short)(struct radeon_device *rdev);
1993 		void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1994 		void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1995 		void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1996 		u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1997 		int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1998 		int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
1999 		u32 (*get_current_sclk)(struct radeon_device *rdev);
2000 		u32 (*get_current_mclk)(struct radeon_device *rdev);
2001 	} dpm;
2002 	/* pageflipping */
2003 	struct {
2004 		void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
2005 		bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
2006 	} pflip;
2007 };
2008 
2009 /*
2010  * Asic structures
2011  */
2012 struct r100_asic {
2013 	const unsigned		*reg_safe_bm;
2014 	unsigned		reg_safe_bm_size;
2015 	u32			hdp_cntl;
2016 };
2017 
2018 struct r300_asic {
2019 	const unsigned		*reg_safe_bm;
2020 	unsigned		reg_safe_bm_size;
2021 	u32			resync_scratch;
2022 	u32			hdp_cntl;
2023 };
2024 
2025 struct r600_asic {
2026 	unsigned		max_pipes;
2027 	unsigned		max_tile_pipes;
2028 	unsigned		max_simds;
2029 	unsigned		max_backends;
2030 	unsigned		max_gprs;
2031 	unsigned		max_threads;
2032 	unsigned		max_stack_entries;
2033 	unsigned		max_hw_contexts;
2034 	unsigned		max_gs_threads;
2035 	unsigned		sx_max_export_size;
2036 	unsigned		sx_max_export_pos_size;
2037 	unsigned		sx_max_export_smx_size;
2038 	unsigned		sq_num_cf_insts;
2039 	unsigned		tiling_nbanks;
2040 	unsigned		tiling_npipes;
2041 	unsigned		tiling_group_size;
2042 	unsigned		tile_config;
2043 	unsigned		backend_map;
2044 	unsigned		active_simds;
2045 };
2046 
2047 struct rv770_asic {
2048 	unsigned		max_pipes;
2049 	unsigned		max_tile_pipes;
2050 	unsigned		max_simds;
2051 	unsigned		max_backends;
2052 	unsigned		max_gprs;
2053 	unsigned		max_threads;
2054 	unsigned		max_stack_entries;
2055 	unsigned		max_hw_contexts;
2056 	unsigned		max_gs_threads;
2057 	unsigned		sx_max_export_size;
2058 	unsigned		sx_max_export_pos_size;
2059 	unsigned		sx_max_export_smx_size;
2060 	unsigned		sq_num_cf_insts;
2061 	unsigned		sx_num_of_sets;
2062 	unsigned		sc_prim_fifo_size;
2063 	unsigned		sc_hiz_tile_fifo_size;
2064 	unsigned		sc_earlyz_tile_fifo_fize;
2065 	unsigned		tiling_nbanks;
2066 	unsigned		tiling_npipes;
2067 	unsigned		tiling_group_size;
2068 	unsigned		tile_config;
2069 	unsigned		backend_map;
2070 	unsigned		active_simds;
2071 };
2072 
2073 struct evergreen_asic {
2074 	unsigned num_ses;
2075 	unsigned max_pipes;
2076 	unsigned max_tile_pipes;
2077 	unsigned max_simds;
2078 	unsigned max_backends;
2079 	unsigned max_gprs;
2080 	unsigned max_threads;
2081 	unsigned max_stack_entries;
2082 	unsigned max_hw_contexts;
2083 	unsigned max_gs_threads;
2084 	unsigned sx_max_export_size;
2085 	unsigned sx_max_export_pos_size;
2086 	unsigned sx_max_export_smx_size;
2087 	unsigned sq_num_cf_insts;
2088 	unsigned sx_num_of_sets;
2089 	unsigned sc_prim_fifo_size;
2090 	unsigned sc_hiz_tile_fifo_size;
2091 	unsigned sc_earlyz_tile_fifo_size;
2092 	unsigned tiling_nbanks;
2093 	unsigned tiling_npipes;
2094 	unsigned tiling_group_size;
2095 	unsigned tile_config;
2096 	unsigned backend_map;
2097 	unsigned active_simds;
2098 };
2099 
2100 struct cayman_asic {
2101 	unsigned max_shader_engines;
2102 	unsigned max_pipes_per_simd;
2103 	unsigned max_tile_pipes;
2104 	unsigned max_simds_per_se;
2105 	unsigned max_backends_per_se;
2106 	unsigned max_texture_channel_caches;
2107 	unsigned max_gprs;
2108 	unsigned max_threads;
2109 	unsigned max_gs_threads;
2110 	unsigned max_stack_entries;
2111 	unsigned sx_num_of_sets;
2112 	unsigned sx_max_export_size;
2113 	unsigned sx_max_export_pos_size;
2114 	unsigned sx_max_export_smx_size;
2115 	unsigned max_hw_contexts;
2116 	unsigned sq_num_cf_insts;
2117 	unsigned sc_prim_fifo_size;
2118 	unsigned sc_hiz_tile_fifo_size;
2119 	unsigned sc_earlyz_tile_fifo_size;
2120 
2121 	unsigned num_shader_engines;
2122 	unsigned num_shader_pipes_per_simd;
2123 	unsigned num_tile_pipes;
2124 	unsigned num_simds_per_se;
2125 	unsigned num_backends_per_se;
2126 	unsigned backend_disable_mask_per_asic;
2127 	unsigned backend_map;
2128 	unsigned num_texture_channel_caches;
2129 	unsigned mem_max_burst_length_bytes;
2130 	unsigned mem_row_size_in_kb;
2131 	unsigned shader_engine_tile_size;
2132 	unsigned num_gpus;
2133 	unsigned multi_gpu_tile_size;
2134 
2135 	unsigned tile_config;
2136 	unsigned active_simds;
2137 };
2138 
2139 struct si_asic {
2140 	unsigned max_shader_engines;
2141 	unsigned max_tile_pipes;
2142 	unsigned max_cu_per_sh;
2143 	unsigned max_sh_per_se;
2144 	unsigned max_backends_per_se;
2145 	unsigned max_texture_channel_caches;
2146 	unsigned max_gprs;
2147 	unsigned max_gs_threads;
2148 	unsigned max_hw_contexts;
2149 	unsigned sc_prim_fifo_size_frontend;
2150 	unsigned sc_prim_fifo_size_backend;
2151 	unsigned sc_hiz_tile_fifo_size;
2152 	unsigned sc_earlyz_tile_fifo_size;
2153 
2154 	unsigned num_tile_pipes;
2155 	unsigned backend_enable_mask;
2156 	unsigned backend_disable_mask_per_asic;
2157 	unsigned backend_map;
2158 	unsigned num_texture_channel_caches;
2159 	unsigned mem_max_burst_length_bytes;
2160 	unsigned mem_row_size_in_kb;
2161 	unsigned shader_engine_tile_size;
2162 	unsigned num_gpus;
2163 	unsigned multi_gpu_tile_size;
2164 
2165 	unsigned tile_config;
2166 	uint32_t tile_mode_array[32];
2167 	uint32_t active_cus;
2168 };
2169 
2170 struct cik_asic {
2171 	unsigned max_shader_engines;
2172 	unsigned max_tile_pipes;
2173 	unsigned max_cu_per_sh;
2174 	unsigned max_sh_per_se;
2175 	unsigned max_backends_per_se;
2176 	unsigned max_texture_channel_caches;
2177 	unsigned max_gprs;
2178 	unsigned max_gs_threads;
2179 	unsigned max_hw_contexts;
2180 	unsigned sc_prim_fifo_size_frontend;
2181 	unsigned sc_prim_fifo_size_backend;
2182 	unsigned sc_hiz_tile_fifo_size;
2183 	unsigned sc_earlyz_tile_fifo_size;
2184 
2185 	unsigned num_tile_pipes;
2186 	unsigned backend_enable_mask;
2187 	unsigned backend_disable_mask_per_asic;
2188 	unsigned backend_map;
2189 	unsigned num_texture_channel_caches;
2190 	unsigned mem_max_burst_length_bytes;
2191 	unsigned mem_row_size_in_kb;
2192 	unsigned shader_engine_tile_size;
2193 	unsigned num_gpus;
2194 	unsigned multi_gpu_tile_size;
2195 
2196 	unsigned tile_config;
2197 	uint32_t tile_mode_array[32];
2198 	uint32_t macrotile_mode_array[16];
2199 	uint32_t active_cus;
2200 };
2201 
2202 union radeon_asic_config {
2203 	struct r300_asic	r300;
2204 	struct r100_asic	r100;
2205 	struct r600_asic	r600;
2206 	struct rv770_asic	rv770;
2207 	struct evergreen_asic	evergreen;
2208 	struct cayman_asic	cayman;
2209 	struct si_asic		si;
2210 	struct cik_asic		cik;
2211 };
2212 
2213 /*
2214  * asic initizalization from radeon_asic.c
2215  */
2216 int radeon_asic_init(struct radeon_device *rdev);
2217 
2218 
2219 /*
2220  * IOCTL.
2221  */
2222 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2223 			  struct drm_file *filp);
2224 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2225 			    struct drm_file *filp);
2226 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2227 			     struct drm_file *filp);
2228 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2229 			 struct drm_file *file_priv);
2230 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2231 			   struct drm_file *file_priv);
2232 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2233 			    struct drm_file *file_priv);
2234 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2235 			   struct drm_file *file_priv);
2236 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2237 				struct drm_file *filp);
2238 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2239 			  struct drm_file *filp);
2240 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2241 			  struct drm_file *filp);
2242 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2243 			      struct drm_file *filp);
2244 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2245 			  struct drm_file *filp);
2246 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2247 			struct drm_file *filp);
2248 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2249 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2250 				struct drm_file *filp);
2251 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2252 				struct drm_file *filp);
2253 
2254 /* VRAM scratch page for HDP bug, default vram page */
2255 struct r600_vram_scratch {
2256 	struct radeon_bo		*robj;
2257 	volatile uint32_t		*ptr;
2258 	u64				gpu_addr;
2259 };
2260 
2261 /*
2262  * ACPI
2263  */
2264 struct radeon_atif_notification_cfg {
2265 	bool enabled;
2266 	int command_code;
2267 };
2268 
2269 struct radeon_atif_notifications {
2270 	bool display_switch;
2271 	bool expansion_mode_change;
2272 	bool thermal_state;
2273 	bool forced_power_state;
2274 	bool system_power_state;
2275 	bool display_conf_change;
2276 	bool px_gfx_switch;
2277 	bool brightness_change;
2278 	bool dgpu_display_event;
2279 };
2280 
2281 struct radeon_atif_functions {
2282 	bool system_params;
2283 	bool sbios_requests;
2284 	bool select_active_disp;
2285 	bool lid_state;
2286 	bool get_tv_standard;
2287 	bool set_tv_standard;
2288 	bool get_panel_expansion_mode;
2289 	bool set_panel_expansion_mode;
2290 	bool temperature_change;
2291 	bool graphics_device_types;
2292 };
2293 
2294 struct radeon_atif {
2295 	struct radeon_atif_notifications notifications;
2296 	struct radeon_atif_functions functions;
2297 	struct radeon_atif_notification_cfg notification_cfg;
2298 	struct radeon_encoder *encoder_for_bl;
2299 };
2300 
2301 struct radeon_atcs_functions {
2302 	bool get_ext_state;
2303 	bool pcie_perf_req;
2304 	bool pcie_dev_rdy;
2305 	bool pcie_bus_width;
2306 };
2307 
2308 struct radeon_atcs {
2309 	struct radeon_atcs_functions functions;
2310 };
2311 
2312 /*
2313  * Core structure, functions and helpers.
2314  */
2315 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2316 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2317 
2318 struct radeon_device {
2319 	struct device			*dev;
2320 	struct drm_device		*ddev;
2321 	struct pci_dev			*pdev;
2322 	struct lock			exclusive_lock;
2323 	/* ASIC */
2324 	union radeon_asic_config	config;
2325 	enum radeon_family		family;
2326 	unsigned long			flags;
2327 	int				usec_timeout;
2328 	enum radeon_pll_errata		pll_errata;
2329 	int				num_gb_pipes;
2330 	int				num_z_pipes;
2331 	int				disp_priority;
2332 	/* BIOS */
2333 	uint8_t				*bios;
2334 	bool				is_atom_bios;
2335 	uint16_t			bios_header_start;
2336 	struct radeon_bo		*stolen_vga_memory;
2337 	/* Register mmio */
2338 	resource_size_t			rmmio_base;
2339 	resource_size_t			rmmio_size;
2340 	/* protects concurrent MM_INDEX/DATA based register access */
2341 	spinlock_t mmio_idx_lock;
2342 	/* protects concurrent SMC based register access */
2343 	spinlock_t smc_idx_lock;
2344 	/* protects concurrent PLL register access */
2345 	spinlock_t pll_idx_lock;
2346 	/* protects concurrent MC register access */
2347 	spinlock_t mc_idx_lock;
2348 	/* protects concurrent PCIE register access */
2349 	spinlock_t pcie_idx_lock;
2350 	/* protects concurrent PCIE_PORT register access */
2351 	spinlock_t pciep_idx_lock;
2352 	/* protects concurrent PIF register access */
2353 	spinlock_t pif_idx_lock;
2354 	/* protects concurrent CG register access */
2355 	spinlock_t cg_idx_lock;
2356 	/* protects concurrent UVD register access */
2357 	spinlock_t uvd_idx_lock;
2358 	/* protects concurrent RCU register access */
2359 	spinlock_t rcu_idx_lock;
2360 	/* protects concurrent DIDT register access */
2361 	spinlock_t didt_idx_lock;
2362 	/* protects concurrent ENDPOINT (audio) register access */
2363 	spinlock_t end_idx_lock;
2364 	void __iomem			*rmmio;
2365 	radeon_rreg_t			mc_rreg;
2366 	radeon_wreg_t			mc_wreg;
2367 	radeon_rreg_t			pll_rreg;
2368 	radeon_wreg_t			pll_wreg;
2369 	uint32_t                        pcie_reg_mask;
2370 	radeon_rreg_t			pciep_rreg;
2371 	radeon_wreg_t			pciep_wreg;
2372 	/* io port */
2373 	int				rio_rid;
2374 	struct resource			*rio_mem;
2375 	resource_size_t			rio_mem_size;
2376 	struct radeon_clock             clock;
2377 	struct radeon_mc		mc;
2378 	struct radeon_gart		gart;
2379 	struct radeon_mode_info		mode_info;
2380 	struct radeon_scratch		scratch;
2381 	struct radeon_doorbell		doorbell;
2382 	struct radeon_mman		mman;
2383 	struct radeon_fence_driver	fence_drv[RADEON_NUM_RINGS];
2384 	wait_queue_head_t		fence_queue;
2385 	u64				fence_context;
2386 	struct lock			ring_lock;
2387 	struct radeon_ring		ring[RADEON_NUM_RINGS];
2388 	bool				ib_pool_ready;
2389 	struct radeon_sa_manager	ring_tmp_bo;
2390 	struct radeon_irq		irq;
2391 	struct radeon_asic		*asic;
2392 	struct radeon_gem		gem;
2393 	struct radeon_pm		pm;
2394 	struct radeon_uvd		uvd;
2395 	struct radeon_vce		vce;
2396 	uint32_t			bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2397 	struct radeon_wb		wb;
2398 	struct radeon_dummy_page	dummy_page;
2399 	bool				shutdown;
2400 	bool				need_dma32;
2401 	bool				accel_working;
2402 	bool				fastfb_working; /* IGP feature*/
2403 	bool				needs_reset, in_reset;
2404 	bool				fictitious_range_registered;
2405 	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2406 	const struct firmware *me_fw;	/* all family ME firmware */
2407 	const struct firmware *pfp_fw;	/* r6/700 PFP firmware */
2408 	const struct firmware *rlc_fw;	/* r6/700 RLC firmware */
2409 	const struct firmware *mc_fw;	/* NI MC firmware */
2410 	const struct firmware *ce_fw;	/* SI CE firmware */
2411 	const struct firmware *mec_fw;	/* CIK MEC firmware */
2412 	const struct firmware *mec2_fw;	/* KV MEC2 firmware */
2413 	const struct firmware *sdma_fw;	/* CIK SDMA firmware */
2414 	const struct firmware *smc_fw;	/* SMC firmware */
2415 	const struct firmware *uvd_fw;	/* UVD firmware */
2416 	const struct firmware *vce_fw;	/* VCE firmware */
2417 	bool new_fw;
2418 	struct r600_vram_scratch vram_scratch;
2419 	int msi_enabled; /* msi enabled */
2420 	struct r600_ih ih; /* r6/700 interrupt ring */
2421 	struct radeon_rlc rlc;
2422 	struct radeon_mec mec;
2423 	struct delayed_work hotplug_work;
2424 	struct work_struct dp_work;
2425 	struct work_struct audio_work;
2426 	int num_crtc; /* number of crtcs */
2427 	struct lock dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2428 	bool has_uvd;
2429 	bool has_vce;
2430 	struct r600_audio audio; /* audio stuff */
2431 	struct {
2432 		ACPI_HANDLE		handle;
2433 		ACPI_NOTIFY_HANDLER	notifier_call;
2434 	} acpi;
2435 	/* only one userspace can use Hyperz features or CMASK at a time */
2436 	struct drm_file *hyperz_filp;
2437 	struct drm_file *cmask_filp;
2438 	/* i2c buses */
2439 	struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2440 	/* debugfs */
2441 	struct radeon_debugfs	debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2442 	unsigned 		debugfs_count;
2443 	/* virtual memory */
2444 	struct radeon_vm_manager	vm_manager;
2445 	struct lock			gpu_clock_mutex;
2446 	/* memory stats */
2447 	atomic64_t			vram_usage;
2448 	atomic64_t			gtt_usage;
2449 	atomic64_t			num_bytes_moved;
2450 	atomic_t			gpu_reset_counter;
2451 	/* ACPI interface */
2452 	struct radeon_atif		atif;
2453 	struct radeon_atcs		atcs;
2454 	/* srbm instance registers */
2455 	struct lock			srbm_mutex;
2456 	/* GRBM index mutex. Protects concurrents access to GRBM index */
2457 	struct lock			grbm_idx_mutex;
2458 	/* clock, powergating flags */
2459 	u32 cg_flags;
2460 	u32 pg_flags;
2461 
2462 #ifdef PM_TODO
2463 	struct dev_pm_domain vga_pm_domain;
2464 #endif
2465 	bool have_disp_power_ref;
2466 	u32 px_quirk_flags;
2467 
2468 	/* tracking pinned memory */
2469 	u64 vram_pin_size;
2470 	u64 gart_pin_size;
2471 
2472 	/* amdkfd interface */
2473 	struct kfd_dev		*kfd;
2474 
2475 	struct lock	mn_lock;
2476 	DECLARE_HASHTABLE(mn_hash, 7);
2477 };
2478 
2479 bool radeon_is_px(struct drm_device *dev);
2480 int radeon_device_init(struct radeon_device *rdev,
2481 		       struct drm_device *ddev,
2482 		       struct pci_dev *pdev,
2483 		       uint32_t flags);
2484 void radeon_device_fini(struct radeon_device *rdev);
2485 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2486 
2487 #define RADEON_MIN_MMIO_SIZE 0x10000
2488 
2489 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2490 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
r100_mm_rreg(struct radeon_device * rdev,uint32_t reg,bool always_indirect)2491 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2492 				    bool always_indirect)
2493 {
2494 	/* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2495 	if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2496 		return readl(((void __iomem *)rdev->rmmio) + reg);
2497 	else
2498 		return r100_mm_rreg_slow(rdev, reg);
2499 }
r100_mm_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v,bool always_indirect)2500 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2501 				bool always_indirect)
2502 {
2503 	if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2504 		writel(v, ((void __iomem *)rdev->rmmio) + reg);
2505 	else
2506 		r100_mm_wreg_slow(rdev, reg, v);
2507 }
2508 
2509 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2510 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2511 
2512 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2513 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2514 
2515 /*
2516  * Cast helper
2517  */
2518 extern const struct dma_fence_ops radeon_fence_ops;
2519 
to_radeon_fence(struct dma_fence * f)2520 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f)
2521 {
2522 	struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2523 
2524 	if (__f->base.ops == &radeon_fence_ops)
2525 		return __f;
2526 
2527 	return NULL;
2528 }
2529 
2530 /*
2531  * Registers read & write functions.
2532  */
2533 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2534 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2535 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2536 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2537 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2538 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2539 #define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
2540 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2541 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2542 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2543 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2544 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2545 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2546 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2547 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2548 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2549 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2550 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2551 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2552 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2553 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2554 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2555 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2556 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2557 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2558 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2559 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2560 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2561 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2562 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2563 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2564 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2565 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2566 #define WREG32_P(reg, val, mask)				\
2567 	do {							\
2568 		uint32_t tmp_ = RREG32(reg);			\
2569 		tmp_ &= (mask);					\
2570 		tmp_ |= ((val) & ~(mask));			\
2571 		WREG32(reg, tmp_);				\
2572 	} while (0)
2573 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2574 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2575 #define WREG32_PLL_P(reg, val, mask)				\
2576 	do {							\
2577 		uint32_t tmp_ = RREG32_PLL(reg);		\
2578 		tmp_ &= (mask);					\
2579 		tmp_ |= ((val) & ~(mask));			\
2580 		WREG32_PLL(reg, tmp_);				\
2581 	} while (0)
2582 #define WREG32_SMC_P(reg, val, mask)				\
2583 	do {							\
2584 		uint32_t tmp_ = RREG32_SMC(reg);		\
2585 		tmp_ &= (mask);					\
2586 		tmp_ |= ((val) & ~(mask));			\
2587 		WREG32_SMC(reg, tmp_);				\
2588 	} while (0)
2589 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2590 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2591 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2592 
2593 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2594 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2595 
2596 /*
2597  * Indirect registers accessors.
2598  * They used to be inlined, but this increases code size by ~65 kbytes.
2599  * Since each performs a pair of MMIO ops
2600  * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2601  * the cost of call+ret is almost negligible. MMIO and locking
2602  * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2603  */
2604 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2605 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2606 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2607 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2608 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2609 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2610 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2611 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2612 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2613 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2614 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2615 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2616 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2617 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2618 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2619 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2620 
2621 void r100_pll_errata_after_index(struct radeon_device *rdev);
2622 
2623 
2624 /*
2625  * ASICs helpers.
2626  */
2627 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2628 			    (rdev->pdev->device == 0x5969))
2629 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2630 		(rdev->family == CHIP_RV200) || \
2631 		(rdev->family == CHIP_RS100) || \
2632 		(rdev->family == CHIP_RS200) || \
2633 		(rdev->family == CHIP_RV250) || \
2634 		(rdev->family == CHIP_RV280) || \
2635 		(rdev->family == CHIP_RS300))
2636 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||	\
2637 		(rdev->family == CHIP_RV350) ||			\
2638 		(rdev->family == CHIP_R350)  ||			\
2639 		(rdev->family == CHIP_RV380) ||			\
2640 		(rdev->family == CHIP_R420)  ||			\
2641 		(rdev->family == CHIP_R423)  ||			\
2642 		(rdev->family == CHIP_RV410) ||			\
2643 		(rdev->family == CHIP_RS400) ||			\
2644 		(rdev->family == CHIP_RS480))
2645 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2646 		(rdev->ddev->pdev->device == 0x9443) || \
2647 		(rdev->ddev->pdev->device == 0x944B) || \
2648 		(rdev->ddev->pdev->device == 0x9506) || \
2649 		(rdev->ddev->pdev->device == 0x9509) || \
2650 		(rdev->ddev->pdev->device == 0x950F) || \
2651 		(rdev->ddev->pdev->device == 0x689C) || \
2652 		(rdev->ddev->pdev->device == 0x689D))
2653 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2654 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||	\
2655 			    (rdev->family == CHIP_RS690)  ||	\
2656 			    (rdev->family == CHIP_RS740)  ||	\
2657 			    (rdev->family >= CHIP_R600))
2658 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2659 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2660 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2661 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2662 			     (rdev->flags & RADEON_IS_IGP))
2663 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2664 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2665 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2666 			     (rdev->flags & RADEON_IS_IGP))
2667 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2668 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2669 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2670 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2671 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2672 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2673 			     (rdev->family == CHIP_MULLINS))
2674 
2675 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2676 			      (rdev->ddev->pdev->device == 0x6850) || \
2677 			      (rdev->ddev->pdev->device == 0x6858) || \
2678 			      (rdev->ddev->pdev->device == 0x6859) || \
2679 			      (rdev->ddev->pdev->device == 0x6840) || \
2680 			      (rdev->ddev->pdev->device == 0x6841) || \
2681 			      (rdev->ddev->pdev->device == 0x6842) || \
2682 			      (rdev->ddev->pdev->device == 0x6843))
2683 
2684 /*
2685  * BIOS helpers.
2686  */
2687 #define RBIOS8(i) (rdev->bios[i])
2688 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2689 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2690 
2691 int radeon_combios_init(struct radeon_device *rdev);
2692 void radeon_combios_fini(struct radeon_device *rdev);
2693 int radeon_atombios_init(struct radeon_device *rdev);
2694 void radeon_atombios_fini(struct radeon_device *rdev);
2695 
2696 
2697 /*
2698  * RING helpers.
2699  */
2700 
2701 /**
2702  * radeon_ring_write - write a value to the ring
2703  *
2704  * @ring: radeon_ring structure holding ring information
2705  * @v: dword (dw) value to write
2706  *
2707  * Write a value to the requested ring buffer (all asics).
2708  */
radeon_ring_write(struct radeon_ring * ring,uint32_t v)2709 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2710 {
2711 	if (ring->count_dw <= 0)
2712 		DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2713 
2714 	ring->ring[ring->wptr++] = v;
2715 	ring->wptr &= ring->ptr_mask;
2716 	ring->count_dw--;
2717 	ring->ring_free_dw--;
2718 }
2719 
2720 /*
2721  * ASICs macro.
2722  */
2723 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2724 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2725 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2726 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2727 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2728 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2729 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
2730 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2731 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2732 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2733 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2734 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2735 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2736 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2737 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2738 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2739 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2740 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2741 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2742 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2743 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2744 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2745 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2746 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2747 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2748 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2749 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2750 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2751 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2752 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2753 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2754 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2755 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2756 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2757 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2758 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2759 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2760 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2761 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2762 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2763 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2764 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2765 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2766 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2767 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2768 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2769 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2770 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2771 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2772 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2773 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2774 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2775 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2776 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2777 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2778 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2779 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2780 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2781 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2782 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2783 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2784 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2785 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2786 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2787 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
2788 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2789 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2790 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2791 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2792 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2793 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2794 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2795 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2796 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2797 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2798 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2799 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2800 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2801 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2802 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2803 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2804 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2805 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2806 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2807 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2808 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2809 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2810 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2811 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2812 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2813 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2814 
2815 /* Common functions */
2816 /* AGP */
2817 extern int radeon_gpu_reset(struct radeon_device *rdev);
2818 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2819 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2820 extern void radeon_agp_disable(struct radeon_device *rdev);
2821 extern int radeon_modeset_init(struct radeon_device *rdev);
2822 extern void radeon_modeset_fini(struct radeon_device *rdev);
2823 extern bool radeon_card_posted(struct radeon_device *rdev);
2824 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2825 extern void radeon_update_display_priority(struct radeon_device *rdev);
2826 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2827 extern void radeon_scratch_init(struct radeon_device *rdev);
2828 extern void radeon_wb_fini(struct radeon_device *rdev);
2829 extern int radeon_wb_init(struct radeon_device *rdev);
2830 extern void radeon_wb_disable(struct radeon_device *rdev);
2831 extern void radeon_surface_init(struct radeon_device *rdev);
2832 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2833 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2834 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2835 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2836 				     uint32_t flags);
2837 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2838 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2839 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2840 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2841 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2842 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
2843 			      bool fbcon, bool freeze);
2844 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2845 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2846 					     const u32 *registers,
2847 					     const u32 array_size);
2848 
2849 /*
2850  * vm
2851  */
2852 int radeon_vm_manager_init(struct radeon_device *rdev);
2853 void radeon_vm_manager_fini(struct radeon_device *rdev);
2854 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2855 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2856 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2857 					  struct radeon_vm *vm,
2858                                           struct list_head *head);
2859 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2860 				       struct radeon_vm *vm, int ring);
2861 void radeon_vm_flush(struct radeon_device *rdev,
2862                      struct radeon_vm *vm,
2863 		     int ring, struct radeon_fence *fence);
2864 void radeon_vm_fence(struct radeon_device *rdev,
2865 		     struct radeon_vm *vm,
2866 		     struct radeon_fence *fence);
2867 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2868 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2869 				    struct radeon_vm *vm);
2870 int radeon_vm_clear_freed(struct radeon_device *rdev,
2871 			  struct radeon_vm *vm);
2872 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2873 			     struct radeon_vm *vm);
2874 int radeon_vm_bo_update(struct radeon_device *rdev,
2875 			struct radeon_bo_va *bo_va,
2876 			struct ttm_mem_reg *mem);
2877 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2878 			     struct radeon_bo *bo);
2879 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2880 				       struct radeon_bo *bo);
2881 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2882 				      struct radeon_vm *vm,
2883 				      struct radeon_bo *bo);
2884 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2885 			  struct radeon_bo_va *bo_va,
2886 			  uint64_t offset,
2887 			  uint32_t flags);
2888 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2889 		      struct radeon_bo_va *bo_va);
2890 
2891 /* audio */
2892 void r600_audio_update_hdmi(struct work_struct *work);
2893 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2894 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2895 void r600_audio_enable(struct radeon_device *rdev,
2896 		       struct r600_audio_pin *pin,
2897 		       u8 enable_mask);
2898 void dce6_audio_enable(struct radeon_device *rdev,
2899 		       struct r600_audio_pin *pin,
2900 		       u8 enable_mask);
2901 
2902 /*
2903  * R600 vram scratch functions
2904  */
2905 int r600_vram_scratch_init(struct radeon_device *rdev);
2906 void r600_vram_scratch_fini(struct radeon_device *rdev);
2907 
2908 /*
2909  * r600 cs checking helper
2910  */
2911 unsigned r600_mip_minify(unsigned size, unsigned level);
2912 bool r600_fmt_is_valid_color(u32 format);
2913 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2914 int r600_fmt_get_blocksize(u32 format);
2915 int r600_fmt_get_nblocksx(u32 format, u32 w);
2916 int r600_fmt_get_nblocksy(u32 format, u32 h);
2917 
2918 /*
2919  * r600 functions used by radeon_encoder.c
2920  */
2921 struct radeon_hdmi_acr {
2922 	u32 clock;
2923 
2924 	int n_32khz;
2925 	int cts_32khz;
2926 
2927 	int n_44_1khz;
2928 	int cts_44_1khz;
2929 
2930 	int n_48khz;
2931 	int cts_48khz;
2932 
2933 };
2934 
2935 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2936 
2937 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2938 				     u32 tiling_pipe_num,
2939 				     u32 max_rb_num,
2940 				     u32 total_max_rb_num,
2941 				     u32 enabled_rb_mask);
2942 
2943 /*
2944  * evergreen functions used by radeon_encoder.c
2945  */
2946 
2947 extern int ni_init_microcode(struct radeon_device *rdev);
2948 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2949 extern void ni_fini_microcode(struct radeon_device *rdev);
2950 
2951 /* radeon_acpi.c */
2952 #if defined(CONFIG_ACPI)
2953 extern int radeon_acpi_init(struct radeon_device *rdev);
2954 extern void radeon_acpi_fini(struct radeon_device *rdev);
2955 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2956 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2957 						u8 perf_req, bool advertise);
2958 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2959 
2960 /* Prototypes added by @dumbbell. */
2961 
2962 /* atombios_encoders.c */
2963 void	radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
2964 	    struct drm_connector *drm_connector);
2965 void	radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
2966 	    uint32_t supported_device, u16 caps);
2967 
2968 /* radeon_atombios.c */
2969 bool	radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
2970 	    struct drm_display_mode *mode);
2971 
2972 /* radeon_legacy_encoders.c */
2973 void	radeon_add_legacy_encoder(struct drm_device *dev,
2974 	    uint32_t encoder_enum, uint32_t supported_device);
2975 void	radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
2976 	    struct drm_connector *drm_connector);
2977 
2978 /* radeon_pm.c */
2979 void	radeon_pm_acpi_event_handler(struct radeon_device *rdev);
2980 
2981 /* radeon_ttm.c */
2982 int	radeon_ttm_init(struct radeon_device *rdev);
2983 void	radeon_ttm_fini(struct radeon_device *rdev);
2984 
2985 /* r600.c */
2986 int r600_ih_ring_alloc(struct radeon_device *rdev);
2987 void r600_ih_ring_fini(struct radeon_device *rdev);
2988 #else
radeon_acpi_init(struct radeon_device * rdev)2989 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
radeon_acpi_fini(struct radeon_device * rdev)2990 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2991 #endif
2992 
2993 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2994 			   struct radeon_cs_packet *pkt,
2995 			   unsigned idx);
2996 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2997 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2998 			   struct radeon_cs_packet *pkt);
2999 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3000 				struct radeon_bo_list **cs_reloc,
3001 				int nomm);
3002 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3003 			       uint32_t *vline_start_end,
3004 			       uint32_t *vline_status);
3005 
3006 /* interrupt control register helpers */
3007 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev,
3008 				      u32 reg, u32 mask,
3009 				      bool enable, const char *name,
3010 				      unsigned n);
3011 
3012 #include "radeon_object.h"
3013 
3014 #endif
3015