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/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-pinebook/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-utilite/u-boot-2015.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-bananapim2/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-rpi4/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-rockpro64/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument

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