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/dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/video/
H A Dbus_vcxk.c23 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
32 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
33 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
44 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
47 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
48 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-riotboard/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-rpi-arm64/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-rock-pi-4/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-rpi2/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-rpi3/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/sysutils/u-boot-rock64/u-boot-2021.07/drivers/video/
H A Dbus_vcxk.c24 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
33 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
34 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
45 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
48 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
49 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
/dports/net-im/openfire/Openfire-4.7.1/xmppserver/src/main/java/org/jivesoftware/openfire/session/
H A DConnectionSettings.java16 public static final String PORT = "xmpp.socket.plain.port"; field in ConnectionSettings.Client
70 public static final String PORT = "xmpp.server.socket.port"; field in ConnectionSettings.Server
105 public static final String PORT = "xmpp.multiplex.socket.port"; field in ConnectionSettings.Multiplex
119 public static final String PORT = "xmpp.component.socket.port"; field in ConnectionSettings.Component
/dports/comms/py-pyserial/pyserial-3.5/test/
H A Dtest_readline.py31 PORT = 'loop://' variable
100 PORT = sys.argv[1] variable
H A Dtest_threaded.py19 PORT = 'loop://' variable
71 PORT = sys.argv[1] variable
H A Dtest_cancel.py17 PORT = 'loop://' variable
105 PORT = sys.argv[1] variable
H A Dtest_asyncio.py16 PORT = '/dev/ttyUSB0' variable
78 PORT = sys.argv[1] variable
/dports/textproc/py-elasticsearch-curator/curator-5.8.4/test/integration/
H A Dtest_close.py12 HOST, PORT = os.environ.get('TEST_ES_SERVER', 'localhost:9200').split(':') variable
13 PORT = int(PORT) if PORT else 9200 variable
/dports/net/py-libcloud/apache-libcloud-3.4.1/test/dns/fixtures/linode/
H A Dresource_list.json6 "PORT": 80, number
18 "PORT": 25565, number
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gcc/libgloss/sparc/
H A Dsalib.c45 #define get_uart_status(PORT) \ argument
48 #define xmt_char(PORT, C) \ argument
51 #define rcv_char(PORT) \ argument
/dports/devel/arm-none-eabi-newlib/newlib-2.4.0/libgloss/sparc/
H A Dsalib.c45 #define get_uart_status(PORT) \ argument
48 #define xmt_char(PORT, C) \ argument
51 #define rcv_char(PORT) \ argument
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gcc/libgloss/sparc/
H A Dsalib.c45 #define get_uart_status(PORT) \ argument
48 #define xmt_char(PORT, C) \ argument
51 #define rcv_char(PORT) \ argument
/dports/sysutils/webmin/webmin-1.981/firewall/
H A Dopen-ports.pl65 PORT: foreach $p (@ARGV) { label
/dports/sysutils/webmin/webmin-1.981/firewall6/
H A Dopen-ports.pl65 PORT: foreach $p (@ARGV) { label

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