1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 1997-2000 Nicolas Souchu
5 * Copyright (c) 2001 Alcove - Nicolas Souchu
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 #include "opt_ppc.h"
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/kernel.h>
37 #include <sys/lock.h>
38 #include <sys/interrupt.h>
39 #include <sys/module.h>
40 #include <sys/malloc.h>
41 #include <sys/mutex.h>
42 #include <sys/proc.h>
43
44 #include <machine/bus.h>
45 #include <machine/resource.h>
46 #include <sys/rman.h>
47
48 #ifdef __i386__
49 #include <vm/vm.h>
50 #include <vm/pmap.h>
51 #include <machine/vmparam.h>
52 #include <machine/pc/bios.h>
53 #endif
54
55 #include <dev/ppbus/ppbconf.h>
56 #include <dev/ppbus/ppb_msq.h>
57
58 #include <dev/ppc/ppcvar.h>
59 #include <dev/ppc/ppcreg.h>
60
61 #include "ppbus_if.h"
62
63 static void ppcintr(void *arg);
64
65 #define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */
66 #define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */
67
68 #define LOG_PPC(function, ppc, string) \
69 if (bootverbose) printf("%s: %s\n", function, string)
70
71 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
72
73 /*
74 * We use critical enter/exit for the simple config locking needed to
75 * detect the devices. We just want to make sure that both of our writes
76 * happen without someone else also writing to those config registers. Since
77 * we just do this at startup, Giant keeps multiple threads from executing,
78 * and critical_enter() then is all that's needed to keep us from being preempted
79 * during the critical sequences with the hardware.
80 *
81 * Note: this doesn't prevent multiple threads from putting the chips into
82 * config mode, but since we only do that to detect the type at startup the
83 * extra overhead isn't needed since Giant protects us from multiple entry
84 * and no other code changes these registers.
85 */
86 #define PPC_CONFIG_LOCK(ppc) critical_enter()
87 #define PPC_CONFIG_UNLOCK(ppc) critical_exit()
88
89 const char ppc_driver_name[] = "ppc";
90
91 static char *ppc_models[] = {
92 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
93 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
94 "SMC FDC37C935", "PC87303", 0
95 };
96
97 /* list of available modes */
98 static char *ppc_avms[] = {
99 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
100 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
101 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
102 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
103 };
104
105 /* list of current executing modes
106 * Note that few modes do not actually exist.
107 */
108 static char *ppc_modes[] = {
109 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
110 "EPP", "EPP", "EPP", "ECP",
111 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
112 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
113 };
114
115 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
116
117 #ifdef __i386__
118 /*
119 * BIOS printer list - used by BIOS probe.
120 */
121 #define BIOS_PPC_PORTS 0x408
122 #define BIOS_PORTS ((short *)BIOS_PADDRTOVADDR(BIOS_PPC_PORTS))
123 #define BIOS_MAX_PPC 4
124 #endif
125
126 /*
127 * ppc_ecp_sync() XXX
128 */
129 int
ppc_ecp_sync(device_t dev)130 ppc_ecp_sync(device_t dev)
131 {
132 int i, r;
133 struct ppc_data *ppc = DEVTOSOFTC(dev);
134
135 PPC_ASSERT_LOCKED(ppc);
136 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
137 return 0;
138
139 r = r_ecr(ppc);
140 if ((r & 0xe0) != PPC_ECR_EPP)
141 return 0;
142
143 for (i = 0; i < 100; i++) {
144 r = r_ecr(ppc);
145 if (r & 0x1)
146 return 0;
147 DELAY(100);
148 }
149
150 device_printf(dev, "ECP sync failed as data still present in FIFO.\n");
151
152 return 0;
153 }
154
155 /*
156 * ppc_detect_fifo()
157 *
158 * Detect parallel port FIFO
159 */
160 static int
ppc_detect_fifo(struct ppc_data * ppc)161 ppc_detect_fifo(struct ppc_data *ppc)
162 {
163 char ecr_sav;
164 char ctr_sav, ctr;
165 short i;
166
167 /* save registers */
168 ecr_sav = r_ecr(ppc);
169 ctr_sav = r_ctr(ppc);
170
171 /* enter ECP configuration mode, no interrupt, no DMA */
172 w_ecr(ppc, 0xf4);
173
174 /* read PWord size - transfers in FIFO mode must be PWord aligned */
175 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
176
177 /* XXX 16 and 32 bits implementations not supported */
178 if (ppc->ppc_pword != PPC_PWORD_8) {
179 LOG_PPC(__func__, ppc, "PWord not supported");
180 goto error;
181 }
182
183 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
184 ctr = r_ctr(ppc);
185 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
186
187 /* enter ECP test mode, no interrupt, no DMA */
188 w_ecr(ppc, 0xd4);
189
190 /* flush the FIFO */
191 for (i=0; i<1024; i++) {
192 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
193 break;
194 r_fifo(ppc);
195 }
196
197 if (i >= 1024) {
198 LOG_PPC(__func__, ppc, "can't flush FIFO");
199 goto error;
200 }
201
202 /* enable interrupts, no DMA */
203 w_ecr(ppc, 0xd0);
204
205 /* determine readIntrThreshold
206 * fill the FIFO until serviceIntr is set
207 */
208 for (i=0; i<1024; i++) {
209 w_fifo(ppc, (char)i);
210 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
211 /* readThreshold reached */
212 ppc->ppc_rthr = i+1;
213 }
214 if (r_ecr(ppc) & PPC_FIFO_FULL) {
215 ppc->ppc_fifo = i+1;
216 break;
217 }
218 }
219
220 if (i >= 1024) {
221 LOG_PPC(__func__, ppc, "can't fill FIFO");
222 goto error;
223 }
224
225 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
226 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
227 w_ecr(ppc, 0xd0); /* enable interrupts */
228
229 /* determine writeIntrThreshold
230 * empty the FIFO until serviceIntr is set
231 */
232 for (i=ppc->ppc_fifo; i>0; i--) {
233 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
234 LOG_PPC(__func__, ppc, "invalid data in FIFO");
235 goto error;
236 }
237 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
238 /* writeIntrThreshold reached */
239 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
240 }
241 /* if FIFO empty before the last byte, error */
242 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
243 LOG_PPC(__func__, ppc, "data lost in FIFO");
244 goto error;
245 }
246 }
247
248 /* FIFO must be empty after the last byte */
249 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
250 LOG_PPC(__func__, ppc, "can't empty the FIFO");
251 goto error;
252 }
253
254 w_ctr(ppc, ctr_sav);
255 w_ecr(ppc, ecr_sav);
256
257 return (0);
258
259 error:
260 w_ctr(ppc, ctr_sav);
261 w_ecr(ppc, ecr_sav);
262
263 return (EINVAL);
264 }
265
266 static int
ppc_detect_port(struct ppc_data * ppc)267 ppc_detect_port(struct ppc_data *ppc)
268 {
269
270 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
271 w_dtr(ppc, 0xaa);
272 if (r_dtr(ppc) != 0xaa)
273 return (0);
274
275 return (1);
276 }
277
278 /*
279 * EPP timeout, according to the PC87332 manual
280 * Semantics of clearing EPP timeout bit.
281 * PC87332 - reading SPP_STR does it...
282 * SMC - write 1 to EPP timeout bit XXX
283 * Others - (?) write 0 to EPP timeout bit
284 */
285 static void
ppc_reset_epp_timeout(struct ppc_data * ppc)286 ppc_reset_epp_timeout(struct ppc_data *ppc)
287 {
288 char r;
289
290 r = r_str(ppc);
291 w_str(ppc, r | 0x1);
292 w_str(ppc, r & 0xfe);
293
294 return;
295 }
296
297 static int
ppc_check_epp_timeout(struct ppc_data * ppc)298 ppc_check_epp_timeout(struct ppc_data *ppc)
299 {
300 ppc_reset_epp_timeout(ppc);
301
302 return (!(r_str(ppc) & TIMEOUT));
303 }
304
305 /*
306 * Configure current operating mode
307 */
308 static int
ppc_generic_setmode(struct ppc_data * ppc,int mode)309 ppc_generic_setmode(struct ppc_data *ppc, int mode)
310 {
311 u_char ecr = 0;
312
313 /* check if mode is available */
314 if (mode && !(ppc->ppc_avm & mode))
315 return (EINVAL);
316
317 /* if ECP mode, configure ecr register */
318 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
319 /* return to byte mode (keeping direction bit),
320 * no interrupt, no DMA to be able to change to
321 * ECP
322 */
323 w_ecr(ppc, PPC_ECR_RESET);
324 ecr = PPC_DISABLE_INTR;
325
326 if (mode & PPB_EPP)
327 return (EINVAL);
328 else if (mode & PPB_ECP)
329 /* select ECP mode */
330 ecr |= PPC_ECR_ECP;
331 else if (mode & PPB_PS2)
332 /* select PS2 mode with ECP */
333 ecr |= PPC_ECR_PS2;
334 else
335 /* select COMPATIBLE/NIBBLE mode */
336 ecr |= PPC_ECR_STD;
337
338 w_ecr(ppc, ecr);
339 }
340
341 ppc->ppc_mode = mode;
342
343 return (0);
344 }
345
346 /*
347 * The ppc driver is free to choose options like FIFO or DMA
348 * if ECP mode is available.
349 *
350 * The 'RAW' option allows the upper drivers to force the ppc mode
351 * even with FIFO, DMA available.
352 */
353 static int
ppc_smclike_setmode(struct ppc_data * ppc,int mode)354 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
355 {
356 u_char ecr = 0;
357
358 /* check if mode is available */
359 if (mode && !(ppc->ppc_avm & mode))
360 return (EINVAL);
361
362 /* if ECP mode, configure ecr register */
363 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
364 /* return to byte mode (keeping direction bit),
365 * no interrupt, no DMA to be able to change to
366 * ECP or EPP mode
367 */
368 w_ecr(ppc, PPC_ECR_RESET);
369 ecr = PPC_DISABLE_INTR;
370
371 if (mode & PPB_EPP)
372 /* select EPP mode */
373 ecr |= PPC_ECR_EPP;
374 else if (mode & PPB_ECP)
375 /* select ECP mode */
376 ecr |= PPC_ECR_ECP;
377 else if (mode & PPB_PS2)
378 /* select PS2 mode with ECP */
379 ecr |= PPC_ECR_PS2;
380 else
381 /* select COMPATIBLE/NIBBLE mode */
382 ecr |= PPC_ECR_STD;
383
384 w_ecr(ppc, ecr);
385 }
386
387 ppc->ppc_mode = mode;
388
389 return (0);
390 }
391
392 #ifdef PPC_PROBE_CHIPSET
393 /*
394 * ppc_pc873xx_detect
395 *
396 * Probe for a Natsemi PC873xx-family part.
397 *
398 * References in this function are to the National Semiconductor
399 * PC87332 datasheet TL/C/11930, May 1995 revision.
400 */
401 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
402 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
403 static int pc873xx_irqtab[] = {5, 7, 5, 0};
404
405 static int pc873xx_regstab[] = {
406 PC873_FER, PC873_FAR, PC873_PTR,
407 PC873_FCR, PC873_PCR, PC873_PMC,
408 PC873_TUP, PC873_SID, PC873_PNP0,
409 PC873_PNP1, PC873_LPTBA, -1
410 };
411
412 static char *pc873xx_rnametab[] = {
413 "FER", "FAR", "PTR", "FCR", "PCR",
414 "PMC", "TUP", "SID", "PNP0", "PNP1",
415 "LPTBA", NULL
416 };
417
418 static int
ppc_pc873xx_detect(struct ppc_data * ppc,int chipset_mode)419 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
420 {
421 static int index = 0;
422 int idport, irq;
423 int ptr, pcr, val, i;
424
425 while ((idport = pc873xx_basetab[index++])) {
426 /* XXX should check first to see if this location is already claimed */
427
428 /*
429 * Pull the 873xx through the power-on ID cycle (2.2,1.).
430 * We can't use this to locate the chip as it may already have
431 * been used by the BIOS.
432 */
433 (void)inb(idport); (void)inb(idport);
434 (void)inb(idport); (void)inb(idport);
435
436 /*
437 * Read the SID byte. Possible values are :
438 *
439 * 01010xxx PC87334
440 * 0001xxxx PC87332
441 * 01110xxx PC87306
442 * 00110xxx PC87303
443 */
444 outb(idport, PC873_SID);
445 val = inb(idport + 1);
446 if ((val & 0xf0) == 0x10) {
447 ppc->ppc_model = NS_PC87332;
448 } else if ((val & 0xf8) == 0x70) {
449 ppc->ppc_model = NS_PC87306;
450 } else if ((val & 0xf8) == 0x50) {
451 ppc->ppc_model = NS_PC87334;
452 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
453 documentation, but probing
454 yielded 0x40... */
455 ppc->ppc_model = NS_PC87303;
456 } else {
457 if (bootverbose && (val != 0xff))
458 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
459 continue ; /* not recognised */
460 }
461
462 /* print registers */
463 if (bootverbose) {
464 printf("PC873xx");
465 for (i=0; pc873xx_regstab[i] != -1; i++) {
466 outb(idport, pc873xx_regstab[i]);
467 printf(" %s=0x%x", pc873xx_rnametab[i],
468 inb(idport + 1) & 0xff);
469 }
470 printf("\n");
471 }
472
473 /*
474 * We think we have one. Is it enabled and where we want it to be?
475 */
476 outb(idport, PC873_FER);
477 val = inb(idport + 1);
478 if (!(val & PC873_PPENABLE)) {
479 if (bootverbose)
480 printf("PC873xx parallel port disabled\n");
481 continue;
482 }
483 outb(idport, PC873_FAR);
484 val = inb(idport + 1);
485 /* XXX we should create a driver instance for every port found */
486 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
487 /* First try to change the port address to that requested... */
488
489 switch (ppc->ppc_base) {
490 case 0x378:
491 val &= 0xfc;
492 break;
493
494 case 0x3bc:
495 val &= 0xfd;
496 break;
497
498 case 0x278:
499 val &= 0xfe;
500 break;
501
502 default:
503 val &= 0xfd;
504 break;
505 }
506
507 outb(idport, PC873_FAR);
508 outb(idport + 1, val);
509 outb(idport + 1, val);
510
511 /* Check for success by reading back the value we supposedly
512 wrote and comparing...*/
513
514 outb(idport, PC873_FAR);
515 val = inb(idport + 1) & 0x3;
516
517 /* If we fail, report the failure... */
518
519 if (pc873xx_porttab[val] != ppc->ppc_base) {
520 if (bootverbose)
521 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
522 pc873xx_porttab[val], ppc->ppc_base);
523 }
524 continue;
525 }
526
527 outb(idport, PC873_PTR);
528 ptr = inb(idport + 1);
529
530 /* get irq settings */
531 if (ppc->ppc_base == 0x378)
532 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
533 else
534 irq = pc873xx_irqtab[val];
535
536 if (bootverbose)
537 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
538
539 /*
540 * Check if irq settings are correct
541 */
542 if (irq != ppc->ppc_irq) {
543 /*
544 * If the chipset is not locked and base address is 0x378,
545 * we have another chance
546 */
547 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
548 if (ppc->ppc_irq == 7) {
549 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
550 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
551 } else {
552 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
553 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
554 }
555 if (bootverbose)
556 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
557 } else {
558 if (bootverbose)
559 printf("PC873xx sorry, can't change irq setting\n");
560 }
561 } else {
562 if (bootverbose)
563 printf("PC873xx irq settings are correct\n");
564 }
565
566 outb(idport, PC873_PCR);
567 pcr = inb(idport + 1);
568
569 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
570 if (bootverbose)
571 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
572
573 ppc->ppc_avm |= PPB_NIBBLE;
574 if (bootverbose)
575 printf(", NIBBLE");
576
577 if (pcr & PC873_EPPEN) {
578 ppc->ppc_avm |= PPB_EPP;
579
580 if (bootverbose)
581 printf(", EPP");
582
583 if (pcr & PC873_EPP19)
584 ppc->ppc_epp = EPP_1_9;
585 else
586 ppc->ppc_epp = EPP_1_7;
587
588 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
589 outb(idport, PC873_PTR);
590 ptr = inb(idport + 1);
591 if (ptr & PC873_EPPRDIR)
592 printf(", Regular mode");
593 else
594 printf(", Automatic mode");
595 }
596 } else if (pcr & PC873_ECPEN) {
597 ppc->ppc_avm |= PPB_ECP;
598 if (bootverbose)
599 printf(", ECP");
600
601 if (pcr & PC873_ECPCLK) { /* XXX */
602 ppc->ppc_avm |= PPB_PS2;
603 if (bootverbose)
604 printf(", PS/2");
605 }
606 } else {
607 outb(idport, PC873_PTR);
608 ptr = inb(idport + 1);
609 if (ptr & PC873_EXTENDED) {
610 ppc->ppc_avm |= PPB_SPP;
611 if (bootverbose)
612 printf(", SPP");
613 }
614 }
615 } else {
616 if (bootverbose)
617 printf("PC873xx unlocked");
618
619 if (chipset_mode & PPB_ECP) {
620 if ((chipset_mode & PPB_EPP) && bootverbose)
621 printf(", ECP+EPP not supported");
622
623 pcr &= ~PC873_EPPEN;
624 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
625 outb(idport + 1, pcr);
626 outb(idport + 1, pcr);
627
628 if (bootverbose)
629 printf(", ECP");
630
631 } else if (chipset_mode & PPB_EPP) {
632 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
633 pcr |= (PC873_EPPEN | PC873_EPP19);
634 outb(idport + 1, pcr);
635 outb(idport + 1, pcr);
636
637 ppc->ppc_epp = EPP_1_9; /* XXX */
638
639 if (bootverbose)
640 printf(", EPP1.9");
641
642 /* enable automatic direction turnover */
643 if (ppc->ppc_model == NS_PC87332) {
644 outb(idport, PC873_PTR);
645 ptr = inb(idport + 1);
646 ptr &= ~PC873_EPPRDIR;
647 outb(idport + 1, ptr);
648 outb(idport + 1, ptr);
649
650 if (bootverbose)
651 printf(", Automatic mode");
652 }
653 } else {
654 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
655 outb(idport + 1, pcr);
656 outb(idport + 1, pcr);
657
658 /* configure extended bit in PTR */
659 outb(idport, PC873_PTR);
660 ptr = inb(idport + 1);
661
662 if (chipset_mode & PPB_PS2) {
663 ptr |= PC873_EXTENDED;
664
665 if (bootverbose)
666 printf(", PS/2");
667
668 } else {
669 /* default to NIBBLE mode */
670 ptr &= ~PC873_EXTENDED;
671
672 if (bootverbose)
673 printf(", NIBBLE");
674 }
675 outb(idport + 1, ptr);
676 outb(idport + 1, ptr);
677 }
678
679 ppc->ppc_avm = chipset_mode;
680 }
681
682 if (bootverbose)
683 printf("\n");
684
685 ppc->ppc_type = PPC_TYPE_GENERIC;
686 ppc_generic_setmode(ppc, chipset_mode);
687
688 return(chipset_mode);
689 }
690 return(-1);
691 }
692
693 /*
694 * ppc_smc37c66xgt_detect
695 *
696 * SMC FDC37C66xGT configuration.
697 */
698 static int
ppc_smc37c66xgt_detect(struct ppc_data * ppc,int chipset_mode)699 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
700 {
701 int i;
702 u_char r;
703 int type = -1;
704 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
705
706 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
707
708 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
709
710 /*
711 * Detection: enter configuration mode and read CRD register.
712 */
713 PPC_CONFIG_LOCK(ppc);
714 outb(csr, SMC665_iCODE);
715 outb(csr, SMC665_iCODE);
716 PPC_CONFIG_UNLOCK(ppc);
717
718 outb(csr, 0xd);
719 if (inb(cio) == 0x65) {
720 type = SMC_37C665GT;
721 goto config;
722 }
723
724 for (i = 0; i < 2; i++) {
725 PPC_CONFIG_LOCK(ppc);
726 outb(csr, SMC666_iCODE);
727 outb(csr, SMC666_iCODE);
728 PPC_CONFIG_UNLOCK(ppc);
729
730 outb(csr, 0xd);
731 if (inb(cio) == 0x66) {
732 type = SMC_37C666GT;
733 break;
734 }
735
736 /* Another chance, CSR may be hard-configured to be at 0x370 */
737 csr = SMC666_CSR;
738 }
739
740 config:
741 /*
742 * If chipset not found, do not continue.
743 */
744 if (type == -1) {
745 outb(csr, 0xaa); /* end config mode */
746 return (-1);
747 }
748
749 /* select CR1 */
750 outb(csr, 0x1);
751
752 /* read the port's address: bits 0 and 1 of CR1 */
753 r = inb(cio) & SMC_CR1_ADDR;
754 if (port_address[(int)r] != ppc->ppc_base) {
755 outb(csr, 0xaa); /* end config mode */
756 return (-1);
757 }
758
759 ppc->ppc_model = type;
760
761 /*
762 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
763 * If SPP mode is detected, try to set ECP+EPP mode
764 */
765
766 if (bootverbose) {
767 outb(csr, 0x1);
768 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x",
769 inb(cio) & 0xff);
770
771 outb(csr, 0x4);
772 printf(" CR4=0x%x", inb(cio) & 0xff);
773 }
774
775 /* select CR1 */
776 outb(csr, 0x1);
777
778 if (!chipset_mode) {
779 /* autodetect mode */
780
781 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
782 if (type == SMC_37C666GT) {
783 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
784 if (bootverbose)
785 printf(" configuration hardwired, supposing " \
786 "ECP+EPP SPP");
787
788 } else
789 if ((inb(cio) & SMC_CR1_MODE) == 0) {
790 /* already in extended parallel port mode, read CR4 */
791 outb(csr, 0x4);
792 r = (inb(cio) & SMC_CR4_EMODE);
793
794 switch (r) {
795 case SMC_SPP:
796 ppc->ppc_avm |= PPB_SPP;
797 if (bootverbose)
798 printf(" SPP");
799 break;
800
801 case SMC_EPPSPP:
802 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
803 if (bootverbose)
804 printf(" EPP SPP");
805 break;
806
807 case SMC_ECP:
808 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
809 if (bootverbose)
810 printf(" ECP SPP");
811 break;
812
813 case SMC_ECPEPP:
814 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
815 if (bootverbose)
816 printf(" ECP+EPP SPP");
817 break;
818 }
819 } else {
820 /* not an extended port mode */
821 ppc->ppc_avm |= PPB_SPP;
822 if (bootverbose)
823 printf(" SPP");
824 }
825
826 } else {
827 /* mode forced */
828 ppc->ppc_avm = chipset_mode;
829
830 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
831 if (type == SMC_37C666GT)
832 goto end_detect;
833
834 r = inb(cio);
835 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
836 /* do not use ECP when the mode is not forced to */
837 outb(cio, r | SMC_CR1_MODE);
838 if (bootverbose)
839 printf(" SPP");
840 } else {
841 /* an extended mode is selected */
842 outb(cio, r & ~SMC_CR1_MODE);
843
844 /* read CR4 register and reset mode field */
845 outb(csr, 0x4);
846 r = inb(cio) & ~SMC_CR4_EMODE;
847
848 if (chipset_mode & PPB_ECP) {
849 if (chipset_mode & PPB_EPP) {
850 outb(cio, r | SMC_ECPEPP);
851 if (bootverbose)
852 printf(" ECP+EPP");
853 } else {
854 outb(cio, r | SMC_ECP);
855 if (bootverbose)
856 printf(" ECP");
857 }
858 } else {
859 /* PPB_EPP is set */
860 outb(cio, r | SMC_EPPSPP);
861 if (bootverbose)
862 printf(" EPP SPP");
863 }
864 }
865 ppc->ppc_avm = chipset_mode;
866 }
867
868 /* set FIFO threshold to 16 */
869 if (ppc->ppc_avm & PPB_ECP) {
870 /* select CRA */
871 outb(csr, 0xa);
872 outb(cio, 16);
873 }
874
875 end_detect:
876
877 if (bootverbose)
878 printf ("\n");
879
880 if (ppc->ppc_avm & PPB_EPP) {
881 /* select CR4 */
882 outb(csr, 0x4);
883 r = inb(cio);
884
885 /*
886 * Set the EPP protocol...
887 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
888 */
889 if (ppc->ppc_epp == EPP_1_9)
890 outb(cio, (r & ~SMC_CR4_EPPTYPE));
891 else
892 outb(cio, (r | SMC_CR4_EPPTYPE));
893 }
894
895 outb(csr, 0xaa); /* end config mode */
896
897 ppc->ppc_type = PPC_TYPE_SMCLIKE;
898 ppc_smclike_setmode(ppc, chipset_mode);
899
900 return (chipset_mode);
901 }
902
903 /*
904 * SMC FDC37C935 configuration
905 * Found on many Alpha machines
906 */
907 static int
ppc_smc37c935_detect(struct ppc_data * ppc,int chipset_mode)908 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
909 {
910 int type = -1;
911
912 PPC_CONFIG_LOCK(ppc);
913 outb(SMC935_CFG, 0x55); /* enter config mode */
914 outb(SMC935_CFG, 0x55);
915 PPC_CONFIG_UNLOCK(ppc);
916
917 outb(SMC935_IND, SMC935_ID); /* check device id */
918 if (inb(SMC935_DAT) == 0x2)
919 type = SMC_37C935;
920
921 if (type == -1) {
922 outb(SMC935_CFG, 0xaa); /* exit config mode */
923 return (-1);
924 }
925
926 ppc->ppc_model = type;
927
928 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
929 outb(SMC935_DAT, 3); /* which is logical device 3 */
930
931 /* set io port base */
932 outb(SMC935_IND, SMC935_PORTHI);
933 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
934 outb(SMC935_IND, SMC935_PORTLO);
935 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
936
937 if (!chipset_mode)
938 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
939 else {
940 ppc->ppc_avm = chipset_mode;
941 outb(SMC935_IND, SMC935_PPMODE);
942 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
943
944 /* SPP + EPP or just plain SPP */
945 if (chipset_mode & (PPB_SPP)) {
946 if (chipset_mode & PPB_EPP) {
947 if (ppc->ppc_epp == EPP_1_9) {
948 outb(SMC935_IND, SMC935_PPMODE);
949 outb(SMC935_DAT, SMC935_EPP19SPP);
950 }
951 if (ppc->ppc_epp == EPP_1_7) {
952 outb(SMC935_IND, SMC935_PPMODE);
953 outb(SMC935_DAT, SMC935_EPP17SPP);
954 }
955 } else {
956 outb(SMC935_IND, SMC935_PPMODE);
957 outb(SMC935_DAT, SMC935_SPP);
958 }
959 }
960
961 /* ECP + EPP or just plain ECP */
962 if (chipset_mode & PPB_ECP) {
963 if (chipset_mode & PPB_EPP) {
964 if (ppc->ppc_epp == EPP_1_9) {
965 outb(SMC935_IND, SMC935_PPMODE);
966 outb(SMC935_DAT, SMC935_ECPEPP19);
967 }
968 if (ppc->ppc_epp == EPP_1_7) {
969 outb(SMC935_IND, SMC935_PPMODE);
970 outb(SMC935_DAT, SMC935_ECPEPP17);
971 }
972 } else {
973 outb(SMC935_IND, SMC935_PPMODE);
974 outb(SMC935_DAT, SMC935_ECP);
975 }
976 }
977 }
978
979 outb(SMC935_CFG, 0xaa); /* exit config mode */
980
981 ppc->ppc_type = PPC_TYPE_SMCLIKE;
982 ppc_smclike_setmode(ppc, chipset_mode);
983
984 return (chipset_mode);
985 }
986
987 /*
988 * Winbond W83877F stuff
989 *
990 * EFER: extended function enable register
991 * EFIR: extended function index register
992 * EFDR: extended function data register
993 */
994 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
995 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
996
997 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
998 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
999 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
1000 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1001
1002 static int
ppc_w83877f_detect(struct ppc_data * ppc,int chipset_mode)1003 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
1004 {
1005 int i, j, efer;
1006 unsigned char r, hefere, hefras;
1007
1008 for (i = 0; i < 4; i ++) {
1009 /* first try to enable configuration registers */
1010 efer = w83877f_efers[i];
1011
1012 /* write the key to the EFER */
1013 for (j = 0; j < w83877f_keyiter[i]; j ++)
1014 outb (efer, w83877f_keys[i]);
1015
1016 /* then check HEFERE and HEFRAS bits */
1017 outb (efir, 0x0c);
1018 hefere = inb(efdr) & WINB_HEFERE;
1019
1020 outb (efir, 0x16);
1021 hefras = inb(efdr) & WINB_HEFRAS;
1022
1023 /*
1024 * HEFRAS HEFERE
1025 * 0 1 write 89h to 250h (power-on default)
1026 * 1 0 write 86h twice to 3f0h
1027 * 1 1 write 87h twice to 3f0h
1028 * 0 0 write 88h to 250h
1029 */
1030 if ((hefere | hefras) == w83877f_hefs[i])
1031 goto found;
1032 }
1033
1034 return (-1); /* failed */
1035
1036 found:
1037 /* check base port address - read from CR23 */
1038 outb(efir, 0x23);
1039 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1040 return (-1);
1041
1042 /* read CHIP ID from CR9/bits0-3 */
1043 outb(efir, 0x9);
1044
1045 switch (inb(efdr) & WINB_CHIPID) {
1046 case WINB_W83877F_ID:
1047 ppc->ppc_model = WINB_W83877F;
1048 break;
1049
1050 case WINB_W83877AF_ID:
1051 ppc->ppc_model = WINB_W83877AF;
1052 break;
1053
1054 default:
1055 ppc->ppc_model = WINB_UNKNOWN;
1056 }
1057
1058 if (bootverbose) {
1059 /* dump of registers */
1060 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]);
1061 for (i = 0; i <= 0xd; i ++) {
1062 outb(efir, i);
1063 printf("0x%x ", inb(efdr));
1064 }
1065 for (i = 0x10; i <= 0x17; i ++) {
1066 outb(efir, i);
1067 printf("0x%x ", inb(efdr));
1068 }
1069 outb(efir, 0x1e);
1070 printf("0x%x ", inb(efdr));
1071 for (i = 0x20; i <= 0x29; i ++) {
1072 outb(efir, i);
1073 printf("0x%x ", inb(efdr));
1074 }
1075 printf("\n");
1076 }
1077
1078 ppc->ppc_type = PPC_TYPE_GENERIC;
1079
1080 if (!chipset_mode) {
1081 /* autodetect mode */
1082
1083 /* select CR0 */
1084 outb(efir, 0x0);
1085 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1086
1087 /* select CR9 */
1088 outb(efir, 0x9);
1089 r |= (inb(efdr) & WINB_PRTMODS2);
1090
1091 switch (r) {
1092 case WINB_W83757:
1093 if (bootverbose)
1094 device_printf(ppc->ppc_dev,
1095 "W83757 compatible mode\n");
1096 return (-1); /* generic or SMC-like */
1097
1098 case WINB_EXTFDC:
1099 case WINB_EXTADP:
1100 case WINB_EXT2FDD:
1101 case WINB_JOYSTICK:
1102 if (bootverbose)
1103 device_printf(ppc->ppc_dev,
1104 "not in parallel port mode\n");
1105 return (-1);
1106
1107 case (WINB_PARALLEL | WINB_EPP_SPP):
1108 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1109 if (bootverbose)
1110 device_printf(ppc->ppc_dev, "EPP SPP\n");
1111 break;
1112
1113 case (WINB_PARALLEL | WINB_ECP):
1114 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1115 if (bootverbose)
1116 device_printf(ppc->ppc_dev, "ECP SPP\n");
1117 break;
1118
1119 case (WINB_PARALLEL | WINB_ECP_EPP):
1120 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1121 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1122
1123 if (bootverbose)
1124 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n");
1125 break;
1126 default:
1127 printf("%s: unknown case (0x%x)!\n", __func__, r);
1128 }
1129
1130 } else {
1131 /* mode forced */
1132
1133 /* select CR9 and set PRTMODS2 bit */
1134 outb(efir, 0x9);
1135 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1136
1137 /* select CR0 and reset PRTMODSx bits */
1138 outb(efir, 0x0);
1139 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1140
1141 if (chipset_mode & PPB_ECP) {
1142 if (chipset_mode & PPB_EPP) {
1143 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1144 if (bootverbose)
1145 device_printf(ppc->ppc_dev,
1146 "ECP+EPP\n");
1147
1148 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1149
1150 } else {
1151 outb(efdr, inb(efdr) | WINB_ECP);
1152 if (bootverbose)
1153 device_printf(ppc->ppc_dev, "ECP\n");
1154 }
1155 } else {
1156 /* select EPP_SPP otherwise */
1157 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1158 if (bootverbose)
1159 device_printf(ppc->ppc_dev, "EPP SPP\n");
1160 }
1161 ppc->ppc_avm = chipset_mode;
1162 }
1163
1164 /* exit configuration mode */
1165 outb(efer, 0xaa);
1166
1167 switch (ppc->ppc_type) {
1168 case PPC_TYPE_SMCLIKE:
1169 ppc_smclike_setmode(ppc, chipset_mode);
1170 break;
1171 default:
1172 ppc_generic_setmode(ppc, chipset_mode);
1173 break;
1174 }
1175
1176 return (chipset_mode);
1177 }
1178 #endif
1179
1180 /*
1181 * ppc_generic_detect
1182 */
1183 static int
ppc_generic_detect(struct ppc_data * ppc,int chipset_mode)1184 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1185 {
1186 /* default to generic */
1187 ppc->ppc_type = PPC_TYPE_GENERIC;
1188
1189 if (bootverbose)
1190 device_printf(ppc->ppc_dev, "SPP");
1191
1192 /* first, check for ECP */
1193 w_ecr(ppc, PPC_ECR_PS2);
1194 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1195 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1196 if (bootverbose)
1197 printf(" ECP ");
1198
1199 /* search for SMC style ECP+EPP mode */
1200 w_ecr(ppc, PPC_ECR_EPP);
1201 }
1202
1203 /* try to reset EPP timeout bit */
1204 if (ppc_check_epp_timeout(ppc)) {
1205 ppc->ppc_dtm |= PPB_EPP;
1206
1207 if (ppc->ppc_dtm & PPB_ECP) {
1208 /* SMC like chipset found */
1209 ppc->ppc_model = SMC_LIKE;
1210 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1211
1212 if (bootverbose)
1213 printf(" ECP+EPP");
1214 } else {
1215 if (bootverbose)
1216 printf(" EPP");
1217 }
1218 } else {
1219 /* restore to standard mode */
1220 w_ecr(ppc, PPC_ECR_STD);
1221 }
1222
1223 /* XXX try to detect NIBBLE and PS2 modes */
1224 ppc->ppc_dtm |= PPB_NIBBLE;
1225
1226 if (chipset_mode)
1227 ppc->ppc_avm = chipset_mode;
1228 else
1229 ppc->ppc_avm = ppc->ppc_dtm;
1230
1231 if (bootverbose)
1232 printf("\n");
1233
1234 switch (ppc->ppc_type) {
1235 case PPC_TYPE_SMCLIKE:
1236 ppc_smclike_setmode(ppc, chipset_mode);
1237 break;
1238 default:
1239 ppc_generic_setmode(ppc, chipset_mode);
1240 break;
1241 }
1242
1243 return (chipset_mode);
1244 }
1245
1246 /*
1247 * ppc_detect()
1248 *
1249 * mode is the mode suggested at boot
1250 */
1251 static int
ppc_detect(struct ppc_data * ppc,int chipset_mode)1252 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1253 #ifdef PPC_PROBE_CHIPSET
1254 int i, mode;
1255
1256 /* list of supported chipsets */
1257 int (*chipset_detect[])(struct ppc_data *, int) = {
1258 ppc_pc873xx_detect,
1259 ppc_smc37c66xgt_detect,
1260 ppc_w83877f_detect,
1261 ppc_smc37c935_detect,
1262 ppc_generic_detect,
1263 NULL
1264 };
1265 #endif
1266
1267 /* if can't find the port and mode not forced return error */
1268 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1269 return (EIO); /* failed, port not present */
1270
1271 /* assume centronics compatible mode is supported */
1272 ppc->ppc_avm = PPB_COMPATIBLE;
1273
1274 #ifdef PPC_PROBE_CHIPSET
1275 /* we have to differenciate available chipset modes,
1276 * chipset running modes and IEEE-1284 operating modes
1277 *
1278 * after detection, the port must support running in compatible mode
1279 */
1280 if (ppc->ppc_flags & 0x40) {
1281 if (bootverbose)
1282 printf("ppc: chipset forced to generic\n");
1283 #endif
1284
1285 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1286
1287 #ifdef PPC_PROBE_CHIPSET
1288 } else {
1289 for (i=0; chipset_detect[i] != NULL; i++) {
1290 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1291 ppc->ppc_mode = mode;
1292 break;
1293 }
1294 }
1295 }
1296 #endif
1297
1298 /* configure/detect ECP FIFO */
1299 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1300 ppc_detect_fifo(ppc);
1301
1302 return (0);
1303 }
1304
1305 /*
1306 * ppc_exec_microseq()
1307 *
1308 * Execute a microsequence.
1309 * Microsequence mechanism is supposed to handle fast I/O operations.
1310 */
1311 int
ppc_exec_microseq(device_t dev,struct ppb_microseq ** p_msq)1312 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1313 {
1314 struct ppc_data *ppc = DEVTOSOFTC(dev);
1315 struct ppb_microseq *mi;
1316 char cc, *p;
1317 int i, iter, len;
1318 int error;
1319
1320 int reg;
1321 char mask;
1322 int accum = 0;
1323 char *ptr = NULL;
1324
1325 struct ppb_microseq *stack = NULL;
1326
1327 /* microsequence registers are equivalent to PC-like port registers */
1328
1329 #define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg))
1330 #define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte))
1331
1332 #define INCR_PC (mi ++) /* increment program counter */
1333
1334 PPC_ASSERT_LOCKED(ppc);
1335 mi = *p_msq;
1336 for (;;) {
1337 switch (mi->opcode) {
1338 case MS_OP_RSET:
1339 cc = r_reg(mi->arg[0].i, ppc);
1340 cc &= (char)mi->arg[2].i; /* clear mask */
1341 cc |= (char)mi->arg[1].i; /* assert mask */
1342 w_reg(mi->arg[0].i, ppc, cc);
1343 INCR_PC;
1344 break;
1345
1346 case MS_OP_RASSERT_P:
1347 reg = mi->arg[1].i;
1348 ptr = ppc->ppc_ptr;
1349
1350 if ((len = mi->arg[0].i) == MS_ACCUM) {
1351 accum = ppc->ppc_accum;
1352 for (; accum; accum--)
1353 w_reg(reg, ppc, *ptr++);
1354 ppc->ppc_accum = accum;
1355 } else
1356 for (i=0; i<len; i++)
1357 w_reg(reg, ppc, *ptr++);
1358 ppc->ppc_ptr = ptr;
1359
1360 INCR_PC;
1361 break;
1362
1363 case MS_OP_RFETCH_P:
1364 reg = mi->arg[1].i;
1365 mask = (char)mi->arg[2].i;
1366 ptr = ppc->ppc_ptr;
1367
1368 if ((len = mi->arg[0].i) == MS_ACCUM) {
1369 accum = ppc->ppc_accum;
1370 for (; accum; accum--)
1371 *ptr++ = r_reg(reg, ppc) & mask;
1372 ppc->ppc_accum = accum;
1373 } else
1374 for (i=0; i<len; i++)
1375 *ptr++ = r_reg(reg, ppc) & mask;
1376 ppc->ppc_ptr = ptr;
1377
1378 INCR_PC;
1379 break;
1380
1381 case MS_OP_RFETCH:
1382 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1383 (char)mi->arg[1].i;
1384 INCR_PC;
1385 break;
1386
1387 case MS_OP_RASSERT:
1388 case MS_OP_DELAY:
1389
1390 /* let's suppose the next instr. is the same */
1391 prefetch:
1392 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1393 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1394
1395 if (mi->opcode == MS_OP_DELAY) {
1396 DELAY(mi->arg[0].i);
1397 INCR_PC;
1398 goto prefetch;
1399 }
1400 break;
1401
1402 case MS_OP_ADELAY:
1403 if (mi->arg[0].i) {
1404 PPC_UNLOCK(ppc);
1405 pause("ppbdelay", mi->arg[0].i * (hz/1000));
1406 PPC_LOCK(ppc);
1407 }
1408 INCR_PC;
1409 break;
1410
1411 case MS_OP_TRIG:
1412 reg = mi->arg[0].i;
1413 iter = mi->arg[1].i;
1414 p = (char *)mi->arg[2].p;
1415
1416 /* XXX delay limited to 255 us */
1417 for (i=0; i<iter; i++) {
1418 w_reg(reg, ppc, *p++);
1419 DELAY((unsigned char)*p++);
1420 }
1421 INCR_PC;
1422 break;
1423
1424 case MS_OP_SET:
1425 ppc->ppc_accum = mi->arg[0].i;
1426 INCR_PC;
1427 break;
1428
1429 case MS_OP_DBRA:
1430 if (--ppc->ppc_accum > 0)
1431 mi += mi->arg[0].i;
1432 INCR_PC;
1433 break;
1434
1435 case MS_OP_BRSET:
1436 cc = r_str(ppc);
1437 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1438 mi += mi->arg[1].i;
1439 INCR_PC;
1440 break;
1441
1442 case MS_OP_BRCLEAR:
1443 cc = r_str(ppc);
1444 if ((cc & (char)mi->arg[0].i) == 0)
1445 mi += mi->arg[1].i;
1446 INCR_PC;
1447 break;
1448
1449 case MS_OP_BRSTAT:
1450 cc = r_str(ppc);
1451 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1452 (char)mi->arg[0].i)
1453 mi += mi->arg[2].i;
1454 INCR_PC;
1455 break;
1456
1457 case MS_OP_C_CALL:
1458 /*
1459 * If the C call returns !0 then end the microseq.
1460 * The current state of ptr is passed to the C function
1461 */
1462 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1463 return (error);
1464
1465 INCR_PC;
1466 break;
1467
1468 case MS_OP_PTR:
1469 ppc->ppc_ptr = (char *)mi->arg[0].p;
1470 INCR_PC;
1471 break;
1472
1473 case MS_OP_CALL:
1474 if (stack)
1475 panic("%s: too much calls", __func__);
1476
1477 if (mi->arg[0].p) {
1478 /* store the state of the actual
1479 * microsequence
1480 */
1481 stack = mi;
1482
1483 /* jump to the new microsequence */
1484 mi = (struct ppb_microseq *)mi->arg[0].p;
1485 } else
1486 INCR_PC;
1487
1488 break;
1489
1490 case MS_OP_SUBRET:
1491 /* retrieve microseq and pc state before the call */
1492 mi = stack;
1493
1494 /* reset the stack */
1495 stack = NULL;
1496
1497 /* XXX return code */
1498
1499 INCR_PC;
1500 break;
1501
1502 case MS_OP_PUT:
1503 case MS_OP_GET:
1504 case MS_OP_RET:
1505 /* can't return to ppb level during the execution
1506 * of a submicrosequence */
1507 if (stack)
1508 panic("%s: can't return to ppb level",
1509 __func__);
1510
1511 /* update pc for ppb level of execution */
1512 *p_msq = mi;
1513
1514 /* return to ppb level of execution */
1515 return (0);
1516
1517 default:
1518 panic("%s: unknown microsequence opcode 0x%x",
1519 __func__, mi->opcode);
1520 }
1521 }
1522
1523 /* unreached */
1524 }
1525
1526 static void
ppcintr(void * arg)1527 ppcintr(void *arg)
1528 {
1529 struct ppc_data *ppc = arg;
1530 u_char ctr, ecr, str;
1531
1532 /*
1533 * If we have any child interrupt handlers registered, let
1534 * them handle this interrupt.
1535 *
1536 * XXX: If DMA is in progress should we just complete that w/o
1537 * doing this?
1538 */
1539 PPC_LOCK(ppc);
1540 if (ppc->ppc_intr_hook != NULL &&
1541 ppc->ppc_intr_hook(ppc->ppc_intr_arg) == 0) {
1542 PPC_UNLOCK(ppc);
1543 return;
1544 }
1545
1546 str = r_str(ppc);
1547 ctr = r_ctr(ppc);
1548 ecr = r_ecr(ppc);
1549
1550 #if defined(PPC_DEBUG) && PPC_DEBUG > 1
1551 printf("![%x/%x/%x]", ctr, ecr, str);
1552 #endif
1553
1554 /* don't use ecp mode with IRQENABLE set */
1555 if (ctr & IRQENABLE) {
1556 PPC_UNLOCK(ppc);
1557 return;
1558 }
1559
1560 /* interrupts are generated by nFault signal
1561 * only in ECP mode */
1562 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1563 /* check if ppc driver has programmed the
1564 * nFault interrupt */
1565 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1566 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1567 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1568 } else {
1569 /* shall be handled by underlying layers XXX */
1570 PPC_UNLOCK(ppc);
1571 return;
1572 }
1573 }
1574
1575 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1576 /* disable interrupts (should be done by hardware though) */
1577 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1578 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1579 ecr = r_ecr(ppc);
1580
1581 /* check if DMA completed */
1582 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1583 #ifdef PPC_DEBUG
1584 printf("a");
1585 #endif
1586 /* stop DMA */
1587 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1588 ecr = r_ecr(ppc);
1589
1590 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1591 #ifdef PPC_DEBUG
1592 printf("d");
1593 #endif
1594 ppc->ppc_dmadone(ppc);
1595 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1596
1597 /* wakeup the waiting process */
1598 wakeup(ppc);
1599 }
1600 }
1601 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1602 /* classic interrupt I/O */
1603 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1604 }
1605 PPC_UNLOCK(ppc);
1606
1607 return;
1608 }
1609
1610 int
ppc_read(device_t dev,char * buf,int len,int mode)1611 ppc_read(device_t dev, char *buf, int len, int mode)
1612 {
1613 return (EINVAL);
1614 }
1615
1616 int
ppc_write(device_t dev,char * buf,int len,int how)1617 ppc_write(device_t dev, char *buf, int len, int how)
1618 {
1619 return (EINVAL);
1620 }
1621
1622 int
ppc_reset_epp(device_t dev)1623 ppc_reset_epp(device_t dev)
1624 {
1625 struct ppc_data *ppc = DEVTOSOFTC(dev);
1626
1627 PPC_ASSERT_LOCKED(ppc);
1628 ppc_reset_epp_timeout(ppc);
1629
1630 return 0;
1631 }
1632
1633 int
ppc_setmode(device_t dev,int mode)1634 ppc_setmode(device_t dev, int mode)
1635 {
1636 struct ppc_data *ppc = DEVTOSOFTC(dev);
1637
1638 PPC_ASSERT_LOCKED(ppc);
1639 switch (ppc->ppc_type) {
1640 case PPC_TYPE_SMCLIKE:
1641 return (ppc_smclike_setmode(ppc, mode));
1642 break;
1643
1644 case PPC_TYPE_GENERIC:
1645 default:
1646 return (ppc_generic_setmode(ppc, mode));
1647 break;
1648 }
1649
1650 /* not reached */
1651 return (ENXIO);
1652 }
1653
1654 int
ppc_probe(device_t dev,int rid)1655 ppc_probe(device_t dev, int rid)
1656 {
1657 struct ppc_data *ppc;
1658 #ifdef __i386__
1659 static short next_bios_ppc = 0;
1660 int error;
1661 rman_res_t port;
1662 #endif
1663
1664 /*
1665 * Allocate the ppc_data structure.
1666 */
1667 ppc = DEVTOSOFTC(dev);
1668 bzero(ppc, sizeof(struct ppc_data));
1669
1670 ppc->rid_ioport = rid;
1671
1672 #ifdef __i386__
1673 /* retrieve ISA parameters */
1674 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL);
1675
1676 /*
1677 * If port not specified, use bios list.
1678 */
1679 if (error) {
1680 if ((next_bios_ppc < BIOS_MAX_PPC) &&
1681 (*(BIOS_PORTS + next_bios_ppc) != 0)) {
1682 port = *(BIOS_PORTS + next_bios_ppc++);
1683 if (bootverbose)
1684 device_printf(dev,
1685 "parallel port found at 0x%jx\n", port);
1686 } else {
1687 device_printf(dev, "parallel port not found.\n");
1688 return (ENXIO);
1689 }
1690 bus_set_resource(dev, SYS_RES_IOPORT, rid, port,
1691 IO_LPTSIZE_EXTENDED);
1692 }
1693 #endif
1694
1695 /* IO port is mandatory */
1696
1697 /* Try "extended" IO port range...*/
1698 ppc->res_ioport = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
1699 &ppc->rid_ioport,
1700 IO_LPTSIZE_EXTENDED,
1701 RF_ACTIVE);
1702
1703 if (ppc->res_ioport != 0) {
1704 if (bootverbose)
1705 device_printf(dev, "using extended I/O port range\n");
1706 } else {
1707 /* Failed? If so, then try the "normal" IO port range... */
1708 ppc->res_ioport = bus_alloc_resource_anywhere(dev,
1709 SYS_RES_IOPORT,
1710 &ppc->rid_ioport,
1711 IO_LPTSIZE_NORMAL,
1712 RF_ACTIVE);
1713 if (ppc->res_ioport != 0) {
1714 if (bootverbose)
1715 device_printf(dev, "using normal I/O port range\n");
1716 } else {
1717 if (bootverbose)
1718 device_printf(dev, "cannot reserve I/O port range\n");
1719 goto error;
1720 }
1721 }
1722
1723 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1724
1725 ppc->ppc_flags = device_get_flags(dev);
1726
1727 if (!(ppc->ppc_flags & 0x20)) {
1728 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1729 &ppc->rid_irq,
1730 RF_SHAREABLE);
1731 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1732 &ppc->rid_drq,
1733 RF_ACTIVE);
1734 }
1735
1736 if (ppc->res_irq)
1737 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1738 if (ppc->res_drq)
1739 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1740
1741 ppc->ppc_dev = dev;
1742 ppc->ppc_model = GENERIC;
1743
1744 ppc->ppc_mode = PPB_COMPATIBLE;
1745 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1746
1747 ppc->ppc_type = PPC_TYPE_GENERIC;
1748
1749 /*
1750 * Try to detect the chipset and its mode.
1751 */
1752 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1753 goto error;
1754
1755 return (0);
1756
1757 error:
1758 if (ppc->res_irq != 0) {
1759 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1760 ppc->res_irq);
1761 }
1762 if (ppc->res_ioport != 0) {
1763 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1764 ppc->res_ioport);
1765 }
1766 if (ppc->res_drq != 0) {
1767 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1768 ppc->res_drq);
1769 }
1770 return (ENXIO);
1771 }
1772
1773 int
ppc_attach(device_t dev)1774 ppc_attach(device_t dev)
1775 {
1776 struct ppc_data *ppc = DEVTOSOFTC(dev);
1777 int error;
1778
1779 mtx_init(&ppc->ppc_lock, device_get_nameunit(dev), "ppc", MTX_DEF);
1780
1781 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1782 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1783 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1784 ppc_epp_protocol[ppc->ppc_epp] : "");
1785
1786 if (ppc->ppc_fifo)
1787 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1788 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1789
1790 if (ppc->res_irq) {
1791 /* default to the tty mask for registration */ /* XXX */
1792 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY |
1793 INTR_MPSAFE, NULL, ppcintr, ppc, &ppc->intr_cookie);
1794 if (error) {
1795 device_printf(dev,
1796 "failed to register interrupt handler: %d\n",
1797 error);
1798 mtx_destroy(&ppc->ppc_lock);
1799 return (error);
1800 }
1801 }
1802
1803 /* add ppbus as a child of this isa to parallel bridge */
1804 ppc->ppbus = device_add_child(dev, "ppbus", DEVICE_UNIT_ANY);
1805
1806 /*
1807 * Probe the ppbus and attach devices found.
1808 */
1809 device_probe_and_attach(ppc->ppbus);
1810
1811 return (0);
1812 }
1813
1814 int
ppc_detach(device_t dev)1815 ppc_detach(device_t dev)
1816 {
1817 struct ppc_data *ppc = DEVTOSOFTC(dev);
1818
1819 if (ppc->res_irq == 0) {
1820 return (ENXIO);
1821 }
1822
1823 /* detach & delete all children */
1824 device_delete_children(dev);
1825
1826 if (ppc->res_irq != 0) {
1827 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie);
1828 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1829 ppc->res_irq);
1830 }
1831 if (ppc->res_ioport != 0) {
1832 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1833 ppc->res_ioport);
1834 }
1835 if (ppc->res_drq != 0) {
1836 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1837 ppc->res_drq);
1838 }
1839
1840 mtx_destroy(&ppc->ppc_lock);
1841
1842 return (0);
1843 }
1844
1845 u_char
ppc_io(device_t ppcdev,int iop,u_char * addr,int cnt,u_char byte)1846 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
1847 {
1848 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
1849
1850 PPC_ASSERT_LOCKED(ppc);
1851 switch (iop) {
1852 case PPB_OUTSB_EPP:
1853 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1854 break;
1855 case PPB_OUTSW_EPP:
1856 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1857 break;
1858 case PPB_OUTSL_EPP:
1859 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1860 break;
1861 case PPB_INSB_EPP:
1862 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1863 break;
1864 case PPB_INSW_EPP:
1865 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1866 break;
1867 case PPB_INSL_EPP:
1868 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1869 break;
1870 case PPB_RDTR:
1871 return (r_dtr(ppc));
1872 case PPB_RSTR:
1873 return (r_str(ppc));
1874 case PPB_RCTR:
1875 return (r_ctr(ppc));
1876 case PPB_REPP_A:
1877 return (r_epp_A(ppc));
1878 case PPB_REPP_D:
1879 return (r_epp_D(ppc));
1880 case PPB_RECR:
1881 return (r_ecr(ppc));
1882 case PPB_RFIFO:
1883 return (r_fifo(ppc));
1884 case PPB_WDTR:
1885 w_dtr(ppc, byte);
1886 break;
1887 case PPB_WSTR:
1888 w_str(ppc, byte);
1889 break;
1890 case PPB_WCTR:
1891 w_ctr(ppc, byte);
1892 break;
1893 case PPB_WEPP_A:
1894 w_epp_A(ppc, byte);
1895 break;
1896 case PPB_WEPP_D:
1897 w_epp_D(ppc, byte);
1898 break;
1899 case PPB_WECR:
1900 w_ecr(ppc, byte);
1901 break;
1902 case PPB_WFIFO:
1903 w_fifo(ppc, byte);
1904 break;
1905 default:
1906 panic("%s: unknown I/O operation", __func__);
1907 break;
1908 }
1909
1910 return (0); /* not significative */
1911 }
1912
1913 int
ppc_read_ivar(device_t bus,device_t dev,int index,uintptr_t * val)1914 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
1915 {
1916 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1917
1918 switch (index) {
1919 case PPC_IVAR_EPP_PROTO:
1920 PPC_ASSERT_LOCKED(ppc);
1921 *val = (u_long)ppc->ppc_epp;
1922 break;
1923 case PPC_IVAR_LOCK:
1924 *val = (uintptr_t)&ppc->ppc_lock;
1925 break;
1926 default:
1927 return (ENOENT);
1928 }
1929
1930 return (0);
1931 }
1932
1933 int
ppc_write_ivar(device_t bus,device_t dev,int index,uintptr_t val)1934 ppc_write_ivar(device_t bus, device_t dev, int index, uintptr_t val)
1935 {
1936 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1937
1938 switch (index) {
1939 case PPC_IVAR_INTR_HANDLER:
1940 PPC_ASSERT_LOCKED(ppc);
1941 if (dev != ppc->ppbus)
1942 return (EINVAL);
1943 if (val == 0) {
1944 ppc->ppc_intr_hook = NULL;
1945 break;
1946 }
1947 if (ppc->ppc_intr_hook != NULL)
1948 return (EBUSY);
1949 ppc->ppc_intr_hook = (void *)val;
1950 ppc->ppc_intr_arg = device_get_softc(dev);
1951 break;
1952 default:
1953 return (ENOENT);
1954 }
1955
1956 return (0);
1957 }
1958
1959 /*
1960 * We allow child devices to allocate an IRQ resource at rid 0 for their
1961 * interrupt handlers.
1962 */
1963 struct resource *
ppc_alloc_resource(device_t bus,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)1964 ppc_alloc_resource(device_t bus, device_t child, int type, int *rid,
1965 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1966 {
1967 struct ppc_data *ppc = DEVTOSOFTC(bus);
1968
1969 switch (type) {
1970 case SYS_RES_IRQ:
1971 if (*rid == 0)
1972 return (ppc->res_irq);
1973 break;
1974 }
1975 return (NULL);
1976 }
1977
1978 int
ppc_release_resource(device_t bus,device_t child,struct resource * r)1979 ppc_release_resource(device_t bus, device_t child, struct resource *r)
1980 {
1981 struct ppc_data *ppc = DEVTOSOFTC(bus);
1982
1983 if (r == ppc->res_irq)
1984 return (0);
1985 return (EINVAL);
1986 }
1987
1988 MODULE_DEPEND(ppc, ppbus, 1, 1, 1);
1989