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Searched defs:PPLL_FREQ_CTRL0__reg_tmg_fcw0_frac_MASK (Results 1 – 2 of 2) sorted by last modified time

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_sh_mask.h361 #define PPLL_FREQ_CTRL0__reg_tmg_fcw0_frac_MASK macro
H A Ddce_11_2_sh_mask.h18362 #define PPLL_FREQ_CTRL0__reg_tmg_fcw0_frac_MASK 0xffff macro