1 /* $OpenBSD: omap3_prcmreg.h,v 1.3 2013/10/28 11:11:50 rapha Exp $ */ 2 /* 3 * Copyright (c) 2007, 2009, 2012 Dale Rahn <drahn@dalerahn.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 /* XXX - verify these definitions and correctly merge them with omap4 */ 19 #define CM_FCLKEN_IVA2 0x0000 20 #define CM_CLKEN_PLL_IVA2 0x0004 21 #define CM_IDLEST_IVA2 0x0020 22 #define CM_IDLEST_PLL_IVA2 0x0024 23 #define CM_AUTOIDLE_PLL_IVA2 0x0034 24 #define CM_CLKSEL1_PLL_IVA2 0x0040 25 #define CM_CLKSEL2_PLL_IVA2 0x0044 26 #define CM_CLKSTCTRL_IVA2 0x0048 27 #define CM_CLKSTST_IVA2 0x004c 28 #define CM_CLKSEL_MPU 0x0940 29 #define CM_CLKSTCTRL_MPU 0x0948 30 #define RM_RSTST_MPU 0x0958 31 #define PM_WKDEP_MPU 0x09C8 32 #define PM_EVGENCTRL_MPU 0x09D4 33 #define PM_EVEGENONTIM_MPU 0x09D8 34 #define PM_EVEGENOFFTIM_MPU 0x09DC 35 #define PM_PWSTCTRL_MPU 0x09E0 36 #define PM_PWSTST_MPU 0x09E4 37 #define CM_FCLKEN1_CORE 0x0a00 38 #define CM_FCLKEN1_CORE_MSK 0x41fffe00 39 #define CM_FCLKEN2_CORE 0x0a04 40 #define CM_FCLKEN2_CORE_MSK 0x00000000 41 #define CM_FCLKEN3_CORE 0x0a08 42 #define CM_FCLKEN3_CORE_MSK 0x00000007 43 #define CM_ICLKEN1_CORE 0x0a10 44 #define CM_ICLKEN1_CORE_MSK 0x7ffffed2 45 #define CM_ICLKEN2_CORE 0x0a14 46 #define CM_ICLKEN2_CORE_MSK 0x0000001f 47 #define CM_ICLKEN3_CORE 0x0a18 48 #define CM_ICLKEN3_CORE_MSK 0x00000004 49 #define CM_ICLKEN4_CORE 0x0a1C 50 #define CM_IDLEST1_CORE 0x0a20 51 #define CM_IDLEST2_CORE 0x0a24 52 #define CM_IDLEST4_CORE 0x0a2C 53 #define CM_AUTOIDLE1_CORE 0x0a30 54 #define CM_AUTOIDLE2_CORE 0x0a34 55 #define CM_AUTOIDLE3_CORE 0x0a38 56 #define CM_AUTOIDLE4_CORE 0x0a3C 57 #define CM_CLKSEL1_CORE 0x0a40 58 #define CM_CLKSEL2_CORE 0x0a44 59 #define CM_CLKSTCTRL_CORE 0x0a48 60 #define PM_WKEN1_CORE 0x0aA0 61 #define PM_WKEN2_CORE 0x0aA4 62 #define PM_WKST1_CORE 0x0aB0 63 #define PM_WKST2_CORE 0x0aB4 64 #define PM_WKDEP_CORE 0x0aC8 65 #define PM_PWSTCTRL_CORE 0x0aE0 66 #define PM_PWSTST_CORE 0x0aE4 67 #define CM_FCLKEN_GFX 0x0b00 68 #define CM_ICLKEN_GFX 0x0b10 69 #define CM_IDLEST_GFX 0x0b20 70 #define CM_CLKSEL_GFX 0x0b40 71 #define CM_CLKSTCTRL_GFX 0x0b48 72 #define RM_RSTCTRL_GFX 0x0b50 73 #define RM_RSTST_GFX 0x0b58 74 #define PM_WKDEP_GFX 0x0bC8 75 #define PM_PWSTCTRL_GFX 0x0bE0 76 #define PM_PWSTST_GFX 0x0bE4 77 #define CM_FCLKEN_WKUP 0x0c00 78 #define CM_FCLKEN_WKUP_MSK 0x00000029 79 #define CM_ICLKEN_WKUP 0x0c10 80 #define CM_ICLKEN_WKUP_MSK 0x0000002d 81 #define CM_IDLEST_WKUP 0x0c20 82 #define CM_AUTOIDLE_WKUP 0x0c30 83 #define CM_CLKSEL_WKUP 0x0c40 84 #define RM_RSTCTRL_WKUP 0x0c50 85 #define RM_RSTTIME_WKUP 0x0c54 86 #define RM_RSTST_WKUP 0x0c58 87 #define PM_WKEN_WKUP 0x0cA0 88 #define PM_WKST_WKUP 0x0cB0 89 #define CM_CLKEN_PLL 0x0d00 90 #define CM_CLKEN2_PLL 0x0d04 91 #define CM_IDLEST_CKGEN 0x0d20 92 #define CM_AUTOIDLE_PLL 0x0d30 93 #define CM_AUTOIDLE2_PLL 0x0d34 94 #define CM_CLKSEL1_PLL 0x0d40 95 #define CM_CLKSEL2_PLL 0x0d44 96 #define CM_CLKSEL3_PLL 0x0d48 97 #define CM_CLKSEL4_PLL 0x0d4C 98 #define CM_CLKSEL5_PLL 0x0d50 99 #define CM_FCLKEN_PER 0x1000 100 #define CM_FCLKEN_PER_MSK 0x0003ffff 101 #define CM_ICLKEN_PER 0x1010 102 #define CM_ICLKEN_PER_MSK 0x0003ffff 103 #define CM_IDLEST_PER 0x1020 104 #define CM_AUTOIDLE_PER 0x1030 105 #define CM_CLKSEL_PER 0x1040 106 #define CM_SLEEPDEP_PER 0x1044 107 #define CM_CLKSTCTRL_PER 0x1048 108 #define CM_CLKSTST_PER 0x104C 109 #define CM_CLKSEL1_EMU 0x1140 110 #define CM_CLKSTCTRL_EMU 0x1148 111 #define CM_CLKSTST_EMU 0x114C 112 #define CM_CLKSEL2_EMU 0x1150 113 #define CM_CLKSEL3_EMU 0x1154 114 #define CM_POLCTRL 0x129C 115 #define CM_IDLEST_NEON 0x1320 116 #define CM_CLKSTCTRL_NEON 0x1348 117 #define CM_FCLKEN_USBHOST 0x1400 118 #define CM_FCLKEN_USBHOST_MSK 0x00000003 119 #define CM_ICLKEN_USBHOST 0x1410 120 #define CM_ICLKEN_USBHOST_MSK 0x00000001 121 #define CM_IDLEST_USBHOST 0x1420 122 #define CM_AUTOIDLE_USBHOST 0x1430 123 #define CM_SLEEPDEP_USBHOST 0x1444 124 #define CM_CLKSTCTRL_USBHOST 0x1448 125 #define CM_CLKSTST_USBHOST 0x144C 126 127 128 #define PRCM_REG_CORE_CLK1 0 129 #define PRCM_REG_CORE_CLK1_FADDR CM_FCLKEN1_CORE 130 #define PRCM_REG_CORE_CLK1_IADDR CM_ICLKEN1_CORE 131 #define PRCM_REG_CORE_CLK1_FMASK CM_FCLKEN1_CORE_MSK 132 #define PRCM_REG_CORE_CLK1_IMASK CM_ICLKEN1_CORE_MSK 133 #define PRCM_REG_CORE_CLK1_BASE (PRCM_REG_CORE_CLK1*32) 134 #define PRCM_CLK_EN_MMC3 (PRCM_REG_CORE_CLK1_BASE + 30) 135 #define PRCM_CLK_EN_ICR (PRCM_REG_CORE_CLK1_BASE + 29) 136 #define PRCM_CLK_EN_AES2 (PRCM_REG_CORE_CLK1_BASE + 28) 137 #define PRCM_CLK_EN_SHA12 (PRCM_REG_CORE_CLK1_BASE + 27) 138 #define PRCM_CLK_EN_DES2 (PRCM_REG_CORE_CLK1_BASE + 26) 139 #define PRCM_CLK_EN_MMC2 (PRCM_REG_CORE_CLK1_BASE + 25) 140 #define PRCM_CLK_EN_MMC1 (PRCM_REG_CORE_CLK1_BASE + 24) 141 #define PRCM_CLK_EN_MSPRO (PRCM_REG_CORE_CLK1_BASE + 23) 142 #define PRCM_CLK_EN_HDQ (PRCM_REG_CORE_CLK1_BASE + 22) 143 #define PRCM_CLK_EN_MCSPI4 (PRCM_REG_CORE_CLK1_BASE + 21) 144 #define PRCM_CLK_EN_MCSPI3 (PRCM_REG_CORE_CLK1_BASE + 20) 145 #define PRCM_CLK_EN_MCSPI2 (PRCM_REG_CORE_CLK1_BASE + 19) 146 #define PRCM_CLK_EN_MCSPI1 (PRCM_REG_CORE_CLK1_BASE + 18) 147 #define PRCM_CLK_EN_I2C3 (PRCM_REG_CORE_CLK1_BASE + 17) 148 #define PRCM_CLK_EN_I2C2 (PRCM_REG_CORE_CLK1_BASE + 16) 149 #define PRCM_CLK_EN_I2C1 (PRCM_REG_CORE_CLK1_BASE + 15) 150 #define PRCM_CLK_EN_UART2 (PRCM_REG_CORE_CLK1_BASE + 14) 151 #define PRCM_CLK_EN_UART1 (PRCM_REG_CORE_CLK1_BASE + 13) 152 #define PRCM_CLK_EN_GPT11 (PRCM_REG_CORE_CLK1_BASE + 12) 153 #define PRCM_CLK_EN_GPT10 (PRCM_REG_CORE_CLK1_BASE + 11) 154 #define PRCM_CLK_EN_MCBSP5 (PRCM_REG_CORE_CLK1_BASE + 10) 155 #define PRCM_CLK_EN_MCBSP1 (PRCM_REG_CORE_CLK1_BASE + 9) 156 #define PRCM_CLK_EN_MAILBOXES (PRCM_REG_CORE_CLK1_BASE + 7) 157 #define PRCM_CLK_EN_OMAPCTRL (PRCM_REG_CORE_CLK1_BASE + 6) 158 #define PRCM_CLK_EN_HSOTGUSB (PRCM_REG_CORE_CLK1_BASE + 4) 159 #define PRCM_CLK_EN_SDRC (PRCM_REG_CORE_CLK1_BASE + 1) 160 161 #define PRCM_REG_CORE_CLK2 1 162 #define PRCM_REG_CORE_CLK2_FADDR CM_FCLKEN2_CORE 163 #define PRCM_REG_CORE_CLK2_IADDR CM_ICLKEN2_CORE 164 #define PRCM_REG_CORE_CLK2_FMASK CM_FCLKEN2_CORE_MSK 165 #define PRCM_REG_CORE_CLK2_IMASK CM_ICLKEN2_CORE_MSK 166 #define PRCM_REG_CORE_CLK2_BASE (PRCM_REG_CORE_CLK2*32) 167 168 #define PRCM_REG_CORE_CLK3 2 169 #define PRCM_REG_CORE_CLK3_FADDR CM_FCLKEN3_CORE 170 #define PRCM_REG_CORE_CLK3_IADDR CM_ICLKEN3_CORE 171 #define PRCM_REG_CORE_CLK3_FMASK CM_FCLKEN3_CORE_MSK 172 #define PRCM_REG_CORE_CLK3_IMASK CM_ICLKEN3_CORE_MSK 173 #define PRCM_REG_CORE_CLK3_BASE (PRCM_REG_CORE_CLK3*32) 174 #define PRCM_CORE_EN_USBTLL (PRCM_REG_CORE_CLK3_BASE + 2) 175 #define PRCM_CORE_EN_TS (PRCM_REG_CORE_CLK3_BASE + 1) 176 #define PRCM_CORE_EN_CPEFUSE (PRCM_REG_CORE_CLK3_BASE + 0) 177 178 #define PRCM_REG_WKUP 3 179 #define PRCM_REG_WKUP_FADDR CM_FCLKEN_WKUP 180 #define PRCM_REG_WKUP_IADDR CM_ICLKEN_WKUP 181 #define PRCM_REG_WKUP_FMASK CM_FCLKEN_WKUP_MSK 182 #define PRCM_REG_WKUP_IMASK CM_ICLKEN_WKUP_MSK 183 #define PRCM_REG_WKUP_BASE (PRCM_REG_WKUP*32) 184 #define PRCM_CLK_EN_MPU_WDT (PRCM_REG_WKUP_BASE + 5) 185 #define PRCM_CLK_EN_GPIO1 (PRCM_REG_WKUP_BASE + 3) 186 #define PRCM_CLK_EN_32KSYNC (PRCM_REG_WKUP_BASE + 2) 187 #define PRCM_CLK_EN_GPT1 (PRCM_REG_WKUP_BASE + 0) 188 189 #define PRCM_REG_PER 4 190 #define PRCM_REG_PER_FADDR CM_FCLKEN_PER 191 #define PRCM_REG_PER_IADDR CM_ICLKEN_PER 192 #define PRCM_REG_PER_FMASK CM_FCLKEN_PER_MSK 193 #define PRCM_REG_PER_IMASK CM_ICLKEN_PER_MSK 194 #define PRCM_REG_PER_BASE (PRCM_REG_PER*32) 195 #define PRCM_CLK_EN_GPIO6 (PRCM_REG_PER_BASE + 17) 196 #define PRCM_CLK_EN_GPIO5 (PRCM_REG_PER_BASE + 16) 197 #define PRCM_CLK_EN_GPIO4 (PRCM_REG_PER_BASE + 15) 198 #define PRCM_CLK_EN_GPIO3 (PRCM_REG_PER_BASE + 14) 199 #define PRCM_CLK_EN_GPIO2 (PRCM_REG_PER_BASE + 13) 200 #define PRCM_CLK_EN_WDT3 (PRCM_REG_PER_BASE + 12) 201 #define PRCM_CLK_EN_UART3 (PRCM_REG_PER_BASE + 11) 202 #define PRCM_CLK_EN_GPT9 (PRCM_REG_PER_BASE + 10) 203 #define PRCM_CLK_EN_GPT8 (PRCM_REG_PER_BASE + 9) 204 #define PRCM_CLK_EN_GPT7 (PRCM_REG_PER_BASE + 8) 205 #define PRCM_CLK_EN_GPT6 (PRCM_REG_PER_BASE + 7) 206 #define PRCM_CLK_EN_GPT5 (PRCM_REG_PER_BASE + 6) 207 #define PRCM_CLK_EN_GPT4 (PRCM_REG_PER_BASE + 5) 208 #define PRCM_CLK_EN_GPT3 (PRCM_REG_PER_BASE + 4) 209 #define PRCM_CLK_EN_GPT2 (PRCM_REG_PER_BASE + 3) 210 #define PRCM_CLK_EN_MCBSP4 (PRCM_REG_PER_BASE + 2) 211 #define PRCM_CLK_EN_MCBSP3 (PRCM_REG_PER_BASE + 1) 212 #define PRCM_CLK_EN_MCBSP2 (PRCM_REG_PER_BASE + 0) 213 214 #define PRCM_REG_USBHOST 5 215 #define PRCM_REG_USBHOST_FADDR CM_FCLKEN_USBHOST 216 #define PRCM_REG_USBHOST_IADDR CM_ICLKEN_USBHOST 217 #define PRCM_REG_USBHOST_FMASK CM_FCLKEN_USBHOST_MSK 218 #define PRCM_REG_USBHOST_IMASK CM_ICLKEN_USBHOST_MSK 219 #define PRCM_REG_USBHOST_BASE (PRCM_REG_USBHOST*32) 220 #define PRCM_CLK_EN_USBHOST2 (PRCM_REG_USBHOST_BASE + 1) 221 #define PRCM_CLK_EN_USBHOST1 (PRCM_REG_USBHOST_BASE + 0) 222 #define PRCM_CLK_EN_USB (PRCM_REG_USBHOST_BASE + 0) 223