1 /* Copyright (c) 2002, Marek Michalkiewicz 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: io76c711.h 2456 2014-11-19 09:57:29Z saaadhu $ */ 32 33 /* avr/io76c711.h - definitions for AT76C711 */ 34 35 #ifndef _AVR_IO76C711_H_ 36 #define _AVR_IO76C711_H_ 1 37 38 /* This file should only be included from <avr/io.h>, never directly. */ 39 40 #ifndef _AVR_IO_H_ 41 # error "Include <avr/io.h> instead of this file." 42 #endif 43 44 #ifndef _AVR_IOXXX_H_ 45 # define _AVR_IOXXX_H_ "io76c711.h" 46 #else 47 # error "Attempt to include more than one <avr/ioXXX.h> file." 48 #endif 49 50 /* I/O registers */ 51 52 /* 0x00-0x0C reserved */ 53 54 /* SPI */ 55 #define SPCR _SFR_IO8(0x0D) 56 #define SPSR _SFR_IO8(0x0E) 57 #define SPDR _SFR_IO8(0x0F) 58 59 /* Port D */ 60 #define PIND _SFR_IO8(0x10) 61 #define DDRD _SFR_IO8(0x11) 62 #define PORTD _SFR_IO8(0x12) 63 64 /* Peripheral Enable Register */ 65 #define PERIPHEN _SFR_IO8(0x13) 66 67 /* Clock Control Register */ 68 #define CLK_CNTR _SFR_IO8(0x14) 69 70 /* Data Register, Port C */ 71 #define PORTC _SFR_IO8(0x15) 72 73 /* Port B */ 74 #define PINB _SFR_IO8(0x16) 75 #define DDRB _SFR_IO8(0x17) 76 #define PORTB _SFR_IO8(0x18) 77 78 /* Port A */ 79 #define PINA _SFR_IO8(0x19) 80 #define DDRA _SFR_IO8(0x1A) 81 #define PORTA _SFR_IO8(0x1B) 82 83 /* 0x1C-0x1F reserved */ 84 85 #define IRDAMOD _SFR_IO8(0x20) 86 87 #define WDTCR _SFR_IO8(0x21) 88 89 /* 0x22-0x25 reserved */ 90 /* Timer 1 */ 91 #define ICR1 _SFR_IO16(0x26) 92 #define ICR1L _SFR_IO8(0x26) 93 #define ICR1H _SFR_IO8(0x27) 94 #define OCR1B _SFR_IO16(0x28) 95 #define OCR1BL _SFR_IO8(0x28) 96 #define OCR1BH _SFR_IO8(0x29) 97 #define OCR1A _SFR_IO16(0x2A) 98 #define OCR1AL _SFR_IO8(0x2A) 99 #define OCR1AH _SFR_IO8(0x2B) 100 #define TCNT1 _SFR_IO16(0x2C) 101 #define TCNT1L _SFR_IO8(0x2C) 102 #define TCNT1H _SFR_IO8(0x2D) 103 #define TCCR1B _SFR_IO8(0x2E) 104 #define TCCR1A _SFR_IO8(0x2F) 105 106 /* 0x30 reserved */ 107 108 /* Timer 0 */ 109 #define PRELD _SFR_IO8(0x31) 110 #define TCNT0 _SFR_IO8(0x32) 111 #define TCCR0 _SFR_IO8(0x33) 112 113 #define MCUSR _SFR_IO8(0x34) 114 #define MCUCR _SFR_IO8(0x35) 115 116 #define TIFR _SFR_IO8(0x36) 117 #define TIMSK _SFR_IO8(0x37) 118 119 /* 0x38 reserved */ 120 121 #define EIMSK _SFR_IO8(0x39) 122 123 /* 0x3A-0x3C reserved */ 124 125 /* 0x3D..0x3E SP */ 126 127 /* 0x3F SREG */ 128 129 /* Interrupt vectors */ 130 131 #define SIG_SUSPEND_RESUME _VECTOR(1) 132 #define SIG_INTERRUPT0 _VECTOR(2) 133 #define SIG_INPUT_CAPTURE1 _VECTOR(3) 134 #define SIG_OUTPUT_COMPARE1A _VECTOR(4) 135 #define SIG_OUTPUT_COMPARE1B _VECTOR(5) 136 #define SIG_OVERFLOW1 _VECTOR(6) 137 #define SIG_OVERFLOW0 _VECTOR(7) 138 #define SIG_SPI _VECTOR(8) 139 #define SIG_TDMAC _VECTOR(9) 140 #define SIG_UART0 _VECTOR(10) 141 #define SIG_RDMAC _VECTOR(11) 142 #define SIG_USB_HW _VECTOR(12) 143 #define SIG_UART1 _VECTOR(13) 144 #define SIG_INTERRUPT1 _VECTOR(14) 145 146 #define _VECTORS_SIZE 60 147 148 /* Bit numbers */ 149 150 /* EIMSK */ 151 /* bits 7-4 reserved */ 152 #define POL1 3 153 #define POL0 2 154 #define INT1 1 155 #define INT0 0 156 157 /* TIMSK */ 158 #define TOIE1 7 159 #define OCIE1A 6 160 #define OCIE1B 5 161 /* bit 4 reserved */ 162 #define TICIE1 3 163 /* bit 2 reserved */ 164 #define TOIE0 1 165 /* bit 0 reserved */ 166 167 /* TIFR */ 168 #define TOV1 7 169 #define OCF1A 6 170 #define OCF1B 5 171 /* bit 4 reserved */ 172 #define ICF1 3 173 /* bit 2 reserved */ 174 #define TOV0 1 175 /* bit 0 reserved */ 176 177 /* MCUCR */ 178 /* bits 7-6 reserved */ 179 #define SE 5 180 #define SM1 4 181 #define SM0 3 182 /* bits 2-0 reserved */ 183 184 /* MCUSR */ 185 /* bits 7-2 reserved */ 186 #define EXTRF 1 187 #define PORF 0 188 189 /* TCCR0 */ 190 /* bits 7-6 reserved */ 191 #define COM01 5 192 #define COM00 4 193 #define CTC0 3 194 #define CS02 2 195 #define CS01 1 196 #define CS00 0 197 198 /* TCCR1A */ 199 #define COM1A1 7 200 #define COM1A0 6 201 #define COM1B1 5 202 #define COM1B0 4 203 /* bits 3-0 reserved */ 204 205 /* TCCR1B */ 206 #define ICNC1 7 207 #define ICES1 6 208 /* bits 5-4 reserved */ 209 #define CTC1 3 210 #define CS12 2 211 #define CS11 1 212 #define CS10 0 213 214 /* WDTCR */ 215 /* bits 7-5 reserved */ 216 #define WDTOE 4 217 #define WDE 3 218 #define WDP2 2 219 #define WDP1 1 220 #define WDP0 0 221 222 /* IRDAMOD */ 223 /* bits 7-3 reserved */ 224 #define POL 2 225 #define MODE 1 226 #define EN 0 227 228 /* PORTA */ 229 #define PA7 7 230 #define PA6 6 231 #define PA5 5 232 #define PA4 4 233 #define PA3 3 234 #define PA2 2 235 #define PA1 1 236 #define PA0 0 237 238 /* DDRA */ 239 #define DDA7 7 240 #define DDA6 6 241 #define DDA5 5 242 #define DDA4 4 243 #define DDA3 3 244 #define DDA2 2 245 #define DDA1 1 246 #define DDA0 0 247 248 /* PINA */ 249 #define PINA7 7 250 #define PINA6 6 251 #define PINA5 5 252 #define PINA4 4 253 #define PINA3 3 254 #define PINA2 2 255 #define PINA1 1 256 #define PINA0 0 257 258 /* 259 PB7 = SCK 260 PB6 = MISO 261 PB5 = MOSI 262 PB4 = SS# 263 PB2 = ICP 264 PB1 = T1 265 PB0 = T0 266 */ 267 268 /* PORTB */ 269 #define PB7 7 270 #define PB6 6 271 #define PB5 5 272 #define PB4 4 273 #define PB3 3 274 #define PB2 2 275 #define PB1 1 276 #define PB0 0 277 278 /* DDRB */ 279 #define DDB7 7 280 #define DDB6 6 281 #define DDB5 5 282 #define DDB4 4 283 #define DDB3 3 284 #define DDB2 2 285 #define DDB1 1 286 #define DDB0 0 287 288 /* PINB */ 289 #define PINB7 7 290 #define PINB6 6 291 #define PINB5 5 292 #define PINB4 4 293 #define PINB3 3 294 #define PINB2 2 295 #define PINB1 1 296 #define PINB0 0 297 298 /* PORTC */ 299 /* bits 7-4 reserved */ 300 #define PC3 3 301 #define PC2 2 302 #define PC1 1 303 #define PC0 0 304 305 /* 306 PD7 = INT1 / OC1B 307 PD6 = INT0 / OC1A 308 PD1 = TXD 309 PD0 = RXD 310 */ 311 312 /* PORTD */ 313 #define PD7 7 314 #define PD6 6 315 #define PD5 5 316 #define PD4 4 317 #define PD3 3 318 #define PD2 2 319 #define PD1 1 320 #define PD0 0 321 322 /* DDRD */ 323 #define DDD7 7 324 #define DDD6 6 325 #define DDD5 5 326 #define DDD4 4 327 #define DDD3 3 328 #define DDD2 2 329 #define DDD1 1 330 #define DDD0 0 331 332 /* PIND */ 333 #define PIND7 7 334 #define PIND6 6 335 #define PIND5 5 336 #define PIND4 4 337 #define PIND3 3 338 #define PIND2 2 339 #define PIND1 1 340 #define PIND0 0 341 342 /* CLK_CNTR */ 343 /* bits 7-5 reserved */ 344 #define UOSC 4 345 #define UCK 3 346 #define IRCK 2 347 /* bits 1-0 reserved */ 348 349 /* PERIPHEN */ 350 /* bits 7-3 reserved */ 351 #define IRDA 2 352 #define UART 1 353 #define USB 0 354 355 /* SPSR */ 356 #define SPIF 7 357 #define WCOL 6 358 /* bits 5-0 reserved */ 359 360 /* SPCR */ 361 #define SPIE 7 362 #define SPE 6 363 #define DORD 5 364 #define MSTR 4 365 #define CPOL 3 366 #define CPHA 2 367 #define SPR1 1 368 #define SPR0 0 369 370 /* Memory mapped registers (XXX - not yet changed to use _SFR_MEM8() macros) */ 371 372 /* UART */ 373 #define UART0_BASE 0x2020 374 #define UART1_BASE 0x2030 375 /* offsets from the base address */ 376 #define US_RHR 0x00 377 #define US_THR 0x00 378 #define US_IER 0x01 379 #define US_FCR 0x02 380 #define US_PMR 0x03 381 #define US_MR 0x04 382 #define US_CSR 0x05 383 #define US_CR 0x06 384 #define US_BL 0x07 385 #define US_BM 0x08 386 #define US_RTO 0x09 387 #define US_TTG 0x0A 388 389 /* DMA */ 390 #define DMA_BASE 0x2000 391 /* offsets from the base address */ 392 #define TXTADL 0x01 393 #define TXPLL 0x03 394 #define TXPLM 0x04 395 #define TXTPLL 0x05 396 #define TXTPLM 0x06 397 #define RXTADL 0x07 398 #define RXTADMEN 0x08 399 #define RSPLL 0x09 400 #define RXPLM 0x0A 401 #define RXTPLL 0x0B 402 #define RXTPLM 0x0C 403 #define INTCST 0x0D 404 /* XXX DPORG register mentioned on page 20, but undocumented */ 405 406 /* XXX Program Memory Control Bit mentioned on page 20, but undocumented */ 407 #define PROGRAM_MEMORY_CONTROL_BIT 0x2040 408 409 /* USB */ 410 #define USB_BASE 0x1000 411 /* offsets from the base address */ 412 #define FRM_NUM_H 0x0FD 413 #define FRM_NUM_L 0x0FC 414 #define GLB_STATE 0x0FB 415 #define SPRSR 0x0FA 416 #define SPRSIE 0x0F9 417 #define UISR 0x0F7 418 #define UIAR 0x0F5 419 #define FADDR 0x0F2 420 #define ENDPPGPG 0x0F1 421 #define ECR0 0x0EF 422 #define ECR1 0x0EE 423 #define ECR2 0x0ED 424 #define ECR3 0x0EC 425 #define ECR4 0x0EB 426 #define ECR5 0x0EA 427 #define ECR6 0x0E9 428 #define ECR7 0x0E8 429 #define CSR0 0x0DF 430 #define CSR1 0x0DE 431 #define CSR2 0x0DD 432 #define CSR3 0x0DC 433 #define CSR4 0x0DB 434 #define CSR5 0x0DA 435 #define CSR6 0x0D9 436 #define CSR7 0x0D8 437 #define FDR0 0x0CF 438 #define FDR1 0x0CE 439 #define FDR2 0x0CD 440 #define FDR3 0x0CC 441 #define FDR4 0x0CB 442 #define FDR5 0x0CA 443 #define FDR6 0x0C9 444 #define FDR7 0x0C8 445 #define FBYTE_CNT0_L 0x0BF 446 #define FBYTE_CNT1_L 0x0BE 447 #define FBYTE_CNT2_L 0x0BD 448 #define FBYTE_CNT3_L 0x0BC 449 #define FBYTE_CNT4_L 0x0BB 450 #define FBYTE_CNT5_L 0x0BA 451 #define FBYTE_CNT6_L 0x0B9 452 #define FBYTE_CNT7_L 0x0B8 453 #define FBYTE_CNT0_H 0x0AF 454 #define FBYTE_CNT1_H 0x0AE 455 #define FBYTE_CNT2_H 0x0AD 456 #define FBYTE_CNT3_H 0x0AC 457 #define FBYTE_CNT4_H 0x0AB 458 #define FBYTE_CNT5_H 0x0AA 459 #define FBYTE_CNT6_H 0x0A9 460 #define FBYTE_CNT7_H 0x0A8 461 #define SLP_MD_EN 0x100 462 #define IRQ_EN 0x101 463 #define IRQ_STAT 0x102 464 #define SUSP_WUP 0x103 465 #define PA_EN 0x104 466 #define USB_DMA_ADL 0x105 467 #define USB_DMA_ADH 0x106 468 #define USB_DMA_PLR 0x107 469 #define USB_DMA_EAD 0x108 470 #define USB_DMA_PLT 0x109 471 #define USB_DMA_EN 0x10A 472 473 /* Last memory addresses */ 474 #define RAMSTART 0x60 475 #define RAMEND 0x07FF 476 #define XRAMEND RAMEND 477 #define E2END 0 478 #define FLASHEND 0x3FFF 479 480 /* 481 AT76C711 data space memory map (ranges not listed are reserved): 482 0x0000 - 0x001F - AVR registers 483 0x0020 - 0x005F - AVR I/O space 484 0x0060 - 0x07FF - AVR data SRAM 485 0x1000 - 0x1FFF - USB (not all locations used) 486 0x2000 - 0x201F - DMA controller 487 0x2020 - 0x202F - UART0 488 0x2030 - 0x203F - UART1 (IRDA) 489 0x2040 - the mysterious Program Memory Control bit (???) 490 0x3000 - 0x37FF - DPRAM 491 0x8000 - 0xBFFF - program SRAM (read/write), would be nice if other 492 AVR devices did that as well (no need to use LPM!) 493 494 */ 495 496 #define SLEEP_MODE_IDLE 0 497 #define SLEEP_MODE_ADC _BV(SM0) 498 #define SLEEP_MODE_PWR_DOWN _BV(SM1) 499 #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) 500 501 #endif /* _AVR_IO76C711_H_ */ 502