1 /* Definitions of target machine for GCC for IA-32. 2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING. If not, write to 19 the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20 Boston, MA 02110-1301, USA. */ 21 22 /* The purpose of this file is to define the characteristics of the i386, 23 independent of assembler syntax or operating system. 24 25 Three other files build on this one to describe a specific assembler syntax: 26 bsd386.h, att386.h, and sun386.h. 27 28 The actual tm.h file for a particular system should include 29 this file, and then the file for the appropriate assembler syntax. 30 31 Many macros that specify assembler syntax are omitted entirely from 32 this file because they really belong in the files for particular 33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 35 that start with ASM_ or end in ASM_OP. */ 36 37 /* Define the specific costs for a given cpu */ 38 39 struct processor_costs { 40 const int add; /* cost of an add instruction */ 41 const int lea; /* cost of a lea instruction */ 42 const int shift_var; /* variable shift costs */ 43 const int shift_const; /* constant shift costs */ 44 const int mult_init[5]; /* cost of starting a multiply 45 in QImode, HImode, SImode, DImode, TImode*/ 46 const int mult_bit; /* cost of multiply per each bit set */ 47 const int divide[5]; /* cost of a divide/mod 48 in QImode, HImode, SImode, DImode, TImode*/ 49 int movsx; /* The cost of movsx operation. */ 50 int movzx; /* The cost of movzx operation. */ 51 const int large_insn; /* insns larger than this cost more */ 52 const int move_ratio; /* The threshold of number of scalar 53 memory-to-memory move insns. */ 54 const int movzbl_load; /* cost of loading using movzbl */ 55 const int int_load[3]; /* cost of loading integer registers 56 in QImode, HImode and SImode relative 57 to reg-reg move (2). */ 58 const int int_store[3]; /* cost of storing integer register 59 in QImode, HImode and SImode */ 60 const int fp_move; /* cost of reg,reg fld/fst */ 61 const int fp_load[3]; /* cost of loading FP register 62 in SFmode, DFmode and XFmode */ 63 const int fp_store[3]; /* cost of storing FP register 64 in SFmode, DFmode and XFmode */ 65 const int mmx_move; /* cost of moving MMX register. */ 66 const int mmx_load[2]; /* cost of loading MMX register 67 in SImode and DImode */ 68 const int mmx_store[2]; /* cost of storing MMX register 69 in SImode and DImode */ 70 const int sse_move; /* cost of moving SSE register. */ 71 const int sse_load[3]; /* cost of loading SSE register 72 in SImode, DImode and TImode*/ 73 const int sse_store[3]; /* cost of storing SSE register 74 in SImode, DImode and TImode*/ 75 const int mmxsse_to_integer; /* cost of moving mmxsse register to 76 integer and vice versa. */ 77 const int prefetch_block; /* bytes moved to cache for prefetch. */ 78 const int simultaneous_prefetches; /* number of parallel prefetch 79 operations. */ 80 const int branch_cost; /* Default value for BRANCH_COST. */ 81 const int fadd; /* cost of FADD and FSUB instructions. */ 82 const int fmul; /* cost of FMUL instruction. */ 83 const int fdiv; /* cost of FDIV instruction. */ 84 const int fabs; /* cost of FABS instruction. */ 85 const int fchs; /* cost of FCHS instruction. */ 86 const int fsqrt; /* cost of FSQRT instruction. */ 87 }; 88 89 extern const struct processor_costs *ix86_cost; 90 91 /* Macros used in the machine description to test the flags. */ 92 93 /* configure can arrange to make this 2, to force a 486. */ 94 95 #ifndef TARGET_CPU_DEFAULT 96 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic 97 #endif 98 99 #ifndef TARGET_FPMATH_DEFAULT 100 #define TARGET_FPMATH_DEFAULT \ 101 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) 102 #endif 103 104 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS 105 106 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 107 compile-time constant. */ 108 #ifdef IN_LIBGCC2 109 #undef TARGET_64BIT 110 #ifdef __x86_64__ 111 #define TARGET_64BIT 1 112 #else 113 #define TARGET_64BIT 0 114 #endif 115 #else 116 #ifndef TARGET_BI_ARCH 117 #undef TARGET_64BIT 118 #if TARGET_64BIT_DEFAULT 119 #define TARGET_64BIT 1 120 #else 121 #define TARGET_64BIT 0 122 #endif 123 #endif 124 #endif 125 126 #define HAS_LONG_COND_BRANCH 1 127 #define HAS_LONG_UNCOND_BRANCH 1 128 129 #define TARGET_386 (ix86_tune == PROCESSOR_I386) 130 #define TARGET_486 (ix86_tune == PROCESSOR_I486) 131 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 132 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 133 #define TARGET_K6 (ix86_tune == PROCESSOR_K6) 134 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 135 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 136 #define TARGET_K8 (ix86_tune == PROCESSOR_K8) 137 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 138 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) 139 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) 140 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) 141 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) 142 143 #define TUNEMASK (1 << ix86_tune) 144 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; 145 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch; 146 extern const int x86_branch_hints, x86_unroll_strlen; 147 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; 148 extern const int x86_use_himode_fiop, x86_use_simode_fiop; 149 extern const int x86_use_mov0, x86_use_cltd, x86_read_modify_write; 150 extern const int x86_read_modify, x86_split_long_moves; 151 extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix; 152 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; 153 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves; 154 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; 155 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; 156 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move; 157 extern const int x86_epilogue_using_move, x86_decompose_lea; 158 extern const int x86_arch_always_fancy_math_387, x86_shift1; 159 extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs; 160 extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor; 161 extern const int x86_use_ffreep; 162 extern const int x86_inter_unit_moves, x86_schedule; 163 extern const int x86_use_bt; 164 extern const int x86_cmpxchg, x86_cmpxchg8b, x86_cmpxchg16b, x86_xadd; 165 extern const int x86_use_incdec; 166 extern const int x86_pad_returns; 167 extern const int x86_partial_flag_reg_stall; 168 extern int x86_prefetch_sse; 169 170 #define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK) 171 #define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK) 172 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK) 173 #define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK) 174 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK) 175 /* For sane SSE instruction set generation we need fcomi instruction. It is 176 safe to enable all CMOVE instructions. */ 177 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) 178 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) 179 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK) 180 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK) 181 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK) 182 #define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT) 183 #define TARGET_MOVX (x86_movx & TUNEMASK) 184 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK) 185 #define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK) 186 #define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK) 187 #define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK) 188 #define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK) 189 #define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK) 190 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK) 191 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK) 192 #define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK) 193 #define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK) 194 #define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK) 195 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK) 196 #define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK) 197 #define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK) 198 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK) 199 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK) 200 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK) 201 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK) 202 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK) 203 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK) 204 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK) 205 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK) 206 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 207 (x86_sse_partial_reg_dependency & TUNEMASK) 208 #define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK) 209 #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK) 210 #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK) 211 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK) 212 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK) 213 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK) 214 #define TARGET_PREFETCH_SSE (x86_prefetch_sse) 215 #define TARGET_SHIFT1 (x86_shift1 & TUNEMASK) 216 #define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK) 217 #define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK) 218 #define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK) 219 #define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK) 220 #define TARGET_SCHEDULE (x86_schedule & TUNEMASK) 221 #define TARGET_USE_BT (x86_use_bt & TUNEMASK) 222 #define TARGET_USE_INCDEC (x86_use_incdec & TUNEMASK) 223 #define TARGET_PAD_RETURNS (x86_pad_returns & TUNEMASK) 224 225 #define ASSEMBLER_DIALECT (ix86_asm_dialect) 226 227 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 228 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ 229 && (ix86_fpmath & FPMATH_387)) 230 231 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 232 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) 233 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) 234 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) 235 236 #define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch)) 237 #define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch)) 238 #define TARGET_CMPXCHG16B (x86_cmpxchg16b & (1 << ix86_arch)) 239 #define TARGET_XADD (x86_xadd & (1 << ix86_arch)) 240 241 #ifndef TARGET_64BIT_DEFAULT 242 #define TARGET_64BIT_DEFAULT 0 243 #endif 244 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 245 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 246 #endif 247 248 /* Once GDB has been enhanced to deal with functions without frame 249 pointers, we can change this to allow for elimination of 250 the frame pointer in leaf functions. */ 251 #define TARGET_DEFAULT 0 252 253 /* This is not really a target flag, but is done this way so that 254 it's analogous to similar code for Mach-O on PowerPC. darwin.h 255 redefines this to 1. */ 256 #define TARGET_MACHO 0 257 258 /* Subtargets may reset this to 1 in order to enable 96-bit long double 259 with the rounding mode forced to 53 bits. */ 260 #define TARGET_96_ROUND_53_LONG_DOUBLE 0 261 262 /* Sometimes certain combinations of command options do not make 263 sense on a particular target machine. You can define a macro 264 `OVERRIDE_OPTIONS' to take account of this. This macro, if 265 defined, is executed once just after all the command options have 266 been parsed. 267 268 Don't use this macro to turn on various extra optimizations for 269 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 270 271 #define OVERRIDE_OPTIONS override_options () 272 273 /* Define this to change the optimizations performed by default. */ 274 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 275 optimization_options ((LEVEL), (SIZE)) 276 277 /* -march=native handling only makes sense with compiler running on 278 an x86 or x86_64 chip. If changing this condition, also change 279 the condition in driver-i386.c. */ 280 #if defined(__i386__) || defined(__x86_64__) 281 /* In driver-i386.c. */ 282 extern const char *host_detect_local_cpu (int argc, const char **argv); 283 #define EXTRA_SPEC_FUNCTIONS \ 284 { "local_cpu_detect", host_detect_local_cpu }, 285 #define HAVE_LOCAL_CPU_DETECT 286 #endif 287 288 /* Support for configure-time defaults of some command line options. 289 The order here is important so that -march doesn't squash the 290 tune or cpu values. */ 291 #define OPTION_DEFAULT_SPECS \ 292 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 293 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 294 {"arch", "%{!march=*:-march=%(VALUE)}"} 295 296 /* Specs for the compiler proper */ 297 298 #ifndef CC1_CPU_SPEC 299 #define CC1_CPU_SPEC_1 "\ 300 %{!mtune*: \ 301 %{m386:mtune=i386 \ 302 %n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \ 303 %{m486:-mtune=i486 \ 304 %n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \ 305 %{mpentium:-mtune=pentium \ 306 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \ 307 %{mpentiumpro:-mtune=pentiumpro \ 308 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \ 309 %{mcpu=*:-mtune=%* \ 310 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \ 311 %<mcpu=* \ 312 %{mintel-syntax:-masm=intel \ 313 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 314 %{mno-intel-syntax:-masm=att \ 315 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 316 317 #ifndef HAVE_LOCAL_CPU_DETECT 318 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 319 #else 320 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ 321 "%{march=native:%<march=native %:local_cpu_detect(arch) \ 322 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \ 323 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 324 #endif 325 #endif 326 327 /* Target CPU builtins. */ 328 #define TARGET_CPU_CPP_BUILTINS() \ 329 do \ 330 { \ 331 size_t arch_len = strlen (ix86_arch_string); \ 332 size_t tune_len = strlen (ix86_tune_string); \ 333 int last_arch_char = ix86_arch_string[arch_len - 1]; \ 334 int last_tune_char = ix86_tune_string[tune_len - 1]; \ 335 \ 336 if (TARGET_64BIT) \ 337 { \ 338 builtin_assert ("cpu=x86_64"); \ 339 builtin_assert ("machine=x86_64"); \ 340 builtin_define ("__amd64"); \ 341 builtin_define ("__amd64__"); \ 342 builtin_define ("__x86_64"); \ 343 builtin_define ("__x86_64__"); \ 344 } \ 345 else \ 346 { \ 347 builtin_assert ("cpu=i386"); \ 348 builtin_assert ("machine=i386"); \ 349 builtin_define_std ("i386"); \ 350 } \ 351 \ 352 /* Built-ins based on -mtune= (or -march= if no \ 353 -mtune= given). */ \ 354 if (TARGET_386) \ 355 builtin_define ("__tune_i386__"); \ 356 else if (TARGET_486) \ 357 builtin_define ("__tune_i486__"); \ 358 else if (TARGET_PENTIUM) \ 359 { \ 360 builtin_define ("__tune_i586__"); \ 361 builtin_define ("__tune_pentium__"); \ 362 if (last_tune_char == 'x') \ 363 builtin_define ("__tune_pentium_mmx__"); \ 364 } \ 365 else if (TARGET_PENTIUMPRO) \ 366 { \ 367 builtin_define ("__tune_i686__"); \ 368 builtin_define ("__tune_pentiumpro__"); \ 369 switch (last_tune_char) \ 370 { \ 371 case '3': \ 372 builtin_define ("__tune_pentium3__"); \ 373 /* FALLTHRU */ \ 374 case '2': \ 375 builtin_define ("__tune_pentium2__"); \ 376 break; \ 377 } \ 378 } \ 379 else if (TARGET_K6) \ 380 { \ 381 builtin_define ("__tune_k6__"); \ 382 if (last_tune_char == '2') \ 383 builtin_define ("__tune_k6_2__"); \ 384 else if (last_tune_char == '3') \ 385 builtin_define ("__tune_k6_3__"); \ 386 } \ 387 else if (TARGET_ATHLON) \ 388 { \ 389 builtin_define ("__tune_athlon__"); \ 390 /* Only plain "athlon" lacks SSE. */ \ 391 if (last_tune_char != 'n') \ 392 builtin_define ("__tune_athlon_sse__"); \ 393 } \ 394 else if (TARGET_K8) \ 395 builtin_define ("__tune_k8__"); \ 396 else if (TARGET_PENTIUM4) \ 397 builtin_define ("__tune_pentium4__"); \ 398 else if (TARGET_NOCONA) \ 399 builtin_define ("__tune_nocona__"); \ 400 \ 401 if (TARGET_MMX) \ 402 builtin_define ("__MMX__"); \ 403 if (TARGET_3DNOW) \ 404 builtin_define ("__3dNOW__"); \ 405 if (TARGET_3DNOW_A) \ 406 builtin_define ("__3dNOW_A__"); \ 407 if (TARGET_SSE) \ 408 builtin_define ("__SSE__"); \ 409 if (TARGET_SSE2) \ 410 builtin_define ("__SSE2__"); \ 411 if (TARGET_SSE3) \ 412 builtin_define ("__SSE3__"); \ 413 if (TARGET_SSE_MATH && TARGET_SSE) \ 414 builtin_define ("__SSE_MATH__"); \ 415 if (TARGET_SSE_MATH && TARGET_SSE2) \ 416 builtin_define ("__SSE2_MATH__"); \ 417 \ 418 /* Built-ins based on -march=. */ \ 419 if (ix86_arch == PROCESSOR_I486) \ 420 { \ 421 builtin_define ("__i486"); \ 422 builtin_define ("__i486__"); \ 423 } \ 424 else if (ix86_arch == PROCESSOR_PENTIUM) \ 425 { \ 426 builtin_define ("__i586"); \ 427 builtin_define ("__i586__"); \ 428 builtin_define ("__pentium"); \ 429 builtin_define ("__pentium__"); \ 430 if (last_arch_char == 'x') \ 431 builtin_define ("__pentium_mmx__"); \ 432 } \ 433 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \ 434 { \ 435 builtin_define ("__i686"); \ 436 builtin_define ("__i686__"); \ 437 builtin_define ("__pentiumpro"); \ 438 builtin_define ("__pentiumpro__"); \ 439 } \ 440 else if (ix86_arch == PROCESSOR_K6) \ 441 { \ 442 \ 443 builtin_define ("__k6"); \ 444 builtin_define ("__k6__"); \ 445 if (last_arch_char == '2') \ 446 builtin_define ("__k6_2__"); \ 447 else if (last_arch_char == '3') \ 448 builtin_define ("__k6_3__"); \ 449 } \ 450 else if (ix86_arch == PROCESSOR_ATHLON) \ 451 { \ 452 builtin_define ("__athlon"); \ 453 builtin_define ("__athlon__"); \ 454 /* Only plain "athlon" lacks SSE. */ \ 455 if (last_arch_char != 'n') \ 456 builtin_define ("__athlon_sse__"); \ 457 } \ 458 else if (ix86_arch == PROCESSOR_K8) \ 459 { \ 460 builtin_define ("__k8"); \ 461 builtin_define ("__k8__"); \ 462 } \ 463 else if (ix86_arch == PROCESSOR_PENTIUM4) \ 464 { \ 465 builtin_define ("__pentium4"); \ 466 builtin_define ("__pentium4__"); \ 467 } \ 468 else if (ix86_arch == PROCESSOR_NOCONA) \ 469 { \ 470 builtin_define ("__nocona"); \ 471 builtin_define ("__nocona__"); \ 472 } \ 473 } \ 474 while (0) 475 476 #define TARGET_CPU_DEFAULT_i386 0 477 #define TARGET_CPU_DEFAULT_i486 1 478 #define TARGET_CPU_DEFAULT_pentium 2 479 #define TARGET_CPU_DEFAULT_pentium_mmx 3 480 #define TARGET_CPU_DEFAULT_pentiumpro 4 481 #define TARGET_CPU_DEFAULT_pentium2 5 482 #define TARGET_CPU_DEFAULT_pentium3 6 483 #define TARGET_CPU_DEFAULT_pentium4 7 484 #define TARGET_CPU_DEFAULT_k6 8 485 #define TARGET_CPU_DEFAULT_k6_2 9 486 #define TARGET_CPU_DEFAULT_k6_3 10 487 #define TARGET_CPU_DEFAULT_athlon 11 488 #define TARGET_CPU_DEFAULT_athlon_sse 12 489 #define TARGET_CPU_DEFAULT_k8 13 490 #define TARGET_CPU_DEFAULT_pentium_m 14 491 #define TARGET_CPU_DEFAULT_prescott 15 492 #define TARGET_CPU_DEFAULT_nocona 16 493 #define TARGET_CPU_DEFAULT_generic 17 494 495 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ 496 "pentiumpro", "pentium2", "pentium3", \ 497 "pentium4", "k6", "k6-2", "k6-3",\ 498 "athlon", "athlon-4", "k8", \ 499 "pentium-m", "prescott", "nocona", \ 500 "generic"} 501 502 #ifndef CC1_SPEC 503 #define CC1_SPEC "%(cc1_cpu) " 504 #endif 505 506 /* This macro defines names of additional specifications to put in the 507 specs that can be used in various specifications like CC1_SPEC. Its 508 definition is an initializer with a subgrouping for each command option. 509 510 Each subgrouping contains a string constant, that defines the 511 specification name, and a string constant that used by the GCC driver 512 program. 513 514 Do not define this macro if it does not need to do anything. */ 515 516 #ifndef SUBTARGET_EXTRA_SPECS 517 #define SUBTARGET_EXTRA_SPECS 518 #endif 519 520 #define EXTRA_SPECS \ 521 { "cc1_cpu", CC1_CPU_SPEC }, \ 522 SUBTARGET_EXTRA_SPECS 523 524 /* target machine storage layout */ 525 526 #define LONG_DOUBLE_TYPE_SIZE 80 527 528 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the 529 FPU, assume that the fpcw is set to extended precision; when using 530 only SSE, rounding is correct; when using both SSE and the FPU, 531 the rounding precision is indeterminate, since either may be chosen 532 apparently at random. */ 533 #define TARGET_FLT_EVAL_METHOD \ 534 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) 535 536 #define SHORT_TYPE_SIZE 16 537 #define INT_TYPE_SIZE 32 538 #define FLOAT_TYPE_SIZE 32 539 #define LONG_TYPE_SIZE BITS_PER_WORD 540 #define DOUBLE_TYPE_SIZE 64 541 #define LONG_LONG_TYPE_SIZE 64 542 543 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 544 #define MAX_BITS_PER_WORD 64 545 #else 546 #define MAX_BITS_PER_WORD 32 547 #endif 548 549 /* Define this if most significant byte of a word is the lowest numbered. */ 550 /* That is true on the 80386. */ 551 552 #define BITS_BIG_ENDIAN 0 553 554 /* Define this if most significant byte of a word is the lowest numbered. */ 555 /* That is not true on the 80386. */ 556 #define BYTES_BIG_ENDIAN 0 557 558 /* Define this if most significant word of a multiword number is the lowest 559 numbered. */ 560 /* Not true for 80386 */ 561 #define WORDS_BIG_ENDIAN 0 562 563 /* Width of a word, in units (bytes). */ 564 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 565 #ifdef IN_LIBGCC2 566 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 567 #else 568 #define MIN_UNITS_PER_WORD 4 569 #endif 570 571 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 572 #define PARM_BOUNDARY BITS_PER_WORD 573 574 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 575 #define STACK_BOUNDARY BITS_PER_WORD 576 577 /* Boundary (in *bits*) on which the stack pointer prefers to be 578 aligned; the compiler cannot rely on having this alignment. */ 579 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 580 581 /* As of July 2001, many runtimes do not align the stack properly when 582 entering main. This causes expand_main_function to forcibly align 583 the stack, which results in aligned frames for functions called from 584 main, though it does nothing for the alignment of main itself. */ 585 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ 586 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) 587 588 /* Minimum allocation boundary for the code of a function. */ 589 #define FUNCTION_BOUNDARY 8 590 591 /* C++ stores the virtual bit in the lowest bit of function pointers. */ 592 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 593 594 /* Alignment of field after `int : 0' in a structure. */ 595 596 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 597 598 /* Minimum size in bits of the largest boundary to which any 599 and all fundamental data types supported by the hardware 600 might need to be aligned. No data type wants to be aligned 601 rounder than this. 602 603 Pentium+ prefers DFmode values to be aligned to 64 bit boundary 604 and Pentium Pro XFmode values at 128 bit boundaries. */ 605 606 #define BIGGEST_ALIGNMENT 128 607 608 /* Decide whether a variable of mode MODE should be 128 bit aligned. */ 609 #define ALIGN_MODE_128(MODE) \ 610 ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) 611 612 /* The published ABIs say that doubles should be aligned on word 613 boundaries, so lower the alignment for structure fields unless 614 -malign-double is set. */ 615 616 /* ??? Blah -- this macro is used directly by libobjc. Since it 617 supports no vector modes, cut out the complexity and fall back 618 on BIGGEST_FIELD_ALIGNMENT. */ 619 #ifdef IN_TARGET_LIBS 620 #ifdef __x86_64__ 621 #define BIGGEST_FIELD_ALIGNMENT 128 622 #else 623 #define BIGGEST_FIELD_ALIGNMENT 32 624 #endif 625 #else 626 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 627 x86_field_alignment (FIELD, COMPUTED) 628 #endif 629 630 /* If defined, a C expression to compute the alignment given to a 631 constant that is being placed in memory. EXP is the constant 632 and ALIGN is the alignment that the object would ordinarily have. 633 The value of this macro is used instead of that alignment to align 634 the object. 635 636 If this macro is not defined, then ALIGN is used. 637 638 The typical use of this macro is to increase alignment for string 639 constants to be word aligned so that `strcpy' calls that copy 640 constants can be done inline. */ 641 642 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 643 644 /* If defined, a C expression to compute the alignment for a static 645 variable. TYPE is the data type, and ALIGN is the alignment that 646 the object would ordinarily have. The value of this macro is used 647 instead of that alignment to align the object. 648 649 If this macro is not defined, then ALIGN is used. 650 651 One use of this macro is to increase alignment of medium-size 652 data to make it all fit in fewer cache lines. Another is to 653 cause character arrays to be word-aligned so that `strcpy' calls 654 that copy constants to character arrays can be done inline. */ 655 656 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 657 658 /* If defined, a C expression to compute the alignment for a local 659 variable. TYPE is the data type, and ALIGN is the alignment that 660 the object would ordinarily have. The value of this macro is used 661 instead of that alignment to align the object. 662 663 If this macro is not defined, then ALIGN is used. 664 665 One use of this macro is to increase alignment of medium-size 666 data to make it all fit in fewer cache lines. */ 667 668 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) 669 670 /* If defined, a C expression that gives the alignment boundary, in 671 bits, of an argument with the specified mode and type. If it is 672 not defined, `PARM_BOUNDARY' is used for all arguments. */ 673 674 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 675 ix86_function_arg_boundary ((MODE), (TYPE)) 676 677 /* Set this nonzero if move instructions will actually fail to work 678 when given unaligned data. */ 679 #define STRICT_ALIGNMENT 0 680 681 /* If bit field type is int, don't let it cross an int, 682 and give entire struct the alignment of an int. */ 683 /* Required on the 386 since it doesn't have bit-field insns. */ 684 #define PCC_BITFIELD_TYPE_MATTERS 1 685 686 /* Standard register usage. */ 687 688 /* This processor has special stack-like registers. See reg-stack.c 689 for details. */ 690 691 #define STACK_REGS 692 #define IS_STACK_MODE(MODE) \ 693 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \ 694 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \ 695 || (MODE) == XFmode) 696 697 /* Number of actual hardware registers. 698 The hardware registers are assigned numbers for the compiler 699 from 0 to just below FIRST_PSEUDO_REGISTER. 700 All registers that the compiler knows about must be given numbers, 701 even those that are not normally considered general registers. 702 703 In the 80386 we give the 8 general purpose registers the numbers 0-7. 704 We number the floating point registers 8-15. 705 Note that registers 0-7 can be accessed as a short or int, 706 while only 0-3 may be used with byte `mov' instructions. 707 708 Reg 16 does not correspond to any hardware register, but instead 709 appears in the RTL as an argument pointer prior to reload, and is 710 eliminated during reloading in favor of either the stack or frame 711 pointer. */ 712 713 #define FIRST_PSEUDO_REGISTER 53 714 715 /* Number of hardware registers that go into the DWARF-2 unwind info. 716 If not defined, equals FIRST_PSEUDO_REGISTER. */ 717 718 #define DWARF_FRAME_REGISTERS 17 719 720 /* 1 for registers that have pervasive standard uses 721 and are not available for the register allocator. 722 On the 80386, the stack pointer is such, as is the arg pointer. 723 724 The value is zero if the register is not fixed on either 32 or 725 64 bit targets, one if the register if fixed on both 32 and 64 726 bit targets, two if it is only fixed on 32bit targets and three 727 if its only fixed on 64bit targets. 728 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. 729 */ 730 #define FIXED_REGISTERS \ 731 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 732 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 733 /*arg,flags,fpsr,dir,frame*/ \ 734 1, 1, 1, 1, 1, \ 735 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 736 0, 0, 0, 0, 0, 0, 0, 0, \ 737 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 738 0, 0, 0, 0, 0, 0, 0, 0, \ 739 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 740 2, 2, 2, 2, 2, 2, 2, 2, \ 741 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 742 2, 2, 2, 2, 2, 2, 2, 2} 743 744 745 /* 1 for registers not available across function calls. 746 These must include the FIXED_REGISTERS and also any 747 registers that can be used without being saved. 748 The latter must include the registers where values are returned 749 and the register where structure-value addresses are passed. 750 Aside from that, you can include as many other registers as you like. 751 752 The value is zero if the register is not call used on either 32 or 753 64 bit targets, one if the register if call used on both 32 and 64 754 bit targets, two if it is only call used on 32bit targets and three 755 if its only call used on 64bit targets. 756 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. 757 */ 758 #define CALL_USED_REGISTERS \ 759 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 760 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 761 /*arg,flags,fpsr,dir,frame*/ \ 762 1, 1, 1, 1, 1, \ 763 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 764 1, 1, 1, 1, 1, 1, 1, 1, \ 765 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 766 1, 1, 1, 1, 1, 1, 1, 1, \ 767 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 768 1, 1, 1, 1, 2, 2, 2, 2, \ 769 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 770 1, 1, 1, 1, 1, 1, 1, 1} \ 771 772 /* Order in which to allocate registers. Each register must be 773 listed once, even those in FIXED_REGISTERS. List frame pointer 774 late and fixed registers last. Note that, in general, we prefer 775 registers listed in CALL_USED_REGISTERS, keeping the others 776 available for storage of persistent values. 777 778 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, 779 so this is just empty initializer for array. */ 780 781 #define REG_ALLOC_ORDER \ 782 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 783 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 784 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 785 48, 49, 50, 51, 52 } 786 787 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 788 to be rearranged based on a particular function. When using sse math, 789 we want to allocate SSE before x87 registers and vice vera. */ 790 791 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () 792 793 794 /* Macro to conditionally modify fixed_regs/call_used_regs. */ 795 #define CONDITIONAL_REGISTER_USAGE \ 796 do { \ 797 int i; \ 798 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 799 { \ 800 if (fixed_regs[i] > 1) \ 801 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \ 802 if (call_used_regs[i] > 1) \ 803 call_used_regs[i] = (call_used_regs[i] \ 804 == (TARGET_64BIT ? 3 : 2)); \ 805 } \ 806 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 807 { \ 808 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 809 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 810 } \ 811 if (! TARGET_MMX) \ 812 { \ 813 int i; \ 814 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 815 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ 816 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ 817 } \ 818 if (! TARGET_SSE) \ 819 { \ 820 int i; \ 821 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 822 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ 823 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ 824 } \ 825 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ 826 { \ 827 int i; \ 828 HARD_REG_SET x; \ 829 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ 830 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 831 if (TEST_HARD_REG_BIT (x, i)) \ 832 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ 833 } \ 834 if (! TARGET_64BIT) \ 835 { \ 836 int i; \ 837 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \ 838 reg_names[i] = ""; \ 839 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \ 840 reg_names[i] = ""; \ 841 } \ 842 } while (0) 843 844 /* Return number of consecutive hard regs needed starting at reg REGNO 845 to hold something of mode MODE. 846 This is ordinarily the length in words of a value of mode MODE 847 but can be less for certain modes in special long registers. 848 849 Actually there are no two word move instructions for consecutive 850 registers. And only registers 0-3 may have mov byte instructions 851 applied to them. 852 */ 853 854 #define HARD_REGNO_NREGS(REGNO, MODE) \ 855 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 856 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 857 : ((MODE) == XFmode \ 858 ? (TARGET_64BIT ? 2 : 3) \ 859 : (MODE) == XCmode \ 860 ? (TARGET_64BIT ? 4 : 6) \ 861 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 862 863 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ 864 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ 865 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 866 ? 0 \ 867 : ((MODE) == XFmode || (MODE) == XCmode)) \ 868 : 0) 869 870 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) 871 872 #define VALID_SSE2_REG_MODE(MODE) \ 873 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 874 || (MODE) == V2DImode || (MODE) == DFmode) 875 876 #define VALID_SSE_REG_MODE(MODE) \ 877 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 878 || (MODE) == SFmode || (MODE) == TFmode) 879 880 #define VALID_MMX_REG_MODE_3DNOW(MODE) \ 881 ((MODE) == V2SFmode || (MODE) == SFmode) 882 883 #define VALID_MMX_REG_MODE(MODE) \ 884 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ 885 || (MODE) == V2SImode || (MODE) == SImode) 886 887 /* ??? No autovectorization into MMX or 3DNOW until we can reliably 888 place emms and femms instructions. */ 889 #define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD) 890 891 #define VALID_FP_MODE_P(MODE) \ 892 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 893 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 894 895 #define VALID_INT_MODE_P(MODE) \ 896 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 897 || (MODE) == DImode \ 898 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 899 || (MODE) == CDImode \ 900 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 901 || (MODE) == TFmode || (MODE) == TCmode))) 902 903 /* Return true for modes passed in SSE registers. */ 904 #define SSE_REG_MODE_P(MODE) \ 905 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \ 906 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ 907 || (MODE) == V4SFmode || (MODE) == V4SImode) 908 909 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 910 911 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 912 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 913 914 /* Value is 1 if it is a good idea to tie two pseudo registers 915 when one has mode MODE1 and one has mode MODE2. 916 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 917 for any hard reg, then this must be 0 for correct output. */ 918 919 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) 920 921 /* It is possible to write patterns to move flags; but until someone 922 does it, */ 923 #define AVOID_CCMODE_COPIES 924 925 /* Specify the modes required to caller save a given hard regno. 926 We do this on i386 to prevent flags from being saved at all. 927 928 Kill any attempts to combine saving of modes. */ 929 930 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 931 (CC_REGNO_P (REGNO) ? VOIDmode \ 932 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 933 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\ 934 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 935 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ 936 : (MODE)) 937 /* Specify the registers used for certain standard purposes. 938 The values of these macros are register numbers. */ 939 940 /* on the 386 the pc register is %eip, and is not usable as a general 941 register. The ordinary mov instructions won't work */ 942 /* #define PC_REGNUM */ 943 944 /* Register to use for pushing function arguments. */ 945 #define STACK_POINTER_REGNUM 7 946 947 /* Base register for access to local variables of the function. */ 948 #define HARD_FRAME_POINTER_REGNUM 6 949 950 /* Base register for access to local variables of the function. */ 951 #define FRAME_POINTER_REGNUM 20 952 953 /* First floating point reg */ 954 #define FIRST_FLOAT_REG 8 955 956 /* First & last stack-like regs */ 957 #define FIRST_STACK_REG FIRST_FLOAT_REG 958 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 959 960 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 961 #define LAST_SSE_REG (FIRST_SSE_REG + 7) 962 963 #define FIRST_MMX_REG (LAST_SSE_REG + 1) 964 #define LAST_MMX_REG (FIRST_MMX_REG + 7) 965 966 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 967 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 968 969 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 970 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 971 972 /* Value should be nonzero if functions must have frame pointers. 973 Zero means the frame pointer need not be set up (and parms 974 may be accessed via the stack pointer) in functions that seem suitable. 975 This is computed in `reload', in reload1.c. */ 976 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () 977 978 /* Override this in other tm.h files to cope with various OS lossage 979 requiring a frame pointer. */ 980 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 981 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 982 #endif 983 984 /* Make sure we can access arbitrary call frames. */ 985 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 986 987 /* Base register for access to arguments of the function. */ 988 #define ARG_POINTER_REGNUM 16 989 990 /* Register in which static-chain is passed to a function. 991 We do use ECX as static chain register for 32 bit ABI. On the 992 64bit ABI, ECX is an argument register, so we use R10 instead. */ 993 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) 994 995 /* Register to hold the addressing base for position independent 996 code access to data items. We don't use PIC pointer for 64bit 997 mode. Define the regnum to dummy value to prevent gcc from 998 pessimizing code dealing with EBX. 999 1000 To avoid clobbering a call-saved register unnecessarily, we renumber 1001 the pic register when possible. The change is visible after the 1002 prologue has been emitted. */ 1003 1004 #define REAL_PIC_OFFSET_TABLE_REGNUM 3 1005 1006 #define PIC_OFFSET_TABLE_REGNUM \ 1007 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ 1008 || !flag_pic ? INVALID_REGNUM \ 1009 : reload_completed ? REGNO (pic_offset_table_rtx) \ 1010 : REAL_PIC_OFFSET_TABLE_REGNUM) 1011 1012 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1013 1014 /* A C expression which can inhibit the returning of certain function 1015 values in registers, based on the type of value. A nonzero value 1016 says to return the function value in memory, just as large 1017 structures are always returned. Here TYPE will be a C expression 1018 of type `tree', representing the data type of the value. 1019 1020 Note that values of mode `BLKmode' must be explicitly handled by 1021 this macro. Also, the option `-fpcc-struct-return' takes effect 1022 regardless of this macro. On most systems, it is possible to 1023 leave the macro undefined; this causes a default definition to be 1024 used, whose value is the constant 1 for `BLKmode' values, and 0 1025 otherwise. 1026 1027 Do not use this macro to indicate that structures and unions 1028 should always be returned in memory. You should instead use 1029 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ 1030 1031 #define RETURN_IN_MEMORY(TYPE) \ 1032 ix86_return_in_memory (TYPE) 1033 1034 /* This is overridden by <cygwin.h>. */ 1035 #define MS_AGGREGATE_RETURN 0 1036 1037 /* This is overridden by <netware.h>. */ 1038 #define KEEP_AGGREGATE_RETURN_POINTER 0 1039 1040 /* Define the classes of registers for register constraints in the 1041 machine description. Also define ranges of constants. 1042 1043 One of the classes must always be named ALL_REGS and include all hard regs. 1044 If there is more than one class, another class must be named NO_REGS 1045 and contain no registers. 1046 1047 The name GENERAL_REGS must be the name of a class (or an alias for 1048 another name such as ALL_REGS). This is the class of registers 1049 that is allowed by "g" or "r" in a register constraint. 1050 Also, registers outside this class are allocated only when 1051 instructions express preferences for them. 1052 1053 The classes must be numbered in nondecreasing order; that is, 1054 a larger-numbered class must never be contained completely 1055 in a smaller-numbered class. 1056 1057 For any two classes, it is very desirable that there be another 1058 class that represents their union. 1059 1060 It might seem that class BREG is unnecessary, since no useful 386 1061 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1062 and the "b" register constraint is useful in asms for syscalls. 1063 1064 The flags and fpsr registers are in no class. */ 1065 1066 enum reg_class 1067 { 1068 NO_REGS, 1069 AREG, DREG, CREG, BREG, SIREG, DIREG, 1070 AD_REGS, /* %eax/%edx for DImode */ 1071 Q_REGS, /* %eax %ebx %ecx %edx */ 1072 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1073 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1074 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1075 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1076 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1077 FLOAT_REGS, 1078 SSE_REGS, 1079 MMX_REGS, 1080 FP_TOP_SSE_REGS, 1081 FP_SECOND_SSE_REGS, 1082 FLOAT_SSE_REGS, 1083 FLOAT_INT_REGS, 1084 INT_SSE_REGS, 1085 FLOAT_INT_SSE_REGS, 1086 ALL_REGS, LIM_REG_CLASSES 1087 }; 1088 1089 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1090 1091 #define INTEGER_CLASS_P(CLASS) \ 1092 reg_class_subset_p ((CLASS), GENERAL_REGS) 1093 #define FLOAT_CLASS_P(CLASS) \ 1094 reg_class_subset_p ((CLASS), FLOAT_REGS) 1095 #define SSE_CLASS_P(CLASS) \ 1096 ((CLASS) == SSE_REGS) 1097 #define MMX_CLASS_P(CLASS) \ 1098 ((CLASS) == MMX_REGS) 1099 #define MAYBE_INTEGER_CLASS_P(CLASS) \ 1100 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1101 #define MAYBE_FLOAT_CLASS_P(CLASS) \ 1102 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1103 #define MAYBE_SSE_CLASS_P(CLASS) \ 1104 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1105 #define MAYBE_MMX_CLASS_P(CLASS) \ 1106 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1107 1108 #define Q_CLASS_P(CLASS) \ 1109 reg_class_subset_p ((CLASS), Q_REGS) 1110 1111 /* Give names of register classes as strings for dump file. */ 1112 1113 #define REG_CLASS_NAMES \ 1114 { "NO_REGS", \ 1115 "AREG", "DREG", "CREG", "BREG", \ 1116 "SIREG", "DIREG", \ 1117 "AD_REGS", \ 1118 "Q_REGS", "NON_Q_REGS", \ 1119 "INDEX_REGS", \ 1120 "LEGACY_REGS", \ 1121 "GENERAL_REGS", \ 1122 "FP_TOP_REG", "FP_SECOND_REG", \ 1123 "FLOAT_REGS", \ 1124 "SSE_REGS", \ 1125 "MMX_REGS", \ 1126 "FP_TOP_SSE_REGS", \ 1127 "FP_SECOND_SSE_REGS", \ 1128 "FLOAT_SSE_REGS", \ 1129 "FLOAT_INT_REGS", \ 1130 "INT_SSE_REGS", \ 1131 "FLOAT_INT_SSE_REGS", \ 1132 "ALL_REGS" } 1133 1134 /* Define which registers fit in which classes. 1135 This is an initializer for a vector of HARD_REG_SET 1136 of length N_REG_CLASSES. */ 1137 1138 #define REG_CLASS_CONTENTS \ 1139 { { 0x00, 0x0 }, \ 1140 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1141 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1142 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1143 { 0x03, 0x0 }, /* AD_REGS */ \ 1144 { 0x0f, 0x0 }, /* Q_REGS */ \ 1145 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1146 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1147 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1148 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1149 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1150 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1151 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1152 { 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1153 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1154 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1155 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1156 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1157 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1158 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1159 { 0xffffffff,0x1fffff } \ 1160 } 1161 1162 /* The same information, inverted: 1163 Return the class number of the smallest class containing 1164 reg number REGNO. This could be a conditional expression 1165 or could index an array. */ 1166 1167 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1168 1169 /* When defined, the compiler allows registers explicitly used in the 1170 rtl to be used as spill registers but prevents the compiler from 1171 extending the lifetime of these registers. */ 1172 1173 #define SMALL_REGISTER_CLASSES 1 1174 1175 #define QI_REG_P(X) \ 1176 (REG_P (X) && REGNO (X) < 4) 1177 1178 #define GENERAL_REGNO_P(N) \ 1179 ((N) < 8 || REX_INT_REGNO_P (N)) 1180 1181 #define GENERAL_REG_P(X) \ 1182 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1183 1184 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1185 1186 #define NON_QI_REG_P(X) \ 1187 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) 1188 1189 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) 1190 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1191 1192 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1193 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) 1194 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1195 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1196 1197 #define SSE_REGNO_P(N) \ 1198 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ 1199 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) 1200 1201 #define REX_SSE_REGNO_P(N) \ 1202 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG) 1203 1204 #define SSE_REGNO(N) \ 1205 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1206 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1207 1208 #define SSE_FLOAT_MODE_P(MODE) \ 1209 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1210 1211 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) 1212 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1213 1214 #define STACK_REG_P(XOP) \ 1215 (REG_P (XOP) && \ 1216 REGNO (XOP) >= FIRST_STACK_REG && \ 1217 REGNO (XOP) <= LAST_STACK_REG) 1218 1219 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) 1220 1221 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1222 1223 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1224 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1225 1226 /* The class value for index registers, and the one for base regs. */ 1227 1228 #define INDEX_REG_CLASS INDEX_REGS 1229 #define BASE_REG_CLASS GENERAL_REGS 1230 1231 /* Place additional restrictions on the register class to use when it 1232 is necessary to be able to hold a value of mode MODE in a reload 1233 register for which class CLASS would ordinarily be used. */ 1234 1235 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1236 ((MODE) == QImode && !TARGET_64BIT \ 1237 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1238 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1239 ? Q_REGS : (CLASS)) 1240 1241 /* Given an rtx X being reloaded into a reg required to be 1242 in class CLASS, return the class of reg to actually use. 1243 In general this is just CLASS; but on some machines 1244 in some cases it is preferable to use a more restrictive class. 1245 On the 80386 series, we prevent floating constants from being 1246 reloaded into floating registers (since no move-insn can do that) 1247 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1248 1249 /* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1250 QImode must go into class Q_REGS. 1251 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1252 movdf to do mem-to-mem moves through integer regs. */ 1253 1254 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1255 ix86_preferred_reload_class ((X), (CLASS)) 1256 1257 /* Discourage putting floating-point values in SSE registers unless 1258 SSE math is being used, and likewise for the 387 registers. */ 1259 1260 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ 1261 ix86_preferred_output_reload_class ((X), (CLASS)) 1262 1263 /* If we are copying between general and FP registers, we need a memory 1264 location. The same is true for SSE and MMX registers. */ 1265 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1266 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1267 1268 /* QImode spills from non-QI registers need a scratch. This does not 1269 happen often -- the only example so far requires an uninitialized 1270 pseudo. */ 1271 1272 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ 1273 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ 1274 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ 1275 ? Q_REGS : NO_REGS) 1276 1277 /* Return the maximum number of consecutive registers 1278 needed to represent mode MODE in a register of class CLASS. */ 1279 /* On the 80386, this is the size of MODE in words, 1280 except in the FP regs, where a single reg is always enough. */ 1281 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1282 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1283 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1284 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ 1285 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1286 1287 /* A C expression whose value is nonzero if pseudos that have been 1288 assigned to registers of class CLASS would likely be spilled 1289 because registers of CLASS are needed for spill registers. 1290 1291 The default value of this macro returns 1 if CLASS has exactly one 1292 register and zero otherwise. On most machines, this default 1293 should be used. Only define this macro to some other expression 1294 if pseudo allocated by `local-alloc.c' end up in memory because 1295 their hard registers were needed for spill registers. If this 1296 macro returns nonzero for those classes, those pseudos will only 1297 be allocated by `global.c', which knows how to reallocate the 1298 pseudo to another register. If there would not be another 1299 register available for reallocation, you should not change the 1300 definition of this macro since the only effect of such a 1301 definition would be to slow down register allocation. */ 1302 1303 #define CLASS_LIKELY_SPILLED_P(CLASS) \ 1304 (((CLASS) == AREG) \ 1305 || ((CLASS) == DREG) \ 1306 || ((CLASS) == CREG) \ 1307 || ((CLASS) == BREG) \ 1308 || ((CLASS) == AD_REGS) \ 1309 || ((CLASS) == SIREG) \ 1310 || ((CLASS) == DIREG) \ 1311 || ((CLASS) == FP_TOP_REG) \ 1312 || ((CLASS) == FP_SECOND_REG)) 1313 1314 /* Return a class of registers that cannot change FROM mode to TO mode. */ 1315 1316 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1317 ix86_cannot_change_mode_class (FROM, TO, CLASS) 1318 1319 /* Stack layout; function entry, exit and calling. */ 1320 1321 /* Define this if pushing a word on the stack 1322 makes the stack pointer a smaller address. */ 1323 #define STACK_GROWS_DOWNWARD 1324 1325 /* Define this to nonzero if the nominal address of the stack frame 1326 is at the high-address end of the local variables; 1327 that is, each additional local variable allocated 1328 goes at a more negative offset in the frame. */ 1329 #define FRAME_GROWS_DOWNWARD 1 1330 1331 /* Offset within stack frame to start allocating local variables at. 1332 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1333 first local allocated. Otherwise, it is the offset to the BEGINNING 1334 of the first local allocated. */ 1335 #define STARTING_FRAME_OFFSET 0 1336 1337 /* If we generate an insn to push BYTES bytes, 1338 this says how many the stack pointer really advances by. 1339 On 386, we have pushw instruction that decrements by exactly 2 no 1340 matter what the position was, there is no pushb. 1341 But as CIE data alignment factor on this arch is -4, we need to make 1342 sure all stack pointer adjustments are in multiple of 4. 1343 1344 For 64bit ABI we round up to 8 bytes. 1345 */ 1346 1347 #define PUSH_ROUNDING(BYTES) \ 1348 (TARGET_64BIT \ 1349 ? (((BYTES) + 7) & (-8)) \ 1350 : (((BYTES) + 3) & (-4))) 1351 1352 /* If defined, the maximum amount of space required for outgoing arguments will 1353 be computed and placed into the variable 1354 `current_function_outgoing_args_size'. No space will be pushed onto the 1355 stack for each call; instead, the function prologue should increase the stack 1356 frame size by this amount. */ 1357 1358 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1359 1360 /* If defined, a C expression whose value is nonzero when we want to use PUSH 1361 instructions to pass outgoing arguments. */ 1362 1363 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1364 1365 /* We want the stack and args grow in opposite directions, even if 1366 PUSH_ARGS is 0. */ 1367 #define PUSH_ARGS_REVERSED 1 1368 1369 /* Offset of first parameter from the argument pointer register value. */ 1370 #define FIRST_PARM_OFFSET(FNDECL) 0 1371 1372 /* Define this macro if functions should assume that stack space has been 1373 allocated for arguments even when their values are passed in registers. 1374 1375 The value of this macro is the size, in bytes, of the area reserved for 1376 arguments passed in registers for the function represented by FNDECL. 1377 1378 This space can be allocated by the caller, or be a part of the 1379 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1380 which. */ 1381 #define REG_PARM_STACK_SPACE(FNDECL) 0 1382 1383 /* Value is the number of bytes of arguments automatically 1384 popped when returning from a subroutine call. 1385 FUNDECL is the declaration node of the function (as a tree), 1386 FUNTYPE is the data type of the function (as a tree), 1387 or for a library call it is an identifier node for the subroutine name. 1388 SIZE is the number of bytes of arguments passed on the stack. 1389 1390 On the 80386, the RTD insn may be used to pop them if the number 1391 of args is fixed, but if the number is variable then the caller 1392 must pop them all. RTD can't be used for library calls now 1393 because the library is compiled with the Unix compiler. 1394 Use of RTD is a selectable option, since it is incompatible with 1395 standard Unix calling sequences. If the option is not selected, 1396 the caller must always pop the args. 1397 1398 The attribute stdcall is equivalent to RTD on a per module basis. */ 1399 1400 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1401 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1402 1403 #define FUNCTION_VALUE_REGNO_P(N) \ 1404 ix86_function_value_regno_p (N) 1405 1406 /* Define how to find the value returned by a library function 1407 assuming the value has mode MODE. */ 1408 1409 #define LIBCALL_VALUE(MODE) \ 1410 ix86_libcall_value (MODE) 1411 1412 /* Define the size of the result block used for communication between 1413 untyped_call and untyped_return. The block contains a DImode value 1414 followed by the block used by fnsave and frstor. */ 1415 1416 #define APPLY_RESULT_SIZE (8+108) 1417 1418 /* 1 if N is a possible register number for function argument passing. */ 1419 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1420 1421 /* Define a data type for recording info about an argument list 1422 during the scan of that argument list. This data type should 1423 hold all necessary information about the function itself 1424 and about the args processed so far, enough to enable macros 1425 such as FUNCTION_ARG to determine where the next arg should go. */ 1426 1427 typedef struct ix86_args { 1428 int words; /* # words passed so far */ 1429 int nregs; /* # registers available for passing */ 1430 int regno; /* next available register number */ 1431 int fastcall; /* fastcall calling convention is used */ 1432 int sse_words; /* # sse words passed so far */ 1433 int sse_nregs; /* # sse registers available for passing */ 1434 int warn_sse; /* True when we want to warn about SSE ABI. */ 1435 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1436 int sse_regno; /* next available sse register number */ 1437 int mmx_words; /* # mmx words passed so far */ 1438 int mmx_nregs; /* # mmx registers available for passing */ 1439 int mmx_regno; /* next available mmx register number */ 1440 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1441 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should 1442 be passed in SSE registers. Otherwise 0. */ 1443 } CUMULATIVE_ARGS; 1444 1445 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1446 for a call to a function whose data type is FNTYPE. 1447 For a library call, FNTYPE is 0. */ 1448 1449 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1450 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1451 1452 /* Update the data in CUM to advance over an argument 1453 of mode MODE and data type TYPE. 1454 (TYPE is null for libcalls where that information may not be available.) */ 1455 1456 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1457 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1458 1459 /* Define where to put the arguments to a function. 1460 Value is zero to push the argument on the stack, 1461 or a hard register in which to store the argument. 1462 1463 MODE is the argument's machine mode. 1464 TYPE is the data type of the argument (as a tree). 1465 This is null for libcalls where that information may 1466 not be available. 1467 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1468 the preceding args and about the function being called. 1469 NAMED is nonzero if this argument is a named parameter 1470 (otherwise it is an extra parameter matching an ellipsis). */ 1471 1472 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1473 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1474 1475 /* Implement `va_start' for varargs and stdarg. */ 1476 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \ 1477 ix86_va_start (VALIST, NEXTARG) 1478 1479 #define TARGET_ASM_FILE_END ix86_file_end 1480 #define NEED_INDICATE_EXEC_STACK 0 1481 1482 /* Output assembler code to FILE to increment profiler label # LABELNO 1483 for profiling a function entry. */ 1484 1485 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) 1486 1487 #define MCOUNT_NAME "_mcount" 1488 1489 #define PROFILE_COUNT_REGISTER "edx" 1490 1491 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1492 the stack pointer does not matter. The value is tested only in 1493 functions that have frame pointers. 1494 No definition is equivalent to always zero. */ 1495 /* Note on the 386 it might be more efficient not to define this since 1496 we have to restore it ourselves from the frame pointer, in order to 1497 use pop */ 1498 1499 #define EXIT_IGNORE_STACK 1 1500 1501 /* Output assembler code for a block containing the constant parts 1502 of a trampoline, leaving space for the variable parts. */ 1503 1504 /* On the 386, the trampoline contains two instructions: 1505 mov #STATIC,ecx 1506 jmp FUNCTION 1507 The trampoline is generated entirely at runtime. The operand of JMP 1508 is the address of FUNCTION relative to the instruction following the 1509 JMP (which is 5 bytes long). */ 1510 1511 /* Length in units of the trampoline for entering a nested function. */ 1512 1513 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) 1514 1515 /* Emit RTL insns to initialize the variable parts of a trampoline. 1516 FNADDR is an RTX for the address of the function's pure code. 1517 CXT is an RTX for the static chain value for the function. */ 1518 1519 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1520 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1521 1522 /* Definitions for register eliminations. 1523 1524 This is an array of structures. Each structure initializes one pair 1525 of eliminable registers. The "from" register number is given first, 1526 followed by "to". Eliminations of the same "from" register are listed 1527 in order of preference. 1528 1529 There are two registers that can always be eliminated on the i386. 1530 The frame pointer and the arg pointer can be replaced by either the 1531 hard frame pointer or to the stack pointer, depending upon the 1532 circumstances. The hard frame pointer is not used before reload and 1533 so it is not eligible for elimination. */ 1534 1535 #define ELIMINABLE_REGS \ 1536 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1537 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1538 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1539 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1540 1541 /* Given FROM and TO register numbers, say whether this elimination is 1542 allowed. Frame pointer elimination is automatically handled. 1543 1544 All other eliminations are valid. */ 1545 1546 #define CAN_ELIMINATE(FROM, TO) \ 1547 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 1548 1549 /* Define the offset between two registers, one to be eliminated, and the other 1550 its replacement, at the start of a routine. */ 1551 1552 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1553 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1554 1555 /* Addressing modes, and classification of registers for them. */ 1556 1557 /* Macros to check register numbers against specific register classes. */ 1558 1559 /* These assume that REGNO is a hard or pseudo reg number. 1560 They give nonzero only if REGNO is a hard reg of the suitable class 1561 or a pseudo reg currently allocated to a suitable hard reg. 1562 Since they use reg_renumber, they are safe only once reg_renumber 1563 has been allocated, which happens in local-alloc.c. */ 1564 1565 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1566 ((REGNO) < STACK_POINTER_REGNUM \ 1567 || (REGNO >= FIRST_REX_INT_REG \ 1568 && (REGNO) <= LAST_REX_INT_REG) \ 1569 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1570 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1571 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) 1572 1573 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1574 ((REGNO) <= STACK_POINTER_REGNUM \ 1575 || (REGNO) == ARG_POINTER_REGNUM \ 1576 || (REGNO) == FRAME_POINTER_REGNUM \ 1577 || (REGNO >= FIRST_REX_INT_REG \ 1578 && (REGNO) <= LAST_REX_INT_REG) \ 1579 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1580 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1581 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) 1582 1583 #define REGNO_OK_FOR_SIREG_P(REGNO) \ 1584 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) 1585 #define REGNO_OK_FOR_DIREG_P(REGNO) \ 1586 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) 1587 1588 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1589 and check its validity for a certain class. 1590 We have two alternate definitions for each of them. 1591 The usual definition accepts all pseudo regs; the other rejects 1592 them unless they have been allocated suitable hard regs. 1593 The symbol REG_OK_STRICT causes the latter definition to be used. 1594 1595 Most source files want to accept pseudo regs in the hope that 1596 they will get allocated to the class that the insn wants them to be in. 1597 Source files for reload pass need to be strict. 1598 After reload, it makes no difference, since pseudo regs have 1599 been eliminated by then. */ 1600 1601 1602 /* Non strict versions, pseudos are ok. */ 1603 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1604 (REGNO (X) < STACK_POINTER_REGNUM \ 1605 || (REGNO (X) >= FIRST_REX_INT_REG \ 1606 && REGNO (X) <= LAST_REX_INT_REG) \ 1607 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1608 1609 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1610 (REGNO (X) <= STACK_POINTER_REGNUM \ 1611 || REGNO (X) == ARG_POINTER_REGNUM \ 1612 || REGNO (X) == FRAME_POINTER_REGNUM \ 1613 || (REGNO (X) >= FIRST_REX_INT_REG \ 1614 && REGNO (X) <= LAST_REX_INT_REG) \ 1615 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1616 1617 /* Strict versions, hard registers only */ 1618 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1619 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1620 1621 #ifndef REG_OK_STRICT 1622 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1623 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1624 1625 #else 1626 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1627 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1628 #endif 1629 1630 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1631 that is a valid memory address for an instruction. 1632 The MODE argument is the machine mode for the MEM expression 1633 that wants to use this address. 1634 1635 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, 1636 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1637 1638 See legitimize_pic_address in i386.c for details as to what 1639 constitutes a legitimate address when -fpic is used. */ 1640 1641 #define MAX_REGS_PER_ADDRESS 2 1642 1643 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1644 1645 /* Nonzero if the constant value X is a legitimate general operand. 1646 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1647 1648 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) 1649 1650 #ifdef REG_OK_STRICT 1651 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1652 do { \ 1653 if (legitimate_address_p ((MODE), (X), 1)) \ 1654 goto ADDR; \ 1655 } while (0) 1656 1657 #else 1658 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1659 do { \ 1660 if (legitimate_address_p ((MODE), (X), 0)) \ 1661 goto ADDR; \ 1662 } while (0) 1663 1664 #endif 1665 1666 /* If defined, a C expression to determine the base term of address X. 1667 This macro is used in only one place: `find_base_term' in alias.c. 1668 1669 It is always safe for this macro to not be defined. It exists so 1670 that alias analysis can understand machine-dependent addresses. 1671 1672 The typical use of this macro is to handle addresses containing 1673 a label_ref or symbol_ref within an UNSPEC. */ 1674 1675 #define FIND_BASE_TERM(X) ix86_find_base_term (X) 1676 1677 /* Try machine-dependent ways of modifying an illegitimate address 1678 to be legitimate. If we find one, return the new, valid address. 1679 This macro is used in only one place: `memory_address' in explow.c. 1680 1681 OLDX is the address as it was before break_out_memory_refs was called. 1682 In some cases it is useful to look at this to decide what needs to be done. 1683 1684 MODE and WIN are passed so that this macro can use 1685 GO_IF_LEGITIMATE_ADDRESS. 1686 1687 It is always safe for this macro to do nothing. It exists to recognize 1688 opportunities to optimize the output. 1689 1690 For the 80386, we handle X+REG by loading X into a register R and 1691 using R+REG. R will go in a general reg and indexing will be used. 1692 However, if REG is a broken-out memory address or multiplication, 1693 nothing needs to be done because REG can certainly go in a general reg. 1694 1695 When -fpic is used, special handling is needed for symbolic references. 1696 See comments by legitimize_pic_address in i386.c for details. */ 1697 1698 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 1699 do { \ 1700 (X) = legitimize_address ((X), (OLDX), (MODE)); \ 1701 if (memory_address_p ((MODE), (X))) \ 1702 goto WIN; \ 1703 } while (0) 1704 1705 #define REWRITE_ADDRESS(X) rewrite_address (X) 1706 1707 /* Nonzero if the constant value X is a legitimate general operand 1708 when generating PIC code. It is given that flag_pic is on and 1709 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1710 1711 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1712 1713 #define SYMBOLIC_CONST(X) \ 1714 (GET_CODE (X) == SYMBOL_REF \ 1715 || GET_CODE (X) == LABEL_REF \ 1716 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 1717 1718 /* Go to LABEL if ADDR (a legitimate address expression) 1719 has an effect that depends on the machine mode it is used for. 1720 On the 80386, only postdecrement and postincrement address depend thus 1721 (the amount of decrement or increment being the length of the operand). */ 1722 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 1723 do { \ 1724 if (GET_CODE (ADDR) == POST_INC \ 1725 || GET_CODE (ADDR) == POST_DEC) \ 1726 goto LABEL; \ 1727 } while (0) 1728 1729 /* Max number of args passed in registers. If this is more than 3, we will 1730 have problems with ebx (register #4), since it is a caller save register and 1731 is also used as the pic register in ELF. So for now, don't allow more than 1732 3 registers to be passed in registers. */ 1733 1734 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3) 1735 1736 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0)) 1737 1738 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 1739 1740 1741 /* Specify the machine mode that this machine uses 1742 for the index in the tablejump instruction. */ 1743 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) 1744 1745 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1746 #define DEFAULT_SIGNED_CHAR 1 1747 1748 /* Number of bytes moved into a data cache for a single prefetch operation. */ 1749 #define PREFETCH_BLOCK ix86_cost->prefetch_block 1750 1751 /* Number of prefetch operations that can be done in parallel. */ 1752 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches 1753 1754 /* Max number of bytes we can move from memory to memory 1755 in one reasonably fast instruction. */ 1756 #define MOVE_MAX 16 1757 1758 /* MOVE_MAX_PIECES is the number of bytes at a time which we can 1759 move efficiently, as opposed to MOVE_MAX which is the maximum 1760 number of bytes we can move with a single instruction. */ 1761 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 1762 1763 /* If a memory-to-memory move would take MOVE_RATIO or more simple 1764 move-instruction pairs, we will do a movmem or libcall instead. 1765 Increasing the value will always make code faster, but eventually 1766 incurs high cost in increased code size. 1767 1768 If you don't define this, a reasonable default is used. */ 1769 1770 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) 1771 1772 /* If a clear memory operation would take CLEAR_RATIO or more simple 1773 move-instruction sequences, we will do a clrmem or libcall instead. */ 1774 1775 #define CLEAR_RATIO (optimize_size ? 2 \ 1776 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio) 1777 1778 /* Define if shifts truncate the shift count 1779 which implies one can omit a sign-extension or zero-extension 1780 of a shift count. */ 1781 /* On i386, shifts do truncate the count. But bit opcodes don't. */ 1782 1783 /* #define SHIFT_COUNT_TRUNCATED */ 1784 1785 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1786 is done just by pretending it is already truncated. */ 1787 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1788 1789 /* A macro to update M and UNSIGNEDP when an object whose type is 1790 TYPE and which has the specified mode and signedness is to be 1791 stored in a register. This macro is only called when TYPE is a 1792 scalar type. 1793 1794 On i386 it is sometimes useful to promote HImode and QImode 1795 quantities to SImode. The choice depends on target type. */ 1796 1797 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1798 do { \ 1799 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 1800 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 1801 (MODE) = SImode; \ 1802 } while (0) 1803 1804 /* Specify the machine mode that pointers have. 1805 After generation of rtl, the compiler makes no further distinction 1806 between pointers and any other objects of this machine mode. */ 1807 #define Pmode (TARGET_64BIT ? DImode : SImode) 1808 1809 /* A function address in a call instruction 1810 is a byte address (for indexing purposes) 1811 so give the MEM rtx a byte's mode. */ 1812 #define FUNCTION_MODE QImode 1813 1814 /* A C expression for the cost of moving data from a register in class FROM to 1815 one in class TO. The classes are expressed using the enumeration values 1816 such as `GENERAL_REGS'. A value of 2 is the default; other values are 1817 interpreted relative to that. 1818 1819 It is not required that the cost always equal 2 when FROM is the same as TO; 1820 on some machines it is expensive to move between registers if they are not 1821 general registers. */ 1822 1823 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 1824 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 1825 1826 /* A C expression for the cost of moving data of mode M between a 1827 register and memory. A value of 2 is the default; this cost is 1828 relative to those in `REGISTER_MOVE_COST'. 1829 1830 If moving between registers and memory is more expensive than 1831 between two registers, you should define this macro to express the 1832 relative cost. */ 1833 1834 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 1835 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 1836 1837 /* A C expression for the cost of a branch instruction. A value of 1 1838 is the default; other values are interpreted relative to that. */ 1839 1840 #define BRANCH_COST ix86_branch_cost 1841 1842 /* Define this macro as a C expression which is nonzero if accessing 1843 less than a word of memory (i.e. a `char' or a `short') is no 1844 faster than accessing a word of memory, i.e., if such access 1845 require more than one instruction or if there is no difference in 1846 cost between byte and (aligned) word loads. 1847 1848 When this macro is not defined, the compiler will access a field by 1849 finding the smallest containing object; when it is defined, a 1850 fullword load will be used if alignment permits. Unless bytes 1851 accesses are faster than word accesses, using word accesses is 1852 preferable since it may eliminate subsequent memory access if 1853 subsequent accesses occur to other fields in the same word of the 1854 structure, but to different bytes. */ 1855 1856 #define SLOW_BYTE_ACCESS 0 1857 1858 /* Nonzero if access to memory by shorts is slow and undesirable. */ 1859 #define SLOW_SHORT_ACCESS 0 1860 1861 /* Define this macro to be the value 1 if unaligned accesses have a 1862 cost many times greater than aligned accesses, for example if they 1863 are emulated in a trap handler. 1864 1865 When this macro is nonzero, the compiler will act as if 1866 `STRICT_ALIGNMENT' were nonzero when generating code for block 1867 moves. This can cause significantly more instructions to be 1868 produced. Therefore, do not set this macro nonzero if unaligned 1869 accesses only add a cycle or two to the time for a memory access. 1870 1871 If the value of this macro is always zero, it need not be defined. */ 1872 1873 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 1874 1875 /* Define this macro if it is as good or better to call a constant 1876 function address than to call an address kept in a register. 1877 1878 Desirable on the 386 because a CALL with a constant address is 1879 faster than one with a register address. */ 1880 1881 #define NO_FUNCTION_CSE 1882 1883 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1884 return the mode to be used for the comparison. 1885 1886 For floating-point equality comparisons, CCFPEQmode should be used. 1887 VOIDmode should be used in all other cases. 1888 1889 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 1890 possible, to allow for more combinations. */ 1891 1892 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 1893 1894 /* Return nonzero if MODE implies a floating point inequality can be 1895 reversed. */ 1896 1897 #define REVERSIBLE_CC_MODE(MODE) 1 1898 1899 /* A C expression whose value is reversed condition code of the CODE for 1900 comparison done in CC_MODE mode. */ 1901 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) 1902 1903 1904 /* Control the assembler format that we output, to the extent 1905 this does not vary between assemblers. */ 1906 1907 /* How to refer to registers in assembler output. 1908 This sequence is indexed by compiler's hard-register-number (see above). */ 1909 1910 /* In order to refer to the first 8 regs as 32 bit regs, prefix an "e". 1911 For non floating point regs, the following are the HImode names. 1912 1913 For float regs, the stack top is sometimes referred to as "%st(0)" 1914 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ 1915 1916 #define HI_REGISTER_NAMES \ 1917 {"ax","dx","cx","bx","si","di","bp","sp", \ 1918 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 1919 "argp", "flags", "fpsr", "dirflag", "frame", \ 1920 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 1921 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ 1922 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 1923 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 1924 1925 #define REGISTER_NAMES HI_REGISTER_NAMES 1926 1927 /* Table of additional register names to use in user input. */ 1928 1929 #define ADDITIONAL_REGISTER_NAMES \ 1930 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 1931 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 1932 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 1933 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 1934 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 1935 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } 1936 1937 /* Note we are omitting these since currently I don't know how 1938 to get gcc to use these, since they want the same but different 1939 number as al, and ax. 1940 */ 1941 1942 #define QI_REGISTER_NAMES \ 1943 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 1944 1945 /* These parallel the array above, and can be used to access bits 8:15 1946 of regs 0 through 3. */ 1947 1948 #define QI_HIGH_REGISTER_NAMES \ 1949 {"ah", "dh", "ch", "bh", } 1950 1951 /* How to renumber registers for dbx and gdb. */ 1952 1953 #define DBX_REGISTER_NUMBER(N) \ 1954 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 1955 1956 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 1957 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 1958 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 1959 1960 /* Before the prologue, RA is at 0(%esp). */ 1961 #define INCOMING_RETURN_ADDR_RTX \ 1962 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 1963 1964 /* After the prologue, RA is at -4(AP) in the current frame. */ 1965 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 1966 ((COUNT) == 0 \ 1967 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 1968 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 1969 1970 /* PC is dbx register 8; let's use that column for RA. */ 1971 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 1972 1973 /* Before the prologue, the top of the frame is at 4(%esp). */ 1974 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 1975 1976 /* Describe how we implement __builtin_eh_return. */ 1977 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 1978 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 1979 1980 1981 /* Select a format to encode pointers in exception handling data. CODE 1982 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1983 true if the symbol may be affected by dynamic relocations. 1984 1985 ??? All x86 object file formats are capable of representing this. 1986 After all, the relocation needed is the same as for the call insn. 1987 Whether or not a particular assembler allows us to enter such, I 1988 guess we'll have to see. */ 1989 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 1990 asm_preferred_eh_data_format ((CODE), (GLOBAL)) 1991 1992 /* This is how to output an insn to push a register on the stack. 1993 It need not be very fast code. */ 1994 1995 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 1996 do { \ 1997 if (TARGET_64BIT) \ 1998 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 1999 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2000 else \ 2001 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2002 } while (0) 2003 2004 /* This is how to output an insn to pop a register from the stack. 2005 It need not be very fast code. */ 2006 2007 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2008 do { \ 2009 if (TARGET_64BIT) \ 2010 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 2011 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2012 else \ 2013 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2014 } while (0) 2015 2016 /* This is how to output an element of a case-vector that is absolute. */ 2017 2018 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2019 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2020 2021 /* This is how to output an element of a case-vector that is relative. */ 2022 2023 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2024 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2025 2026 /* Under some conditions we need jump tables in the text section, 2027 because the assembler cannot handle label differences between 2028 sections. This is the case for x86_64 on Mach-O for example. */ 2029 2030 #define JUMP_TABLES_IN_TEXT_SECTION \ 2031 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ 2032 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) 2033 2034 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2035 and switch back. For x86 we do this only to save a few bytes that 2036 would otherwise be unused in the text section. */ 2037 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2038 asm (SECTION_OP "\n\t" \ 2039 "call " USER_LABEL_PREFIX #FUNC "\n" \ 2040 TEXT_SECTION_ASM_OP); 2041 2042 /* Print operand X (an rtx) in assembler syntax to file FILE. 2043 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2044 Effect of various CODE letters is described in i386.c near 2045 print_operand function. */ 2046 2047 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2048 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&') 2049 2050 #define PRINT_OPERAND(FILE, X, CODE) \ 2051 print_operand ((FILE), (X), (CODE)) 2052 2053 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2054 print_operand_address ((FILE), (ADDR)) 2055 2056 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ 2057 do { \ 2058 if (! output_addr_const_extra (FILE, (X))) \ 2059 goto FAIL; \ 2060 } while (0); 2061 2062 /* a letter which is not needed by the normal asm syntax, which 2063 we can use for operand syntax in the extended asm */ 2064 2065 #define ASM_OPERAND_LETTER '#' 2066 #define RET return "" 2067 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) 2068 2069 /* Which processor to schedule for. The cpu attribute defines a list that 2070 mirrors this list, so changes to i386.md must be made at the same time. */ 2071 2072 enum processor_type 2073 { 2074 PROCESSOR_I386, /* 80386 */ 2075 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 2076 PROCESSOR_PENTIUM, 2077 PROCESSOR_PENTIUMPRO, 2078 PROCESSOR_K6, 2079 PROCESSOR_ATHLON, 2080 PROCESSOR_PENTIUM4, 2081 PROCESSOR_K8, 2082 PROCESSOR_NOCONA, 2083 PROCESSOR_GENERIC32, 2084 PROCESSOR_GENERIC64, 2085 PROCESSOR_max 2086 }; 2087 2088 extern enum processor_type ix86_tune; 2089 extern enum processor_type ix86_arch; 2090 2091 enum fpmath_unit 2092 { 2093 FPMATH_387 = 1, 2094 FPMATH_SSE = 2 2095 }; 2096 2097 extern enum fpmath_unit ix86_fpmath; 2098 2099 enum tls_dialect 2100 { 2101 TLS_DIALECT_GNU, 2102 TLS_DIALECT_GNU2, 2103 TLS_DIALECT_SUN 2104 }; 2105 2106 extern enum tls_dialect ix86_tls_dialect; 2107 2108 enum cmodel { 2109 CM_32, /* The traditional 32-bit ABI. */ 2110 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ 2111 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ 2112 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ 2113 CM_LARGE, /* No assumptions. */ 2114 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */ 2115 CM_MEDIUM_PIC /* Assumes code+got/plt fits in a 31 bit region. */ 2116 }; 2117 2118 extern enum cmodel ix86_cmodel; 2119 2120 /* Size of the RED_ZONE area. */ 2121 #define RED_ZONE_SIZE 128 2122 /* Reserved area of the red zone for temporaries. */ 2123 #define RED_ZONE_RESERVE 8 2124 2125 enum asm_dialect { 2126 ASM_ATT, 2127 ASM_INTEL 2128 }; 2129 2130 extern enum asm_dialect ix86_asm_dialect; 2131 extern unsigned int ix86_preferred_stack_boundary; 2132 extern int ix86_branch_cost, ix86_section_threshold; 2133 2134 /* Smallest class containing REGNO. */ 2135 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 2136 2137 extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 2138 extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 2139 extern rtx ix86_compare_emitted; 2140 2141 /* To properly truncate FP values into integers, we need to set i387 control 2142 word. We can't emit proper mode switching code before reload, as spills 2143 generated by reload may truncate values incorrectly, but we still can avoid 2144 redundant computation of new control word by the mode switching pass. 2145 The fldcw instructions are still emitted redundantly, but this is probably 2146 not going to be noticeable problem, as most CPUs do have fast path for 2147 the sequence. 2148 2149 The machinery is to emit simple truncation instructions and split them 2150 before reload to instructions having USEs of two memory locations that 2151 are filled by this code to old and new control word. 2152 2153 Post-reload pass may be later used to eliminate the redundant fildcw if 2154 needed. */ 2155 2156 enum ix86_entity 2157 { 2158 I387_TRUNC = 0, 2159 I387_FLOOR, 2160 I387_CEIL, 2161 I387_MASK_PM, 2162 MAX_386_ENTITIES 2163 }; 2164 2165 enum ix86_stack_slot 2166 { 2167 SLOT_VIRTUAL = 0, 2168 SLOT_TEMP, 2169 SLOT_CW_STORED, 2170 SLOT_CW_TRUNC, 2171 SLOT_CW_FLOOR, 2172 SLOT_CW_CEIL, 2173 SLOT_CW_MASK_PM, 2174 MAX_386_STACK_LOCALS 2175 }; 2176 2177 /* Define this macro if the port needs extra instructions inserted 2178 for mode switching in an optimizing compilation. */ 2179 2180 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 2181 ix86_optimize_mode_switching[(ENTITY)] 2182 2183 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 2184 initializer for an array of integers. Each initializer element N 2185 refers to an entity that needs mode switching, and specifies the 2186 number of different modes that might need to be set for this 2187 entity. The position of the initializer in the initializer - 2188 starting counting at zero - determines the integer that is used to 2189 refer to the mode-switched entity in question. */ 2190 2191 #define NUM_MODES_FOR_MODE_SWITCHING \ 2192 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 2193 2194 /* ENTITY is an integer specifying a mode-switched entity. If 2195 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 2196 return an integer value not larger than the corresponding element 2197 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 2198 must be switched into prior to the execution of INSN. */ 2199 2200 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) 2201 2202 /* This macro specifies the order in which modes for ENTITY are 2203 processed. 0 is the highest priority. */ 2204 2205 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 2206 2207 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 2208 is the set of hard registers live at the point where the insn(s) 2209 are to be inserted. */ 2210 2211 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 2212 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \ 2213 ? emit_i387_cw_initialization (MODE), 0 \ 2214 : 0) 2215 2216 2217 /* Avoid renaming of stack registers, as doing so in combination with 2218 scheduling just increases amount of live registers at time and in 2219 the turn amount of fxch instructions needed. 2220 2221 ??? Maybe Pentium chips benefits from renaming, someone can try.... */ 2222 2223 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 2224 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) 2225 2226 2227 #define DLL_IMPORT_EXPORT_PREFIX '#' 2228 2229 #define FASTCALL_PREFIX '@' 2230 2231 struct machine_function GTY(()) 2232 { 2233 struct stack_local_entry *stack_locals; 2234 const char *some_ld_name; 2235 rtx force_align_arg_pointer; 2236 int save_varrargs_registers; 2237 int accesses_prev_frame; 2238 int optimize_mode_switching[MAX_386_ENTITIES]; 2239 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to 2240 determine the style used. */ 2241 int use_fast_prologue_epilogue; 2242 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed 2243 for. */ 2244 int use_fast_prologue_epilogue_nregs; 2245 /* If true, the current function needs the default PIC register, not 2246 an alternate register (on x86) and must not use the red zone (on 2247 x86_64), even if it's a leaf function. We don't want the 2248 function to be regarded as non-leaf because TLS calls need not 2249 affect register allocation. This flag is set when a TLS call 2250 instruction is expanded within a function, and never reset, even 2251 if all such instructions are optimized away. Use the 2252 ix86_current_function_calls_tls_descriptor macro for a better 2253 approximation. */ 2254 int tls_descriptor_call_expanded_p; 2255 }; 2256 2257 #define ix86_stack_locals (cfun->machine->stack_locals) 2258 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers) 2259 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 2260 #define ix86_tls_descriptor_calls_expanded_in_cfun \ 2261 (cfun->machine->tls_descriptor_call_expanded_p) 2262 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS 2263 calls are optimized away, we try to detect cases in which it was 2264 optimized away. Since such instructions (use (reg REG_SP)), we can 2265 verify whether there's any such instruction live by testing that 2266 REG_SP is live. */ 2267 #define ix86_current_function_calls_tls_descriptor \ 2268 (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG]) 2269 2270 /* Control behavior of x86_file_start. */ 2271 #define X86_FILE_START_VERSION_DIRECTIVE false 2272 #define X86_FILE_START_FLTUSED false 2273 2274 /* Flag to mark data that is in the large address area. */ 2275 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 2276 #define SYMBOL_REF_FAR_ADDR_P(X) \ 2277 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) 2278 /* 2279 Local variables: 2280 version-control: t 2281 End: 2282 */ 2283