1 /* $NetBSD: mtpr.h,v 1.24 2021/11/02 11:26:05 ryo Exp $ */
2
3 /*
4 * Copyright (c) 1994 Ludd, University of Lule}, Sweden.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 /* All bugs are subject to removal without further notice */
29
30 #ifndef _VAX_MTPR_H_
31 #define _VAX_MTPR_H_
32
33 /******************************************************************************
34
35 Processor register numbers in the VAX /IC
36
37 ******************************************************************************/
38
39
40 #define PR_KSP 0 /* Kernel Stack Pointer */
41 #define PR_ESP 1 /* Executive Stack Pointer */
42 #define PR_SSP 2 /* Supervisor Stack Pointer */
43 #define PR_USP 3 /* User Stack Pointer */
44 #define PR_ISP 4 /* Interrupt Stack Pointer */
45
46 #define PR_P0BR 8 /* P0 Base Register */
47 #define PR_P0LR 9 /* P0 Length Register */
48 #define PR_P1BR 10 /* P1 Base Register */
49 #define PR_P1LR 11 /* P1 Length Register */
50 #define PR_SBR 12 /* System Base Register */
51 #define PR_SLR 13 /* System Limit Register */
52 #define PR_PCBB 16 /* Process Control Block Base */
53 #define PR_SCBB 17 /* System Control Block Base */
54 #define PR_IPL 18 /* Interrupt Priority Level */
55 #define PR_ASTLVL 19 /* AST Level */
56 #define PR_SIRR 20 /* Software Interrupt Request */
57 #define PR_SISR 21 /* Software Interrupt Summary */
58 #define PR_IPIR 22 /* KA820 Interprocessor register */
59 #define PR_MCSR 23 /* Machine Check Status Register 11/750 */
60 #define PR_ICCS 24 /* Interval Clock Control */
61 #define PR_NICR 25 /* Next Interval Count */
62 #define PR_ICR 26 /* Interval Count */
63 #define PR_TODR 27 /* Time Of Year (optional) */
64 #define PR_CSRS 28 /* Console Storage R/S */
65 #define PR_CSRD 29 /* Console Storage R/D */
66 #define PR_CSTS 30 /* Console Storage T/S */
67 #define PR_CSTD 31 /* Console Storage T/D */
68 #define PR_RXCS 32 /* Console Receiver C/S */
69 #define PR_RXDB 33 /* Console Receiver D/B */
70 #define PR_TXCS 34 /* Console Transmit C/S */
71 #define PR_TXDB 35 /* Console Transmit D/B */
72 #define PR_TBDR 36 /* Translation Buffer Group Disable Register 11/750 */
73 #define PR_CADR 37 /* Cache Disable Register 11/750 */
74 #define PR_MCESR 38 /* Machiune Check Error Summary Register 11/750 */
75 #define PR_CAER 39 /* Cache Error Register 11/750 */
76 #define PR_ACCS 40 /* Accelerator control register */
77 #define PR_SAVISP 41 /* Console Saved ISP */
78 #define PR_SAVPC 42 /* Console Saved PC */
79 #define PR_SAVPSL 43 /* Console Saved PSL */
80 #define PR_WCSA 44 /* WCS Address */
81 #define PR_WCSB 45 /* WCS Data */
82 #define PR_SBIFS 48 /* SBI Fault/Status */
83 #define PR_SBIS 49 /* SBI Silo */
84 #define PR_SBISC 50 /* SBI Silo Comparator */
85 #define PR_SBIMT 51 /* SBI Silo Maintenance */
86 #define PR_SBIER 52 /* SBI Error Register */
87 #define PR_SBITA 53 /* SBI Timeout Address Register */
88 #define PR_SBIQC 54 /* SBI Quadword Clear */
89 #define PR_IUR 55 /* Initialize Unibus Register 11/750 */
90 #define PR_MAPEN 56 /* Memory Management Enable */
91 #define PR_TBIA 57 /* Trans. Buf. Invalidate All */
92 #define PR_TBIS 58 /* Trans. Buf. Invalidate Single */
93 #define PR_TBDATA 59 /* Translation Buffer Data */
94 #define PR_MBRK 60 /* Microprogram Break */
95 #define PR_PMR 61 /* Performance Monnitor Enable */
96 #define PR_SID 62 /* System ID Register */
97 #define PR_TBCHK 63 /* Translation Buffer Check */
98
99 #define PR_PAMACC 64 /* Physical Address Memory Map Access (KA86) */
100 #define PR_PAMLOC 65 /* Physical Address Memory Map Location (KA86) */
101 #define PR_CSWP 66 /* Cache Sweep (KA86) */
102 #define PR_MDECC 67 /* MBOX Data Ecc Register (KA86) */
103 #define PR_MENA 68 /* MBOX Error Enable Register (KA86) */
104 #define PR_MDCTL 69 /* MBOX Data Control Register (KA86) */
105 #define PR_MCCTL 70 /* MBOX Mcc Control Register (KA86) */
106 #define PR_MERG 71 /* MBOX Error Generator Register (KA86) */
107 #define PR_CRBT 72 /* Console Reboot (KA86) */
108 #define PR_DFI 73 /* Diagnostic Fault Insertion Register (KA86) */
109 #define PR_EHSR 74 /* Error Handling Status Register (KA86) */
110 #define PR_STXCS 76 /* Console Storage C/S (KA86) */
111 #define PR_STXDB 77 /* Console Storage D/B (KA86) */
112 #define PR_ESPA 78 /* EBOX Scratchpad Address (KA86) */
113 #define PR_ESPD 79 /* EBOX Scratchpad Data (KA86) */
114
115 #define PR_RXCS1 80 /* Serial-Line Unit 1 Receive CSR (KA820) */
116 #define PR_RXDB1 81 /* Serial-Line Unit 1 Receive Data Buffer (KA820) */
117 #define PR_TXCS1 82 /* Serial-Line Unit 1 Transmit CSR (KA820) */
118 #define PR_TXDB1 83 /* Serial-Line Unit 1 Transmit Data Buffer (KA820) */
119 #define PR_RXCS2 84 /* Serial-Line Unit 2 Receive CSR (KA820) */
120 #define PR_RXDB2 85 /* Serial-Line Unit 2 Receive Data Buffer (KA820) */
121 #define PR_TXCS2 86 /* Serial-Line Unit 2 Transmit CSR (KA820) */
122 #define PR_TXDB2 87 /* Serial-Line Unit 2 Transmit Data Buffer (KA820) */
123 #define PR_RXCS3 88 /* Serial-Line Unit 3 Receive CSR (KA820) */
124 #define PR_RXDB3 89 /* Serial-Line Unit 3 Receive Data Buffer (KA820) */
125 #define PR_TXCS3 90 /* Serial-Line Unit 3 Transmit CSR (KA820) */
126 #define PR_TXDB3 91 /* Serial-Line Unit 3 Transmit Data Buffer (KA820) */
127 #define PR_RXCD 92 /* Receive Console Data from another CPU (KA820) */
128 #define PR_CACHEX 93 /* Cache invalidate Register (KA820) */
129 #define PR_BINID 94 /* VAXBI node ID Register (KA820) */
130 #define PR_BISTOP 95 /* VAXBI Stop Register (KA820) */
131
132 #define PR_BCBTS 113 /* Backup Cache Tag Store (KA670) */
133 #define PR_BCP1TS 114 /* Primary Tag Store 1st half (KA670) */
134 #define PR_BCP2TS 115 /* Primary Tag Store 2st half (KA670) */
135 #define PR_BCRFR 116 /* Refresh Register (KA670) */
136 #define PR_BCIDX 117 /* Index Register (KA670) */
137 #define PR_BCSTS 118 /* Status (KA670) */
138 #define PR_BCCTL 119 /* Control Register (KA670) */
139 #define PR_BCERR 120 /* Error Address (KA670) */
140 #define PR_BCFBTS 121 /* Flush backup tag store (KA670) */
141 #define PR_BCFPTS 122 /* Flush primary tag store (KA670) */
142
143 #define PR_VINTSR 123 /* vector i/f error status (KA43/KA46) */
144 #define PR_PCTAG 124 /* primary cache tag store (KA43/KA46) */
145 #define PR_PCIDX 125 /* primary cache index (KA43/KA46) */
146 #define PR_PCERR 126 /* primary cache error address (KA43/KA46) */
147 #define PR_PCSTS 127 /* primary cache status (KA43/KA46) */
148
149 #define PR_VPSR 144 /* Vector processor status register */
150 #define PR_VAER 145 /* Vector arithmetic error register */
151 #define PR_VMAC 146 /* Vector memory activity register */
152 #define PR_VTBIA 147 /* Vector TBIA */
153 #define PR_VSAR 148 /* Vector state address register */
154 #define PR_VIADR 157 /* Vector indirect address register */
155 #define PR_VIDLO 158 /* Vector indirect data low */
156 #define PR_VIDHI 159 /* Vector indirect data high */
157
158 /* Definitions for AST */
159 #define AST_NO 4
160 #define AST_OK 3
161
162 #ifndef _LOCORE
163
164 static inline __always_inline void
mtpr(register_t val,int reg)165 mtpr(register_t val, int reg)
166 {
167 __asm volatile (
168 "mtpr %0,%1"
169 : /* No output */
170 : "g" (val), "g" (reg)
171 : "memory");
172 }
173
174 static inline __always_inline register_t
mfpr(int reg)175 mfpr(int reg)
176 {
177 register_t __val;
178 __asm volatile (
179 "mfpr %1,%0"
180 : "=g" (__val)
181 : "g" (reg));
182 return __val;
183 }
184 #endif /* _LOCORE */
185
186 #endif /* _VAX_MTPR_H_ */
187