1 /*- 2 * Copyright (c) 1982, 1986 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * %sccs.include.redist.c% 6 * 7 * @(#)psreg.h 7.3 (Berkeley) 05/09/91 8 */ 9 10 11 /* 12 * The Real Nitty Gritty Device Registers 13 */ 14 15 struct psdevice { 16 short int ps_data; /* data register */ 17 short int ps_addr; /* address register */ 18 short int ps_wcount; /* word count register */ 19 short int ps_busaddr; /* unibus address register */ 20 short int ps_iostat; /* io status register */ 21 }; 22 23 /* 24 * Possible ioctl's 25 */ 26 #define PSIOAUTOREFRESH _IO('p', 0) /* auto refresh */ 27 #define PSIOSINGLEREFRESH _IO('p', 1) /* single refresh */ 28 #define PSIOAUTOMAP _IO('p', 2) /* auto map */ 29 #define PSIOSINGLEMAP _IO('p', 3) /* single map */ 30 #define PSIODOUBLEBUFFER _IO('p', 4) /* double buffer */ 31 #define PSIOSINGLEBUFFER _IO('p', 5) /* single buffer */ 32 #define PSIOWAITREFRESH _IO('p', 6) /* await refresh */ 33 #define PSIOWAITMAP _IO('p', 7) /* await map */ 34 #define PSIOWAITHIT _IO('p', 8) /* await hit */ 35 #define PSIOSTOPREFRESH _IO('p', 9) /* stop refresh */ 36 #define PSIOSTOPMAP _IO('p',10) /* stop map */ 37 #define PSIOGETADDR _IOR('p',11, int) /* get Unibus address */ 38 #define PSIOTIMEREFRESH _IO('p',12) /* time refresh */ 39 40 /* 41 * Picture system io status register bits 42 */ 43 44 #define DIOREADY 0100000 45 #define PSAHOLD 040000 46 #define PSRESET 020000 47 #define DIORESET 010000 48 #define DMARESET 04000 49 #define PSIE 0400 50 #define DMAREADY 0200 51 #define DMAIE 0100 52 #define PASSIVE 010 53 #define DMAIN 04 54 #define NEXEM 02 55 #define GO 01 56 57 /* 58 * Picture system memory mapping control registers: SCB 0177400-0177410 59 */ 60 61 #define EXMMR_DMA 0177400 62 #define EXMMR_DIO 0177404 63 #define EXMMR_RC 0177405 64 #define EXMMR_MAPOUT 0177406 65 #define EXMMR_MAPIN 0177407 66 #define EXMSR 0177410 67 68 /* 69 * Extended memory status register bits 70 */ 71 72 #define DBERROR 0100000 73 #define SBERROR 040000 74 #define MEMREADY 0200 75 #define DBIE 0100 76 #define MMENBL 02 77 #define INITMEM 01 78 79 /* 80 * Size of extended memory 81 */ 82 83 #define NEXMPAGES (256*2) 84 #define WORDSPERPAGE (256) 85 86 /* 87 * MAP picture processor registers: SCB 0177750-0177753 88 */ 89 90 #define MAOL 0177750 91 #define MAOA 0177751 92 #define MAIA 0177752 93 #define MASR 0177753 94 #define MAMSR 0177754 95 96 /* 97 * MAP status register bits 98 */ 99 100 #define PPDONE 0100000 101 #define FIFOFULL 040000 102 #define FIFOEMPTY 020000 103 #define HIT 010000 104 #define IB 04000 105 #define TAKE 02000 106 #define MMODE 01400 107 #define MOSTOPPED 0200 108 #define IOUT 0100 109 #define MAO 040 110 #define MAI 020 111 #define HIT_HOLD 010 112 #define RSR_HOLD 04 113 #define VEC_HOLD 02 114 #define MAP_RESET 01 115 116 /* 117 * Refresh controller registers: SCB 0177730-0177737 118 */ 119 120 #define RFCSN 0177730 121 #define RFSN 0177731 122 #define RFAWA 0177732 123 #define RFAWL 0177733 124 #define RFAIA 0177734 125 #define RFASA 0177735 126 #define RFAIL 0177736 127 #define RFSR 0177737 128 129 /* 130 * Refresh controller status register bits 131 */ 132 133 #define RFSTOPPED 0100000 134 #define RFHOLD 040000 135 #define RFSTART 020000 136 #define AUTOREF 010000 137 #define RFBLANK 04000 138 #define RIGHT 02000 139 #define LGFIFO_FULL 01000 140 #define NOT_EXEC 0200 141 #define SKIPSEG 0100 142 #define WRITEBACK 040 143 #define SEARCH 020 144 #define MATCH_HOLD 010 145 #define MATCH_DEC 04 146 #define SEARCH_MODE 03 147 148 /* 149 * Interrupt control 150 */ 151 152 #define RTCREQ 0177760 153 #define RTCIE 0177761 154 #define SYSREQ 0177762 155 #define SYSIE 0177763 156 #define DEVREQ 0177764 157 #define DEVIE 0177765 158 159 /* 160 * System interrupt request bits 161 */ 162 163 #define LPEN_REQ 0200 164 #define MATCH_REQ 0100 165 #define WBSTOP_REQ 040 166 #define RFSTOP_REQ 020 167 #define MOSTOP_REQ 010 168 #define JUMP_REQ 04 169 #define HIT_REQ 02 170 #define HALT_REQ 01 171 172 /* 173 * Real-Time Clock registers 174 */ 175 176 #define RTCCNT 0177744 177 #define RTCSR 0177745 178 179 /* 180 * Real-Time Clock status register bits 181 */ 182 183 #define HZ120 040 184 #define EXT 020 185 #define SYNC 010 186 #define EXTSEL2 04 187 #define EXTSEL1 02 188 #define RUN 01 189 190 /* 191 * Control dials a/d registers 192 */ 193 194 #define ADDR0 0177500 195 #define ADDR1 0177501 196 #define ADDR2 0177502 197 #define ADDR3 0177503 198 #define ADDR4 0177504 199 #define ADDR5 0177505 200 #define ADDR6 0177506 201 #define ADDR7 0177507 202 203 /* 204 * Function switches and lights 205 */ 206 207 #define FSWR 0177626 208 #define FSLR 0177627 209